1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/highmem.h> 32 #include <linux/nmi.h> 33 #include <linux/pagevec.h> 34 #include <linux/scatterlist.h> 35 #include <linux/string_helpers.h> 36 #include <linux/utsname.h> 37 #include <linux/zlib.h> 38 39 #include <drm/drm_cache.h> 40 #include <drm/drm_print.h> 41 42 #include "display/intel_dmc.h" 43 #include "display/intel_overlay.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_pm.h" 50 #include "gt/intel_gt_regs.h" 51 52 #include "i915_driver.h" 53 #include "i915_drv.h" 54 #include "i915_gpu_error.h" 55 #include "i915_memcpy.h" 56 #include "i915_scatterlist.h" 57 #include "i915_utils.h" 58 59 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 60 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 61 62 static void __sg_set_buf(struct scatterlist *sg, 63 void *addr, unsigned int len, loff_t it) 64 { 65 sg->page_link = (unsigned long)virt_to_page(addr); 66 sg->offset = offset_in_page(addr); 67 sg->length = len; 68 sg->dma_address = it; 69 } 70 71 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 72 { 73 if (!len) 74 return false; 75 76 if (e->bytes + len + 1 <= e->size) 77 return true; 78 79 if (e->bytes) { 80 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 81 e->iter += e->bytes; 82 e->buf = NULL; 83 e->bytes = 0; 84 } 85 86 if (e->cur == e->end) { 87 struct scatterlist *sgl; 88 89 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 90 if (!sgl) { 91 e->err = -ENOMEM; 92 return false; 93 } 94 95 if (e->cur) { 96 e->cur->offset = 0; 97 e->cur->length = 0; 98 e->cur->page_link = 99 (unsigned long)sgl | SG_CHAIN; 100 } else { 101 e->sgl = sgl; 102 } 103 104 e->cur = sgl; 105 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 106 } 107 108 e->size = ALIGN(len + 1, SZ_64K); 109 e->buf = kmalloc(e->size, ALLOW_FAIL); 110 if (!e->buf) { 111 e->size = PAGE_ALIGN(len + 1); 112 e->buf = kmalloc(e->size, GFP_KERNEL); 113 } 114 if (!e->buf) { 115 e->err = -ENOMEM; 116 return false; 117 } 118 119 return true; 120 } 121 122 __printf(2, 0) 123 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 124 const char *fmt, va_list args) 125 { 126 va_list ap; 127 int len; 128 129 if (e->err) 130 return; 131 132 va_copy(ap, args); 133 len = vsnprintf(NULL, 0, fmt, ap); 134 va_end(ap); 135 if (len <= 0) { 136 e->err = len; 137 return; 138 } 139 140 if (!__i915_error_grow(e, len)) 141 return; 142 143 GEM_BUG_ON(e->bytes >= e->size); 144 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 145 if (len < 0) { 146 e->err = len; 147 return; 148 } 149 e->bytes += len; 150 } 151 152 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 153 { 154 unsigned len; 155 156 if (e->err || !str) 157 return; 158 159 len = strlen(str); 160 if (!__i915_error_grow(e, len)) 161 return; 162 163 GEM_BUG_ON(e->bytes + len > e->size); 164 memcpy(e->buf + e->bytes, str, len); 165 e->bytes += len; 166 } 167 168 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 169 #define err_puts(e, s) i915_error_puts(e, s) 170 171 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 172 { 173 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 174 } 175 176 static inline struct drm_printer 177 i915_error_printer(struct drm_i915_error_state_buf *e) 178 { 179 struct drm_printer p = { 180 .printfn = __i915_printfn_error, 181 .arg = e, 182 }; 183 return p; 184 } 185 186 /* single threaded page allocator with a reserved stash for emergencies */ 187 static void pool_fini(struct pagevec *pv) 188 { 189 pagevec_release(pv); 190 } 191 192 static int pool_refill(struct pagevec *pv, gfp_t gfp) 193 { 194 while (pagevec_space(pv)) { 195 struct page *p; 196 197 p = alloc_page(gfp); 198 if (!p) 199 return -ENOMEM; 200 201 pagevec_add(pv, p); 202 } 203 204 return 0; 205 } 206 207 static int pool_init(struct pagevec *pv, gfp_t gfp) 208 { 209 int err; 210 211 pagevec_init(pv); 212 213 err = pool_refill(pv, gfp); 214 if (err) 215 pool_fini(pv); 216 217 return err; 218 } 219 220 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 221 { 222 struct page *p; 223 224 p = alloc_page(gfp); 225 if (!p && pagevec_count(pv)) 226 p = pv->pages[--pv->nr]; 227 228 return p ? page_address(p) : NULL; 229 } 230 231 static void pool_free(struct pagevec *pv, void *addr) 232 { 233 struct page *p = virt_to_page(addr); 234 235 if (pagevec_space(pv)) 236 pagevec_add(pv, p); 237 else 238 __free_page(p); 239 } 240 241 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 242 243 struct i915_vma_compress { 244 struct pagevec pool; 245 struct z_stream_s zstream; 246 void *tmp; 247 }; 248 249 static bool compress_init(struct i915_vma_compress *c) 250 { 251 struct z_stream_s *zstream = &c->zstream; 252 253 if (pool_init(&c->pool, ALLOW_FAIL)) 254 return false; 255 256 zstream->workspace = 257 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 258 ALLOW_FAIL); 259 if (!zstream->workspace) { 260 pool_fini(&c->pool); 261 return false; 262 } 263 264 c->tmp = NULL; 265 if (i915_has_memcpy_from_wc()) 266 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 267 268 return true; 269 } 270 271 static bool compress_start(struct i915_vma_compress *c) 272 { 273 struct z_stream_s *zstream = &c->zstream; 274 void *workspace = zstream->workspace; 275 276 memset(zstream, 0, sizeof(*zstream)); 277 zstream->workspace = workspace; 278 279 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 280 } 281 282 static void *compress_next_page(struct i915_vma_compress *c, 283 struct i915_vma_coredump *dst) 284 { 285 void *page_addr; 286 struct page *page; 287 288 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 289 if (!page_addr) 290 return ERR_PTR(-ENOMEM); 291 292 page = virt_to_page(page_addr); 293 list_add_tail(&page->lru, &dst->page_list); 294 return page_addr; 295 } 296 297 static int compress_page(struct i915_vma_compress *c, 298 void *src, 299 struct i915_vma_coredump *dst, 300 bool wc) 301 { 302 struct z_stream_s *zstream = &c->zstream; 303 304 zstream->next_in = src; 305 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 306 zstream->next_in = c->tmp; 307 zstream->avail_in = PAGE_SIZE; 308 309 do { 310 if (zstream->avail_out == 0) { 311 zstream->next_out = compress_next_page(c, dst); 312 if (IS_ERR(zstream->next_out)) 313 return PTR_ERR(zstream->next_out); 314 315 zstream->avail_out = PAGE_SIZE; 316 } 317 318 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 319 return -EIO; 320 321 cond_resched(); 322 } while (zstream->avail_in); 323 324 /* Fallback to uncompressed if we increase size? */ 325 if (0 && zstream->total_out > zstream->total_in) 326 return -E2BIG; 327 328 return 0; 329 } 330 331 static int compress_flush(struct i915_vma_compress *c, 332 struct i915_vma_coredump *dst) 333 { 334 struct z_stream_s *zstream = &c->zstream; 335 336 do { 337 switch (zlib_deflate(zstream, Z_FINISH)) { 338 case Z_OK: /* more space requested */ 339 zstream->next_out = compress_next_page(c, dst); 340 if (IS_ERR(zstream->next_out)) 341 return PTR_ERR(zstream->next_out); 342 343 zstream->avail_out = PAGE_SIZE; 344 break; 345 346 case Z_STREAM_END: 347 goto end; 348 349 default: /* any error */ 350 return -EIO; 351 } 352 } while (1); 353 354 end: 355 memset(zstream->next_out, 0, zstream->avail_out); 356 dst->unused = zstream->avail_out; 357 return 0; 358 } 359 360 static void compress_finish(struct i915_vma_compress *c) 361 { 362 zlib_deflateEnd(&c->zstream); 363 } 364 365 static void compress_fini(struct i915_vma_compress *c) 366 { 367 kfree(c->zstream.workspace); 368 if (c->tmp) 369 pool_free(&c->pool, c->tmp); 370 pool_fini(&c->pool); 371 } 372 373 static void err_compression_marker(struct drm_i915_error_state_buf *m) 374 { 375 err_puts(m, ":"); 376 } 377 378 #else 379 380 struct i915_vma_compress { 381 struct pagevec pool; 382 }; 383 384 static bool compress_init(struct i915_vma_compress *c) 385 { 386 return pool_init(&c->pool, ALLOW_FAIL) == 0; 387 } 388 389 static bool compress_start(struct i915_vma_compress *c) 390 { 391 return true; 392 } 393 394 static int compress_page(struct i915_vma_compress *c, 395 void *src, 396 struct i915_vma_coredump *dst, 397 bool wc) 398 { 399 void *ptr; 400 401 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 402 if (!ptr) 403 return -ENOMEM; 404 405 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 406 memcpy(ptr, src, PAGE_SIZE); 407 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 408 cond_resched(); 409 410 return 0; 411 } 412 413 static int compress_flush(struct i915_vma_compress *c, 414 struct i915_vma_coredump *dst) 415 { 416 return 0; 417 } 418 419 static void compress_finish(struct i915_vma_compress *c) 420 { 421 } 422 423 static void compress_fini(struct i915_vma_compress *c) 424 { 425 pool_fini(&c->pool); 426 } 427 428 static void err_compression_marker(struct drm_i915_error_state_buf *m) 429 { 430 err_puts(m, "~"); 431 } 432 433 #endif 434 435 static void error_print_instdone(struct drm_i915_error_state_buf *m, 436 const struct intel_engine_coredump *ee) 437 { 438 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 439 int slice; 440 int subslice; 441 int iter; 442 443 err_printf(m, " INSTDONE: 0x%08x\n", 444 ee->instdone.instdone); 445 446 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 447 return; 448 449 err_printf(m, " SC_INSTDONE: 0x%08x\n", 450 ee->instdone.slice_common); 451 452 if (GRAPHICS_VER(m->i915) <= 6) 453 return; 454 455 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) { 456 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 457 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 458 slice, subslice, 459 ee->instdone.sampler[slice][subslice]); 460 461 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 462 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 463 slice, subslice, 464 ee->instdone.row[slice][subslice]); 465 } else { 466 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 467 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 468 slice, subslice, 469 ee->instdone.sampler[slice][subslice]); 470 471 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 472 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 473 slice, subslice, 474 ee->instdone.row[slice][subslice]); 475 } 476 477 if (GRAPHICS_VER(m->i915) < 12) 478 return; 479 480 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 481 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 482 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 483 slice, subslice, 484 ee->instdone.geom_svg[slice][subslice]); 485 } 486 487 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 488 ee->instdone.slice_common_extra[0]); 489 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 490 ee->instdone.slice_common_extra[1]); 491 } 492 493 static void error_print_request(struct drm_i915_error_state_buf *m, 494 const char *prefix, 495 const struct i915_request_coredump *erq) 496 { 497 if (!erq->seqno) 498 return; 499 500 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 501 prefix, erq->pid, erq->context, erq->seqno, 502 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 503 &erq->flags) ? "!" : "", 504 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 505 &erq->flags) ? "+" : "", 506 erq->sched_attr.priority, 507 erq->head, erq->tail); 508 } 509 510 static void error_print_context(struct drm_i915_error_state_buf *m, 511 const char *header, 512 const struct i915_gem_context_coredump *ctx) 513 { 514 const u32 period = to_gt(m->i915)->clock_period_ns; 515 516 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 517 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 518 ctx->guilty, ctx->active, 519 ctx->total_runtime * period, 520 mul_u32_u32(ctx->avg_runtime, period)); 521 } 522 523 static struct i915_vma_coredump * 524 __find_vma(struct i915_vma_coredump *vma, const char *name) 525 { 526 while (vma) { 527 if (strcmp(vma->name, name) == 0) 528 return vma; 529 vma = vma->next; 530 } 531 532 return NULL; 533 } 534 535 static struct i915_vma_coredump * 536 find_batch(const struct intel_engine_coredump *ee) 537 { 538 return __find_vma(ee->vma, "batch"); 539 } 540 541 static void error_print_engine(struct drm_i915_error_state_buf *m, 542 const struct intel_engine_coredump *ee) 543 { 544 struct i915_vma_coredump *batch; 545 int n; 546 547 err_printf(m, "%s command stream:\n", ee->engine->name); 548 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 549 err_printf(m, " START: 0x%08x\n", ee->start); 550 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 551 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 552 ee->tail, ee->rq_post, ee->rq_tail); 553 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 554 err_printf(m, " MODE: 0x%08x\n", ee->mode); 555 err_printf(m, " HWS: 0x%08x\n", ee->hws); 556 err_printf(m, " ACTHD: 0x%08x %08x\n", 557 (u32)(ee->acthd>>32), (u32)ee->acthd); 558 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 559 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 560 err_printf(m, " ESR: 0x%08x\n", ee->esr); 561 562 error_print_instdone(m, ee); 563 564 batch = find_batch(ee); 565 if (batch) { 566 u64 start = batch->gtt_offset; 567 u64 end = start + batch->gtt_size; 568 569 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 570 upper_32_bits(start), lower_32_bits(start), 571 upper_32_bits(end), lower_32_bits(end)); 572 } 573 if (GRAPHICS_VER(m->i915) >= 4) { 574 err_printf(m, " BBADDR: 0x%08x_%08x\n", 575 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 576 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 577 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 578 } 579 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 580 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 581 lower_32_bits(ee->faddr)); 582 if (GRAPHICS_VER(m->i915) >= 6) { 583 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 584 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 585 } 586 if (HAS_PPGTT(m->i915)) { 587 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 588 589 if (GRAPHICS_VER(m->i915) >= 8) { 590 int i; 591 for (i = 0; i < 4; i++) 592 err_printf(m, " PDP%d: 0x%016llx\n", 593 i, ee->vm_info.pdp[i]); 594 } else { 595 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 596 ee->vm_info.pp_dir_base); 597 } 598 } 599 err_printf(m, " hung: %u\n", ee->hung); 600 err_printf(m, " engine reset count: %u\n", ee->reset_count); 601 602 for (n = 0; n < ee->num_ports; n++) { 603 err_printf(m, " ELSP[%d]:", n); 604 error_print_request(m, " ", &ee->execlist[n]); 605 } 606 607 error_print_context(m, " Active context: ", &ee->context); 608 } 609 610 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 611 { 612 va_list args; 613 614 va_start(args, f); 615 i915_error_vprintf(e, f, args); 616 va_end(args); 617 } 618 619 static void print_error_vma(struct drm_i915_error_state_buf *m, 620 const struct intel_engine_cs *engine, 621 const struct i915_vma_coredump *vma) 622 { 623 char out[ASCII85_BUFSZ]; 624 struct page *page; 625 626 if (!vma) 627 return; 628 629 err_printf(m, "%s --- %s = 0x%08x %08x\n", 630 engine ? engine->name : "global", vma->name, 631 upper_32_bits(vma->gtt_offset), 632 lower_32_bits(vma->gtt_offset)); 633 634 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 635 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 636 637 err_compression_marker(m); 638 list_for_each_entry(page, &vma->page_list, lru) { 639 int i, len; 640 const u32 *addr = page_address(page); 641 642 len = PAGE_SIZE; 643 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 644 len -= vma->unused; 645 len = ascii85_encode_len(len); 646 647 for (i = 0; i < len; i++) 648 err_puts(m, ascii85_encode(addr[i], out)); 649 } 650 err_puts(m, "\n"); 651 } 652 653 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 654 struct i915_gpu_coredump *error) 655 { 656 struct drm_printer p = i915_error_printer(m); 657 658 intel_device_info_print_static(&error->device_info, &p); 659 intel_device_info_print_runtime(&error->runtime_info, &p); 660 intel_driver_caps_print(&error->driver_caps, &p); 661 } 662 663 static void err_print_params(struct drm_i915_error_state_buf *m, 664 const struct i915_params *params) 665 { 666 struct drm_printer p = i915_error_printer(m); 667 668 i915_params_dump(params, &p); 669 } 670 671 static void err_print_pciid(struct drm_i915_error_state_buf *m, 672 struct drm_i915_private *i915) 673 { 674 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 675 676 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 677 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 678 err_printf(m, "PCI Subsystem: %04x:%04x\n", 679 pdev->subsystem_vendor, 680 pdev->subsystem_device); 681 } 682 683 static void err_print_uc(struct drm_i915_error_state_buf *m, 684 const struct intel_uc_coredump *error_uc) 685 { 686 struct drm_printer p = i915_error_printer(m); 687 688 intel_uc_fw_dump(&error_uc->guc_fw, &p); 689 intel_uc_fw_dump(&error_uc->huc_fw, &p); 690 print_error_vma(m, NULL, error_uc->guc_log); 691 } 692 693 static void err_free_sgl(struct scatterlist *sgl) 694 { 695 while (sgl) { 696 struct scatterlist *sg; 697 698 for (sg = sgl; !sg_is_chain(sg); sg++) { 699 kfree(sg_virt(sg)); 700 if (sg_is_last(sg)) 701 break; 702 } 703 704 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 705 free_page((unsigned long)sgl); 706 sgl = sg; 707 } 708 } 709 710 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 711 struct intel_gt_coredump *gt) 712 { 713 struct drm_printer p = i915_error_printer(m); 714 715 intel_gt_info_print(>->info, &p); 716 intel_sseu_print_topology(>->info.sseu, &p); 717 } 718 719 static void err_print_gt(struct drm_i915_error_state_buf *m, 720 struct intel_gt_coredump *gt) 721 { 722 const struct intel_engine_coredump *ee; 723 int i; 724 725 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 726 err_printf(m, "EIR: 0x%08x\n", gt->eir); 727 err_printf(m, "IER: 0x%08x\n", gt->ier); 728 for (i = 0; i < gt->ngtier; i++) 729 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 730 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 731 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 732 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 733 734 for (i = 0; i < gt->nfence; i++) 735 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 736 737 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 738 err_printf(m, "ERROR: 0x%08x\n", gt->error); 739 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 740 } 741 742 if (GRAPHICS_VER(m->i915) >= 8) 743 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 744 gt->fault_data1, gt->fault_data0); 745 746 if (GRAPHICS_VER(m->i915) == 7) 747 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 748 749 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 750 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 751 752 if (GRAPHICS_VER(m->i915) == 12) 753 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 754 755 if (GRAPHICS_VER(m->i915) >= 12) { 756 int i; 757 758 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 759 /* 760 * SFC_DONE resides in the VD forcewake domain, so it 761 * only exists if the corresponding VCS engine is 762 * present. 763 */ 764 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 765 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 766 continue; 767 768 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 769 gt->sfc_done[i]); 770 } 771 772 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 773 } 774 775 for (ee = gt->engine; ee; ee = ee->next) { 776 const struct i915_vma_coredump *vma; 777 778 error_print_engine(m, ee); 779 for (vma = ee->vma; vma; vma = vma->next) 780 print_error_vma(m, ee->engine, vma); 781 } 782 783 if (gt->uc) 784 err_print_uc(m, gt->uc); 785 786 err_print_gt_info(m, gt); 787 } 788 789 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 790 struct i915_gpu_coredump *error) 791 { 792 const struct intel_engine_coredump *ee; 793 struct timespec64 ts; 794 795 if (*error->error_msg) 796 err_printf(m, "%s\n", error->error_msg); 797 err_printf(m, "Kernel: %s %s\n", 798 init_utsname()->release, 799 init_utsname()->machine); 800 err_printf(m, "Driver: %s\n", DRIVER_DATE); 801 ts = ktime_to_timespec64(error->time); 802 err_printf(m, "Time: %lld s %ld us\n", 803 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 804 ts = ktime_to_timespec64(error->boottime); 805 err_printf(m, "Boottime: %lld s %ld us\n", 806 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 807 ts = ktime_to_timespec64(error->uptime); 808 err_printf(m, "Uptime: %lld s %ld us\n", 809 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 810 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 811 error->capture, jiffies_to_msecs(jiffies - error->capture)); 812 813 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 814 err_printf(m, "Active process (on ring %s): %s [%d]\n", 815 ee->engine->name, 816 ee->context.comm, 817 ee->context.pid); 818 819 err_printf(m, "Reset count: %u\n", error->reset_count); 820 err_printf(m, "Suspend count: %u\n", error->suspend_count); 821 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 822 err_printf(m, "Subplatform: 0x%x\n", 823 intel_subplatform(&error->runtime_info, 824 error->device_info.platform)); 825 err_print_pciid(m, m->i915); 826 827 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 828 829 intel_dmc_print_error_state(m, m->i915); 830 831 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 832 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 833 834 if (error->gt) 835 err_print_gt(m, error->gt); 836 837 if (error->overlay) 838 intel_overlay_print_error_state(m, error->overlay); 839 840 err_print_capabilities(m, error); 841 err_print_params(m, &error->params); 842 } 843 844 static int err_print_to_sgl(struct i915_gpu_coredump *error) 845 { 846 struct drm_i915_error_state_buf m; 847 848 if (IS_ERR(error)) 849 return PTR_ERR(error); 850 851 if (READ_ONCE(error->sgl)) 852 return 0; 853 854 memset(&m, 0, sizeof(m)); 855 m.i915 = error->i915; 856 857 __err_print_to_sgl(&m, error); 858 859 if (m.buf) { 860 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 861 m.bytes = 0; 862 m.buf = NULL; 863 } 864 if (m.cur) { 865 GEM_BUG_ON(m.end < m.cur); 866 sg_mark_end(m.cur - 1); 867 } 868 GEM_BUG_ON(m.sgl && !m.cur); 869 870 if (m.err) { 871 err_free_sgl(m.sgl); 872 return m.err; 873 } 874 875 if (cmpxchg(&error->sgl, NULL, m.sgl)) 876 err_free_sgl(m.sgl); 877 878 return 0; 879 } 880 881 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 882 char *buf, loff_t off, size_t rem) 883 { 884 struct scatterlist *sg; 885 size_t count; 886 loff_t pos; 887 int err; 888 889 if (!error || !rem) 890 return 0; 891 892 err = err_print_to_sgl(error); 893 if (err) 894 return err; 895 896 sg = READ_ONCE(error->fit); 897 if (!sg || off < sg->dma_address) 898 sg = error->sgl; 899 if (!sg) 900 return 0; 901 902 pos = sg->dma_address; 903 count = 0; 904 do { 905 size_t len, start; 906 907 if (sg_is_chain(sg)) { 908 sg = sg_chain_ptr(sg); 909 GEM_BUG_ON(sg_is_chain(sg)); 910 } 911 912 len = sg->length; 913 if (pos + len <= off) { 914 pos += len; 915 continue; 916 } 917 918 start = sg->offset; 919 if (pos < off) { 920 GEM_BUG_ON(off - pos > len); 921 len -= off - pos; 922 start += off - pos; 923 pos = off; 924 } 925 926 len = min(len, rem); 927 GEM_BUG_ON(!len || len > sg->length); 928 929 memcpy(buf, page_address(sg_page(sg)) + start, len); 930 931 count += len; 932 pos += len; 933 934 buf += len; 935 rem -= len; 936 if (!rem) { 937 WRITE_ONCE(error->fit, sg); 938 break; 939 } 940 } while (!sg_is_last(sg++)); 941 942 return count; 943 } 944 945 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 946 { 947 while (vma) { 948 struct i915_vma_coredump *next = vma->next; 949 struct page *page, *n; 950 951 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 952 list_del_init(&page->lru); 953 __free_page(page); 954 } 955 956 kfree(vma); 957 vma = next; 958 } 959 } 960 961 static void cleanup_params(struct i915_gpu_coredump *error) 962 { 963 i915_params_free(&error->params); 964 } 965 966 static void cleanup_uc(struct intel_uc_coredump *uc) 967 { 968 kfree(uc->guc_fw.path); 969 kfree(uc->huc_fw.path); 970 i915_vma_coredump_free(uc->guc_log); 971 972 kfree(uc); 973 } 974 975 static void cleanup_gt(struct intel_gt_coredump *gt) 976 { 977 while (gt->engine) { 978 struct intel_engine_coredump *ee = gt->engine; 979 980 gt->engine = ee->next; 981 982 i915_vma_coredump_free(ee->vma); 983 kfree(ee); 984 } 985 986 if (gt->uc) 987 cleanup_uc(gt->uc); 988 989 kfree(gt); 990 } 991 992 void __i915_gpu_coredump_free(struct kref *error_ref) 993 { 994 struct i915_gpu_coredump *error = 995 container_of(error_ref, typeof(*error), ref); 996 997 while (error->gt) { 998 struct intel_gt_coredump *gt = error->gt; 999 1000 error->gt = gt->next; 1001 cleanup_gt(gt); 1002 } 1003 1004 kfree(error->overlay); 1005 1006 cleanup_params(error); 1007 1008 err_free_sgl(error->sgl); 1009 kfree(error); 1010 } 1011 1012 static struct i915_vma_coredump * 1013 i915_vma_coredump_create(const struct intel_gt *gt, 1014 const struct i915_vma_resource *vma_res, 1015 struct i915_vma_compress *compress, 1016 const char *name) 1017 1018 { 1019 struct i915_ggtt *ggtt = gt->ggtt; 1020 const u64 slot = ggtt->error_capture.start; 1021 struct i915_vma_coredump *dst; 1022 struct sgt_iter iter; 1023 int ret; 1024 1025 might_sleep(); 1026 1027 if (!vma_res || !vma_res->bi.pages || !compress) 1028 return NULL; 1029 1030 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1031 if (!dst) 1032 return NULL; 1033 1034 if (!compress_start(compress)) { 1035 kfree(dst); 1036 return NULL; 1037 } 1038 1039 INIT_LIST_HEAD(&dst->page_list); 1040 strcpy(dst->name, name); 1041 dst->next = NULL; 1042 1043 dst->gtt_offset = vma_res->start; 1044 dst->gtt_size = vma_res->node_size; 1045 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1046 dst->unused = 0; 1047 1048 ret = -EINVAL; 1049 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1050 void __iomem *s; 1051 dma_addr_t dma; 1052 1053 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1054 mutex_lock(&ggtt->error_mutex); 1055 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1056 I915_CACHE_NONE, 0); 1057 mb(); 1058 1059 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1060 ret = compress_page(compress, 1061 (void __force *)s, dst, 1062 true); 1063 io_mapping_unmap(s); 1064 1065 mb(); 1066 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1067 mutex_unlock(&ggtt->error_mutex); 1068 if (ret) 1069 break; 1070 } 1071 } else if (vma_res->bi.lmem) { 1072 struct intel_memory_region *mem = vma_res->mr; 1073 dma_addr_t dma; 1074 1075 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1076 void __iomem *s; 1077 1078 s = io_mapping_map_wc(&mem->iomap, 1079 dma - mem->region.start, 1080 PAGE_SIZE); 1081 ret = compress_page(compress, 1082 (void __force *)s, dst, 1083 true); 1084 io_mapping_unmap(s); 1085 if (ret) 1086 break; 1087 } 1088 } else { 1089 struct page *page; 1090 1091 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1092 void *s; 1093 1094 drm_clflush_pages(&page, 1); 1095 1096 s = kmap(page); 1097 ret = compress_page(compress, s, dst, false); 1098 kunmap(page); 1099 1100 drm_clflush_pages(&page, 1); 1101 1102 if (ret) 1103 break; 1104 } 1105 } 1106 1107 if (ret || compress_flush(compress, dst)) { 1108 struct page *page, *n; 1109 1110 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1111 list_del_init(&page->lru); 1112 pool_free(&compress->pool, page_address(page)); 1113 } 1114 1115 kfree(dst); 1116 dst = NULL; 1117 } 1118 compress_finish(compress); 1119 1120 return dst; 1121 } 1122 1123 static void gt_record_fences(struct intel_gt_coredump *gt) 1124 { 1125 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1126 struct intel_uncore *uncore = gt->_gt->uncore; 1127 int i; 1128 1129 if (GRAPHICS_VER(uncore->i915) >= 6) { 1130 for (i = 0; i < ggtt->num_fences; i++) 1131 gt->fence[i] = 1132 intel_uncore_read64(uncore, 1133 FENCE_REG_GEN6_LO(i)); 1134 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1135 for (i = 0; i < ggtt->num_fences; i++) 1136 gt->fence[i] = 1137 intel_uncore_read64(uncore, 1138 FENCE_REG_965_LO(i)); 1139 } else { 1140 for (i = 0; i < ggtt->num_fences; i++) 1141 gt->fence[i] = 1142 intel_uncore_read(uncore, FENCE_REG(i)); 1143 } 1144 gt->nfence = i; 1145 } 1146 1147 static void engine_record_registers(struct intel_engine_coredump *ee) 1148 { 1149 const struct intel_engine_cs *engine = ee->engine; 1150 struct drm_i915_private *i915 = engine->i915; 1151 1152 if (GRAPHICS_VER(i915) >= 6) { 1153 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1154 1155 if (GRAPHICS_VER(i915) >= 12) 1156 ee->fault_reg = intel_uncore_read(engine->uncore, 1157 GEN12_RING_FAULT_REG); 1158 else if (GRAPHICS_VER(i915) >= 8) 1159 ee->fault_reg = intel_uncore_read(engine->uncore, 1160 GEN8_RING_FAULT_REG); 1161 else 1162 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1163 } 1164 1165 if (GRAPHICS_VER(i915) >= 4) { 1166 ee->esr = ENGINE_READ(engine, RING_ESR); 1167 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1168 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1169 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1170 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1171 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1172 ee->ccid = ENGINE_READ(engine, CCID); 1173 if (GRAPHICS_VER(i915) >= 8) { 1174 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1175 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1176 } 1177 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1178 } else { 1179 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1180 ee->ipeir = ENGINE_READ(engine, IPEIR); 1181 ee->ipehr = ENGINE_READ(engine, IPEHR); 1182 } 1183 1184 intel_engine_get_instdone(engine, &ee->instdone); 1185 1186 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1187 ee->acthd = intel_engine_get_active_head(engine); 1188 ee->start = ENGINE_READ(engine, RING_START); 1189 ee->head = ENGINE_READ(engine, RING_HEAD); 1190 ee->tail = ENGINE_READ(engine, RING_TAIL); 1191 ee->ctl = ENGINE_READ(engine, RING_CTL); 1192 if (GRAPHICS_VER(i915) > 2) 1193 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1194 1195 if (!HWS_NEEDS_PHYSICAL(i915)) { 1196 i915_reg_t mmio; 1197 1198 if (GRAPHICS_VER(i915) == 7) { 1199 switch (engine->id) { 1200 default: 1201 MISSING_CASE(engine->id); 1202 fallthrough; 1203 case RCS0: 1204 mmio = RENDER_HWS_PGA_GEN7; 1205 break; 1206 case BCS0: 1207 mmio = BLT_HWS_PGA_GEN7; 1208 break; 1209 case VCS0: 1210 mmio = BSD_HWS_PGA_GEN7; 1211 break; 1212 case VECS0: 1213 mmio = VEBOX_HWS_PGA_GEN7; 1214 break; 1215 } 1216 } else if (GRAPHICS_VER(engine->i915) == 6) { 1217 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1218 } else { 1219 /* XXX: gen8 returns to sanity */ 1220 mmio = RING_HWS_PGA(engine->mmio_base); 1221 } 1222 1223 ee->hws = intel_uncore_read(engine->uncore, mmio); 1224 } 1225 1226 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1227 1228 if (HAS_PPGTT(i915)) { 1229 int i; 1230 1231 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1232 1233 if (GRAPHICS_VER(i915) == 6) { 1234 ee->vm_info.pp_dir_base = 1235 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1236 } else if (GRAPHICS_VER(i915) == 7) { 1237 ee->vm_info.pp_dir_base = 1238 ENGINE_READ(engine, RING_PP_DIR_BASE); 1239 } else if (GRAPHICS_VER(i915) >= 8) { 1240 u32 base = engine->mmio_base; 1241 1242 for (i = 0; i < 4; i++) { 1243 ee->vm_info.pdp[i] = 1244 intel_uncore_read(engine->uncore, 1245 GEN8_RING_PDP_UDW(base, i)); 1246 ee->vm_info.pdp[i] <<= 32; 1247 ee->vm_info.pdp[i] |= 1248 intel_uncore_read(engine->uncore, 1249 GEN8_RING_PDP_LDW(base, i)); 1250 } 1251 } 1252 } 1253 } 1254 1255 static void record_request(const struct i915_request *request, 1256 struct i915_request_coredump *erq) 1257 { 1258 erq->flags = request->fence.flags; 1259 erq->context = request->fence.context; 1260 erq->seqno = request->fence.seqno; 1261 erq->sched_attr = request->sched.attr; 1262 erq->head = request->head; 1263 erq->tail = request->tail; 1264 1265 erq->pid = 0; 1266 rcu_read_lock(); 1267 if (!intel_context_is_closed(request->context)) { 1268 const struct i915_gem_context *ctx; 1269 1270 ctx = rcu_dereference(request->context->gem_context); 1271 if (ctx) 1272 erq->pid = pid_nr(ctx->pid); 1273 } 1274 rcu_read_unlock(); 1275 } 1276 1277 static void engine_record_execlists(struct intel_engine_coredump *ee) 1278 { 1279 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1280 struct i915_request * const *port = el->active; 1281 unsigned int n = 0; 1282 1283 while (*port) 1284 record_request(*port++, &ee->execlist[n++]); 1285 1286 ee->num_ports = n; 1287 } 1288 1289 static bool record_context(struct i915_gem_context_coredump *e, 1290 const struct i915_request *rq) 1291 { 1292 struct i915_gem_context *ctx; 1293 struct task_struct *task; 1294 bool simulated; 1295 1296 rcu_read_lock(); 1297 ctx = rcu_dereference(rq->context->gem_context); 1298 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1299 ctx = NULL; 1300 rcu_read_unlock(); 1301 if (!ctx) 1302 return true; 1303 1304 rcu_read_lock(); 1305 task = pid_task(ctx->pid, PIDTYPE_PID); 1306 if (task) { 1307 strcpy(e->comm, task->comm); 1308 e->pid = task->pid; 1309 } 1310 rcu_read_unlock(); 1311 1312 e->sched_attr = ctx->sched; 1313 e->guilty = atomic_read(&ctx->guilty_count); 1314 e->active = atomic_read(&ctx->active_count); 1315 1316 e->total_runtime = rq->context->runtime.total; 1317 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1318 1319 simulated = i915_gem_context_no_error_capture(ctx); 1320 1321 i915_gem_context_put(ctx); 1322 return simulated; 1323 } 1324 1325 struct intel_engine_capture_vma { 1326 struct intel_engine_capture_vma *next; 1327 struct i915_vma_resource *vma_res; 1328 char name[16]; 1329 bool lockdep_cookie; 1330 }; 1331 1332 static struct intel_engine_capture_vma * 1333 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1334 struct i915_vma_resource *vma_res, 1335 gfp_t gfp, const char *name) 1336 { 1337 struct intel_engine_capture_vma *c; 1338 1339 if (!vma_res) 1340 return next; 1341 1342 c = kmalloc(sizeof(*c), gfp); 1343 if (!c) 1344 return next; 1345 1346 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1347 kfree(c); 1348 return next; 1349 } 1350 1351 strcpy(c->name, name); 1352 c->vma_res = i915_vma_resource_get(vma_res); 1353 1354 c->next = next; 1355 return c; 1356 } 1357 1358 static struct intel_engine_capture_vma * 1359 capture_vma(struct intel_engine_capture_vma *next, 1360 struct i915_vma *vma, 1361 const char *name, 1362 gfp_t gfp) 1363 { 1364 if (!vma) 1365 return next; 1366 1367 /* 1368 * If the vma isn't pinned, then the vma should be snapshotted 1369 * to a struct i915_vma_snapshot at command submission time. 1370 * Not here. 1371 */ 1372 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1373 return next; 1374 1375 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1376 1377 return next; 1378 } 1379 1380 static struct intel_engine_capture_vma * 1381 capture_user(struct intel_engine_capture_vma *capture, 1382 const struct i915_request *rq, 1383 gfp_t gfp) 1384 { 1385 struct i915_capture_list *c; 1386 1387 for (c = rq->capture_list; c; c = c->next) 1388 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1389 "user"); 1390 1391 return capture; 1392 } 1393 1394 static void add_vma(struct intel_engine_coredump *ee, 1395 struct i915_vma_coredump *vma) 1396 { 1397 if (vma) { 1398 vma->next = ee->vma; 1399 ee->vma = vma; 1400 } 1401 } 1402 1403 static struct i915_vma_coredump * 1404 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1405 const char *name, struct i915_vma_compress *compress) 1406 { 1407 struct i915_vma_coredump *ret = NULL; 1408 struct i915_vma_resource *vma_res; 1409 bool lockdep_cookie; 1410 1411 if (!vma) 1412 return NULL; 1413 1414 vma_res = vma->resource; 1415 1416 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1417 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1418 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1419 } 1420 1421 return ret; 1422 } 1423 1424 static void add_vma_coredump(struct intel_engine_coredump *ee, 1425 const struct intel_gt *gt, 1426 struct i915_vma *vma, 1427 const char *name, 1428 struct i915_vma_compress *compress) 1429 { 1430 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1431 } 1432 1433 struct intel_engine_coredump * 1434 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1435 { 1436 struct intel_engine_coredump *ee; 1437 1438 ee = kzalloc(sizeof(*ee), gfp); 1439 if (!ee) 1440 return NULL; 1441 1442 ee->engine = engine; 1443 1444 engine_record_registers(ee); 1445 engine_record_execlists(ee); 1446 1447 return ee; 1448 } 1449 1450 struct intel_engine_capture_vma * 1451 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1452 struct i915_request *rq, 1453 gfp_t gfp) 1454 { 1455 struct intel_engine_capture_vma *vma = NULL; 1456 1457 ee->simulated |= record_context(&ee->context, rq); 1458 if (ee->simulated) 1459 return NULL; 1460 1461 /* 1462 * We need to copy these to an anonymous buffer 1463 * as the simplest method to avoid being overwritten 1464 * by userspace. 1465 */ 1466 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1467 vma = capture_user(vma, rq, gfp); 1468 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1469 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1470 1471 ee->rq_head = rq->head; 1472 ee->rq_post = rq->postfix; 1473 ee->rq_tail = rq->tail; 1474 1475 return vma; 1476 } 1477 1478 void 1479 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1480 struct intel_engine_capture_vma *capture, 1481 struct i915_vma_compress *compress) 1482 { 1483 const struct intel_engine_cs *engine = ee->engine; 1484 1485 while (capture) { 1486 struct intel_engine_capture_vma *this = capture; 1487 struct i915_vma_resource *vma_res = this->vma_res; 1488 1489 add_vma(ee, 1490 i915_vma_coredump_create(engine->gt, vma_res, 1491 compress, this->name)); 1492 1493 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1494 i915_vma_resource_put(vma_res); 1495 1496 capture = this->next; 1497 kfree(this); 1498 } 1499 1500 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1501 "HW Status", compress); 1502 1503 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1504 "WA context", compress); 1505 } 1506 1507 static struct intel_engine_coredump * 1508 capture_engine(struct intel_engine_cs *engine, 1509 struct i915_vma_compress *compress) 1510 { 1511 struct intel_engine_capture_vma *capture = NULL; 1512 struct intel_engine_coredump *ee; 1513 struct intel_context *ce; 1514 struct i915_request *rq = NULL; 1515 unsigned long flags; 1516 1517 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL); 1518 if (!ee) 1519 return NULL; 1520 1521 ce = intel_engine_get_hung_context(engine); 1522 if (ce) { 1523 intel_engine_clear_hung_context(engine); 1524 rq = intel_context_find_active_request(ce); 1525 if (!rq || !i915_request_started(rq)) 1526 goto no_request_capture; 1527 } else { 1528 /* 1529 * Getting here with GuC enabled means it is a forced error capture 1530 * with no actual hang. So, no need to attempt the execlist search. 1531 */ 1532 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1533 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1534 rq = intel_engine_execlist_find_hung_request(engine); 1535 spin_unlock_irqrestore(&engine->sched_engine->lock, 1536 flags); 1537 } 1538 } 1539 if (rq) 1540 rq = i915_request_get_rcu(rq); 1541 1542 if (!rq) 1543 goto no_request_capture; 1544 1545 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1546 if (!capture) { 1547 i915_request_put(rq); 1548 goto no_request_capture; 1549 } 1550 1551 intel_engine_coredump_add_vma(ee, capture, compress); 1552 i915_request_put(rq); 1553 1554 return ee; 1555 1556 no_request_capture: 1557 kfree(ee); 1558 return NULL; 1559 } 1560 1561 static void 1562 gt_record_engines(struct intel_gt_coredump *gt, 1563 intel_engine_mask_t engine_mask, 1564 struct i915_vma_compress *compress) 1565 { 1566 struct intel_engine_cs *engine; 1567 enum intel_engine_id id; 1568 1569 for_each_engine(engine, gt->_gt, id) { 1570 struct intel_engine_coredump *ee; 1571 1572 /* Refill our page pool before entering atomic section */ 1573 pool_refill(&compress->pool, ALLOW_FAIL); 1574 1575 ee = capture_engine(engine, compress); 1576 if (!ee) 1577 continue; 1578 1579 ee->hung = engine->mask & engine_mask; 1580 1581 gt->simulated |= ee->simulated; 1582 if (ee->simulated) { 1583 kfree(ee); 1584 continue; 1585 } 1586 1587 ee->next = gt->engine; 1588 gt->engine = ee; 1589 } 1590 } 1591 1592 static struct intel_uc_coredump * 1593 gt_record_uc(struct intel_gt_coredump *gt, 1594 struct i915_vma_compress *compress) 1595 { 1596 const struct intel_uc *uc = >->_gt->uc; 1597 struct intel_uc_coredump *error_uc; 1598 1599 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1600 if (!error_uc) 1601 return NULL; 1602 1603 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1604 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1605 1606 /* Non-default firmware paths will be specified by the modparam. 1607 * As modparams are generally accesible from the userspace make 1608 * explicit copies of the firmware paths. 1609 */ 1610 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1611 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1612 error_uc->guc_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1613 "GuC log buffer", compress); 1614 1615 return error_uc; 1616 } 1617 1618 /* Capture all registers which don't fit into another category. */ 1619 static void gt_record_regs(struct intel_gt_coredump *gt) 1620 { 1621 struct intel_uncore *uncore = gt->_gt->uncore; 1622 struct drm_i915_private *i915 = uncore->i915; 1623 int i; 1624 1625 /* 1626 * General organization 1627 * 1. Registers specific to a single generation 1628 * 2. Registers which belong to multiple generations 1629 * 3. Feature specific registers. 1630 * 4. Everything else 1631 * Please try to follow the order. 1632 */ 1633 1634 /* 1: Registers specific to a single generation */ 1635 if (IS_VALLEYVIEW(i915)) { 1636 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1637 gt->ier = intel_uncore_read(uncore, VLV_IER); 1638 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1639 } 1640 1641 if (GRAPHICS_VER(i915) == 7) 1642 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1643 1644 if (GRAPHICS_VER(i915) >= 12) { 1645 gt->fault_data0 = intel_uncore_read(uncore, 1646 GEN12_FAULT_TLB_DATA0); 1647 gt->fault_data1 = intel_uncore_read(uncore, 1648 GEN12_FAULT_TLB_DATA1); 1649 } else if (GRAPHICS_VER(i915) >= 8) { 1650 gt->fault_data0 = intel_uncore_read(uncore, 1651 GEN8_FAULT_TLB_DATA0); 1652 gt->fault_data1 = intel_uncore_read(uncore, 1653 GEN8_FAULT_TLB_DATA1); 1654 } 1655 1656 if (GRAPHICS_VER(i915) == 6) { 1657 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1658 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1659 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1660 } 1661 1662 /* 2: Registers which belong to multiple generations */ 1663 if (GRAPHICS_VER(i915) >= 7) 1664 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1665 1666 if (GRAPHICS_VER(i915) >= 6) { 1667 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1668 if (GRAPHICS_VER(i915) < 12) { 1669 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1670 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1671 } 1672 } 1673 1674 /* 3: Feature specific registers */ 1675 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1676 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1677 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1678 } 1679 1680 if (IS_GRAPHICS_VER(i915, 8, 11)) 1681 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1682 1683 if (GRAPHICS_VER(i915) == 12) 1684 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1685 1686 if (GRAPHICS_VER(i915) >= 12) { 1687 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1688 /* 1689 * SFC_DONE resides in the VD forcewake domain, so it 1690 * only exists if the corresponding VCS engine is 1691 * present. 1692 */ 1693 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1694 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1695 continue; 1696 1697 gt->sfc_done[i] = 1698 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1699 } 1700 1701 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1702 } 1703 1704 /* 4: Everything else */ 1705 if (GRAPHICS_VER(i915) >= 11) { 1706 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1707 gt->gtier[0] = 1708 intel_uncore_read(uncore, 1709 GEN11_RENDER_COPY_INTR_ENABLE); 1710 gt->gtier[1] = 1711 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1712 gt->gtier[2] = 1713 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1714 gt->gtier[3] = 1715 intel_uncore_read(uncore, 1716 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1717 gt->gtier[4] = 1718 intel_uncore_read(uncore, 1719 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1720 gt->gtier[5] = 1721 intel_uncore_read(uncore, 1722 GEN11_GUNIT_CSME_INTR_ENABLE); 1723 gt->ngtier = 6; 1724 } else if (GRAPHICS_VER(i915) >= 8) { 1725 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1726 for (i = 0; i < 4; i++) 1727 gt->gtier[i] = 1728 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1729 gt->ngtier = 4; 1730 } else if (HAS_PCH_SPLIT(i915)) { 1731 gt->ier = intel_uncore_read(uncore, DEIER); 1732 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1733 gt->ngtier = 1; 1734 } else if (GRAPHICS_VER(i915) == 2) { 1735 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1736 } else if (!IS_VALLEYVIEW(i915)) { 1737 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1738 } 1739 gt->eir = intel_uncore_read(uncore, EIR); 1740 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1741 } 1742 1743 static void gt_record_info(struct intel_gt_coredump *gt) 1744 { 1745 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1746 } 1747 1748 /* 1749 * Generate a semi-unique error code. The code is not meant to have meaning, The 1750 * code's only purpose is to try to prevent false duplicated bug reports by 1751 * grossly estimating a GPU error state. 1752 * 1753 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1754 * the hang if we could strip the GTT offset information from it. 1755 * 1756 * It's only a small step better than a random number in its current form. 1757 */ 1758 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1759 { 1760 /* 1761 * IPEHR would be an ideal way to detect errors, as it's the gross 1762 * measure of "the command that hung." However, has some very common 1763 * synchronization commands which almost always appear in the case 1764 * strictly a client bug. Use instdone to differentiate those some. 1765 */ 1766 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1767 } 1768 1769 static const char *error_msg(struct i915_gpu_coredump *error) 1770 { 1771 struct intel_engine_coredump *first = NULL; 1772 unsigned int hung_classes = 0; 1773 struct intel_gt_coredump *gt; 1774 int len; 1775 1776 for (gt = error->gt; gt; gt = gt->next) { 1777 struct intel_engine_coredump *cs; 1778 1779 for (cs = gt->engine; cs; cs = cs->next) { 1780 if (cs->hung) { 1781 hung_classes |= BIT(cs->engine->uabi_class); 1782 if (!first) 1783 first = cs; 1784 } 1785 } 1786 } 1787 1788 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1789 "GPU HANG: ecode %d:%x:%08x", 1790 GRAPHICS_VER(error->i915), hung_classes, 1791 generate_ecode(first)); 1792 if (first && first->context.pid) { 1793 /* Just show the first executing process, more is confusing */ 1794 len += scnprintf(error->error_msg + len, 1795 sizeof(error->error_msg) - len, 1796 ", in %s [%d]", 1797 first->context.comm, first->context.pid); 1798 } 1799 1800 return error->error_msg; 1801 } 1802 1803 static void capture_gen(struct i915_gpu_coredump *error) 1804 { 1805 struct drm_i915_private *i915 = error->i915; 1806 1807 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1808 error->suspended = i915->runtime_pm.suspended; 1809 1810 error->iommu = i915_vtd_active(i915); 1811 error->reset_count = i915_reset_count(&i915->gpu_error); 1812 error->suspend_count = i915->suspend_count; 1813 1814 i915_params_copy(&error->params, &i915->params); 1815 memcpy(&error->device_info, 1816 INTEL_INFO(i915), 1817 sizeof(error->device_info)); 1818 memcpy(&error->runtime_info, 1819 RUNTIME_INFO(i915), 1820 sizeof(error->runtime_info)); 1821 error->driver_caps = i915->caps; 1822 } 1823 1824 struct i915_gpu_coredump * 1825 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1826 { 1827 struct i915_gpu_coredump *error; 1828 1829 if (!i915->params.error_capture) 1830 return NULL; 1831 1832 error = kzalloc(sizeof(*error), gfp); 1833 if (!error) 1834 return NULL; 1835 1836 kref_init(&error->ref); 1837 error->i915 = i915; 1838 1839 error->time = ktime_get_real(); 1840 error->boottime = ktime_get_boottime(); 1841 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1842 error->capture = jiffies; 1843 1844 capture_gen(error); 1845 1846 return error; 1847 } 1848 1849 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1850 1851 struct intel_gt_coredump * 1852 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1853 { 1854 struct intel_gt_coredump *gc; 1855 1856 gc = kzalloc(sizeof(*gc), gfp); 1857 if (!gc) 1858 return NULL; 1859 1860 gc->_gt = gt; 1861 gc->awake = intel_gt_pm_is_awake(gt); 1862 1863 gt_record_regs(gc); 1864 gt_record_fences(gc); 1865 1866 return gc; 1867 } 1868 1869 struct i915_vma_compress * 1870 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1871 { 1872 struct i915_vma_compress *compress; 1873 1874 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1875 if (!compress) 1876 return NULL; 1877 1878 if (!compress_init(compress)) { 1879 kfree(compress); 1880 return NULL; 1881 } 1882 1883 return compress; 1884 } 1885 1886 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1887 struct i915_vma_compress *compress) 1888 { 1889 if (!compress) 1890 return; 1891 1892 compress_fini(compress); 1893 kfree(compress); 1894 } 1895 1896 static struct i915_gpu_coredump * 1897 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1898 { 1899 struct drm_i915_private *i915 = gt->i915; 1900 struct i915_gpu_coredump *error; 1901 1902 /* Check if GPU capture has been disabled */ 1903 error = READ_ONCE(i915->gpu_error.first_error); 1904 if (IS_ERR(error)) 1905 return error; 1906 1907 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1908 if (!error) 1909 return ERR_PTR(-ENOMEM); 1910 1911 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL); 1912 if (error->gt) { 1913 struct i915_vma_compress *compress; 1914 1915 compress = i915_vma_capture_prepare(error->gt); 1916 if (!compress) { 1917 kfree(error->gt); 1918 kfree(error); 1919 return ERR_PTR(-ENOMEM); 1920 } 1921 1922 gt_record_info(error->gt); 1923 gt_record_engines(error->gt, engine_mask, compress); 1924 1925 if (INTEL_INFO(i915)->has_gt_uc) 1926 error->gt->uc = gt_record_uc(error->gt, compress); 1927 1928 i915_vma_capture_finish(error->gt, compress); 1929 1930 error->simulated |= error->gt->simulated; 1931 } 1932 1933 error->overlay = intel_overlay_capture_error_state(i915); 1934 1935 return error; 1936 } 1937 1938 struct i915_gpu_coredump * 1939 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1940 { 1941 static DEFINE_MUTEX(capture_mutex); 1942 int ret = mutex_lock_interruptible(&capture_mutex); 1943 struct i915_gpu_coredump *dump; 1944 1945 if (ret) 1946 return ERR_PTR(ret); 1947 1948 dump = __i915_gpu_coredump(gt, engine_mask); 1949 mutex_unlock(&capture_mutex); 1950 1951 return dump; 1952 } 1953 1954 void i915_error_state_store(struct i915_gpu_coredump *error) 1955 { 1956 struct drm_i915_private *i915; 1957 static bool warned; 1958 1959 if (IS_ERR_OR_NULL(error)) 1960 return; 1961 1962 i915 = error->i915; 1963 drm_info(&i915->drm, "%s\n", error_msg(error)); 1964 1965 if (error->simulated || 1966 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1967 return; 1968 1969 i915_gpu_coredump_get(error); 1970 1971 if (!xchg(&warned, true) && 1972 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1973 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1974 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1975 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1976 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1977 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1978 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1979 i915->drm.primary->index); 1980 } 1981 } 1982 1983 /** 1984 * i915_capture_error_state - capture an error record for later analysis 1985 * @gt: intel_gt which originated the hang 1986 * @engine_mask: hung engines 1987 * 1988 * 1989 * Should be called when an error is detected (either a hang or an error 1990 * interrupt) to capture error state from the time of the error. Fills 1991 * out a structure which becomes available in debugfs for user level tools 1992 * to pick up. 1993 */ 1994 void i915_capture_error_state(struct intel_gt *gt, 1995 intel_engine_mask_t engine_mask) 1996 { 1997 struct i915_gpu_coredump *error; 1998 1999 error = i915_gpu_coredump(gt, engine_mask); 2000 if (IS_ERR(error)) { 2001 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2002 return; 2003 } 2004 2005 i915_error_state_store(error); 2006 i915_gpu_coredump_put(error); 2007 } 2008 2009 struct i915_gpu_coredump * 2010 i915_first_error_state(struct drm_i915_private *i915) 2011 { 2012 struct i915_gpu_coredump *error; 2013 2014 spin_lock_irq(&i915->gpu_error.lock); 2015 error = i915->gpu_error.first_error; 2016 if (!IS_ERR_OR_NULL(error)) 2017 i915_gpu_coredump_get(error); 2018 spin_unlock_irq(&i915->gpu_error.lock); 2019 2020 return error; 2021 } 2022 2023 void i915_reset_error_state(struct drm_i915_private *i915) 2024 { 2025 struct i915_gpu_coredump *error; 2026 2027 spin_lock_irq(&i915->gpu_error.lock); 2028 error = i915->gpu_error.first_error; 2029 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2030 i915->gpu_error.first_error = NULL; 2031 spin_unlock_irq(&i915->gpu_error.lock); 2032 2033 if (!IS_ERR_OR_NULL(error)) 2034 i915_gpu_coredump_put(error); 2035 } 2036 2037 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2038 { 2039 spin_lock_irq(&i915->gpu_error.lock); 2040 if (!i915->gpu_error.first_error) 2041 i915->gpu_error.first_error = ERR_PTR(err); 2042 spin_unlock_irq(&i915->gpu_error.lock); 2043 } 2044