1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include <linux/stop_machine.h> 32 #include <linux/zlib.h> 33 #include <drm/drm_print.h> 34 35 #include "i915_drv.h" 36 37 static inline const struct intel_engine_cs * 38 engine_lookup(const struct drm_i915_private *i915, unsigned int id) 39 { 40 if (id >= I915_NUM_ENGINES) 41 return NULL; 42 43 return i915->engine[id]; 44 } 45 46 static inline const char * 47 __engine_name(const struct intel_engine_cs *engine) 48 { 49 return engine ? engine->name : ""; 50 } 51 52 static const char * 53 engine_name(const struct drm_i915_private *i915, unsigned int id) 54 { 55 return __engine_name(engine_lookup(i915, id)); 56 } 57 58 static const char *tiling_flag(int tiling) 59 { 60 switch (tiling) { 61 default: 62 case I915_TILING_NONE: return ""; 63 case I915_TILING_X: return " X"; 64 case I915_TILING_Y: return " Y"; 65 } 66 } 67 68 static const char *dirty_flag(int dirty) 69 { 70 return dirty ? " dirty" : ""; 71 } 72 73 static const char *purgeable_flag(int purgeable) 74 { 75 return purgeable ? " purgeable" : ""; 76 } 77 78 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 79 { 80 81 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 82 e->err = -ENOSPC; 83 return false; 84 } 85 86 if (e->bytes == e->size - 1 || e->err) 87 return false; 88 89 return true; 90 } 91 92 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 93 unsigned len) 94 { 95 if (e->pos + len <= e->start) { 96 e->pos += len; 97 return false; 98 } 99 100 /* First vsnprintf needs to fit in its entirety for memmove */ 101 if (len >= e->size) { 102 e->err = -EIO; 103 return false; 104 } 105 106 return true; 107 } 108 109 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 110 unsigned len) 111 { 112 /* If this is first printf in this window, adjust it so that 113 * start position matches start of the buffer 114 */ 115 116 if (e->pos < e->start) { 117 const size_t off = e->start - e->pos; 118 119 /* Should not happen but be paranoid */ 120 if (off > len || e->bytes) { 121 e->err = -EIO; 122 return; 123 } 124 125 memmove(e->buf, e->buf + off, len - off); 126 e->bytes = len - off; 127 e->pos = e->start; 128 return; 129 } 130 131 e->bytes += len; 132 e->pos += len; 133 } 134 135 __printf(2, 0) 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 137 const char *f, va_list args) 138 { 139 unsigned len; 140 141 if (!__i915_error_ok(e)) 142 return; 143 144 /* Seek the first printf which is hits start position */ 145 if (e->pos < e->start) { 146 va_list tmp; 147 148 va_copy(tmp, args); 149 len = vsnprintf(NULL, 0, f, tmp); 150 va_end(tmp); 151 152 if (!__i915_error_seek(e, len)) 153 return; 154 } 155 156 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 157 if (len >= e->size - e->bytes) 158 len = e->size - e->bytes - 1; 159 160 __i915_error_advance(e, len); 161 } 162 163 static void i915_error_puts(struct drm_i915_error_state_buf *e, 164 const char *str) 165 { 166 unsigned len; 167 168 if (!__i915_error_ok(e)) 169 return; 170 171 len = strlen(str); 172 173 /* Seek the first printf which is hits start position */ 174 if (e->pos < e->start) { 175 if (!__i915_error_seek(e, len)) 176 return; 177 } 178 179 if (len >= e->size - e->bytes) 180 len = e->size - e->bytes - 1; 181 memcpy(e->buf + e->bytes, str, len); 182 183 __i915_error_advance(e, len); 184 } 185 186 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 187 #define err_puts(e, s) i915_error_puts(e, s) 188 189 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 190 { 191 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 192 } 193 194 static inline struct drm_printer 195 i915_error_printer(struct drm_i915_error_state_buf *e) 196 { 197 struct drm_printer p = { 198 .printfn = __i915_printfn_error, 199 .arg = e, 200 }; 201 return p; 202 } 203 204 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 205 206 struct compress { 207 struct z_stream_s zstream; 208 void *tmp; 209 }; 210 211 static bool compress_init(struct compress *c) 212 { 213 struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream)); 214 215 zstream->workspace = 216 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 217 GFP_ATOMIC | __GFP_NOWARN); 218 if (!zstream->workspace) 219 return false; 220 221 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) { 222 kfree(zstream->workspace); 223 return false; 224 } 225 226 c->tmp = NULL; 227 if (i915_has_memcpy_from_wc()) 228 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN); 229 230 return true; 231 } 232 233 static int compress_page(struct compress *c, 234 void *src, 235 struct drm_i915_error_object *dst) 236 { 237 struct z_stream_s *zstream = &c->zstream; 238 239 zstream->next_in = src; 240 if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 241 zstream->next_in = c->tmp; 242 zstream->avail_in = PAGE_SIZE; 243 244 do { 245 if (zstream->avail_out == 0) { 246 unsigned long page; 247 248 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); 249 if (!page) 250 return -ENOMEM; 251 252 dst->pages[dst->page_count++] = (void *)page; 253 254 zstream->next_out = (void *)page; 255 zstream->avail_out = PAGE_SIZE; 256 } 257 258 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK) 259 return -EIO; 260 } while (zstream->avail_in); 261 262 /* Fallback to uncompressed if we increase size? */ 263 if (0 && zstream->total_out > zstream->total_in) 264 return -E2BIG; 265 266 return 0; 267 } 268 269 static void compress_fini(struct compress *c, 270 struct drm_i915_error_object *dst) 271 { 272 struct z_stream_s *zstream = &c->zstream; 273 274 if (dst) { 275 zlib_deflate(zstream, Z_FINISH); 276 dst->unused = zstream->avail_out; 277 } 278 279 zlib_deflateEnd(zstream); 280 kfree(zstream->workspace); 281 282 if (c->tmp) 283 free_page((unsigned long)c->tmp); 284 } 285 286 static void err_compression_marker(struct drm_i915_error_state_buf *m) 287 { 288 err_puts(m, ":"); 289 } 290 291 #else 292 293 struct compress { 294 }; 295 296 static bool compress_init(struct compress *c) 297 { 298 return true; 299 } 300 301 static int compress_page(struct compress *c, 302 void *src, 303 struct drm_i915_error_object *dst) 304 { 305 unsigned long page; 306 void *ptr; 307 308 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); 309 if (!page) 310 return -ENOMEM; 311 312 ptr = (void *)page; 313 if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE)) 314 memcpy(ptr, src, PAGE_SIZE); 315 dst->pages[dst->page_count++] = ptr; 316 317 return 0; 318 } 319 320 static void compress_fini(struct compress *c, 321 struct drm_i915_error_object *dst) 322 { 323 } 324 325 static void err_compression_marker(struct drm_i915_error_state_buf *m) 326 { 327 err_puts(m, "~"); 328 } 329 330 #endif 331 332 static void print_error_buffers(struct drm_i915_error_state_buf *m, 333 const char *name, 334 struct drm_i915_error_buffer *err, 335 int count) 336 { 337 int i; 338 339 err_printf(m, "%s [%d]:\n", name, count); 340 341 while (count--) { 342 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 343 upper_32_bits(err->gtt_offset), 344 lower_32_bits(err->gtt_offset), 345 err->size, 346 err->read_domains, 347 err->write_domain); 348 for (i = 0; i < I915_NUM_ENGINES; i++) 349 err_printf(m, "%02x ", err->rseqno[i]); 350 351 err_printf(m, "] %02x", err->wseqno); 352 err_puts(m, tiling_flag(err->tiling)); 353 err_puts(m, dirty_flag(err->dirty)); 354 err_puts(m, purgeable_flag(err->purgeable)); 355 err_puts(m, err->userptr ? " userptr" : ""); 356 err_puts(m, err->engine != -1 ? " " : ""); 357 err_puts(m, engine_name(m->i915, err->engine)); 358 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 359 360 if (err->name) 361 err_printf(m, " (name: %d)", err->name); 362 if (err->fence_reg != I915_FENCE_REG_NONE) 363 err_printf(m, " (fence: %d)", err->fence_reg); 364 365 err_puts(m, "\n"); 366 err++; 367 } 368 } 369 370 static void error_print_instdone(struct drm_i915_error_state_buf *m, 371 const struct drm_i915_error_engine *ee) 372 { 373 int slice; 374 int subslice; 375 376 err_printf(m, " INSTDONE: 0x%08x\n", 377 ee->instdone.instdone); 378 379 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) 380 return; 381 382 err_printf(m, " SC_INSTDONE: 0x%08x\n", 383 ee->instdone.slice_common); 384 385 if (INTEL_GEN(m->i915) <= 6) 386 return; 387 388 for_each_instdone_slice_subslice(m->i915, slice, subslice) 389 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 390 slice, subslice, 391 ee->instdone.sampler[slice][subslice]); 392 393 for_each_instdone_slice_subslice(m->i915, slice, subslice) 394 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 395 slice, subslice, 396 ee->instdone.row[slice][subslice]); 397 } 398 399 static const char *bannable(const struct drm_i915_error_context *ctx) 400 { 401 return ctx->bannable ? "" : " (unbannable)"; 402 } 403 404 static void error_print_request(struct drm_i915_error_state_buf *m, 405 const char *prefix, 406 const struct drm_i915_error_request *erq) 407 { 408 if (!erq->seqno) 409 return; 410 411 err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d, emitted %dms ago, head %08x, tail %08x\n", 412 prefix, erq->pid, erq->ban_score, 413 erq->context, erq->seqno, erq->priority, 414 jiffies_to_msecs(jiffies - erq->jiffies), 415 erq->head, erq->tail); 416 } 417 418 static void error_print_context(struct drm_i915_error_state_buf *m, 419 const char *header, 420 const struct drm_i915_error_context *ctx) 421 { 422 err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n", 423 header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id, 424 ctx->priority, ctx->ban_score, bannable(ctx), 425 ctx->guilty, ctx->active); 426 } 427 428 static void error_print_engine(struct drm_i915_error_state_buf *m, 429 const struct drm_i915_error_engine *ee) 430 { 431 int n; 432 433 err_printf(m, "%s command stream:\n", 434 engine_name(m->i915, ee->engine_id)); 435 err_printf(m, " IDLE?: %s\n", yesno(ee->idle)); 436 err_printf(m, " START: 0x%08x\n", ee->start); 437 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 438 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 439 ee->tail, ee->rq_post, ee->rq_tail); 440 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 441 err_printf(m, " MODE: 0x%08x\n", ee->mode); 442 err_printf(m, " HWS: 0x%08x\n", ee->hws); 443 err_printf(m, " ACTHD: 0x%08x %08x\n", 444 (u32)(ee->acthd>>32), (u32)ee->acthd); 445 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 446 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 447 448 error_print_instdone(m, ee); 449 450 if (ee->batchbuffer) { 451 u64 start = ee->batchbuffer->gtt_offset; 452 u64 end = start + ee->batchbuffer->gtt_size; 453 454 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 455 upper_32_bits(start), lower_32_bits(start), 456 upper_32_bits(end), lower_32_bits(end)); 457 } 458 if (INTEL_GEN(m->i915) >= 4) { 459 err_printf(m, " BBADDR: 0x%08x_%08x\n", 460 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 461 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 462 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 463 } 464 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 465 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 466 lower_32_bits(ee->faddr)); 467 if (INTEL_GEN(m->i915) >= 6) { 468 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 469 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 470 err_printf(m, " SYNC_0: 0x%08x\n", 471 ee->semaphore_mboxes[0]); 472 err_printf(m, " SYNC_1: 0x%08x\n", 473 ee->semaphore_mboxes[1]); 474 if (HAS_VEBOX(m->i915)) 475 err_printf(m, " SYNC_2: 0x%08x\n", 476 ee->semaphore_mboxes[2]); 477 } 478 if (USES_PPGTT(m->i915)) { 479 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 480 481 if (INTEL_GEN(m->i915) >= 8) { 482 int i; 483 for (i = 0; i < 4; i++) 484 err_printf(m, " PDP%d: 0x%016llx\n", 485 i, ee->vm_info.pdp[i]); 486 } else { 487 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 488 ee->vm_info.pp_dir_base); 489 } 490 } 491 err_printf(m, " seqno: 0x%08x\n", ee->seqno); 492 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno); 493 err_printf(m, " waiting: %s\n", yesno(ee->waiting)); 494 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head); 495 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail); 496 err_printf(m, " hangcheck stall: %s\n", yesno(ee->hangcheck_stalled)); 497 err_printf(m, " hangcheck action: %s\n", 498 hangcheck_action_to_str(ee->hangcheck_action)); 499 err_printf(m, " hangcheck action timestamp: %lu, %u ms ago\n", 500 ee->hangcheck_timestamp, 501 jiffies_to_msecs(jiffies - ee->hangcheck_timestamp)); 502 err_printf(m, " engine reset count: %u\n", ee->reset_count); 503 504 for (n = 0; n < ee->num_ports; n++) { 505 err_printf(m, " ELSP[%d]:", n); 506 error_print_request(m, " ", &ee->execlist[n]); 507 } 508 509 error_print_context(m, " Active context: ", &ee->context); 510 } 511 512 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 513 { 514 va_list args; 515 516 va_start(args, f); 517 i915_error_vprintf(e, f, args); 518 va_end(args); 519 } 520 521 static int 522 ascii85_encode_len(int len) 523 { 524 return DIV_ROUND_UP(len, 4); 525 } 526 527 static bool 528 ascii85_encode(u32 in, char *out) 529 { 530 int i; 531 532 if (in == 0) 533 return false; 534 535 out[5] = '\0'; 536 for (i = 5; i--; ) { 537 out[i] = '!' + in % 85; 538 in /= 85; 539 } 540 541 return true; 542 } 543 544 static void print_error_obj(struct drm_i915_error_state_buf *m, 545 struct intel_engine_cs *engine, 546 const char *name, 547 struct drm_i915_error_object *obj) 548 { 549 char out[6]; 550 int page; 551 552 if (!obj) 553 return; 554 555 if (name) { 556 err_printf(m, "%s --- %s = 0x%08x %08x\n", 557 engine ? engine->name : "global", name, 558 upper_32_bits(obj->gtt_offset), 559 lower_32_bits(obj->gtt_offset)); 560 } 561 562 err_compression_marker(m); 563 for (page = 0; page < obj->page_count; page++) { 564 int i, len; 565 566 len = PAGE_SIZE; 567 if (page == obj->page_count - 1) 568 len -= obj->unused; 569 len = ascii85_encode_len(len); 570 571 for (i = 0; i < len; i++) { 572 if (ascii85_encode(obj->pages[page][i], out)) 573 err_puts(m, out); 574 else 575 err_puts(m, "z"); 576 } 577 } 578 err_puts(m, "\n"); 579 } 580 581 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 582 const struct intel_device_info *info) 583 { 584 struct drm_printer p = i915_error_printer(m); 585 586 intel_device_info_dump_flags(info, &p); 587 } 588 589 static void err_print_params(struct drm_i915_error_state_buf *m, 590 const struct i915_params *params) 591 { 592 struct drm_printer p = i915_error_printer(m); 593 594 i915_params_dump(params, &p); 595 } 596 597 static void err_print_pciid(struct drm_i915_error_state_buf *m, 598 struct drm_i915_private *i915) 599 { 600 struct pci_dev *pdev = i915->drm.pdev; 601 602 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 603 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 604 err_printf(m, "PCI Subsystem: %04x:%04x\n", 605 pdev->subsystem_vendor, 606 pdev->subsystem_device); 607 } 608 609 static void err_print_uc(struct drm_i915_error_state_buf *m, 610 const struct i915_error_uc *error_uc) 611 { 612 struct drm_printer p = i915_error_printer(m); 613 const struct i915_gpu_state *error = 614 container_of(error_uc, typeof(*error), uc); 615 616 if (!error->device_info.has_guc) 617 return; 618 619 intel_uc_fw_dump(&error_uc->guc_fw, &p); 620 intel_uc_fw_dump(&error_uc->huc_fw, &p); 621 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log); 622 } 623 624 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 625 const struct i915_gpu_state *error) 626 { 627 struct drm_i915_private *dev_priv = m->i915; 628 struct drm_i915_error_object *obj; 629 struct timespec64 ts; 630 int i, j; 631 632 if (!error) { 633 err_printf(m, "No error state collected\n"); 634 return 0; 635 } 636 637 if (*error->error_msg) 638 err_printf(m, "%s\n", error->error_msg); 639 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 640 ts = ktime_to_timespec64(error->time); 641 err_printf(m, "Time: %lld s %ld us\n", 642 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 643 ts = ktime_to_timespec64(error->boottime); 644 err_printf(m, "Boottime: %lld s %ld us\n", 645 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 646 ts = ktime_to_timespec64(error->uptime); 647 err_printf(m, "Uptime: %lld s %ld us\n", 648 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 649 650 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 651 if (error->engine[i].hangcheck_stalled && 652 error->engine[i].context.pid) { 653 err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n", 654 engine_name(m->i915, i), 655 error->engine[i].context.comm, 656 error->engine[i].context.pid, 657 error->engine[i].context.ban_score, 658 bannable(&error->engine[i].context)); 659 } 660 } 661 err_printf(m, "Reset count: %u\n", error->reset_count); 662 err_printf(m, "Suspend count: %u\n", error->suspend_count); 663 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 664 err_print_pciid(m, error->i915); 665 666 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 667 668 if (HAS_CSR(dev_priv)) { 669 struct intel_csr *csr = &dev_priv->csr; 670 671 err_printf(m, "DMC loaded: %s\n", 672 yesno(csr->dmc_payload != NULL)); 673 err_printf(m, "DMC fw version: %d.%d\n", 674 CSR_VERSION_MAJOR(csr->version), 675 CSR_VERSION_MINOR(csr->version)); 676 } 677 678 err_printf(m, "GT awake: %s\n", yesno(error->awake)); 679 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 680 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 681 err_printf(m, "EIR: 0x%08x\n", error->eir); 682 err_printf(m, "IER: 0x%08x\n", error->ier); 683 for (i = 0; i < error->ngtier; i++) 684 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]); 685 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 686 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 687 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 688 err_printf(m, "CCID: 0x%08x\n", error->ccid); 689 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 690 691 for (i = 0; i < error->nfence; i++) 692 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 693 694 if (INTEL_GEN(dev_priv) >= 6) { 695 err_printf(m, "ERROR: 0x%08x\n", error->error); 696 697 if (INTEL_GEN(dev_priv) >= 8) 698 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 699 error->fault_data1, error->fault_data0); 700 701 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 702 } 703 704 if (IS_GEN7(dev_priv)) 705 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 706 707 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 708 if (error->engine[i].engine_id != -1) 709 error_print_engine(m, &error->engine[i]); 710 } 711 712 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) { 713 char buf[128]; 714 int len, first = 1; 715 716 if (!error->active_vm[i]) 717 break; 718 719 len = scnprintf(buf, sizeof(buf), "Active ("); 720 for (j = 0; j < ARRAY_SIZE(error->engine); j++) { 721 if (error->engine[j].vm != error->active_vm[i]) 722 continue; 723 724 len += scnprintf(buf + len, sizeof(buf), "%s%s", 725 first ? "" : ", ", 726 dev_priv->engine[j]->name); 727 first = 0; 728 } 729 scnprintf(buf + len, sizeof(buf), ")"); 730 print_error_buffers(m, buf, 731 error->active_bo[i], 732 error->active_bo_count[i]); 733 } 734 735 print_error_buffers(m, "Pinned (global)", 736 error->pinned_bo, 737 error->pinned_bo_count); 738 739 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 740 const struct drm_i915_error_engine *ee = &error->engine[i]; 741 742 obj = ee->batchbuffer; 743 if (obj) { 744 err_puts(m, dev_priv->engine[i]->name); 745 if (ee->context.pid) 746 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)", 747 ee->context.comm, 748 ee->context.pid, 749 ee->context.handle, 750 ee->context.hw_id, 751 ee->context.ban_score, 752 bannable(&ee->context)); 753 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 754 upper_32_bits(obj->gtt_offset), 755 lower_32_bits(obj->gtt_offset)); 756 print_error_obj(m, dev_priv->engine[i], NULL, obj); 757 } 758 759 for (j = 0; j < ee->user_bo_count; j++) 760 print_error_obj(m, dev_priv->engine[i], 761 "user", ee->user_bo[j]); 762 763 if (ee->num_requests) { 764 err_printf(m, "%s --- %d requests\n", 765 dev_priv->engine[i]->name, 766 ee->num_requests); 767 for (j = 0; j < ee->num_requests; j++) 768 error_print_request(m, " ", &ee->requests[j]); 769 } 770 771 if (IS_ERR(ee->waiters)) { 772 err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n", 773 dev_priv->engine[i]->name); 774 } else if (ee->num_waiters) { 775 err_printf(m, "%s --- %d waiters\n", 776 dev_priv->engine[i]->name, 777 ee->num_waiters); 778 for (j = 0; j < ee->num_waiters; j++) { 779 err_printf(m, " seqno 0x%08x for %s [%d]\n", 780 ee->waiters[j].seqno, 781 ee->waiters[j].comm, 782 ee->waiters[j].pid); 783 } 784 } 785 786 print_error_obj(m, dev_priv->engine[i], 787 "ringbuffer", ee->ringbuffer); 788 789 print_error_obj(m, dev_priv->engine[i], 790 "HW Status", ee->hws_page); 791 792 print_error_obj(m, dev_priv->engine[i], 793 "HW context", ee->ctx); 794 795 print_error_obj(m, dev_priv->engine[i], 796 "WA context", ee->wa_ctx); 797 798 print_error_obj(m, dev_priv->engine[i], 799 "WA batchbuffer", ee->wa_batchbuffer); 800 801 print_error_obj(m, dev_priv->engine[i], 802 "NULL context", ee->default_state); 803 } 804 805 if (error->overlay) 806 intel_overlay_print_error_state(m, error->overlay); 807 808 if (error->display) 809 intel_display_print_error_state(m, error->display); 810 811 err_print_capabilities(m, &error->device_info); 812 err_print_params(m, &error->params); 813 err_print_uc(m, &error->uc); 814 815 if (m->bytes == 0 && m->err) 816 return m->err; 817 818 return 0; 819 } 820 821 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 822 struct drm_i915_private *i915, 823 size_t count, loff_t pos) 824 { 825 memset(ebuf, 0, sizeof(*ebuf)); 826 ebuf->i915 = i915; 827 828 /* We need to have enough room to store any i915_error_state printf 829 * so that we can move it to start position. 830 */ 831 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 832 ebuf->buf = kmalloc(ebuf->size, 833 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN); 834 835 if (ebuf->buf == NULL) { 836 ebuf->size = PAGE_SIZE; 837 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL); 838 } 839 840 if (ebuf->buf == NULL) { 841 ebuf->size = 128; 842 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL); 843 } 844 845 if (ebuf->buf == NULL) 846 return -ENOMEM; 847 848 ebuf->start = pos; 849 850 return 0; 851 } 852 853 static void i915_error_object_free(struct drm_i915_error_object *obj) 854 { 855 int page; 856 857 if (obj == NULL) 858 return; 859 860 for (page = 0; page < obj->page_count; page++) 861 free_page((unsigned long)obj->pages[page]); 862 863 kfree(obj); 864 } 865 866 static __always_inline void free_param(const char *type, void *x) 867 { 868 if (!__builtin_strcmp(type, "char *")) 869 kfree(*(void **)x); 870 } 871 872 static void cleanup_params(struct i915_gpu_state *error) 873 { 874 #define FREE(T, x, ...) free_param(#T, &error->params.x); 875 I915_PARAMS_FOR_EACH(FREE); 876 #undef FREE 877 } 878 879 static void cleanup_uc_state(struct i915_gpu_state *error) 880 { 881 struct i915_error_uc *error_uc = &error->uc; 882 883 kfree(error_uc->guc_fw.path); 884 kfree(error_uc->huc_fw.path); 885 i915_error_object_free(error_uc->guc_log); 886 } 887 888 void __i915_gpu_state_free(struct kref *error_ref) 889 { 890 struct i915_gpu_state *error = 891 container_of(error_ref, typeof(*error), ref); 892 long i, j; 893 894 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 895 struct drm_i915_error_engine *ee = &error->engine[i]; 896 897 for (j = 0; j < ee->user_bo_count; j++) 898 i915_error_object_free(ee->user_bo[j]); 899 kfree(ee->user_bo); 900 901 i915_error_object_free(ee->batchbuffer); 902 i915_error_object_free(ee->wa_batchbuffer); 903 i915_error_object_free(ee->ringbuffer); 904 i915_error_object_free(ee->hws_page); 905 i915_error_object_free(ee->ctx); 906 i915_error_object_free(ee->wa_ctx); 907 908 kfree(ee->requests); 909 if (!IS_ERR_OR_NULL(ee->waiters)) 910 kfree(ee->waiters); 911 } 912 913 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++) 914 kfree(error->active_bo[i]); 915 kfree(error->pinned_bo); 916 917 kfree(error->overlay); 918 kfree(error->display); 919 920 cleanup_params(error); 921 cleanup_uc_state(error); 922 923 kfree(error); 924 } 925 926 static struct drm_i915_error_object * 927 i915_error_object_create(struct drm_i915_private *i915, 928 struct i915_vma *vma) 929 { 930 struct i915_ggtt *ggtt = &i915->ggtt; 931 const u64 slot = ggtt->error_capture.start; 932 struct drm_i915_error_object *dst; 933 struct compress compress; 934 unsigned long num_pages; 935 struct sgt_iter iter; 936 dma_addr_t dma; 937 938 if (!vma) 939 return NULL; 940 941 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 942 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 943 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), 944 GFP_ATOMIC | __GFP_NOWARN); 945 if (!dst) 946 return NULL; 947 948 dst->gtt_offset = vma->node.start; 949 dst->gtt_size = vma->node.size; 950 dst->page_count = 0; 951 dst->unused = 0; 952 953 if (!compress_init(&compress)) { 954 kfree(dst); 955 return NULL; 956 } 957 958 for_each_sgt_dma(dma, iter, vma->pages) { 959 void __iomem *s; 960 int ret; 961 962 ggtt->base.insert_page(&ggtt->base, dma, slot, 963 I915_CACHE_NONE, 0); 964 965 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot); 966 ret = compress_page(&compress, (void __force *)s, dst); 967 io_mapping_unmap_atomic(s); 968 969 if (ret) 970 goto unwind; 971 } 972 goto out; 973 974 unwind: 975 while (dst->page_count--) 976 free_page((unsigned long)dst->pages[dst->page_count]); 977 kfree(dst); 978 dst = NULL; 979 980 out: 981 compress_fini(&compress, dst); 982 ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE); 983 return dst; 984 } 985 986 /* The error capture is special as tries to run underneath the normal 987 * locking rules - so we use the raw version of the i915_gem_active lookup. 988 */ 989 static inline uint32_t 990 __active_get_seqno(struct i915_gem_active *active) 991 { 992 struct drm_i915_gem_request *request; 993 994 request = __i915_gem_active_peek(active); 995 return request ? request->global_seqno : 0; 996 } 997 998 static inline int 999 __active_get_engine_id(struct i915_gem_active *active) 1000 { 1001 struct drm_i915_gem_request *request; 1002 1003 request = __i915_gem_active_peek(active); 1004 return request ? request->engine->id : -1; 1005 } 1006 1007 static void capture_bo(struct drm_i915_error_buffer *err, 1008 struct i915_vma *vma) 1009 { 1010 struct drm_i915_gem_object *obj = vma->obj; 1011 int i; 1012 1013 err->size = obj->base.size; 1014 err->name = obj->base.name; 1015 1016 for (i = 0; i < I915_NUM_ENGINES; i++) 1017 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]); 1018 err->wseqno = __active_get_seqno(&obj->frontbuffer_write); 1019 err->engine = __active_get_engine_id(&obj->frontbuffer_write); 1020 1021 err->gtt_offset = vma->node.start; 1022 err->read_domains = obj->base.read_domains; 1023 err->write_domain = obj->base.write_domain; 1024 err->fence_reg = vma->fence ? vma->fence->id : -1; 1025 err->tiling = i915_gem_object_get_tiling(obj); 1026 err->dirty = obj->mm.dirty; 1027 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED; 1028 err->userptr = obj->userptr.mm != NULL; 1029 err->cache_level = obj->cache_level; 1030 } 1031 1032 static u32 capture_error_bo(struct drm_i915_error_buffer *err, 1033 int count, struct list_head *head, 1034 bool pinned_only) 1035 { 1036 struct i915_vma *vma; 1037 int i = 0; 1038 1039 list_for_each_entry(vma, head, vm_link) { 1040 if (pinned_only && !i915_vma_is_pinned(vma)) 1041 continue; 1042 1043 capture_bo(err++, vma); 1044 if (++i == count) 1045 break; 1046 } 1047 1048 return i; 1049 } 1050 1051 /* Generate a semi-unique error code. The code is not meant to have meaning, The 1052 * code's only purpose is to try to prevent false duplicated bug reports by 1053 * grossly estimating a GPU error state. 1054 * 1055 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1056 * the hang if we could strip the GTT offset information from it. 1057 * 1058 * It's only a small step better than a random number in its current form. 1059 */ 1060 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 1061 struct i915_gpu_state *error, 1062 int *engine_id) 1063 { 1064 uint32_t error_code = 0; 1065 int i; 1066 1067 /* IPEHR would be an ideal way to detect errors, as it's the gross 1068 * measure of "the command that hung." However, has some very common 1069 * synchronization commands which almost always appear in the case 1070 * strictly a client bug. Use instdone to differentiate those some. 1071 */ 1072 for (i = 0; i < I915_NUM_ENGINES; i++) { 1073 if (error->engine[i].hangcheck_stalled) { 1074 if (engine_id) 1075 *engine_id = i; 1076 1077 return error->engine[i].ipehr ^ 1078 error->engine[i].instdone.instdone; 1079 } 1080 } 1081 1082 return error_code; 1083 } 1084 1085 static void i915_gem_record_fences(struct drm_i915_private *dev_priv, 1086 struct i915_gpu_state *error) 1087 { 1088 int i; 1089 1090 if (INTEL_GEN(dev_priv) >= 6) { 1091 for (i = 0; i < dev_priv->num_fence_regs; i++) 1092 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 1093 } else if (INTEL_GEN(dev_priv) >= 4) { 1094 for (i = 0; i < dev_priv->num_fence_regs; i++) 1095 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 1096 } else { 1097 for (i = 0; i < dev_priv->num_fence_regs; i++) 1098 error->fence[i] = I915_READ(FENCE_REG(i)); 1099 } 1100 error->nfence = i; 1101 } 1102 1103 static inline u32 1104 gen8_engine_sync_index(struct intel_engine_cs *engine, 1105 struct intel_engine_cs *other) 1106 { 1107 int idx; 1108 1109 /* 1110 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; 1111 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; 1112 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; 1113 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; 1114 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; 1115 */ 1116 1117 idx = (other - engine) - 1; 1118 if (idx < 0) 1119 idx += I915_NUM_ENGINES; 1120 1121 return idx; 1122 } 1123 1124 static void gen6_record_semaphore_state(struct intel_engine_cs *engine, 1125 struct drm_i915_error_engine *ee) 1126 { 1127 struct drm_i915_private *dev_priv = engine->i915; 1128 1129 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); 1130 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); 1131 if (HAS_VEBOX(dev_priv)) 1132 ee->semaphore_mboxes[2] = 1133 I915_READ(RING_SYNC_2(engine->mmio_base)); 1134 } 1135 1136 static void error_record_engine_waiters(struct intel_engine_cs *engine, 1137 struct drm_i915_error_engine *ee) 1138 { 1139 struct intel_breadcrumbs *b = &engine->breadcrumbs; 1140 struct drm_i915_error_waiter *waiter; 1141 struct rb_node *rb; 1142 int count; 1143 1144 ee->num_waiters = 0; 1145 ee->waiters = NULL; 1146 1147 if (RB_EMPTY_ROOT(&b->waiters)) 1148 return; 1149 1150 if (!spin_trylock_irq(&b->rb_lock)) { 1151 ee->waiters = ERR_PTR(-EDEADLK); 1152 return; 1153 } 1154 1155 count = 0; 1156 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb)) 1157 count++; 1158 spin_unlock_irq(&b->rb_lock); 1159 1160 waiter = NULL; 1161 if (count) 1162 waiter = kmalloc_array(count, 1163 sizeof(struct drm_i915_error_waiter), 1164 GFP_ATOMIC); 1165 if (!waiter) 1166 return; 1167 1168 if (!spin_trylock_irq(&b->rb_lock)) { 1169 kfree(waiter); 1170 ee->waiters = ERR_PTR(-EDEADLK); 1171 return; 1172 } 1173 1174 ee->waiters = waiter; 1175 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 1176 struct intel_wait *w = rb_entry(rb, typeof(*w), node); 1177 1178 strcpy(waiter->comm, w->tsk->comm); 1179 waiter->pid = w->tsk->pid; 1180 waiter->seqno = w->seqno; 1181 waiter++; 1182 1183 if (++ee->num_waiters == count) 1184 break; 1185 } 1186 spin_unlock_irq(&b->rb_lock); 1187 } 1188 1189 static void error_record_engine_registers(struct i915_gpu_state *error, 1190 struct intel_engine_cs *engine, 1191 struct drm_i915_error_engine *ee) 1192 { 1193 struct drm_i915_private *dev_priv = engine->i915; 1194 1195 if (INTEL_GEN(dev_priv) >= 6) { 1196 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); 1197 if (INTEL_GEN(dev_priv) >= 8) { 1198 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); 1199 } else { 1200 gen6_record_semaphore_state(engine, ee); 1201 ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); 1202 } 1203 } 1204 1205 if (INTEL_GEN(dev_priv) >= 4) { 1206 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); 1207 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); 1208 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); 1209 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); 1210 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); 1211 if (INTEL_GEN(dev_priv) >= 8) { 1212 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; 1213 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; 1214 } 1215 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); 1216 } else { 1217 ee->faddr = I915_READ(DMA_FADD_I8XX); 1218 ee->ipeir = I915_READ(IPEIR); 1219 ee->ipehr = I915_READ(IPEHR); 1220 } 1221 1222 intel_engine_get_instdone(engine, &ee->instdone); 1223 1224 ee->waiting = intel_engine_has_waiter(engine); 1225 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); 1226 ee->acthd = intel_engine_get_active_head(engine); 1227 ee->seqno = intel_engine_get_seqno(engine); 1228 ee->last_seqno = intel_engine_last_submit(engine); 1229 ee->start = I915_READ_START(engine); 1230 ee->head = I915_READ_HEAD(engine); 1231 ee->tail = I915_READ_TAIL(engine); 1232 ee->ctl = I915_READ_CTL(engine); 1233 if (INTEL_GEN(dev_priv) > 2) 1234 ee->mode = I915_READ_MODE(engine); 1235 1236 if (!HWS_NEEDS_PHYSICAL(dev_priv)) { 1237 i915_reg_t mmio; 1238 1239 if (IS_GEN7(dev_priv)) { 1240 switch (engine->id) { 1241 default: 1242 case RCS: 1243 mmio = RENDER_HWS_PGA_GEN7; 1244 break; 1245 case BCS: 1246 mmio = BLT_HWS_PGA_GEN7; 1247 break; 1248 case VCS: 1249 mmio = BSD_HWS_PGA_GEN7; 1250 break; 1251 case VECS: 1252 mmio = VEBOX_HWS_PGA_GEN7; 1253 break; 1254 } 1255 } else if (IS_GEN6(engine->i915)) { 1256 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1257 } else { 1258 /* XXX: gen8 returns to sanity */ 1259 mmio = RING_HWS_PGA(engine->mmio_base); 1260 } 1261 1262 ee->hws = I915_READ(mmio); 1263 } 1264 1265 ee->idle = intel_engine_is_idle(engine); 1266 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp; 1267 ee->hangcheck_action = engine->hangcheck.action; 1268 ee->hangcheck_stalled = engine->hangcheck.stalled; 1269 ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error, 1270 engine); 1271 1272 if (USES_PPGTT(dev_priv)) { 1273 int i; 1274 1275 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); 1276 1277 if (IS_GEN6(dev_priv)) 1278 ee->vm_info.pp_dir_base = 1279 I915_READ(RING_PP_DIR_BASE_READ(engine)); 1280 else if (IS_GEN7(dev_priv)) 1281 ee->vm_info.pp_dir_base = 1282 I915_READ(RING_PP_DIR_BASE(engine)); 1283 else if (INTEL_GEN(dev_priv) >= 8) 1284 for (i = 0; i < 4; i++) { 1285 ee->vm_info.pdp[i] = 1286 I915_READ(GEN8_RING_PDP_UDW(engine, i)); 1287 ee->vm_info.pdp[i] <<= 32; 1288 ee->vm_info.pdp[i] |= 1289 I915_READ(GEN8_RING_PDP_LDW(engine, i)); 1290 } 1291 } 1292 } 1293 1294 static void record_request(struct drm_i915_gem_request *request, 1295 struct drm_i915_error_request *erq) 1296 { 1297 erq->context = request->ctx->hw_id; 1298 erq->priority = request->priotree.priority; 1299 erq->ban_score = atomic_read(&request->ctx->ban_score); 1300 erq->seqno = request->global_seqno; 1301 erq->jiffies = request->emitted_jiffies; 1302 erq->head = request->head; 1303 erq->tail = request->tail; 1304 1305 rcu_read_lock(); 1306 erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0; 1307 rcu_read_unlock(); 1308 } 1309 1310 static void engine_record_requests(struct intel_engine_cs *engine, 1311 struct drm_i915_gem_request *first, 1312 struct drm_i915_error_engine *ee) 1313 { 1314 struct drm_i915_gem_request *request; 1315 int count; 1316 1317 count = 0; 1318 request = first; 1319 list_for_each_entry_from(request, &engine->timeline->requests, link) 1320 count++; 1321 if (!count) 1322 return; 1323 1324 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC); 1325 if (!ee->requests) 1326 return; 1327 1328 ee->num_requests = count; 1329 1330 count = 0; 1331 request = first; 1332 list_for_each_entry_from(request, &engine->timeline->requests, link) { 1333 if (count >= ee->num_requests) { 1334 /* 1335 * If the ring request list was changed in 1336 * between the point where the error request 1337 * list was created and dimensioned and this 1338 * point then just exit early to avoid crashes. 1339 * 1340 * We don't need to communicate that the 1341 * request list changed state during error 1342 * state capture and that the error state is 1343 * slightly incorrect as a consequence since we 1344 * are typically only interested in the request 1345 * list state at the point of error state 1346 * capture, not in any changes happening during 1347 * the capture. 1348 */ 1349 break; 1350 } 1351 1352 record_request(request, &ee->requests[count++]); 1353 } 1354 ee->num_requests = count; 1355 } 1356 1357 static void error_record_engine_execlists(struct intel_engine_cs *engine, 1358 struct drm_i915_error_engine *ee) 1359 { 1360 const struct intel_engine_execlists * const execlists = &engine->execlists; 1361 unsigned int n; 1362 1363 for (n = 0; n < execlists_num_ports(execlists); n++) { 1364 struct drm_i915_gem_request *rq = port_request(&execlists->port[n]); 1365 1366 if (!rq) 1367 break; 1368 1369 record_request(rq, &ee->execlist[n]); 1370 } 1371 1372 ee->num_ports = n; 1373 } 1374 1375 static void record_context(struct drm_i915_error_context *e, 1376 struct i915_gem_context *ctx) 1377 { 1378 if (ctx->pid) { 1379 struct task_struct *task; 1380 1381 rcu_read_lock(); 1382 task = pid_task(ctx->pid, PIDTYPE_PID); 1383 if (task) { 1384 strcpy(e->comm, task->comm); 1385 e->pid = task->pid; 1386 } 1387 rcu_read_unlock(); 1388 } 1389 1390 e->handle = ctx->user_handle; 1391 e->hw_id = ctx->hw_id; 1392 e->priority = ctx->priority; 1393 e->ban_score = atomic_read(&ctx->ban_score); 1394 e->bannable = i915_gem_context_is_bannable(ctx); 1395 e->guilty = atomic_read(&ctx->guilty_count); 1396 e->active = atomic_read(&ctx->active_count); 1397 } 1398 1399 static void request_record_user_bo(struct drm_i915_gem_request *request, 1400 struct drm_i915_error_engine *ee) 1401 { 1402 struct i915_gem_capture_list *c; 1403 struct drm_i915_error_object **bo; 1404 long count; 1405 1406 count = 0; 1407 for (c = request->capture_list; c; c = c->next) 1408 count++; 1409 1410 bo = NULL; 1411 if (count) 1412 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC); 1413 if (!bo) 1414 return; 1415 1416 count = 0; 1417 for (c = request->capture_list; c; c = c->next) { 1418 bo[count] = i915_error_object_create(request->i915, c->vma); 1419 if (!bo[count]) 1420 break; 1421 count++; 1422 } 1423 1424 ee->user_bo = bo; 1425 ee->user_bo_count = count; 1426 } 1427 1428 static struct drm_i915_error_object * 1429 capture_object(struct drm_i915_private *dev_priv, 1430 struct drm_i915_gem_object *obj) 1431 { 1432 if (obj && i915_gem_object_has_pages(obj)) { 1433 struct i915_vma fake = { 1434 .node = { .start = U64_MAX, .size = obj->base.size }, 1435 .size = obj->base.size, 1436 .pages = obj->mm.pages, 1437 .obj = obj, 1438 }; 1439 1440 return i915_error_object_create(dev_priv, &fake); 1441 } else { 1442 return NULL; 1443 } 1444 } 1445 1446 static void i915_gem_record_rings(struct drm_i915_private *dev_priv, 1447 struct i915_gpu_state *error) 1448 { 1449 struct i915_ggtt *ggtt = &dev_priv->ggtt; 1450 int i; 1451 1452 for (i = 0; i < I915_NUM_ENGINES; i++) { 1453 struct intel_engine_cs *engine = dev_priv->engine[i]; 1454 struct drm_i915_error_engine *ee = &error->engine[i]; 1455 struct drm_i915_gem_request *request; 1456 1457 ee->engine_id = -1; 1458 1459 if (!engine) 1460 continue; 1461 1462 ee->engine_id = i; 1463 1464 error_record_engine_registers(error, engine, ee); 1465 error_record_engine_waiters(engine, ee); 1466 error_record_engine_execlists(engine, ee); 1467 1468 request = i915_gem_find_active_request(engine); 1469 if (request) { 1470 struct intel_ring *ring; 1471 1472 ee->vm = request->ctx->ppgtt ? 1473 &request->ctx->ppgtt->base : &ggtt->base; 1474 1475 record_context(&ee->context, request->ctx); 1476 1477 /* We need to copy these to an anonymous buffer 1478 * as the simplest method to avoid being overwritten 1479 * by userspace. 1480 */ 1481 ee->batchbuffer = 1482 i915_error_object_create(dev_priv, 1483 request->batch); 1484 1485 if (HAS_BROKEN_CS_TLB(dev_priv)) 1486 ee->wa_batchbuffer = 1487 i915_error_object_create(dev_priv, 1488 engine->scratch); 1489 request_record_user_bo(request, ee); 1490 1491 ee->ctx = 1492 i915_error_object_create(dev_priv, 1493 request->ctx->engine[i].state); 1494 1495 error->simulated |= 1496 i915_gem_context_no_error_capture(request->ctx); 1497 1498 ee->rq_head = request->head; 1499 ee->rq_post = request->postfix; 1500 ee->rq_tail = request->tail; 1501 1502 ring = request->ring; 1503 ee->cpu_ring_head = ring->head; 1504 ee->cpu_ring_tail = ring->tail; 1505 ee->ringbuffer = 1506 i915_error_object_create(dev_priv, ring->vma); 1507 1508 engine_record_requests(engine, request, ee); 1509 } 1510 1511 ee->hws_page = 1512 i915_error_object_create(dev_priv, 1513 engine->status_page.vma); 1514 1515 ee->wa_ctx = 1516 i915_error_object_create(dev_priv, engine->wa_ctx.vma); 1517 1518 ee->default_state = 1519 capture_object(dev_priv, engine->default_state); 1520 } 1521 } 1522 1523 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1524 struct i915_gpu_state *error, 1525 struct i915_address_space *vm, 1526 int idx) 1527 { 1528 struct drm_i915_error_buffer *active_bo; 1529 struct i915_vma *vma; 1530 int count; 1531 1532 count = 0; 1533 list_for_each_entry(vma, &vm->active_list, vm_link) 1534 count++; 1535 1536 active_bo = NULL; 1537 if (count) 1538 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC); 1539 if (active_bo) 1540 count = capture_error_bo(active_bo, count, &vm->active_list, false); 1541 else 1542 count = 0; 1543 1544 error->active_vm[idx] = vm; 1545 error->active_bo[idx] = active_bo; 1546 error->active_bo_count[idx] = count; 1547 } 1548 1549 static void i915_capture_active_buffers(struct drm_i915_private *dev_priv, 1550 struct i915_gpu_state *error) 1551 { 1552 int cnt = 0, i, j; 1553 1554 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo)); 1555 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm)); 1556 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count)); 1557 1558 /* Scan each engine looking for unique active contexts/vm */ 1559 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 1560 struct drm_i915_error_engine *ee = &error->engine[i]; 1561 bool found; 1562 1563 if (!ee->vm) 1564 continue; 1565 1566 found = false; 1567 for (j = 0; j < i && !found; j++) 1568 found = error->engine[j].vm == ee->vm; 1569 if (!found) 1570 i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++); 1571 } 1572 } 1573 1574 static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv, 1575 struct i915_gpu_state *error) 1576 { 1577 struct i915_address_space *vm = &dev_priv->ggtt.base; 1578 struct drm_i915_error_buffer *bo; 1579 struct i915_vma *vma; 1580 int count_inactive, count_active; 1581 1582 count_inactive = 0; 1583 list_for_each_entry(vma, &vm->active_list, vm_link) 1584 count_inactive++; 1585 1586 count_active = 0; 1587 list_for_each_entry(vma, &vm->inactive_list, vm_link) 1588 count_active++; 1589 1590 bo = NULL; 1591 if (count_inactive + count_active) 1592 bo = kcalloc(count_inactive + count_active, 1593 sizeof(*bo), GFP_ATOMIC); 1594 if (!bo) 1595 return; 1596 1597 count_inactive = capture_error_bo(bo, count_inactive, 1598 &vm->active_list, true); 1599 count_active = capture_error_bo(bo + count_inactive, count_active, 1600 &vm->inactive_list, true); 1601 error->pinned_bo_count = count_inactive + count_active; 1602 error->pinned_bo = bo; 1603 } 1604 1605 static void capture_uc_state(struct i915_gpu_state *error) 1606 { 1607 struct drm_i915_private *i915 = error->i915; 1608 struct i915_error_uc *error_uc = &error->uc; 1609 1610 /* Capturing uC state won't be useful if there is no GuC */ 1611 if (!error->device_info.has_guc) 1612 return; 1613 1614 error_uc->guc_fw = i915->guc.fw; 1615 error_uc->huc_fw = i915->huc.fw; 1616 1617 /* Non-default firmware paths will be specified by the modparam. 1618 * As modparams are generally accesible from the userspace make 1619 * explicit copies of the firmware paths. 1620 */ 1621 error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC); 1622 error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC); 1623 error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma); 1624 } 1625 1626 /* Capture all registers which don't fit into another category. */ 1627 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1628 struct i915_gpu_state *error) 1629 { 1630 int i; 1631 1632 /* General organization 1633 * 1. Registers specific to a single generation 1634 * 2. Registers which belong to multiple generations 1635 * 3. Feature specific registers. 1636 * 4. Everything else 1637 * Please try to follow the order. 1638 */ 1639 1640 /* 1: Registers specific to a single generation */ 1641 if (IS_VALLEYVIEW(dev_priv)) { 1642 error->gtier[0] = I915_READ(GTIER); 1643 error->ier = I915_READ(VLV_IER); 1644 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); 1645 } 1646 1647 if (IS_GEN7(dev_priv)) 1648 error->err_int = I915_READ(GEN7_ERR_INT); 1649 1650 if (INTEL_GEN(dev_priv) >= 8) { 1651 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1652 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1653 } 1654 1655 if (IS_GEN6(dev_priv)) { 1656 error->forcewake = I915_READ_FW(FORCEWAKE); 1657 error->gab_ctl = I915_READ(GAB_CTL); 1658 error->gfx_mode = I915_READ(GFX_MODE); 1659 } 1660 1661 /* 2: Registers which belong to multiple generations */ 1662 if (INTEL_GEN(dev_priv) >= 7) 1663 error->forcewake = I915_READ_FW(FORCEWAKE_MT); 1664 1665 if (INTEL_GEN(dev_priv) >= 6) { 1666 error->derrmr = I915_READ(DERRMR); 1667 error->error = I915_READ(ERROR_GEN6); 1668 error->done_reg = I915_READ(DONE_REG); 1669 } 1670 1671 if (INTEL_GEN(dev_priv) >= 5) 1672 error->ccid = I915_READ(CCID); 1673 1674 /* 3: Feature specific registers */ 1675 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 1676 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1677 error->gac_eco = I915_READ(GAC_ECO_BITS); 1678 } 1679 1680 /* 4: Everything else */ 1681 if (INTEL_GEN(dev_priv) >= 8) { 1682 error->ier = I915_READ(GEN8_DE_MISC_IER); 1683 for (i = 0; i < 4; i++) 1684 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1685 error->ngtier = 4; 1686 } else if (HAS_PCH_SPLIT(dev_priv)) { 1687 error->ier = I915_READ(DEIER); 1688 error->gtier[0] = I915_READ(GTIER); 1689 error->ngtier = 1; 1690 } else if (IS_GEN2(dev_priv)) { 1691 error->ier = I915_READ16(IER); 1692 } else if (!IS_VALLEYVIEW(dev_priv)) { 1693 error->ier = I915_READ(IER); 1694 } 1695 error->eir = I915_READ(EIR); 1696 error->pgtbl_er = I915_READ(PGTBL_ER); 1697 } 1698 1699 static void i915_error_capture_msg(struct drm_i915_private *dev_priv, 1700 struct i915_gpu_state *error, 1701 u32 engine_mask, 1702 const char *error_msg) 1703 { 1704 u32 ecode; 1705 int engine_id = -1, len; 1706 1707 ecode = i915_error_generate_code(dev_priv, error, &engine_id); 1708 1709 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1710 "GPU HANG: ecode %d:%d:0x%08x", 1711 INTEL_GEN(dev_priv), engine_id, ecode); 1712 1713 if (engine_id != -1 && error->engine[engine_id].context.pid) 1714 len += scnprintf(error->error_msg + len, 1715 sizeof(error->error_msg) - len, 1716 ", in %s [%d]", 1717 error->engine[engine_id].context.comm, 1718 error->engine[engine_id].context.pid); 1719 1720 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1721 ", reason: %s, action: %s", 1722 error_msg, 1723 engine_mask ? "reset" : "continue"); 1724 } 1725 1726 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1727 struct i915_gpu_state *error) 1728 { 1729 error->awake = dev_priv->gt.awake; 1730 error->wakelock = atomic_read(&dev_priv->runtime_pm.wakeref_count); 1731 error->suspended = dev_priv->runtime_pm.suspended; 1732 1733 error->iommu = -1; 1734 #ifdef CONFIG_INTEL_IOMMU 1735 error->iommu = intel_iommu_gfx_mapped; 1736 #endif 1737 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1738 error->suspend_count = dev_priv->suspend_count; 1739 1740 memcpy(&error->device_info, 1741 INTEL_INFO(dev_priv), 1742 sizeof(error->device_info)); 1743 } 1744 1745 static __always_inline void dup_param(const char *type, void *x) 1746 { 1747 if (!__builtin_strcmp(type, "char *")) 1748 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC); 1749 } 1750 1751 static void capture_params(struct i915_gpu_state *error) 1752 { 1753 error->params = i915_modparams; 1754 #define DUP(T, x, ...) dup_param(#T, &error->params.x); 1755 I915_PARAMS_FOR_EACH(DUP); 1756 #undef DUP 1757 } 1758 1759 static int capture(void *data) 1760 { 1761 struct i915_gpu_state *error = data; 1762 1763 error->time = ktime_get_real(); 1764 error->boottime = ktime_get_boottime(); 1765 error->uptime = ktime_sub(ktime_get(), 1766 error->i915->gt.last_init_time); 1767 1768 capture_params(error); 1769 capture_uc_state(error); 1770 1771 i915_capture_gen_state(error->i915, error); 1772 i915_capture_reg_state(error->i915, error); 1773 i915_gem_record_fences(error->i915, error); 1774 i915_gem_record_rings(error->i915, error); 1775 i915_capture_active_buffers(error->i915, error); 1776 i915_capture_pinned_buffers(error->i915, error); 1777 1778 error->overlay = intel_overlay_capture_error_state(error->i915); 1779 error->display = intel_display_capture_error_state(error->i915); 1780 1781 return 0; 1782 } 1783 1784 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1785 1786 struct i915_gpu_state * 1787 i915_capture_gpu_state(struct drm_i915_private *i915) 1788 { 1789 struct i915_gpu_state *error; 1790 1791 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1792 if (!error) 1793 return NULL; 1794 1795 kref_init(&error->ref); 1796 error->i915 = i915; 1797 1798 stop_machine(capture, error, NULL); 1799 1800 return error; 1801 } 1802 1803 /** 1804 * i915_capture_error_state - capture an error record for later analysis 1805 * @dev: drm device 1806 * 1807 * Should be called when an error is detected (either a hang or an error 1808 * interrupt) to capture error state from the time of the error. Fills 1809 * out a structure which becomes available in debugfs for user level tools 1810 * to pick up. 1811 */ 1812 void i915_capture_error_state(struct drm_i915_private *dev_priv, 1813 u32 engine_mask, 1814 const char *error_msg) 1815 { 1816 static bool warned; 1817 struct i915_gpu_state *error; 1818 unsigned long flags; 1819 1820 if (!i915_modparams.error_capture) 1821 return; 1822 1823 if (READ_ONCE(dev_priv->gpu_error.first_error)) 1824 return; 1825 1826 error = i915_capture_gpu_state(dev_priv); 1827 if (!error) { 1828 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1829 return; 1830 } 1831 1832 i915_error_capture_msg(dev_priv, error, engine_mask, error_msg); 1833 DRM_INFO("%s\n", error->error_msg); 1834 1835 if (!error->simulated) { 1836 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1837 if (!dev_priv->gpu_error.first_error) { 1838 dev_priv->gpu_error.first_error = error; 1839 error = NULL; 1840 } 1841 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1842 } 1843 1844 if (error) { 1845 __i915_gpu_state_free(&error->ref); 1846 return; 1847 } 1848 1849 if (!warned && 1850 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1851 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1852 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1853 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1854 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1855 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1856 dev_priv->drm.primary->index); 1857 warned = true; 1858 } 1859 } 1860 1861 struct i915_gpu_state * 1862 i915_first_error_state(struct drm_i915_private *i915) 1863 { 1864 struct i915_gpu_state *error; 1865 1866 spin_lock_irq(&i915->gpu_error.lock); 1867 error = i915->gpu_error.first_error; 1868 if (error) 1869 i915_gpu_state_get(error); 1870 spin_unlock_irq(&i915->gpu_error.lock); 1871 1872 return error; 1873 } 1874 1875 void i915_reset_error_state(struct drm_i915_private *i915) 1876 { 1877 struct i915_gpu_state *error; 1878 1879 spin_lock_irq(&i915->gpu_error.lock); 1880 error = i915->gpu_error.first_error; 1881 i915->gpu_error.first_error = NULL; 1882 spin_unlock_irq(&i915->gpu_error.lock); 1883 1884 i915_gpu_state_put(error); 1885 } 1886