1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_cache.h> 38 #include <drm/drm_print.h> 39 40 #include "display/intel_dmc.h" 41 #include "display/intel_overlay.h" 42 43 #include "gem/i915_gem_context.h" 44 #include "gem/i915_gem_lmem.h" 45 #include "gt/intel_engine_regs.h" 46 #include "gt/intel_gt.h" 47 #include "gt/intel_gt_pm.h" 48 #include "gt/intel_gt_regs.h" 49 50 #include "i915_driver.h" 51 #include "i915_drv.h" 52 #include "i915_gpu_error.h" 53 #include "i915_memcpy.h" 54 #include "i915_scatterlist.h" 55 56 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 57 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 58 59 static void __sg_set_buf(struct scatterlist *sg, 60 void *addr, unsigned int len, loff_t it) 61 { 62 sg->page_link = (unsigned long)virt_to_page(addr); 63 sg->offset = offset_in_page(addr); 64 sg->length = len; 65 sg->dma_address = it; 66 } 67 68 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 69 { 70 if (!len) 71 return false; 72 73 if (e->bytes + len + 1 <= e->size) 74 return true; 75 76 if (e->bytes) { 77 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 78 e->iter += e->bytes; 79 e->buf = NULL; 80 e->bytes = 0; 81 } 82 83 if (e->cur == e->end) { 84 struct scatterlist *sgl; 85 86 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 87 if (!sgl) { 88 e->err = -ENOMEM; 89 return false; 90 } 91 92 if (e->cur) { 93 e->cur->offset = 0; 94 e->cur->length = 0; 95 e->cur->page_link = 96 (unsigned long)sgl | SG_CHAIN; 97 } else { 98 e->sgl = sgl; 99 } 100 101 e->cur = sgl; 102 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 103 } 104 105 e->size = ALIGN(len + 1, SZ_64K); 106 e->buf = kmalloc(e->size, ALLOW_FAIL); 107 if (!e->buf) { 108 e->size = PAGE_ALIGN(len + 1); 109 e->buf = kmalloc(e->size, GFP_KERNEL); 110 } 111 if (!e->buf) { 112 e->err = -ENOMEM; 113 return false; 114 } 115 116 return true; 117 } 118 119 __printf(2, 0) 120 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 121 const char *fmt, va_list args) 122 { 123 va_list ap; 124 int len; 125 126 if (e->err) 127 return; 128 129 va_copy(ap, args); 130 len = vsnprintf(NULL, 0, fmt, ap); 131 va_end(ap); 132 if (len <= 0) { 133 e->err = len; 134 return; 135 } 136 137 if (!__i915_error_grow(e, len)) 138 return; 139 140 GEM_BUG_ON(e->bytes >= e->size); 141 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 142 if (len < 0) { 143 e->err = len; 144 return; 145 } 146 e->bytes += len; 147 } 148 149 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 150 { 151 unsigned len; 152 153 if (e->err || !str) 154 return; 155 156 len = strlen(str); 157 if (!__i915_error_grow(e, len)) 158 return; 159 160 GEM_BUG_ON(e->bytes + len > e->size); 161 memcpy(e->buf + e->bytes, str, len); 162 e->bytes += len; 163 } 164 165 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 166 #define err_puts(e, s) i915_error_puts(e, s) 167 168 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 169 { 170 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 171 } 172 173 static inline struct drm_printer 174 i915_error_printer(struct drm_i915_error_state_buf *e) 175 { 176 struct drm_printer p = { 177 .printfn = __i915_printfn_error, 178 .arg = e, 179 }; 180 return p; 181 } 182 183 /* single threaded page allocator with a reserved stash for emergencies */ 184 static void pool_fini(struct pagevec *pv) 185 { 186 pagevec_release(pv); 187 } 188 189 static int pool_refill(struct pagevec *pv, gfp_t gfp) 190 { 191 while (pagevec_space(pv)) { 192 struct page *p; 193 194 p = alloc_page(gfp); 195 if (!p) 196 return -ENOMEM; 197 198 pagevec_add(pv, p); 199 } 200 201 return 0; 202 } 203 204 static int pool_init(struct pagevec *pv, gfp_t gfp) 205 { 206 int err; 207 208 pagevec_init(pv); 209 210 err = pool_refill(pv, gfp); 211 if (err) 212 pool_fini(pv); 213 214 return err; 215 } 216 217 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 218 { 219 struct page *p; 220 221 p = alloc_page(gfp); 222 if (!p && pagevec_count(pv)) 223 p = pv->pages[--pv->nr]; 224 225 return p ? page_address(p) : NULL; 226 } 227 228 static void pool_free(struct pagevec *pv, void *addr) 229 { 230 struct page *p = virt_to_page(addr); 231 232 if (pagevec_space(pv)) 233 pagevec_add(pv, p); 234 else 235 __free_page(p); 236 } 237 238 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 239 240 struct i915_vma_compress { 241 struct pagevec pool; 242 struct z_stream_s zstream; 243 void *tmp; 244 }; 245 246 static bool compress_init(struct i915_vma_compress *c) 247 { 248 struct z_stream_s *zstream = &c->zstream; 249 250 if (pool_init(&c->pool, ALLOW_FAIL)) 251 return false; 252 253 zstream->workspace = 254 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 255 ALLOW_FAIL); 256 if (!zstream->workspace) { 257 pool_fini(&c->pool); 258 return false; 259 } 260 261 c->tmp = NULL; 262 if (i915_has_memcpy_from_wc()) 263 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 264 265 return true; 266 } 267 268 static bool compress_start(struct i915_vma_compress *c) 269 { 270 struct z_stream_s *zstream = &c->zstream; 271 void *workspace = zstream->workspace; 272 273 memset(zstream, 0, sizeof(*zstream)); 274 zstream->workspace = workspace; 275 276 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 277 } 278 279 static void *compress_next_page(struct i915_vma_compress *c, 280 struct i915_vma_coredump *dst) 281 { 282 void *page_addr; 283 struct page *page; 284 285 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 286 if (!page_addr) 287 return ERR_PTR(-ENOMEM); 288 289 page = virt_to_page(page_addr); 290 list_add_tail(&page->lru, &dst->page_list); 291 return page_addr; 292 } 293 294 static int compress_page(struct i915_vma_compress *c, 295 void *src, 296 struct i915_vma_coredump *dst, 297 bool wc) 298 { 299 struct z_stream_s *zstream = &c->zstream; 300 301 zstream->next_in = src; 302 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 303 zstream->next_in = c->tmp; 304 zstream->avail_in = PAGE_SIZE; 305 306 do { 307 if (zstream->avail_out == 0) { 308 zstream->next_out = compress_next_page(c, dst); 309 if (IS_ERR(zstream->next_out)) 310 return PTR_ERR(zstream->next_out); 311 312 zstream->avail_out = PAGE_SIZE; 313 } 314 315 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 316 return -EIO; 317 318 cond_resched(); 319 } while (zstream->avail_in); 320 321 /* Fallback to uncompressed if we increase size? */ 322 if (0 && zstream->total_out > zstream->total_in) 323 return -E2BIG; 324 325 return 0; 326 } 327 328 static int compress_flush(struct i915_vma_compress *c, 329 struct i915_vma_coredump *dst) 330 { 331 struct z_stream_s *zstream = &c->zstream; 332 333 do { 334 switch (zlib_deflate(zstream, Z_FINISH)) { 335 case Z_OK: /* more space requested */ 336 zstream->next_out = compress_next_page(c, dst); 337 if (IS_ERR(zstream->next_out)) 338 return PTR_ERR(zstream->next_out); 339 340 zstream->avail_out = PAGE_SIZE; 341 break; 342 343 case Z_STREAM_END: 344 goto end; 345 346 default: /* any error */ 347 return -EIO; 348 } 349 } while (1); 350 351 end: 352 memset(zstream->next_out, 0, zstream->avail_out); 353 dst->unused = zstream->avail_out; 354 return 0; 355 } 356 357 static void compress_finish(struct i915_vma_compress *c) 358 { 359 zlib_deflateEnd(&c->zstream); 360 } 361 362 static void compress_fini(struct i915_vma_compress *c) 363 { 364 kfree(c->zstream.workspace); 365 if (c->tmp) 366 pool_free(&c->pool, c->tmp); 367 pool_fini(&c->pool); 368 } 369 370 static void err_compression_marker(struct drm_i915_error_state_buf *m) 371 { 372 err_puts(m, ":"); 373 } 374 375 #else 376 377 struct i915_vma_compress { 378 struct pagevec pool; 379 }; 380 381 static bool compress_init(struct i915_vma_compress *c) 382 { 383 return pool_init(&c->pool, ALLOW_FAIL) == 0; 384 } 385 386 static bool compress_start(struct i915_vma_compress *c) 387 { 388 return true; 389 } 390 391 static int compress_page(struct i915_vma_compress *c, 392 void *src, 393 struct i915_vma_coredump *dst, 394 bool wc) 395 { 396 void *ptr; 397 398 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 399 if (!ptr) 400 return -ENOMEM; 401 402 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 403 memcpy(ptr, src, PAGE_SIZE); 404 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 405 cond_resched(); 406 407 return 0; 408 } 409 410 static int compress_flush(struct i915_vma_compress *c, 411 struct i915_vma_coredump *dst) 412 { 413 return 0; 414 } 415 416 static void compress_finish(struct i915_vma_compress *c) 417 { 418 } 419 420 static void compress_fini(struct i915_vma_compress *c) 421 { 422 pool_fini(&c->pool); 423 } 424 425 static void err_compression_marker(struct drm_i915_error_state_buf *m) 426 { 427 err_puts(m, "~"); 428 } 429 430 #endif 431 432 static void error_print_instdone(struct drm_i915_error_state_buf *m, 433 const struct intel_engine_coredump *ee) 434 { 435 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 436 int slice; 437 int subslice; 438 int iter; 439 440 err_printf(m, " INSTDONE: 0x%08x\n", 441 ee->instdone.instdone); 442 443 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 444 return; 445 446 err_printf(m, " SC_INSTDONE: 0x%08x\n", 447 ee->instdone.slice_common); 448 449 if (GRAPHICS_VER(m->i915) <= 6) 450 return; 451 452 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) { 453 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 454 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 455 slice, subslice, 456 ee->instdone.sampler[slice][subslice]); 457 458 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 459 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 460 slice, subslice, 461 ee->instdone.row[slice][subslice]); 462 } else { 463 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 464 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 465 slice, subslice, 466 ee->instdone.sampler[slice][subslice]); 467 468 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 469 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 470 slice, subslice, 471 ee->instdone.row[slice][subslice]); 472 } 473 474 if (GRAPHICS_VER(m->i915) < 12) 475 return; 476 477 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 478 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 479 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 480 slice, subslice, 481 ee->instdone.geom_svg[slice][subslice]); 482 } 483 484 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 485 ee->instdone.slice_common_extra[0]); 486 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 487 ee->instdone.slice_common_extra[1]); 488 } 489 490 static void error_print_request(struct drm_i915_error_state_buf *m, 491 const char *prefix, 492 const struct i915_request_coredump *erq) 493 { 494 if (!erq->seqno) 495 return; 496 497 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 498 prefix, erq->pid, erq->context, erq->seqno, 499 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 500 &erq->flags) ? "!" : "", 501 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 502 &erq->flags) ? "+" : "", 503 erq->sched_attr.priority, 504 erq->head, erq->tail); 505 } 506 507 static void error_print_context(struct drm_i915_error_state_buf *m, 508 const char *header, 509 const struct i915_gem_context_coredump *ctx) 510 { 511 const u32 period = to_gt(m->i915)->clock_period_ns; 512 513 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 514 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 515 ctx->guilty, ctx->active, 516 ctx->total_runtime * period, 517 mul_u32_u32(ctx->avg_runtime, period)); 518 } 519 520 static struct i915_vma_coredump * 521 __find_vma(struct i915_vma_coredump *vma, const char *name) 522 { 523 while (vma) { 524 if (strcmp(vma->name, name) == 0) 525 return vma; 526 vma = vma->next; 527 } 528 529 return NULL; 530 } 531 532 static struct i915_vma_coredump * 533 find_batch(const struct intel_engine_coredump *ee) 534 { 535 return __find_vma(ee->vma, "batch"); 536 } 537 538 static void error_print_engine(struct drm_i915_error_state_buf *m, 539 const struct intel_engine_coredump *ee) 540 { 541 struct i915_vma_coredump *batch; 542 int n; 543 544 err_printf(m, "%s command stream:\n", ee->engine->name); 545 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 546 err_printf(m, " START: 0x%08x\n", ee->start); 547 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 548 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 549 ee->tail, ee->rq_post, ee->rq_tail); 550 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 551 err_printf(m, " MODE: 0x%08x\n", ee->mode); 552 err_printf(m, " HWS: 0x%08x\n", ee->hws); 553 err_printf(m, " ACTHD: 0x%08x %08x\n", 554 (u32)(ee->acthd>>32), (u32)ee->acthd); 555 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 556 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 557 err_printf(m, " ESR: 0x%08x\n", ee->esr); 558 559 error_print_instdone(m, ee); 560 561 batch = find_batch(ee); 562 if (batch) { 563 u64 start = batch->gtt_offset; 564 u64 end = start + batch->gtt_size; 565 566 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 567 upper_32_bits(start), lower_32_bits(start), 568 upper_32_bits(end), lower_32_bits(end)); 569 } 570 if (GRAPHICS_VER(m->i915) >= 4) { 571 err_printf(m, " BBADDR: 0x%08x_%08x\n", 572 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 573 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 574 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 575 } 576 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 577 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 578 lower_32_bits(ee->faddr)); 579 if (GRAPHICS_VER(m->i915) >= 6) { 580 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 581 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 582 } 583 if (HAS_PPGTT(m->i915)) { 584 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 585 586 if (GRAPHICS_VER(m->i915) >= 8) { 587 int i; 588 for (i = 0; i < 4; i++) 589 err_printf(m, " PDP%d: 0x%016llx\n", 590 i, ee->vm_info.pdp[i]); 591 } else { 592 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 593 ee->vm_info.pp_dir_base); 594 } 595 } 596 err_printf(m, " hung: %u\n", ee->hung); 597 err_printf(m, " engine reset count: %u\n", ee->reset_count); 598 599 for (n = 0; n < ee->num_ports; n++) { 600 err_printf(m, " ELSP[%d]:", n); 601 error_print_request(m, " ", &ee->execlist[n]); 602 } 603 604 error_print_context(m, " Active context: ", &ee->context); 605 } 606 607 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 608 { 609 va_list args; 610 611 va_start(args, f); 612 i915_error_vprintf(e, f, args); 613 va_end(args); 614 } 615 616 static void print_error_vma(struct drm_i915_error_state_buf *m, 617 const struct intel_engine_cs *engine, 618 const struct i915_vma_coredump *vma) 619 { 620 char out[ASCII85_BUFSZ]; 621 struct page *page; 622 623 if (!vma) 624 return; 625 626 err_printf(m, "%s --- %s = 0x%08x %08x\n", 627 engine ? engine->name : "global", vma->name, 628 upper_32_bits(vma->gtt_offset), 629 lower_32_bits(vma->gtt_offset)); 630 631 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 632 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 633 634 err_compression_marker(m); 635 list_for_each_entry(page, &vma->page_list, lru) { 636 int i, len; 637 const u32 *addr = page_address(page); 638 639 len = PAGE_SIZE; 640 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 641 len -= vma->unused; 642 len = ascii85_encode_len(len); 643 644 for (i = 0; i < len; i++) 645 err_puts(m, ascii85_encode(addr[i], out)); 646 } 647 err_puts(m, "\n"); 648 } 649 650 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 651 struct i915_gpu_coredump *error) 652 { 653 struct drm_printer p = i915_error_printer(m); 654 655 intel_device_info_print_static(&error->device_info, &p); 656 intel_device_info_print_runtime(&error->runtime_info, &p); 657 intel_driver_caps_print(&error->driver_caps, &p); 658 } 659 660 static void err_print_params(struct drm_i915_error_state_buf *m, 661 const struct i915_params *params) 662 { 663 struct drm_printer p = i915_error_printer(m); 664 665 i915_params_dump(params, &p); 666 } 667 668 static void err_print_pciid(struct drm_i915_error_state_buf *m, 669 struct drm_i915_private *i915) 670 { 671 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 672 673 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 674 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 675 err_printf(m, "PCI Subsystem: %04x:%04x\n", 676 pdev->subsystem_vendor, 677 pdev->subsystem_device); 678 } 679 680 static void err_print_uc(struct drm_i915_error_state_buf *m, 681 const struct intel_uc_coredump *error_uc) 682 { 683 struct drm_printer p = i915_error_printer(m); 684 685 intel_uc_fw_dump(&error_uc->guc_fw, &p); 686 intel_uc_fw_dump(&error_uc->huc_fw, &p); 687 print_error_vma(m, NULL, error_uc->guc_log); 688 } 689 690 static void err_free_sgl(struct scatterlist *sgl) 691 { 692 while (sgl) { 693 struct scatterlist *sg; 694 695 for (sg = sgl; !sg_is_chain(sg); sg++) { 696 kfree(sg_virt(sg)); 697 if (sg_is_last(sg)) 698 break; 699 } 700 701 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 702 free_page((unsigned long)sgl); 703 sgl = sg; 704 } 705 } 706 707 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 708 struct intel_gt_coredump *gt) 709 { 710 struct drm_printer p = i915_error_printer(m); 711 712 intel_gt_info_print(>->info, &p); 713 intel_sseu_print_topology(>->info.sseu, &p); 714 } 715 716 static void err_print_gt(struct drm_i915_error_state_buf *m, 717 struct intel_gt_coredump *gt) 718 { 719 const struct intel_engine_coredump *ee; 720 int i; 721 722 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 723 err_printf(m, "EIR: 0x%08x\n", gt->eir); 724 err_printf(m, "IER: 0x%08x\n", gt->ier); 725 for (i = 0; i < gt->ngtier; i++) 726 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 727 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 728 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 729 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 730 731 for (i = 0; i < gt->nfence; i++) 732 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 733 734 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 735 err_printf(m, "ERROR: 0x%08x\n", gt->error); 736 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 737 } 738 739 if (GRAPHICS_VER(m->i915) >= 8) 740 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 741 gt->fault_data1, gt->fault_data0); 742 743 if (GRAPHICS_VER(m->i915) == 7) 744 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 745 746 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 747 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 748 749 if (GRAPHICS_VER(m->i915) == 12) 750 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 751 752 if (GRAPHICS_VER(m->i915) >= 12) { 753 int i; 754 755 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 756 /* 757 * SFC_DONE resides in the VD forcewake domain, so it 758 * only exists if the corresponding VCS engine is 759 * present. 760 */ 761 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 762 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 763 continue; 764 765 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 766 gt->sfc_done[i]); 767 } 768 769 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 770 } 771 772 for (ee = gt->engine; ee; ee = ee->next) { 773 const struct i915_vma_coredump *vma; 774 775 error_print_engine(m, ee); 776 for (vma = ee->vma; vma; vma = vma->next) 777 print_error_vma(m, ee->engine, vma); 778 } 779 780 if (gt->uc) 781 err_print_uc(m, gt->uc); 782 783 err_print_gt_info(m, gt); 784 } 785 786 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 787 struct i915_gpu_coredump *error) 788 { 789 const struct intel_engine_coredump *ee; 790 struct timespec64 ts; 791 792 if (*error->error_msg) 793 err_printf(m, "%s\n", error->error_msg); 794 err_printf(m, "Kernel: %s %s\n", 795 init_utsname()->release, 796 init_utsname()->machine); 797 err_printf(m, "Driver: %s\n", DRIVER_DATE); 798 ts = ktime_to_timespec64(error->time); 799 err_printf(m, "Time: %lld s %ld us\n", 800 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 801 ts = ktime_to_timespec64(error->boottime); 802 err_printf(m, "Boottime: %lld s %ld us\n", 803 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 804 ts = ktime_to_timespec64(error->uptime); 805 err_printf(m, "Uptime: %lld s %ld us\n", 806 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 807 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 808 error->capture, jiffies_to_msecs(jiffies - error->capture)); 809 810 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 811 err_printf(m, "Active process (on ring %s): %s [%d]\n", 812 ee->engine->name, 813 ee->context.comm, 814 ee->context.pid); 815 816 err_printf(m, "Reset count: %u\n", error->reset_count); 817 err_printf(m, "Suspend count: %u\n", error->suspend_count); 818 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 819 err_printf(m, "Subplatform: 0x%x\n", 820 intel_subplatform(&error->runtime_info, 821 error->device_info.platform)); 822 err_print_pciid(m, m->i915); 823 824 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 825 826 if (HAS_DMC(m->i915)) { 827 struct intel_dmc *dmc = &m->i915->dmc; 828 829 err_printf(m, "DMC loaded: %s\n", 830 yesno(intel_dmc_has_payload(m->i915) != 0)); 831 err_printf(m, "DMC fw version: %d.%d\n", 832 DMC_VERSION_MAJOR(dmc->version), 833 DMC_VERSION_MINOR(dmc->version)); 834 } 835 836 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 837 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 838 839 if (error->gt) 840 err_print_gt(m, error->gt); 841 842 if (error->overlay) 843 intel_overlay_print_error_state(m, error->overlay); 844 845 err_print_capabilities(m, error); 846 err_print_params(m, &error->params); 847 } 848 849 static int err_print_to_sgl(struct i915_gpu_coredump *error) 850 { 851 struct drm_i915_error_state_buf m; 852 853 if (IS_ERR(error)) 854 return PTR_ERR(error); 855 856 if (READ_ONCE(error->sgl)) 857 return 0; 858 859 memset(&m, 0, sizeof(m)); 860 m.i915 = error->i915; 861 862 __err_print_to_sgl(&m, error); 863 864 if (m.buf) { 865 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 866 m.bytes = 0; 867 m.buf = NULL; 868 } 869 if (m.cur) { 870 GEM_BUG_ON(m.end < m.cur); 871 sg_mark_end(m.cur - 1); 872 } 873 GEM_BUG_ON(m.sgl && !m.cur); 874 875 if (m.err) { 876 err_free_sgl(m.sgl); 877 return m.err; 878 } 879 880 if (cmpxchg(&error->sgl, NULL, m.sgl)) 881 err_free_sgl(m.sgl); 882 883 return 0; 884 } 885 886 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 887 char *buf, loff_t off, size_t rem) 888 { 889 struct scatterlist *sg; 890 size_t count; 891 loff_t pos; 892 int err; 893 894 if (!error || !rem) 895 return 0; 896 897 err = err_print_to_sgl(error); 898 if (err) 899 return err; 900 901 sg = READ_ONCE(error->fit); 902 if (!sg || off < sg->dma_address) 903 sg = error->sgl; 904 if (!sg) 905 return 0; 906 907 pos = sg->dma_address; 908 count = 0; 909 do { 910 size_t len, start; 911 912 if (sg_is_chain(sg)) { 913 sg = sg_chain_ptr(sg); 914 GEM_BUG_ON(sg_is_chain(sg)); 915 } 916 917 len = sg->length; 918 if (pos + len <= off) { 919 pos += len; 920 continue; 921 } 922 923 start = sg->offset; 924 if (pos < off) { 925 GEM_BUG_ON(off - pos > len); 926 len -= off - pos; 927 start += off - pos; 928 pos = off; 929 } 930 931 len = min(len, rem); 932 GEM_BUG_ON(!len || len > sg->length); 933 934 memcpy(buf, page_address(sg_page(sg)) + start, len); 935 936 count += len; 937 pos += len; 938 939 buf += len; 940 rem -= len; 941 if (!rem) { 942 WRITE_ONCE(error->fit, sg); 943 break; 944 } 945 } while (!sg_is_last(sg++)); 946 947 return count; 948 } 949 950 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 951 { 952 while (vma) { 953 struct i915_vma_coredump *next = vma->next; 954 struct page *page, *n; 955 956 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 957 list_del_init(&page->lru); 958 __free_page(page); 959 } 960 961 kfree(vma); 962 vma = next; 963 } 964 } 965 966 static void cleanup_params(struct i915_gpu_coredump *error) 967 { 968 i915_params_free(&error->params); 969 } 970 971 static void cleanup_uc(struct intel_uc_coredump *uc) 972 { 973 kfree(uc->guc_fw.path); 974 kfree(uc->huc_fw.path); 975 i915_vma_coredump_free(uc->guc_log); 976 977 kfree(uc); 978 } 979 980 static void cleanup_gt(struct intel_gt_coredump *gt) 981 { 982 while (gt->engine) { 983 struct intel_engine_coredump *ee = gt->engine; 984 985 gt->engine = ee->next; 986 987 i915_vma_coredump_free(ee->vma); 988 kfree(ee); 989 } 990 991 if (gt->uc) 992 cleanup_uc(gt->uc); 993 994 kfree(gt); 995 } 996 997 void __i915_gpu_coredump_free(struct kref *error_ref) 998 { 999 struct i915_gpu_coredump *error = 1000 container_of(error_ref, typeof(*error), ref); 1001 1002 while (error->gt) { 1003 struct intel_gt_coredump *gt = error->gt; 1004 1005 error->gt = gt->next; 1006 cleanup_gt(gt); 1007 } 1008 1009 kfree(error->overlay); 1010 1011 cleanup_params(error); 1012 1013 err_free_sgl(error->sgl); 1014 kfree(error); 1015 } 1016 1017 static struct i915_vma_coredump * 1018 i915_vma_coredump_create(const struct intel_gt *gt, 1019 const struct i915_vma_resource *vma_res, 1020 struct i915_vma_compress *compress, 1021 const char *name) 1022 1023 { 1024 struct i915_ggtt *ggtt = gt->ggtt; 1025 const u64 slot = ggtt->error_capture.start; 1026 struct i915_vma_coredump *dst; 1027 struct sgt_iter iter; 1028 int ret; 1029 1030 might_sleep(); 1031 1032 if (!vma_res || !vma_res->bi.pages || !compress) 1033 return NULL; 1034 1035 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1036 if (!dst) 1037 return NULL; 1038 1039 if (!compress_start(compress)) { 1040 kfree(dst); 1041 return NULL; 1042 } 1043 1044 INIT_LIST_HEAD(&dst->page_list); 1045 strcpy(dst->name, name); 1046 dst->next = NULL; 1047 1048 dst->gtt_offset = vma_res->start; 1049 dst->gtt_size = vma_res->node_size; 1050 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1051 dst->unused = 0; 1052 1053 ret = -EINVAL; 1054 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1055 void __iomem *s; 1056 dma_addr_t dma; 1057 1058 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1059 mutex_lock(&ggtt->error_mutex); 1060 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1061 I915_CACHE_NONE, 0); 1062 mb(); 1063 1064 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1065 ret = compress_page(compress, 1066 (void __force *)s, dst, 1067 true); 1068 io_mapping_unmap(s); 1069 1070 mb(); 1071 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1072 mutex_unlock(&ggtt->error_mutex); 1073 if (ret) 1074 break; 1075 } 1076 } else if (vma_res->bi.lmem) { 1077 struct intel_memory_region *mem = vma_res->mr; 1078 dma_addr_t dma; 1079 1080 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1081 void __iomem *s; 1082 1083 s = io_mapping_map_wc(&mem->iomap, 1084 dma - mem->region.start, 1085 PAGE_SIZE); 1086 ret = compress_page(compress, 1087 (void __force *)s, dst, 1088 true); 1089 io_mapping_unmap(s); 1090 if (ret) 1091 break; 1092 } 1093 } else { 1094 struct page *page; 1095 1096 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1097 void *s; 1098 1099 drm_clflush_pages(&page, 1); 1100 1101 s = kmap(page); 1102 ret = compress_page(compress, s, dst, false); 1103 kunmap(page); 1104 1105 drm_clflush_pages(&page, 1); 1106 1107 if (ret) 1108 break; 1109 } 1110 } 1111 1112 if (ret || compress_flush(compress, dst)) { 1113 struct page *page, *n; 1114 1115 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1116 list_del_init(&page->lru); 1117 pool_free(&compress->pool, page_address(page)); 1118 } 1119 1120 kfree(dst); 1121 dst = NULL; 1122 } 1123 compress_finish(compress); 1124 1125 return dst; 1126 } 1127 1128 static void gt_record_fences(struct intel_gt_coredump *gt) 1129 { 1130 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1131 struct intel_uncore *uncore = gt->_gt->uncore; 1132 int i; 1133 1134 if (GRAPHICS_VER(uncore->i915) >= 6) { 1135 for (i = 0; i < ggtt->num_fences; i++) 1136 gt->fence[i] = 1137 intel_uncore_read64(uncore, 1138 FENCE_REG_GEN6_LO(i)); 1139 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1140 for (i = 0; i < ggtt->num_fences; i++) 1141 gt->fence[i] = 1142 intel_uncore_read64(uncore, 1143 FENCE_REG_965_LO(i)); 1144 } else { 1145 for (i = 0; i < ggtt->num_fences; i++) 1146 gt->fence[i] = 1147 intel_uncore_read(uncore, FENCE_REG(i)); 1148 } 1149 gt->nfence = i; 1150 } 1151 1152 static void engine_record_registers(struct intel_engine_coredump *ee) 1153 { 1154 const struct intel_engine_cs *engine = ee->engine; 1155 struct drm_i915_private *i915 = engine->i915; 1156 1157 if (GRAPHICS_VER(i915) >= 6) { 1158 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1159 1160 if (GRAPHICS_VER(i915) >= 12) 1161 ee->fault_reg = intel_uncore_read(engine->uncore, 1162 GEN12_RING_FAULT_REG); 1163 else if (GRAPHICS_VER(i915) >= 8) 1164 ee->fault_reg = intel_uncore_read(engine->uncore, 1165 GEN8_RING_FAULT_REG); 1166 else 1167 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1168 } 1169 1170 if (GRAPHICS_VER(i915) >= 4) { 1171 ee->esr = ENGINE_READ(engine, RING_ESR); 1172 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1173 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1174 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1175 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1176 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1177 ee->ccid = ENGINE_READ(engine, CCID); 1178 if (GRAPHICS_VER(i915) >= 8) { 1179 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1180 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1181 } 1182 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1183 } else { 1184 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1185 ee->ipeir = ENGINE_READ(engine, IPEIR); 1186 ee->ipehr = ENGINE_READ(engine, IPEHR); 1187 } 1188 1189 intel_engine_get_instdone(engine, &ee->instdone); 1190 1191 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1192 ee->acthd = intel_engine_get_active_head(engine); 1193 ee->start = ENGINE_READ(engine, RING_START); 1194 ee->head = ENGINE_READ(engine, RING_HEAD); 1195 ee->tail = ENGINE_READ(engine, RING_TAIL); 1196 ee->ctl = ENGINE_READ(engine, RING_CTL); 1197 if (GRAPHICS_VER(i915) > 2) 1198 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1199 1200 if (!HWS_NEEDS_PHYSICAL(i915)) { 1201 i915_reg_t mmio; 1202 1203 if (GRAPHICS_VER(i915) == 7) { 1204 switch (engine->id) { 1205 default: 1206 MISSING_CASE(engine->id); 1207 fallthrough; 1208 case RCS0: 1209 mmio = RENDER_HWS_PGA_GEN7; 1210 break; 1211 case BCS0: 1212 mmio = BLT_HWS_PGA_GEN7; 1213 break; 1214 case VCS0: 1215 mmio = BSD_HWS_PGA_GEN7; 1216 break; 1217 case VECS0: 1218 mmio = VEBOX_HWS_PGA_GEN7; 1219 break; 1220 } 1221 } else if (GRAPHICS_VER(engine->i915) == 6) { 1222 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1223 } else { 1224 /* XXX: gen8 returns to sanity */ 1225 mmio = RING_HWS_PGA(engine->mmio_base); 1226 } 1227 1228 ee->hws = intel_uncore_read(engine->uncore, mmio); 1229 } 1230 1231 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1232 1233 if (HAS_PPGTT(i915)) { 1234 int i; 1235 1236 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1237 1238 if (GRAPHICS_VER(i915) == 6) { 1239 ee->vm_info.pp_dir_base = 1240 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1241 } else if (GRAPHICS_VER(i915) == 7) { 1242 ee->vm_info.pp_dir_base = 1243 ENGINE_READ(engine, RING_PP_DIR_BASE); 1244 } else if (GRAPHICS_VER(i915) >= 8) { 1245 u32 base = engine->mmio_base; 1246 1247 for (i = 0; i < 4; i++) { 1248 ee->vm_info.pdp[i] = 1249 intel_uncore_read(engine->uncore, 1250 GEN8_RING_PDP_UDW(base, i)); 1251 ee->vm_info.pdp[i] <<= 32; 1252 ee->vm_info.pdp[i] |= 1253 intel_uncore_read(engine->uncore, 1254 GEN8_RING_PDP_LDW(base, i)); 1255 } 1256 } 1257 } 1258 } 1259 1260 static void record_request(const struct i915_request *request, 1261 struct i915_request_coredump *erq) 1262 { 1263 erq->flags = request->fence.flags; 1264 erq->context = request->fence.context; 1265 erq->seqno = request->fence.seqno; 1266 erq->sched_attr = request->sched.attr; 1267 erq->head = request->head; 1268 erq->tail = request->tail; 1269 1270 erq->pid = 0; 1271 rcu_read_lock(); 1272 if (!intel_context_is_closed(request->context)) { 1273 const struct i915_gem_context *ctx; 1274 1275 ctx = rcu_dereference(request->context->gem_context); 1276 if (ctx) 1277 erq->pid = pid_nr(ctx->pid); 1278 } 1279 rcu_read_unlock(); 1280 } 1281 1282 static void engine_record_execlists(struct intel_engine_coredump *ee) 1283 { 1284 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1285 struct i915_request * const *port = el->active; 1286 unsigned int n = 0; 1287 1288 while (*port) 1289 record_request(*port++, &ee->execlist[n++]); 1290 1291 ee->num_ports = n; 1292 } 1293 1294 static bool record_context(struct i915_gem_context_coredump *e, 1295 const struct i915_request *rq) 1296 { 1297 struct i915_gem_context *ctx; 1298 struct task_struct *task; 1299 bool simulated; 1300 1301 rcu_read_lock(); 1302 ctx = rcu_dereference(rq->context->gem_context); 1303 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1304 ctx = NULL; 1305 rcu_read_unlock(); 1306 if (!ctx) 1307 return true; 1308 1309 rcu_read_lock(); 1310 task = pid_task(ctx->pid, PIDTYPE_PID); 1311 if (task) { 1312 strcpy(e->comm, task->comm); 1313 e->pid = task->pid; 1314 } 1315 rcu_read_unlock(); 1316 1317 e->sched_attr = ctx->sched; 1318 e->guilty = atomic_read(&ctx->guilty_count); 1319 e->active = atomic_read(&ctx->active_count); 1320 1321 e->total_runtime = rq->context->runtime.total; 1322 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1323 1324 simulated = i915_gem_context_no_error_capture(ctx); 1325 1326 i915_gem_context_put(ctx); 1327 return simulated; 1328 } 1329 1330 struct intel_engine_capture_vma { 1331 struct intel_engine_capture_vma *next; 1332 struct i915_vma_resource *vma_res; 1333 char name[16]; 1334 bool lockdep_cookie; 1335 }; 1336 1337 static struct intel_engine_capture_vma * 1338 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1339 struct i915_vma_resource *vma_res, 1340 gfp_t gfp, const char *name) 1341 { 1342 struct intel_engine_capture_vma *c; 1343 1344 if (!vma_res) 1345 return next; 1346 1347 c = kmalloc(sizeof(*c), gfp); 1348 if (!c) 1349 return next; 1350 1351 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1352 kfree(c); 1353 return next; 1354 } 1355 1356 strcpy(c->name, name); 1357 c->vma_res = i915_vma_resource_get(vma_res); 1358 1359 c->next = next; 1360 return c; 1361 } 1362 1363 static struct intel_engine_capture_vma * 1364 capture_vma(struct intel_engine_capture_vma *next, 1365 struct i915_vma *vma, 1366 const char *name, 1367 gfp_t gfp) 1368 { 1369 if (!vma) 1370 return next; 1371 1372 /* 1373 * If the vma isn't pinned, then the vma should be snapshotted 1374 * to a struct i915_vma_snapshot at command submission time. 1375 * Not here. 1376 */ 1377 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1378 return next; 1379 1380 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1381 1382 return next; 1383 } 1384 1385 static struct intel_engine_capture_vma * 1386 capture_user(struct intel_engine_capture_vma *capture, 1387 const struct i915_request *rq, 1388 gfp_t gfp) 1389 { 1390 struct i915_capture_list *c; 1391 1392 for (c = rq->capture_list; c; c = c->next) 1393 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1394 "user"); 1395 1396 return capture; 1397 } 1398 1399 static void add_vma(struct intel_engine_coredump *ee, 1400 struct i915_vma_coredump *vma) 1401 { 1402 if (vma) { 1403 vma->next = ee->vma; 1404 ee->vma = vma; 1405 } 1406 } 1407 1408 static struct i915_vma_coredump * 1409 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1410 const char *name, struct i915_vma_compress *compress) 1411 { 1412 struct i915_vma_coredump *ret = NULL; 1413 struct i915_vma_resource *vma_res; 1414 bool lockdep_cookie; 1415 1416 if (!vma) 1417 return NULL; 1418 1419 vma_res = vma->resource; 1420 1421 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1422 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1423 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1424 } 1425 1426 return ret; 1427 } 1428 1429 static void add_vma_coredump(struct intel_engine_coredump *ee, 1430 const struct intel_gt *gt, 1431 struct i915_vma *vma, 1432 const char *name, 1433 struct i915_vma_compress *compress) 1434 { 1435 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1436 } 1437 1438 struct intel_engine_coredump * 1439 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1440 { 1441 struct intel_engine_coredump *ee; 1442 1443 ee = kzalloc(sizeof(*ee), gfp); 1444 if (!ee) 1445 return NULL; 1446 1447 ee->engine = engine; 1448 1449 engine_record_registers(ee); 1450 engine_record_execlists(ee); 1451 1452 return ee; 1453 } 1454 1455 struct intel_engine_capture_vma * 1456 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1457 struct i915_request *rq, 1458 gfp_t gfp) 1459 { 1460 struct intel_engine_capture_vma *vma = NULL; 1461 1462 ee->simulated |= record_context(&ee->context, rq); 1463 if (ee->simulated) 1464 return NULL; 1465 1466 /* 1467 * We need to copy these to an anonymous buffer 1468 * as the simplest method to avoid being overwritten 1469 * by userspace. 1470 */ 1471 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1472 vma = capture_user(vma, rq, gfp); 1473 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1474 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1475 1476 ee->rq_head = rq->head; 1477 ee->rq_post = rq->postfix; 1478 ee->rq_tail = rq->tail; 1479 1480 return vma; 1481 } 1482 1483 void 1484 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1485 struct intel_engine_capture_vma *capture, 1486 struct i915_vma_compress *compress) 1487 { 1488 const struct intel_engine_cs *engine = ee->engine; 1489 1490 while (capture) { 1491 struct intel_engine_capture_vma *this = capture; 1492 struct i915_vma_resource *vma_res = this->vma_res; 1493 1494 add_vma(ee, 1495 i915_vma_coredump_create(engine->gt, vma_res, 1496 compress, this->name)); 1497 1498 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1499 i915_vma_resource_put(vma_res); 1500 1501 capture = this->next; 1502 kfree(this); 1503 } 1504 1505 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1506 "HW Status", compress); 1507 1508 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1509 "WA context", compress); 1510 } 1511 1512 static struct intel_engine_coredump * 1513 capture_engine(struct intel_engine_cs *engine, 1514 struct i915_vma_compress *compress) 1515 { 1516 struct intel_engine_capture_vma *capture = NULL; 1517 struct intel_engine_coredump *ee; 1518 struct intel_context *ce; 1519 struct i915_request *rq = NULL; 1520 unsigned long flags; 1521 1522 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL); 1523 if (!ee) 1524 return NULL; 1525 1526 ce = intel_engine_get_hung_context(engine); 1527 if (ce) { 1528 intel_engine_clear_hung_context(engine); 1529 rq = intel_context_find_active_request(ce); 1530 if (!rq || !i915_request_started(rq)) 1531 goto no_request_capture; 1532 } else { 1533 /* 1534 * Getting here with GuC enabled means it is a forced error capture 1535 * with no actual hang. So, no need to attempt the execlist search. 1536 */ 1537 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1538 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1539 rq = intel_engine_execlist_find_hung_request(engine); 1540 spin_unlock_irqrestore(&engine->sched_engine->lock, 1541 flags); 1542 } 1543 } 1544 if (rq) 1545 rq = i915_request_get_rcu(rq); 1546 1547 if (!rq) 1548 goto no_request_capture; 1549 1550 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1551 if (!capture) { 1552 i915_request_put(rq); 1553 goto no_request_capture; 1554 } 1555 1556 intel_engine_coredump_add_vma(ee, capture, compress); 1557 i915_request_put(rq); 1558 1559 return ee; 1560 1561 no_request_capture: 1562 kfree(ee); 1563 return NULL; 1564 } 1565 1566 static void 1567 gt_record_engines(struct intel_gt_coredump *gt, 1568 intel_engine_mask_t engine_mask, 1569 struct i915_vma_compress *compress) 1570 { 1571 struct intel_engine_cs *engine; 1572 enum intel_engine_id id; 1573 1574 for_each_engine(engine, gt->_gt, id) { 1575 struct intel_engine_coredump *ee; 1576 1577 /* Refill our page pool before entering atomic section */ 1578 pool_refill(&compress->pool, ALLOW_FAIL); 1579 1580 ee = capture_engine(engine, compress); 1581 if (!ee) 1582 continue; 1583 1584 ee->hung = engine->mask & engine_mask; 1585 1586 gt->simulated |= ee->simulated; 1587 if (ee->simulated) { 1588 kfree(ee); 1589 continue; 1590 } 1591 1592 ee->next = gt->engine; 1593 gt->engine = ee; 1594 } 1595 } 1596 1597 static struct intel_uc_coredump * 1598 gt_record_uc(struct intel_gt_coredump *gt, 1599 struct i915_vma_compress *compress) 1600 { 1601 const struct intel_uc *uc = >->_gt->uc; 1602 struct intel_uc_coredump *error_uc; 1603 1604 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1605 if (!error_uc) 1606 return NULL; 1607 1608 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1609 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1610 1611 /* Non-default firmware paths will be specified by the modparam. 1612 * As modparams are generally accesible from the userspace make 1613 * explicit copies of the firmware paths. 1614 */ 1615 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1616 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1617 error_uc->guc_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1618 "GuC log buffer", compress); 1619 1620 return error_uc; 1621 } 1622 1623 /* Capture all registers which don't fit into another category. */ 1624 static void gt_record_regs(struct intel_gt_coredump *gt) 1625 { 1626 struct intel_uncore *uncore = gt->_gt->uncore; 1627 struct drm_i915_private *i915 = uncore->i915; 1628 int i; 1629 1630 /* 1631 * General organization 1632 * 1. Registers specific to a single generation 1633 * 2. Registers which belong to multiple generations 1634 * 3. Feature specific registers. 1635 * 4. Everything else 1636 * Please try to follow the order. 1637 */ 1638 1639 /* 1: Registers specific to a single generation */ 1640 if (IS_VALLEYVIEW(i915)) { 1641 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1642 gt->ier = intel_uncore_read(uncore, VLV_IER); 1643 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1644 } 1645 1646 if (GRAPHICS_VER(i915) == 7) 1647 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1648 1649 if (GRAPHICS_VER(i915) >= 12) { 1650 gt->fault_data0 = intel_uncore_read(uncore, 1651 GEN12_FAULT_TLB_DATA0); 1652 gt->fault_data1 = intel_uncore_read(uncore, 1653 GEN12_FAULT_TLB_DATA1); 1654 } else if (GRAPHICS_VER(i915) >= 8) { 1655 gt->fault_data0 = intel_uncore_read(uncore, 1656 GEN8_FAULT_TLB_DATA0); 1657 gt->fault_data1 = intel_uncore_read(uncore, 1658 GEN8_FAULT_TLB_DATA1); 1659 } 1660 1661 if (GRAPHICS_VER(i915) == 6) { 1662 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1663 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1664 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1665 } 1666 1667 /* 2: Registers which belong to multiple generations */ 1668 if (GRAPHICS_VER(i915) >= 7) 1669 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1670 1671 if (GRAPHICS_VER(i915) >= 6) { 1672 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1673 if (GRAPHICS_VER(i915) < 12) { 1674 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1675 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1676 } 1677 } 1678 1679 /* 3: Feature specific registers */ 1680 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1681 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1682 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1683 } 1684 1685 if (IS_GRAPHICS_VER(i915, 8, 11)) 1686 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1687 1688 if (GRAPHICS_VER(i915) == 12) 1689 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1690 1691 if (GRAPHICS_VER(i915) >= 12) { 1692 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1693 /* 1694 * SFC_DONE resides in the VD forcewake domain, so it 1695 * only exists if the corresponding VCS engine is 1696 * present. 1697 */ 1698 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1699 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1700 continue; 1701 1702 gt->sfc_done[i] = 1703 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1704 } 1705 1706 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1707 } 1708 1709 /* 4: Everything else */ 1710 if (GRAPHICS_VER(i915) >= 11) { 1711 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1712 gt->gtier[0] = 1713 intel_uncore_read(uncore, 1714 GEN11_RENDER_COPY_INTR_ENABLE); 1715 gt->gtier[1] = 1716 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1717 gt->gtier[2] = 1718 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1719 gt->gtier[3] = 1720 intel_uncore_read(uncore, 1721 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1722 gt->gtier[4] = 1723 intel_uncore_read(uncore, 1724 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1725 gt->gtier[5] = 1726 intel_uncore_read(uncore, 1727 GEN11_GUNIT_CSME_INTR_ENABLE); 1728 gt->ngtier = 6; 1729 } else if (GRAPHICS_VER(i915) >= 8) { 1730 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1731 for (i = 0; i < 4; i++) 1732 gt->gtier[i] = 1733 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1734 gt->ngtier = 4; 1735 } else if (HAS_PCH_SPLIT(i915)) { 1736 gt->ier = intel_uncore_read(uncore, DEIER); 1737 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1738 gt->ngtier = 1; 1739 } else if (GRAPHICS_VER(i915) == 2) { 1740 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1741 } else if (!IS_VALLEYVIEW(i915)) { 1742 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1743 } 1744 gt->eir = intel_uncore_read(uncore, EIR); 1745 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1746 } 1747 1748 static void gt_record_info(struct intel_gt_coredump *gt) 1749 { 1750 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1751 } 1752 1753 /* 1754 * Generate a semi-unique error code. The code is not meant to have meaning, The 1755 * code's only purpose is to try to prevent false duplicated bug reports by 1756 * grossly estimating a GPU error state. 1757 * 1758 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1759 * the hang if we could strip the GTT offset information from it. 1760 * 1761 * It's only a small step better than a random number in its current form. 1762 */ 1763 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1764 { 1765 /* 1766 * IPEHR would be an ideal way to detect errors, as it's the gross 1767 * measure of "the command that hung." However, has some very common 1768 * synchronization commands which almost always appear in the case 1769 * strictly a client bug. Use instdone to differentiate those some. 1770 */ 1771 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1772 } 1773 1774 static const char *error_msg(struct i915_gpu_coredump *error) 1775 { 1776 struct intel_engine_coredump *first = NULL; 1777 unsigned int hung_classes = 0; 1778 struct intel_gt_coredump *gt; 1779 int len; 1780 1781 for (gt = error->gt; gt; gt = gt->next) { 1782 struct intel_engine_coredump *cs; 1783 1784 for (cs = gt->engine; cs; cs = cs->next) { 1785 if (cs->hung) { 1786 hung_classes |= BIT(cs->engine->uabi_class); 1787 if (!first) 1788 first = cs; 1789 } 1790 } 1791 } 1792 1793 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1794 "GPU HANG: ecode %d:%x:%08x", 1795 GRAPHICS_VER(error->i915), hung_classes, 1796 generate_ecode(first)); 1797 if (first && first->context.pid) { 1798 /* Just show the first executing process, more is confusing */ 1799 len += scnprintf(error->error_msg + len, 1800 sizeof(error->error_msg) - len, 1801 ", in %s [%d]", 1802 first->context.comm, first->context.pid); 1803 } 1804 1805 return error->error_msg; 1806 } 1807 1808 static void capture_gen(struct i915_gpu_coredump *error) 1809 { 1810 struct drm_i915_private *i915 = error->i915; 1811 1812 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1813 error->suspended = i915->runtime_pm.suspended; 1814 1815 error->iommu = intel_vtd_active(i915); 1816 error->reset_count = i915_reset_count(&i915->gpu_error); 1817 error->suspend_count = i915->suspend_count; 1818 1819 i915_params_copy(&error->params, &i915->params); 1820 memcpy(&error->device_info, 1821 INTEL_INFO(i915), 1822 sizeof(error->device_info)); 1823 memcpy(&error->runtime_info, 1824 RUNTIME_INFO(i915), 1825 sizeof(error->runtime_info)); 1826 error->driver_caps = i915->caps; 1827 } 1828 1829 struct i915_gpu_coredump * 1830 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1831 { 1832 struct i915_gpu_coredump *error; 1833 1834 if (!i915->params.error_capture) 1835 return NULL; 1836 1837 error = kzalloc(sizeof(*error), gfp); 1838 if (!error) 1839 return NULL; 1840 1841 kref_init(&error->ref); 1842 error->i915 = i915; 1843 1844 error->time = ktime_get_real(); 1845 error->boottime = ktime_get_boottime(); 1846 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1847 error->capture = jiffies; 1848 1849 capture_gen(error); 1850 1851 return error; 1852 } 1853 1854 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1855 1856 struct intel_gt_coredump * 1857 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1858 { 1859 struct intel_gt_coredump *gc; 1860 1861 gc = kzalloc(sizeof(*gc), gfp); 1862 if (!gc) 1863 return NULL; 1864 1865 gc->_gt = gt; 1866 gc->awake = intel_gt_pm_is_awake(gt); 1867 1868 gt_record_regs(gc); 1869 gt_record_fences(gc); 1870 1871 return gc; 1872 } 1873 1874 struct i915_vma_compress * 1875 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1876 { 1877 struct i915_vma_compress *compress; 1878 1879 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1880 if (!compress) 1881 return NULL; 1882 1883 if (!compress_init(compress)) { 1884 kfree(compress); 1885 return NULL; 1886 } 1887 1888 return compress; 1889 } 1890 1891 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1892 struct i915_vma_compress *compress) 1893 { 1894 if (!compress) 1895 return; 1896 1897 compress_fini(compress); 1898 kfree(compress); 1899 } 1900 1901 static struct i915_gpu_coredump * 1902 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1903 { 1904 struct drm_i915_private *i915 = gt->i915; 1905 struct i915_gpu_coredump *error; 1906 1907 /* Check if GPU capture has been disabled */ 1908 error = READ_ONCE(i915->gpu_error.first_error); 1909 if (IS_ERR(error)) 1910 return error; 1911 1912 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1913 if (!error) 1914 return ERR_PTR(-ENOMEM); 1915 1916 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL); 1917 if (error->gt) { 1918 struct i915_vma_compress *compress; 1919 1920 compress = i915_vma_capture_prepare(error->gt); 1921 if (!compress) { 1922 kfree(error->gt); 1923 kfree(error); 1924 return ERR_PTR(-ENOMEM); 1925 } 1926 1927 gt_record_info(error->gt); 1928 gt_record_engines(error->gt, engine_mask, compress); 1929 1930 if (INTEL_INFO(i915)->has_gt_uc) 1931 error->gt->uc = gt_record_uc(error->gt, compress); 1932 1933 i915_vma_capture_finish(error->gt, compress); 1934 1935 error->simulated |= error->gt->simulated; 1936 } 1937 1938 error->overlay = intel_overlay_capture_error_state(i915); 1939 1940 return error; 1941 } 1942 1943 struct i915_gpu_coredump * 1944 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1945 { 1946 static DEFINE_MUTEX(capture_mutex); 1947 int ret = mutex_lock_interruptible(&capture_mutex); 1948 struct i915_gpu_coredump *dump; 1949 1950 if (ret) 1951 return ERR_PTR(ret); 1952 1953 dump = __i915_gpu_coredump(gt, engine_mask); 1954 mutex_unlock(&capture_mutex); 1955 1956 return dump; 1957 } 1958 1959 void i915_error_state_store(struct i915_gpu_coredump *error) 1960 { 1961 struct drm_i915_private *i915; 1962 static bool warned; 1963 1964 if (IS_ERR_OR_NULL(error)) 1965 return; 1966 1967 i915 = error->i915; 1968 drm_info(&i915->drm, "%s\n", error_msg(error)); 1969 1970 if (error->simulated || 1971 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1972 return; 1973 1974 i915_gpu_coredump_get(error); 1975 1976 if (!xchg(&warned, true) && 1977 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1978 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1979 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1980 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1981 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1982 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1983 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1984 i915->drm.primary->index); 1985 } 1986 } 1987 1988 /** 1989 * i915_capture_error_state - capture an error record for later analysis 1990 * @gt: intel_gt which originated the hang 1991 * @engine_mask: hung engines 1992 * 1993 * 1994 * Should be called when an error is detected (either a hang or an error 1995 * interrupt) to capture error state from the time of the error. Fills 1996 * out a structure which becomes available in debugfs for user level tools 1997 * to pick up. 1998 */ 1999 void i915_capture_error_state(struct intel_gt *gt, 2000 intel_engine_mask_t engine_mask) 2001 { 2002 struct i915_gpu_coredump *error; 2003 2004 error = i915_gpu_coredump(gt, engine_mask); 2005 if (IS_ERR(error)) { 2006 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2007 return; 2008 } 2009 2010 i915_error_state_store(error); 2011 i915_gpu_coredump_put(error); 2012 } 2013 2014 struct i915_gpu_coredump * 2015 i915_first_error_state(struct drm_i915_private *i915) 2016 { 2017 struct i915_gpu_coredump *error; 2018 2019 spin_lock_irq(&i915->gpu_error.lock); 2020 error = i915->gpu_error.first_error; 2021 if (!IS_ERR_OR_NULL(error)) 2022 i915_gpu_coredump_get(error); 2023 spin_unlock_irq(&i915->gpu_error.lock); 2024 2025 return error; 2026 } 2027 2028 void i915_reset_error_state(struct drm_i915_private *i915) 2029 { 2030 struct i915_gpu_coredump *error; 2031 2032 spin_lock_irq(&i915->gpu_error.lock); 2033 error = i915->gpu_error.first_error; 2034 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2035 i915->gpu_error.first_error = NULL; 2036 spin_unlock_irq(&i915->gpu_error.lock); 2037 2038 if (!IS_ERR_OR_NULL(error)) 2039 i915_gpu_coredump_put(error); 2040 } 2041 2042 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2043 { 2044 spin_lock_irq(&i915->gpu_error.lock); 2045 if (!i915->gpu_error.first_error) 2046 i915->gpu_error.first_error = ERR_PTR(err); 2047 spin_unlock_irq(&i915->gpu_error.lock); 2048 } 2049