1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include "i915_drv.h" 32 33 static const char *yesno(int v) 34 { 35 return v ? "yes" : "no"; 36 } 37 38 static const char *ring_str(int ring) 39 { 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 case VCS2: return "bsd2"; 46 default: return ""; 47 } 48 } 49 50 static const char *pin_flag(int pinned) 51 { 52 if (pinned > 0) 53 return " P"; 54 else if (pinned < 0) 55 return " p"; 56 else 57 return ""; 58 } 59 60 static const char *tiling_flag(int tiling) 61 { 62 switch (tiling) { 63 default: 64 case I915_TILING_NONE: return ""; 65 case I915_TILING_X: return " X"; 66 case I915_TILING_Y: return " Y"; 67 } 68 } 69 70 static const char *dirty_flag(int dirty) 71 { 72 return dirty ? " dirty" : ""; 73 } 74 75 static const char *purgeable_flag(int purgeable) 76 { 77 return purgeable ? " purgeable" : ""; 78 } 79 80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 81 { 82 83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 84 e->err = -ENOSPC; 85 return false; 86 } 87 88 if (e->bytes == e->size - 1 || e->err) 89 return false; 90 91 return true; 92 } 93 94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 95 unsigned len) 96 { 97 if (e->pos + len <= e->start) { 98 e->pos += len; 99 return false; 100 } 101 102 /* First vsnprintf needs to fit in its entirety for memmove */ 103 if (len >= e->size) { 104 e->err = -EIO; 105 return false; 106 } 107 108 return true; 109 } 110 111 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 112 unsigned len) 113 { 114 /* If this is first printf in this window, adjust it so that 115 * start position matches start of the buffer 116 */ 117 118 if (e->pos < e->start) { 119 const size_t off = e->start - e->pos; 120 121 /* Should not happen but be paranoid */ 122 if (off > len || e->bytes) { 123 e->err = -EIO; 124 return; 125 } 126 127 memmove(e->buf, e->buf + off, len - off); 128 e->bytes = len - off; 129 e->pos = e->start; 130 return; 131 } 132 133 e->bytes += len; 134 e->pos += len; 135 } 136 137 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 138 const char *f, va_list args) 139 { 140 unsigned len; 141 142 if (!__i915_error_ok(e)) 143 return; 144 145 /* Seek the first printf which is hits start position */ 146 if (e->pos < e->start) { 147 va_list tmp; 148 149 va_copy(tmp, args); 150 len = vsnprintf(NULL, 0, f, tmp); 151 va_end(tmp); 152 153 if (!__i915_error_seek(e, len)) 154 return; 155 } 156 157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 158 if (len >= e->size - e->bytes) 159 len = e->size - e->bytes - 1; 160 161 __i915_error_advance(e, len); 162 } 163 164 static void i915_error_puts(struct drm_i915_error_state_buf *e, 165 const char *str) 166 { 167 unsigned len; 168 169 if (!__i915_error_ok(e)) 170 return; 171 172 len = strlen(str); 173 174 /* Seek the first printf which is hits start position */ 175 if (e->pos < e->start) { 176 if (!__i915_error_seek(e, len)) 177 return; 178 } 179 180 if (len >= e->size - e->bytes) 181 len = e->size - e->bytes - 1; 182 memcpy(e->buf + e->bytes, str, len); 183 184 __i915_error_advance(e, len); 185 } 186 187 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 188 #define err_puts(e, s) i915_error_puts(e, s) 189 190 static void print_error_buffers(struct drm_i915_error_state_buf *m, 191 const char *name, 192 struct drm_i915_error_buffer *err, 193 int count) 194 { 195 err_printf(m, "%s [%d]:\n", name, count); 196 197 while (count--) { 198 err_printf(m, " %08x %8u %02x %02x %x %x", 199 err->gtt_offset, 200 err->size, 201 err->read_domains, 202 err->write_domain, 203 err->rseqno, err->wseqno); 204 err_puts(m, pin_flag(err->pinned)); 205 err_puts(m, tiling_flag(err->tiling)); 206 err_puts(m, dirty_flag(err->dirty)); 207 err_puts(m, purgeable_flag(err->purgeable)); 208 err_puts(m, err->userptr ? " userptr" : ""); 209 err_puts(m, err->ring != -1 ? " " : ""); 210 err_puts(m, ring_str(err->ring)); 211 err_puts(m, i915_cache_level_str(err->cache_level)); 212 213 if (err->name) 214 err_printf(m, " (name: %d)", err->name); 215 if (err->fence_reg != I915_FENCE_REG_NONE) 216 err_printf(m, " (fence: %d)", err->fence_reg); 217 218 err_puts(m, "\n"); 219 err++; 220 } 221 } 222 223 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 224 { 225 switch (a) { 226 case HANGCHECK_IDLE: 227 return "idle"; 228 case HANGCHECK_WAIT: 229 return "wait"; 230 case HANGCHECK_ACTIVE: 231 return "active"; 232 case HANGCHECK_ACTIVE_LOOP: 233 return "active (loop)"; 234 case HANGCHECK_KICK: 235 return "kick"; 236 case HANGCHECK_HUNG: 237 return "hung"; 238 } 239 240 return "unknown"; 241 } 242 243 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 244 struct drm_device *dev, 245 struct drm_i915_error_ring *ring) 246 { 247 if (!ring->valid) 248 return; 249 250 err_printf(m, " HEAD: 0x%08x\n", ring->head); 251 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 252 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 253 err_printf(m, " HWS: 0x%08x\n", ring->hws); 254 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 255 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 256 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 257 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 258 if (INTEL_INFO(dev)->gen >= 4) { 259 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 260 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 261 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 262 } 263 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 264 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 265 lower_32_bits(ring->faddr)); 266 if (INTEL_INFO(dev)->gen >= 6) { 267 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 268 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 269 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 270 ring->semaphore_mboxes[0], 271 ring->semaphore_seqno[0]); 272 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 273 ring->semaphore_mboxes[1], 274 ring->semaphore_seqno[1]); 275 if (HAS_VEBOX(dev)) { 276 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 277 ring->semaphore_mboxes[2], 278 ring->semaphore_seqno[2]); 279 } 280 } 281 if (USES_PPGTT(dev)) { 282 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 283 284 if (INTEL_INFO(dev)->gen >= 8) { 285 int i; 286 for (i = 0; i < 4; i++) 287 err_printf(m, " PDP%d: 0x%016llx\n", 288 i, ring->vm_info.pdp[i]); 289 } else { 290 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 291 ring->vm_info.pp_dir_base); 292 } 293 } 294 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 295 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 296 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 297 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 298 err_printf(m, " hangcheck: %s [%d]\n", 299 hangcheck_action_to_str(ring->hangcheck_action), 300 ring->hangcheck_score); 301 } 302 303 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 304 { 305 va_list args; 306 307 va_start(args, f); 308 i915_error_vprintf(e, f, args); 309 va_end(args); 310 } 311 312 static void print_error_obj(struct drm_i915_error_state_buf *m, 313 struct drm_i915_error_object *obj) 314 { 315 int page, offset, elt; 316 317 for (page = offset = 0; page < obj->page_count; page++) { 318 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 319 err_printf(m, "%08x : %08x\n", offset, 320 obj->pages[page][elt]); 321 offset += 4; 322 } 323 } 324 } 325 326 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 327 const struct i915_error_state_file_priv *error_priv) 328 { 329 struct drm_device *dev = error_priv->dev; 330 struct drm_i915_private *dev_priv = dev->dev_private; 331 struct drm_i915_error_state *error = error_priv->error; 332 struct drm_i915_error_object *obj; 333 int i, j, offset, elt; 334 int max_hangcheck_score; 335 336 if (!error) { 337 err_printf(m, "no error state collected\n"); 338 goto out; 339 } 340 341 err_printf(m, "%s\n", error->error_msg); 342 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 343 error->time.tv_usec); 344 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 345 max_hangcheck_score = 0; 346 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 347 if (error->ring[i].hangcheck_score > max_hangcheck_score) 348 max_hangcheck_score = error->ring[i].hangcheck_score; 349 } 350 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 351 if (error->ring[i].hangcheck_score == max_hangcheck_score && 352 error->ring[i].pid != -1) { 353 err_printf(m, "Active process (on ring %s): %s [%d]\n", 354 ring_str(i), 355 error->ring[i].comm, 356 error->ring[i].pid); 357 } 358 } 359 err_printf(m, "Reset count: %u\n", error->reset_count); 360 err_printf(m, "Suspend count: %u\n", error->suspend_count); 361 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 362 err_printf(m, "EIR: 0x%08x\n", error->eir); 363 err_printf(m, "IER: 0x%08x\n", error->ier); 364 if (INTEL_INFO(dev)->gen >= 8) { 365 for (i = 0; i < 4; i++) 366 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 367 error->gtier[i]); 368 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 369 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 370 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 371 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 372 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 373 err_printf(m, "CCID: 0x%08x\n", error->ccid); 374 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 375 376 for (i = 0; i < dev_priv->num_fence_regs; i++) 377 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 378 379 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 380 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 381 error->extra_instdone[i]); 382 383 if (INTEL_INFO(dev)->gen >= 6) { 384 err_printf(m, "ERROR: 0x%08x\n", error->error); 385 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 386 } 387 388 if (INTEL_INFO(dev)->gen == 7) 389 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 390 391 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 392 err_printf(m, "%s command stream:\n", ring_str(i)); 393 i915_ring_error_state(m, dev, &error->ring[i]); 394 } 395 396 if (error->active_bo) 397 print_error_buffers(m, "Active", 398 error->active_bo[0], 399 error->active_bo_count[0]); 400 401 if (error->pinned_bo) 402 print_error_buffers(m, "Pinned", 403 error->pinned_bo[0], 404 error->pinned_bo_count[0]); 405 406 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 407 obj = error->ring[i].batchbuffer; 408 if (obj) { 409 err_puts(m, dev_priv->ring[i].name); 410 if (error->ring[i].pid != -1) 411 err_printf(m, " (submitted by %s [%d])", 412 error->ring[i].comm, 413 error->ring[i].pid); 414 err_printf(m, " --- gtt_offset = 0x%08x\n", 415 obj->gtt_offset); 416 print_error_obj(m, obj); 417 } 418 419 obj = error->ring[i].wa_batchbuffer; 420 if (obj) { 421 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 422 dev_priv->ring[i].name, obj->gtt_offset); 423 print_error_obj(m, obj); 424 } 425 426 if (error->ring[i].num_requests) { 427 err_printf(m, "%s --- %d requests\n", 428 dev_priv->ring[i].name, 429 error->ring[i].num_requests); 430 for (j = 0; j < error->ring[i].num_requests; j++) { 431 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 432 error->ring[i].requests[j].seqno, 433 error->ring[i].requests[j].jiffies, 434 error->ring[i].requests[j].tail); 435 } 436 } 437 438 if ((obj = error->ring[i].ringbuffer)) { 439 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 440 dev_priv->ring[i].name, 441 obj->gtt_offset); 442 print_error_obj(m, obj); 443 } 444 445 if ((obj = error->ring[i].hws_page)) { 446 err_printf(m, "%s --- HW Status = 0x%08x\n", 447 dev_priv->ring[i].name, 448 obj->gtt_offset); 449 offset = 0; 450 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 451 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 452 offset, 453 obj->pages[0][elt], 454 obj->pages[0][elt+1], 455 obj->pages[0][elt+2], 456 obj->pages[0][elt+3]); 457 offset += 16; 458 } 459 } 460 461 if ((obj = error->ring[i].ctx)) { 462 err_printf(m, "%s --- HW Context = 0x%08x\n", 463 dev_priv->ring[i].name, 464 obj->gtt_offset); 465 print_error_obj(m, obj); 466 } 467 } 468 469 if ((obj = error->semaphore_obj)) { 470 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset); 471 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 472 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 473 elt * 4, 474 obj->pages[0][elt], 475 obj->pages[0][elt+1], 476 obj->pages[0][elt+2], 477 obj->pages[0][elt+3]); 478 } 479 } 480 481 if (error->overlay) 482 intel_overlay_print_error_state(m, error->overlay); 483 484 if (error->display) 485 intel_display_print_error_state(m, dev, error->display); 486 487 out: 488 if (m->bytes == 0 && m->err) 489 return m->err; 490 491 return 0; 492 } 493 494 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 495 size_t count, loff_t pos) 496 { 497 memset(ebuf, 0, sizeof(*ebuf)); 498 499 /* We need to have enough room to store any i915_error_state printf 500 * so that we can move it to start position. 501 */ 502 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 503 ebuf->buf = kmalloc(ebuf->size, 504 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 505 506 if (ebuf->buf == NULL) { 507 ebuf->size = PAGE_SIZE; 508 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 509 } 510 511 if (ebuf->buf == NULL) { 512 ebuf->size = 128; 513 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 514 } 515 516 if (ebuf->buf == NULL) 517 return -ENOMEM; 518 519 ebuf->start = pos; 520 521 return 0; 522 } 523 524 static void i915_error_object_free(struct drm_i915_error_object *obj) 525 { 526 int page; 527 528 if (obj == NULL) 529 return; 530 531 for (page = 0; page < obj->page_count; page++) 532 kfree(obj->pages[page]); 533 534 kfree(obj); 535 } 536 537 static void i915_error_state_free(struct kref *error_ref) 538 { 539 struct drm_i915_error_state *error = container_of(error_ref, 540 typeof(*error), ref); 541 int i; 542 543 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 544 i915_error_object_free(error->ring[i].batchbuffer); 545 i915_error_object_free(error->ring[i].ringbuffer); 546 i915_error_object_free(error->ring[i].hws_page); 547 i915_error_object_free(error->ring[i].ctx); 548 kfree(error->ring[i].requests); 549 } 550 551 i915_error_object_free(error->semaphore_obj); 552 kfree(error->active_bo); 553 kfree(error->overlay); 554 kfree(error->display); 555 kfree(error); 556 } 557 558 static struct drm_i915_error_object * 559 i915_error_object_create_sized(struct drm_i915_private *dev_priv, 560 struct drm_i915_gem_object *src, 561 struct i915_address_space *vm, 562 const int num_pages) 563 { 564 struct drm_i915_error_object *dst; 565 int i; 566 u32 reloc_offset; 567 568 if (src == NULL || src->pages == NULL) 569 return NULL; 570 571 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 572 if (dst == NULL) 573 return NULL; 574 575 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm); 576 for (i = 0; i < num_pages; i++) { 577 unsigned long flags; 578 void *d; 579 580 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 581 if (d == NULL) 582 goto unwind; 583 584 local_irq_save(flags); 585 if (src->cache_level == I915_CACHE_NONE && 586 reloc_offset < dev_priv->gtt.mappable_end && 587 src->has_global_gtt_mapping && 588 i915_is_ggtt(vm)) { 589 void __iomem *s; 590 591 /* Simply ignore tiling or any overlapping fence. 592 * It's part of the error state, and this hopefully 593 * captures what the GPU read. 594 */ 595 596 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 597 reloc_offset); 598 memcpy_fromio(d, s, PAGE_SIZE); 599 io_mapping_unmap_atomic(s); 600 } else if (src->stolen) { 601 unsigned long offset; 602 603 offset = dev_priv->mm.stolen_base; 604 offset += src->stolen->start; 605 offset += i << PAGE_SHIFT; 606 607 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); 608 } else { 609 struct page *page; 610 void *s; 611 612 page = i915_gem_object_get_page(src, i); 613 614 drm_clflush_pages(&page, 1); 615 616 s = kmap_atomic(page); 617 memcpy(d, s, PAGE_SIZE); 618 kunmap_atomic(s); 619 620 drm_clflush_pages(&page, 1); 621 } 622 local_irq_restore(flags); 623 624 dst->pages[i] = d; 625 626 reloc_offset += PAGE_SIZE; 627 } 628 dst->page_count = num_pages; 629 630 return dst; 631 632 unwind: 633 while (i--) 634 kfree(dst->pages[i]); 635 kfree(dst); 636 return NULL; 637 } 638 #define i915_error_object_create(dev_priv, src, vm) \ 639 i915_error_object_create_sized((dev_priv), (src), (vm), \ 640 (src)->base.size>>PAGE_SHIFT) 641 642 #define i915_error_ggtt_object_create(dev_priv, src) \ 643 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \ 644 (src)->base.size>>PAGE_SHIFT) 645 646 static void capture_bo(struct drm_i915_error_buffer *err, 647 struct drm_i915_gem_object *obj) 648 { 649 err->size = obj->base.size; 650 err->name = obj->base.name; 651 err->rseqno = obj->last_read_seqno; 652 err->wseqno = obj->last_write_seqno; 653 err->gtt_offset = i915_gem_obj_ggtt_offset(obj); 654 err->read_domains = obj->base.read_domains; 655 err->write_domain = obj->base.write_domain; 656 err->fence_reg = obj->fence_reg; 657 err->pinned = 0; 658 if (i915_gem_obj_is_pinned(obj)) 659 err->pinned = 1; 660 if (obj->user_pin_count > 0) 661 err->pinned = -1; 662 err->tiling = obj->tiling_mode; 663 err->dirty = obj->dirty; 664 err->purgeable = obj->madv != I915_MADV_WILLNEED; 665 err->userptr = obj->userptr.mm != NULL; 666 err->ring = obj->ring ? obj->ring->id : -1; 667 err->cache_level = obj->cache_level; 668 } 669 670 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 671 int count, struct list_head *head) 672 { 673 struct i915_vma *vma; 674 int i = 0; 675 676 list_for_each_entry(vma, head, mm_list) { 677 capture_bo(err++, vma->obj); 678 if (++i == count) 679 break; 680 } 681 682 return i; 683 } 684 685 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 686 int count, struct list_head *head) 687 { 688 struct drm_i915_gem_object *obj; 689 int i = 0; 690 691 list_for_each_entry(obj, head, global_list) { 692 if (!i915_gem_obj_is_pinned(obj)) 693 continue; 694 695 capture_bo(err++, obj); 696 if (++i == count) 697 break; 698 } 699 700 return i; 701 } 702 703 /* Generate a semi-unique error code. The code is not meant to have meaning, The 704 * code's only purpose is to try to prevent false duplicated bug reports by 705 * grossly estimating a GPU error state. 706 * 707 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 708 * the hang if we could strip the GTT offset information from it. 709 * 710 * It's only a small step better than a random number in its current form. 711 */ 712 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 713 struct drm_i915_error_state *error, 714 int *ring_id) 715 { 716 uint32_t error_code = 0; 717 int i; 718 719 /* IPEHR would be an ideal way to detect errors, as it's the gross 720 * measure of "the command that hung." However, has some very common 721 * synchronization commands which almost always appear in the case 722 * strictly a client bug. Use instdone to differentiate those some. 723 */ 724 for (i = 0; i < I915_NUM_RINGS; i++) { 725 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 726 if (ring_id) 727 *ring_id = i; 728 729 return error->ring[i].ipehr ^ error->ring[i].instdone; 730 } 731 } 732 733 return error_code; 734 } 735 736 static void i915_gem_record_fences(struct drm_device *dev, 737 struct drm_i915_error_state *error) 738 { 739 struct drm_i915_private *dev_priv = dev->dev_private; 740 int i; 741 742 /* Fences */ 743 switch (INTEL_INFO(dev)->gen) { 744 case 8: 745 case 7: 746 case 6: 747 for (i = 0; i < dev_priv->num_fence_regs; i++) 748 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 749 break; 750 case 5: 751 case 4: 752 for (i = 0; i < 16; i++) 753 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 754 break; 755 case 3: 756 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 757 for (i = 0; i < 8; i++) 758 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 759 case 2: 760 for (i = 0; i < 8; i++) 761 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 762 break; 763 764 default: 765 BUG(); 766 } 767 } 768 769 770 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 771 struct drm_i915_error_state *error, 772 struct intel_engine_cs *ring, 773 struct drm_i915_error_ring *ering) 774 { 775 struct intel_engine_cs *to; 776 int i; 777 778 if (!i915_semaphore_is_enabled(dev_priv->dev)) 779 return; 780 781 if (!error->semaphore_obj) 782 error->semaphore_obj = 783 i915_error_object_create(dev_priv, 784 dev_priv->semaphore_obj, 785 &dev_priv->gtt.base); 786 787 for_each_ring(to, dev_priv, i) { 788 int idx; 789 u16 signal_offset; 790 u32 *tmp; 791 792 if (ring == to) 793 continue; 794 795 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 796 / 4; 797 tmp = error->semaphore_obj->pages[0]; 798 idx = intel_ring_sync_index(ring, to); 799 800 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 801 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 802 } 803 } 804 805 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 806 struct intel_engine_cs *ring, 807 struct drm_i915_error_ring *ering) 808 { 809 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 810 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 811 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 812 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 813 814 if (HAS_VEBOX(dev_priv->dev)) { 815 ering->semaphore_mboxes[2] = 816 I915_READ(RING_SYNC_2(ring->mmio_base)); 817 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 818 } 819 } 820 821 static void i915_record_ring_state(struct drm_device *dev, 822 struct drm_i915_error_state *error, 823 struct intel_engine_cs *ring, 824 struct drm_i915_error_ring *ering) 825 { 826 struct drm_i915_private *dev_priv = dev->dev_private; 827 828 if (INTEL_INFO(dev)->gen >= 6) { 829 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 830 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 831 if (INTEL_INFO(dev)->gen >= 8) 832 gen8_record_semaphore_state(dev_priv, error, ring, ering); 833 else 834 gen6_record_semaphore_state(dev_priv, ring, ering); 835 } 836 837 if (INTEL_INFO(dev)->gen >= 4) { 838 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 839 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 840 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 841 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 842 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 843 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 844 if (INTEL_INFO(dev)->gen >= 8) { 845 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 846 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 847 } 848 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 849 } else { 850 ering->faddr = I915_READ(DMA_FADD_I8XX); 851 ering->ipeir = I915_READ(IPEIR); 852 ering->ipehr = I915_READ(IPEHR); 853 ering->instdone = I915_READ(INSTDONE); 854 } 855 856 ering->waiting = waitqueue_active(&ring->irq_queue); 857 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 858 ering->seqno = ring->get_seqno(ring, false); 859 ering->acthd = intel_ring_get_active_head(ring); 860 ering->head = I915_READ_HEAD(ring); 861 ering->tail = I915_READ_TAIL(ring); 862 ering->ctl = I915_READ_CTL(ring); 863 864 if (I915_NEED_GFX_HWS(dev)) { 865 int mmio; 866 867 if (IS_GEN7(dev)) { 868 switch (ring->id) { 869 default: 870 case RCS: 871 mmio = RENDER_HWS_PGA_GEN7; 872 break; 873 case BCS: 874 mmio = BLT_HWS_PGA_GEN7; 875 break; 876 case VCS: 877 mmio = BSD_HWS_PGA_GEN7; 878 break; 879 case VECS: 880 mmio = VEBOX_HWS_PGA_GEN7; 881 break; 882 } 883 } else if (IS_GEN6(ring->dev)) { 884 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 885 } else { 886 /* XXX: gen8 returns to sanity */ 887 mmio = RING_HWS_PGA(ring->mmio_base); 888 } 889 890 ering->hws = I915_READ(mmio); 891 } 892 893 ering->cpu_ring_head = ring->buffer->head; 894 ering->cpu_ring_tail = ring->buffer->tail; 895 896 ering->hangcheck_score = ring->hangcheck.score; 897 ering->hangcheck_action = ring->hangcheck.action; 898 899 if (USES_PPGTT(dev)) { 900 int i; 901 902 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 903 904 switch (INTEL_INFO(dev)->gen) { 905 case 8: 906 for (i = 0; i < 4; i++) { 907 ering->vm_info.pdp[i] = 908 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 909 ering->vm_info.pdp[i] <<= 32; 910 ering->vm_info.pdp[i] |= 911 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 912 } 913 break; 914 case 7: 915 ering->vm_info.pp_dir_base = 916 I915_READ(RING_PP_DIR_BASE(ring)); 917 break; 918 case 6: 919 ering->vm_info.pp_dir_base = 920 I915_READ(RING_PP_DIR_BASE_READ(ring)); 921 break; 922 } 923 } 924 } 925 926 927 static void i915_gem_record_active_context(struct intel_engine_cs *ring, 928 struct drm_i915_error_state *error, 929 struct drm_i915_error_ring *ering) 930 { 931 struct drm_i915_private *dev_priv = ring->dev->dev_private; 932 struct drm_i915_gem_object *obj; 933 934 /* Currently render ring is the only HW context user */ 935 if (ring->id != RCS || !error->ccid) 936 return; 937 938 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 939 if (!i915_gem_obj_ggtt_bound(obj)) 940 continue; 941 942 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 943 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 944 break; 945 } 946 } 947 } 948 949 static void i915_gem_record_rings(struct drm_device *dev, 950 struct drm_i915_error_state *error) 951 { 952 struct drm_i915_private *dev_priv = dev->dev_private; 953 struct drm_i915_gem_request *request; 954 int i, count; 955 956 for (i = 0; i < I915_NUM_RINGS; i++) { 957 struct intel_engine_cs *ring = &dev_priv->ring[i]; 958 959 error->ring[i].pid = -1; 960 961 if (ring->dev == NULL) 962 continue; 963 964 error->ring[i].valid = true; 965 966 i915_record_ring_state(dev, error, ring, &error->ring[i]); 967 968 request = i915_gem_find_active_request(ring); 969 if (request) { 970 /* We need to copy these to an anonymous buffer 971 * as the simplest method to avoid being overwritten 972 * by userspace. 973 */ 974 error->ring[i].batchbuffer = 975 i915_error_object_create(dev_priv, 976 request->batch_obj, 977 request->ctx ? 978 request->ctx->vm : 979 &dev_priv->gtt.base); 980 981 if (HAS_BROKEN_CS_TLB(dev_priv->dev) && 982 ring->scratch.obj) 983 error->ring[i].wa_batchbuffer = 984 i915_error_ggtt_object_create(dev_priv, 985 ring->scratch.obj); 986 987 if (request->file_priv) { 988 struct task_struct *task; 989 990 rcu_read_lock(); 991 task = pid_task(request->file_priv->file->pid, 992 PIDTYPE_PID); 993 if (task) { 994 strcpy(error->ring[i].comm, task->comm); 995 error->ring[i].pid = task->pid; 996 } 997 rcu_read_unlock(); 998 } 999 } 1000 1001 error->ring[i].ringbuffer = 1002 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj); 1003 1004 if (ring->status_page.obj) 1005 error->ring[i].hws_page = 1006 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 1007 1008 i915_gem_record_active_context(ring, error, &error->ring[i]); 1009 1010 count = 0; 1011 list_for_each_entry(request, &ring->request_list, list) 1012 count++; 1013 1014 error->ring[i].num_requests = count; 1015 error->ring[i].requests = 1016 kcalloc(count, sizeof(*error->ring[i].requests), 1017 GFP_ATOMIC); 1018 if (error->ring[i].requests == NULL) { 1019 error->ring[i].num_requests = 0; 1020 continue; 1021 } 1022 1023 count = 0; 1024 list_for_each_entry(request, &ring->request_list, list) { 1025 struct drm_i915_error_request *erq; 1026 1027 erq = &error->ring[i].requests[count++]; 1028 erq->seqno = request->seqno; 1029 erq->jiffies = request->emitted_jiffies; 1030 erq->tail = request->tail; 1031 } 1032 } 1033 } 1034 1035 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1036 * VM. 1037 */ 1038 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1039 struct drm_i915_error_state *error, 1040 struct i915_address_space *vm, 1041 const int ndx) 1042 { 1043 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1044 struct drm_i915_gem_object *obj; 1045 struct i915_vma *vma; 1046 int i; 1047 1048 i = 0; 1049 list_for_each_entry(vma, &vm->active_list, mm_list) 1050 i++; 1051 error->active_bo_count[ndx] = i; 1052 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 1053 if (i915_gem_obj_is_pinned(obj)) 1054 i++; 1055 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1056 1057 if (i) { 1058 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1059 if (active_bo) 1060 pinned_bo = active_bo + error->active_bo_count[ndx]; 1061 } 1062 1063 if (active_bo) 1064 error->active_bo_count[ndx] = 1065 capture_active_bo(active_bo, 1066 error->active_bo_count[ndx], 1067 &vm->active_list); 1068 1069 if (pinned_bo) 1070 error->pinned_bo_count[ndx] = 1071 capture_pinned_bo(pinned_bo, 1072 error->pinned_bo_count[ndx], 1073 &dev_priv->mm.bound_list); 1074 error->active_bo[ndx] = active_bo; 1075 error->pinned_bo[ndx] = pinned_bo; 1076 } 1077 1078 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1079 struct drm_i915_error_state *error) 1080 { 1081 struct i915_address_space *vm; 1082 int cnt = 0, i = 0; 1083 1084 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1085 cnt++; 1086 1087 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1088 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1089 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1090 GFP_ATOMIC); 1091 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1092 GFP_ATOMIC); 1093 1094 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1095 i915_gem_capture_vm(dev_priv, error, vm, i++); 1096 } 1097 1098 /* Capture all registers which don't fit into another category. */ 1099 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1100 struct drm_i915_error_state *error) 1101 { 1102 struct drm_device *dev = dev_priv->dev; 1103 int i; 1104 1105 /* General organization 1106 * 1. Registers specific to a single generation 1107 * 2. Registers which belong to multiple generations 1108 * 3. Feature specific registers. 1109 * 4. Everything else 1110 * Please try to follow the order. 1111 */ 1112 1113 /* 1: Registers specific to a single generation */ 1114 if (IS_VALLEYVIEW(dev)) { 1115 error->gtier[0] = I915_READ(GTIER); 1116 error->ier = I915_READ(VLV_IER); 1117 error->forcewake = I915_READ(FORCEWAKE_VLV); 1118 } 1119 1120 if (IS_GEN7(dev)) 1121 error->err_int = I915_READ(GEN7_ERR_INT); 1122 1123 if (IS_GEN6(dev)) { 1124 error->forcewake = I915_READ(FORCEWAKE); 1125 error->gab_ctl = I915_READ(GAB_CTL); 1126 error->gfx_mode = I915_READ(GFX_MODE); 1127 } 1128 1129 /* 2: Registers which belong to multiple generations */ 1130 if (INTEL_INFO(dev)->gen >= 7) 1131 error->forcewake = I915_READ(FORCEWAKE_MT); 1132 1133 if (INTEL_INFO(dev)->gen >= 6) { 1134 error->derrmr = I915_READ(DERRMR); 1135 error->error = I915_READ(ERROR_GEN6); 1136 error->done_reg = I915_READ(DONE_REG); 1137 } 1138 1139 /* 3: Feature specific registers */ 1140 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1141 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1142 error->gac_eco = I915_READ(GAC_ECO_BITS); 1143 } 1144 1145 /* 4: Everything else */ 1146 if (HAS_HW_CONTEXTS(dev)) 1147 error->ccid = I915_READ(CCID); 1148 1149 if (INTEL_INFO(dev)->gen >= 8) { 1150 error->ier = I915_READ(GEN8_DE_MISC_IER); 1151 for (i = 0; i < 4; i++) 1152 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1153 } else if (HAS_PCH_SPLIT(dev)) { 1154 error->ier = I915_READ(DEIER); 1155 error->gtier[0] = I915_READ(GTIER); 1156 } else if (IS_GEN2(dev)) { 1157 error->ier = I915_READ16(IER); 1158 } else if (!IS_VALLEYVIEW(dev)) { 1159 error->ier = I915_READ(IER); 1160 } 1161 error->eir = I915_READ(EIR); 1162 error->pgtbl_er = I915_READ(PGTBL_ER); 1163 1164 i915_get_extra_instdone(dev, error->extra_instdone); 1165 } 1166 1167 static void i915_error_capture_msg(struct drm_device *dev, 1168 struct drm_i915_error_state *error, 1169 bool wedged, 1170 const char *error_msg) 1171 { 1172 struct drm_i915_private *dev_priv = dev->dev_private; 1173 u32 ecode; 1174 int ring_id = -1, len; 1175 1176 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1177 1178 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1179 "GPU HANG: ecode %d:0x%08x", ring_id, ecode); 1180 1181 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1182 len += scnprintf(error->error_msg + len, 1183 sizeof(error->error_msg) - len, 1184 ", in %s [%d]", 1185 error->ring[ring_id].comm, 1186 error->ring[ring_id].pid); 1187 1188 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1189 ", reason: %s, action: %s", 1190 error_msg, 1191 wedged ? "reset" : "continue"); 1192 } 1193 1194 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1195 struct drm_i915_error_state *error) 1196 { 1197 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1198 error->suspend_count = dev_priv->suspend_count; 1199 } 1200 1201 /** 1202 * i915_capture_error_state - capture an error record for later analysis 1203 * @dev: drm device 1204 * 1205 * Should be called when an error is detected (either a hang or an error 1206 * interrupt) to capture error state from the time of the error. Fills 1207 * out a structure which becomes available in debugfs for user level tools 1208 * to pick up. 1209 */ 1210 void i915_capture_error_state(struct drm_device *dev, bool wedged, 1211 const char *error_msg) 1212 { 1213 static bool warned; 1214 struct drm_i915_private *dev_priv = dev->dev_private; 1215 struct drm_i915_error_state *error; 1216 unsigned long flags; 1217 1218 /* Account for pipe specific data like PIPE*STAT */ 1219 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1220 if (!error) { 1221 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1222 return; 1223 } 1224 1225 kref_init(&error->ref); 1226 1227 i915_capture_gen_state(dev_priv, error); 1228 i915_capture_reg_state(dev_priv, error); 1229 i915_gem_capture_buffers(dev_priv, error); 1230 i915_gem_record_fences(dev, error); 1231 i915_gem_record_rings(dev, error); 1232 1233 do_gettimeofday(&error->time); 1234 1235 error->overlay = intel_overlay_capture_error_state(dev); 1236 error->display = intel_display_capture_error_state(dev); 1237 1238 i915_error_capture_msg(dev, error, wedged, error_msg); 1239 DRM_INFO("%s\n", error->error_msg); 1240 1241 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1242 if (dev_priv->gpu_error.first_error == NULL) { 1243 dev_priv->gpu_error.first_error = error; 1244 error = NULL; 1245 } 1246 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1247 1248 if (error) { 1249 i915_error_state_free(&error->ref); 1250 return; 1251 } 1252 1253 if (!warned) { 1254 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1255 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1256 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1257 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1258 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1259 warned = true; 1260 } 1261 } 1262 1263 void i915_error_state_get(struct drm_device *dev, 1264 struct i915_error_state_file_priv *error_priv) 1265 { 1266 struct drm_i915_private *dev_priv = dev->dev_private; 1267 unsigned long flags; 1268 1269 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1270 error_priv->error = dev_priv->gpu_error.first_error; 1271 if (error_priv->error) 1272 kref_get(&error_priv->error->ref); 1273 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1274 1275 } 1276 1277 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1278 { 1279 if (error_priv->error) 1280 kref_put(&error_priv->error->ref, i915_error_state_free); 1281 } 1282 1283 void i915_destroy_error_state(struct drm_device *dev) 1284 { 1285 struct drm_i915_private *dev_priv = dev->dev_private; 1286 struct drm_i915_error_state *error; 1287 unsigned long flags; 1288 1289 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1290 error = dev_priv->gpu_error.first_error; 1291 dev_priv->gpu_error.first_error = NULL; 1292 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1293 1294 if (error) 1295 kref_put(&error->ref, i915_error_state_free); 1296 } 1297 1298 const char *i915_cache_level_str(int type) 1299 { 1300 switch (type) { 1301 case I915_CACHE_NONE: return " uncached"; 1302 case I915_CACHE_LLC: return " snooped or LLC"; 1303 case I915_CACHE_L3_LLC: return " L3+LLC"; 1304 case I915_CACHE_WT: return " WT"; 1305 default: return ""; 1306 } 1307 } 1308 1309 /* NB: please notice the memset */ 1310 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1311 { 1312 struct drm_i915_private *dev_priv = dev->dev_private; 1313 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1314 1315 switch (INTEL_INFO(dev)->gen) { 1316 case 2: 1317 case 3: 1318 instdone[0] = I915_READ(INSTDONE); 1319 break; 1320 case 4: 1321 case 5: 1322 case 6: 1323 instdone[0] = I915_READ(INSTDONE_I965); 1324 instdone[1] = I915_READ(INSTDONE1); 1325 break; 1326 default: 1327 WARN_ONCE(1, "Unsupported platform\n"); 1328 case 7: 1329 case 8: 1330 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1331 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1332 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1333 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1334 break; 1335 } 1336 } 1337