1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/highmem.h> 32 #include <linux/nmi.h> 33 #include <linux/pagevec.h> 34 #include <linux/scatterlist.h> 35 #include <linux/string_helpers.h> 36 #include <linux/utsname.h> 37 #include <linux/zlib.h> 38 39 #include <drm/drm_cache.h> 40 #include <drm/drm_print.h> 41 42 #include "display/intel_dmc.h" 43 #include "display/intel_overlay.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_pm.h" 50 #include "gt/intel_gt_regs.h" 51 #include "gt/uc/intel_guc_capture.h" 52 53 #include "i915_driver.h" 54 #include "i915_drv.h" 55 #include "i915_gpu_error.h" 56 #include "i915_memcpy.h" 57 #include "i915_scatterlist.h" 58 #include "i915_utils.h" 59 60 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 61 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 62 63 static void __sg_set_buf(struct scatterlist *sg, 64 void *addr, unsigned int len, loff_t it) 65 { 66 sg->page_link = (unsigned long)virt_to_page(addr); 67 sg->offset = offset_in_page(addr); 68 sg->length = len; 69 sg->dma_address = it; 70 } 71 72 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 73 { 74 if (!len) 75 return false; 76 77 if (e->bytes + len + 1 <= e->size) 78 return true; 79 80 if (e->bytes) { 81 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 82 e->iter += e->bytes; 83 e->buf = NULL; 84 e->bytes = 0; 85 } 86 87 if (e->cur == e->end) { 88 struct scatterlist *sgl; 89 90 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 91 if (!sgl) { 92 e->err = -ENOMEM; 93 return false; 94 } 95 96 if (e->cur) { 97 e->cur->offset = 0; 98 e->cur->length = 0; 99 e->cur->page_link = 100 (unsigned long)sgl | SG_CHAIN; 101 } else { 102 e->sgl = sgl; 103 } 104 105 e->cur = sgl; 106 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 107 } 108 109 e->size = ALIGN(len + 1, SZ_64K); 110 e->buf = kmalloc(e->size, ALLOW_FAIL); 111 if (!e->buf) { 112 e->size = PAGE_ALIGN(len + 1); 113 e->buf = kmalloc(e->size, GFP_KERNEL); 114 } 115 if (!e->buf) { 116 e->err = -ENOMEM; 117 return false; 118 } 119 120 return true; 121 } 122 123 __printf(2, 0) 124 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 125 const char *fmt, va_list args) 126 { 127 va_list ap; 128 int len; 129 130 if (e->err) 131 return; 132 133 va_copy(ap, args); 134 len = vsnprintf(NULL, 0, fmt, ap); 135 va_end(ap); 136 if (len <= 0) { 137 e->err = len; 138 return; 139 } 140 141 if (!__i915_error_grow(e, len)) 142 return; 143 144 GEM_BUG_ON(e->bytes >= e->size); 145 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 146 if (len < 0) { 147 e->err = len; 148 return; 149 } 150 e->bytes += len; 151 } 152 153 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 154 { 155 unsigned len; 156 157 if (e->err || !str) 158 return; 159 160 len = strlen(str); 161 if (!__i915_error_grow(e, len)) 162 return; 163 164 GEM_BUG_ON(e->bytes + len > e->size); 165 memcpy(e->buf + e->bytes, str, len); 166 e->bytes += len; 167 } 168 169 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 170 #define err_puts(e, s) i915_error_puts(e, s) 171 172 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 173 { 174 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 175 } 176 177 static inline struct drm_printer 178 i915_error_printer(struct drm_i915_error_state_buf *e) 179 { 180 struct drm_printer p = { 181 .printfn = __i915_printfn_error, 182 .arg = e, 183 }; 184 return p; 185 } 186 187 /* single threaded page allocator with a reserved stash for emergencies */ 188 static void pool_fini(struct pagevec *pv) 189 { 190 pagevec_release(pv); 191 } 192 193 static int pool_refill(struct pagevec *pv, gfp_t gfp) 194 { 195 while (pagevec_space(pv)) { 196 struct page *p; 197 198 p = alloc_page(gfp); 199 if (!p) 200 return -ENOMEM; 201 202 pagevec_add(pv, p); 203 } 204 205 return 0; 206 } 207 208 static int pool_init(struct pagevec *pv, gfp_t gfp) 209 { 210 int err; 211 212 pagevec_init(pv); 213 214 err = pool_refill(pv, gfp); 215 if (err) 216 pool_fini(pv); 217 218 return err; 219 } 220 221 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 222 { 223 struct page *p; 224 225 p = alloc_page(gfp); 226 if (!p && pagevec_count(pv)) 227 p = pv->pages[--pv->nr]; 228 229 return p ? page_address(p) : NULL; 230 } 231 232 static void pool_free(struct pagevec *pv, void *addr) 233 { 234 struct page *p = virt_to_page(addr); 235 236 if (pagevec_space(pv)) 237 pagevec_add(pv, p); 238 else 239 __free_page(p); 240 } 241 242 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 243 244 struct i915_vma_compress { 245 struct pagevec pool; 246 struct z_stream_s zstream; 247 void *tmp; 248 }; 249 250 static bool compress_init(struct i915_vma_compress *c) 251 { 252 struct z_stream_s *zstream = &c->zstream; 253 254 if (pool_init(&c->pool, ALLOW_FAIL)) 255 return false; 256 257 zstream->workspace = 258 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 259 ALLOW_FAIL); 260 if (!zstream->workspace) { 261 pool_fini(&c->pool); 262 return false; 263 } 264 265 c->tmp = NULL; 266 if (i915_has_memcpy_from_wc()) 267 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 268 269 return true; 270 } 271 272 static bool compress_start(struct i915_vma_compress *c) 273 { 274 struct z_stream_s *zstream = &c->zstream; 275 void *workspace = zstream->workspace; 276 277 memset(zstream, 0, sizeof(*zstream)); 278 zstream->workspace = workspace; 279 280 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 281 } 282 283 static void *compress_next_page(struct i915_vma_compress *c, 284 struct i915_vma_coredump *dst) 285 { 286 void *page_addr; 287 struct page *page; 288 289 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 290 if (!page_addr) 291 return ERR_PTR(-ENOMEM); 292 293 page = virt_to_page(page_addr); 294 list_add_tail(&page->lru, &dst->page_list); 295 return page_addr; 296 } 297 298 static int compress_page(struct i915_vma_compress *c, 299 void *src, 300 struct i915_vma_coredump *dst, 301 bool wc) 302 { 303 struct z_stream_s *zstream = &c->zstream; 304 305 zstream->next_in = src; 306 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 307 zstream->next_in = c->tmp; 308 zstream->avail_in = PAGE_SIZE; 309 310 do { 311 if (zstream->avail_out == 0) { 312 zstream->next_out = compress_next_page(c, dst); 313 if (IS_ERR(zstream->next_out)) 314 return PTR_ERR(zstream->next_out); 315 316 zstream->avail_out = PAGE_SIZE; 317 } 318 319 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 320 return -EIO; 321 322 cond_resched(); 323 } while (zstream->avail_in); 324 325 /* Fallback to uncompressed if we increase size? */ 326 if (0 && zstream->total_out > zstream->total_in) 327 return -E2BIG; 328 329 return 0; 330 } 331 332 static int compress_flush(struct i915_vma_compress *c, 333 struct i915_vma_coredump *dst) 334 { 335 struct z_stream_s *zstream = &c->zstream; 336 337 do { 338 switch (zlib_deflate(zstream, Z_FINISH)) { 339 case Z_OK: /* more space requested */ 340 zstream->next_out = compress_next_page(c, dst); 341 if (IS_ERR(zstream->next_out)) 342 return PTR_ERR(zstream->next_out); 343 344 zstream->avail_out = PAGE_SIZE; 345 break; 346 347 case Z_STREAM_END: 348 goto end; 349 350 default: /* any error */ 351 return -EIO; 352 } 353 } while (1); 354 355 end: 356 memset(zstream->next_out, 0, zstream->avail_out); 357 dst->unused = zstream->avail_out; 358 return 0; 359 } 360 361 static void compress_finish(struct i915_vma_compress *c) 362 { 363 zlib_deflateEnd(&c->zstream); 364 } 365 366 static void compress_fini(struct i915_vma_compress *c) 367 { 368 kfree(c->zstream.workspace); 369 if (c->tmp) 370 pool_free(&c->pool, c->tmp); 371 pool_fini(&c->pool); 372 } 373 374 static void err_compression_marker(struct drm_i915_error_state_buf *m) 375 { 376 err_puts(m, ":"); 377 } 378 379 #else 380 381 struct i915_vma_compress { 382 struct pagevec pool; 383 }; 384 385 static bool compress_init(struct i915_vma_compress *c) 386 { 387 return pool_init(&c->pool, ALLOW_FAIL) == 0; 388 } 389 390 static bool compress_start(struct i915_vma_compress *c) 391 { 392 return true; 393 } 394 395 static int compress_page(struct i915_vma_compress *c, 396 void *src, 397 struct i915_vma_coredump *dst, 398 bool wc) 399 { 400 void *ptr; 401 402 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 403 if (!ptr) 404 return -ENOMEM; 405 406 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 407 memcpy(ptr, src, PAGE_SIZE); 408 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 409 cond_resched(); 410 411 return 0; 412 } 413 414 static int compress_flush(struct i915_vma_compress *c, 415 struct i915_vma_coredump *dst) 416 { 417 return 0; 418 } 419 420 static void compress_finish(struct i915_vma_compress *c) 421 { 422 } 423 424 static void compress_fini(struct i915_vma_compress *c) 425 { 426 pool_fini(&c->pool); 427 } 428 429 static void err_compression_marker(struct drm_i915_error_state_buf *m) 430 { 431 err_puts(m, "~"); 432 } 433 434 #endif 435 436 static void error_print_instdone(struct drm_i915_error_state_buf *m, 437 const struct intel_engine_coredump *ee) 438 { 439 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 440 int slice; 441 int subslice; 442 int iter; 443 444 err_printf(m, " INSTDONE: 0x%08x\n", 445 ee->instdone.instdone); 446 447 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 448 return; 449 450 err_printf(m, " SC_INSTDONE: 0x%08x\n", 451 ee->instdone.slice_common); 452 453 if (GRAPHICS_VER(m->i915) <= 6) 454 return; 455 456 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) { 457 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 458 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 459 slice, subslice, 460 ee->instdone.sampler[slice][subslice]); 461 462 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 463 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 464 slice, subslice, 465 ee->instdone.row[slice][subslice]); 466 } else { 467 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 468 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 469 slice, subslice, 470 ee->instdone.sampler[slice][subslice]); 471 472 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 473 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 474 slice, subslice, 475 ee->instdone.row[slice][subslice]); 476 } 477 478 if (GRAPHICS_VER(m->i915) < 12) 479 return; 480 481 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 482 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 483 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 484 slice, subslice, 485 ee->instdone.geom_svg[slice][subslice]); 486 } 487 488 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 489 ee->instdone.slice_common_extra[0]); 490 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 491 ee->instdone.slice_common_extra[1]); 492 } 493 494 static void error_print_request(struct drm_i915_error_state_buf *m, 495 const char *prefix, 496 const struct i915_request_coredump *erq) 497 { 498 if (!erq->seqno) 499 return; 500 501 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 502 prefix, erq->pid, erq->context, erq->seqno, 503 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 504 &erq->flags) ? "!" : "", 505 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 506 &erq->flags) ? "+" : "", 507 erq->sched_attr.priority, 508 erq->head, erq->tail); 509 } 510 511 static void error_print_context(struct drm_i915_error_state_buf *m, 512 const char *header, 513 const struct i915_gem_context_coredump *ctx) 514 { 515 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 516 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 517 ctx->guilty, ctx->active, 518 ctx->total_runtime, ctx->avg_runtime); 519 } 520 521 static struct i915_vma_coredump * 522 __find_vma(struct i915_vma_coredump *vma, const char *name) 523 { 524 while (vma) { 525 if (strcmp(vma->name, name) == 0) 526 return vma; 527 vma = vma->next; 528 } 529 530 return NULL; 531 } 532 533 struct i915_vma_coredump * 534 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 535 { 536 return __find_vma(ee->vma, "batch"); 537 } 538 539 static void error_print_engine(struct drm_i915_error_state_buf *m, 540 const struct intel_engine_coredump *ee) 541 { 542 struct i915_vma_coredump *batch; 543 int n; 544 545 err_printf(m, "%s command stream:\n", ee->engine->name); 546 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 547 err_printf(m, " START: 0x%08x\n", ee->start); 548 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 549 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 550 ee->tail, ee->rq_post, ee->rq_tail); 551 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 552 err_printf(m, " MODE: 0x%08x\n", ee->mode); 553 err_printf(m, " HWS: 0x%08x\n", ee->hws); 554 err_printf(m, " ACTHD: 0x%08x %08x\n", 555 (u32)(ee->acthd>>32), (u32)ee->acthd); 556 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 557 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 558 err_printf(m, " ESR: 0x%08x\n", ee->esr); 559 560 error_print_instdone(m, ee); 561 562 batch = intel_gpu_error_find_batch(ee); 563 if (batch) { 564 u64 start = batch->gtt_offset; 565 u64 end = start + batch->gtt_size; 566 567 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 568 upper_32_bits(start), lower_32_bits(start), 569 upper_32_bits(end), lower_32_bits(end)); 570 } 571 if (GRAPHICS_VER(m->i915) >= 4) { 572 err_printf(m, " BBADDR: 0x%08x_%08x\n", 573 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 574 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 575 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 576 } 577 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 578 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 579 lower_32_bits(ee->faddr)); 580 if (GRAPHICS_VER(m->i915) >= 6) { 581 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 582 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 583 } 584 if (GRAPHICS_VER(m->i915) >= 11) { 585 err_printf(m, " NOPID: 0x%08x\n", ee->nopid); 586 err_printf(m, " EXCC: 0x%08x\n", ee->excc); 587 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); 588 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); 589 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); 590 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); 591 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); 592 } 593 if (HAS_PPGTT(m->i915)) { 594 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 595 596 if (GRAPHICS_VER(m->i915) >= 8) { 597 int i; 598 for (i = 0; i < 4; i++) 599 err_printf(m, " PDP%d: 0x%016llx\n", 600 i, ee->vm_info.pdp[i]); 601 } else { 602 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 603 ee->vm_info.pp_dir_base); 604 } 605 } 606 607 for (n = 0; n < ee->num_ports; n++) { 608 err_printf(m, " ELSP[%d]:", n); 609 error_print_request(m, " ", &ee->execlist[n]); 610 } 611 } 612 613 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 614 { 615 va_list args; 616 617 va_start(args, f); 618 i915_error_vprintf(e, f, args); 619 va_end(args); 620 } 621 622 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 623 const struct intel_engine_cs *engine, 624 const struct i915_vma_coredump *vma) 625 { 626 char out[ASCII85_BUFSZ]; 627 struct page *page; 628 629 if (!vma) 630 return; 631 632 err_printf(m, "%s --- %s = 0x%08x %08x\n", 633 engine ? engine->name : "global", vma->name, 634 upper_32_bits(vma->gtt_offset), 635 lower_32_bits(vma->gtt_offset)); 636 637 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 638 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 639 640 err_compression_marker(m); 641 list_for_each_entry(page, &vma->page_list, lru) { 642 int i, len; 643 const u32 *addr = page_address(page); 644 645 len = PAGE_SIZE; 646 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 647 len -= vma->unused; 648 len = ascii85_encode_len(len); 649 650 for (i = 0; i < len; i++) 651 err_puts(m, ascii85_encode(addr[i], out)); 652 } 653 err_puts(m, "\n"); 654 } 655 656 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 657 struct i915_gpu_coredump *error) 658 { 659 struct drm_printer p = i915_error_printer(m); 660 661 intel_device_info_print_static(&error->device_info, &p); 662 intel_device_info_print_runtime(&error->runtime_info, &p); 663 intel_driver_caps_print(&error->driver_caps, &p); 664 } 665 666 static void err_print_params(struct drm_i915_error_state_buf *m, 667 const struct i915_params *params) 668 { 669 struct drm_printer p = i915_error_printer(m); 670 671 i915_params_dump(params, &p); 672 } 673 674 static void err_print_pciid(struct drm_i915_error_state_buf *m, 675 struct drm_i915_private *i915) 676 { 677 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 678 679 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 680 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 681 err_printf(m, "PCI Subsystem: %04x:%04x\n", 682 pdev->subsystem_vendor, 683 pdev->subsystem_device); 684 } 685 686 static void err_print_uc(struct drm_i915_error_state_buf *m, 687 const struct intel_uc_coredump *error_uc) 688 { 689 struct drm_printer p = i915_error_printer(m); 690 691 intel_uc_fw_dump(&error_uc->guc_fw, &p); 692 intel_uc_fw_dump(&error_uc->huc_fw, &p); 693 intel_gpu_error_print_vma(m, NULL, error_uc->guc_log); 694 } 695 696 static void err_free_sgl(struct scatterlist *sgl) 697 { 698 while (sgl) { 699 struct scatterlist *sg; 700 701 for (sg = sgl; !sg_is_chain(sg); sg++) { 702 kfree(sg_virt(sg)); 703 if (sg_is_last(sg)) 704 break; 705 } 706 707 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 708 free_page((unsigned long)sgl); 709 sgl = sg; 710 } 711 } 712 713 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 714 struct intel_gt_coredump *gt) 715 { 716 struct drm_printer p = i915_error_printer(m); 717 718 intel_gt_info_print(>->info, &p); 719 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 720 } 721 722 static void err_print_gt_display(struct drm_i915_error_state_buf *m, 723 struct intel_gt_coredump *gt) 724 { 725 err_printf(m, "IER: 0x%08x\n", gt->ier); 726 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 727 } 728 729 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 730 struct intel_gt_coredump *gt) 731 { 732 int i; 733 734 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 735 err_printf(m, "EIR: 0x%08x\n", gt->eir); 736 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 737 738 for (i = 0; i < gt->ngtier; i++) 739 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 740 } 741 742 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 743 struct intel_gt_coredump *gt) 744 { 745 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 746 747 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 748 err_printf(m, "ERROR: 0x%08x\n", gt->error); 749 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 750 } 751 752 if (GRAPHICS_VER(m->i915) >= 8) 753 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 754 gt->fault_data1, gt->fault_data0); 755 756 if (GRAPHICS_VER(m->i915) == 7) 757 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 758 759 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 760 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 761 762 if (GRAPHICS_VER(m->i915) == 12) 763 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 764 765 if (GRAPHICS_VER(m->i915) >= 12) { 766 int i; 767 768 for (i = 0; i < I915_MAX_SFC; i++) { 769 /* 770 * SFC_DONE resides in the VD forcewake domain, so it 771 * only exists if the corresponding VCS engine is 772 * present. 773 */ 774 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 775 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 776 continue; 777 778 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 779 gt->sfc_done[i]); 780 } 781 782 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 783 } 784 } 785 786 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 787 struct intel_gt_coredump *gt) 788 { 789 int i; 790 791 for (i = 0; i < gt->nfence; i++) 792 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 793 } 794 795 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 796 struct intel_gt_coredump *gt) 797 { 798 const struct intel_engine_coredump *ee; 799 800 for (ee = gt->engine; ee; ee = ee->next) { 801 const struct i915_vma_coredump *vma; 802 803 if (ee->guc_capture_node) 804 intel_guc_capture_print_engine_node(m, ee); 805 else 806 error_print_engine(m, ee); 807 808 err_printf(m, " hung: %u\n", ee->hung); 809 err_printf(m, " engine reset count: %u\n", ee->reset_count); 810 error_print_context(m, " Active context: ", &ee->context); 811 812 for (vma = ee->vma; vma; vma = vma->next) 813 intel_gpu_error_print_vma(m, ee->engine, vma); 814 } 815 816 } 817 818 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 819 struct i915_gpu_coredump *error) 820 { 821 const struct intel_engine_coredump *ee; 822 struct timespec64 ts; 823 824 if (*error->error_msg) 825 err_printf(m, "%s\n", error->error_msg); 826 err_printf(m, "Kernel: %s %s\n", 827 init_utsname()->release, 828 init_utsname()->machine); 829 err_printf(m, "Driver: %s\n", DRIVER_DATE); 830 ts = ktime_to_timespec64(error->time); 831 err_printf(m, "Time: %lld s %ld us\n", 832 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 833 ts = ktime_to_timespec64(error->boottime); 834 err_printf(m, "Boottime: %lld s %ld us\n", 835 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 836 ts = ktime_to_timespec64(error->uptime); 837 err_printf(m, "Uptime: %lld s %ld us\n", 838 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 839 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 840 error->capture, jiffies_to_msecs(jiffies - error->capture)); 841 842 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 843 err_printf(m, "Active process (on ring %s): %s [%d]\n", 844 ee->engine->name, 845 ee->context.comm, 846 ee->context.pid); 847 848 err_printf(m, "Reset count: %u\n", error->reset_count); 849 err_printf(m, "Suspend count: %u\n", error->suspend_count); 850 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 851 err_printf(m, "Subplatform: 0x%x\n", 852 intel_subplatform(&error->runtime_info, 853 error->device_info.platform)); 854 err_print_pciid(m, m->i915); 855 856 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 857 858 intel_dmc_print_error_state(m, m->i915); 859 860 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 861 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 862 863 if (error->gt) { 864 bool print_guc_capture = false; 865 866 if (error->gt->uc && error->gt->uc->is_guc_capture) 867 print_guc_capture = true; 868 869 err_print_gt_display(m, error->gt); 870 err_print_gt_global_nonguc(m, error->gt); 871 err_print_gt_fences(m, error->gt); 872 873 /* 874 * GuC dumped global, eng-class and eng-instance registers together 875 * as part of engine state dump so we print in err_print_gt_engines 876 */ 877 if (!print_guc_capture) 878 err_print_gt_global(m, error->gt); 879 880 err_print_gt_engines(m, error->gt); 881 882 if (error->gt->uc) 883 err_print_uc(m, error->gt->uc); 884 885 err_print_gt_info(m, error->gt); 886 } 887 888 if (error->overlay) 889 intel_overlay_print_error_state(m, error->overlay); 890 891 err_print_capabilities(m, error); 892 err_print_params(m, &error->params); 893 } 894 895 static int err_print_to_sgl(struct i915_gpu_coredump *error) 896 { 897 struct drm_i915_error_state_buf m; 898 899 if (IS_ERR(error)) 900 return PTR_ERR(error); 901 902 if (READ_ONCE(error->sgl)) 903 return 0; 904 905 memset(&m, 0, sizeof(m)); 906 m.i915 = error->i915; 907 908 __err_print_to_sgl(&m, error); 909 910 if (m.buf) { 911 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 912 m.bytes = 0; 913 m.buf = NULL; 914 } 915 if (m.cur) { 916 GEM_BUG_ON(m.end < m.cur); 917 sg_mark_end(m.cur - 1); 918 } 919 GEM_BUG_ON(m.sgl && !m.cur); 920 921 if (m.err) { 922 err_free_sgl(m.sgl); 923 return m.err; 924 } 925 926 if (cmpxchg(&error->sgl, NULL, m.sgl)) 927 err_free_sgl(m.sgl); 928 929 return 0; 930 } 931 932 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 933 char *buf, loff_t off, size_t rem) 934 { 935 struct scatterlist *sg; 936 size_t count; 937 loff_t pos; 938 int err; 939 940 if (!error || !rem) 941 return 0; 942 943 err = err_print_to_sgl(error); 944 if (err) 945 return err; 946 947 sg = READ_ONCE(error->fit); 948 if (!sg || off < sg->dma_address) 949 sg = error->sgl; 950 if (!sg) 951 return 0; 952 953 pos = sg->dma_address; 954 count = 0; 955 do { 956 size_t len, start; 957 958 if (sg_is_chain(sg)) { 959 sg = sg_chain_ptr(sg); 960 GEM_BUG_ON(sg_is_chain(sg)); 961 } 962 963 len = sg->length; 964 if (pos + len <= off) { 965 pos += len; 966 continue; 967 } 968 969 start = sg->offset; 970 if (pos < off) { 971 GEM_BUG_ON(off - pos > len); 972 len -= off - pos; 973 start += off - pos; 974 pos = off; 975 } 976 977 len = min(len, rem); 978 GEM_BUG_ON(!len || len > sg->length); 979 980 memcpy(buf, page_address(sg_page(sg)) + start, len); 981 982 count += len; 983 pos += len; 984 985 buf += len; 986 rem -= len; 987 if (!rem) { 988 WRITE_ONCE(error->fit, sg); 989 break; 990 } 991 } while (!sg_is_last(sg++)); 992 993 return count; 994 } 995 996 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 997 { 998 while (vma) { 999 struct i915_vma_coredump *next = vma->next; 1000 struct page *page, *n; 1001 1002 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 1003 list_del_init(&page->lru); 1004 __free_page(page); 1005 } 1006 1007 kfree(vma); 1008 vma = next; 1009 } 1010 } 1011 1012 static void cleanup_params(struct i915_gpu_coredump *error) 1013 { 1014 i915_params_free(&error->params); 1015 } 1016 1017 static void cleanup_uc(struct intel_uc_coredump *uc) 1018 { 1019 kfree(uc->guc_fw.path); 1020 kfree(uc->huc_fw.path); 1021 i915_vma_coredump_free(uc->guc_log); 1022 1023 kfree(uc); 1024 } 1025 1026 static void cleanup_gt(struct intel_gt_coredump *gt) 1027 { 1028 while (gt->engine) { 1029 struct intel_engine_coredump *ee = gt->engine; 1030 1031 gt->engine = ee->next; 1032 1033 i915_vma_coredump_free(ee->vma); 1034 intel_guc_capture_free_node(ee); 1035 kfree(ee); 1036 } 1037 1038 if (gt->uc) 1039 cleanup_uc(gt->uc); 1040 1041 kfree(gt); 1042 } 1043 1044 void __i915_gpu_coredump_free(struct kref *error_ref) 1045 { 1046 struct i915_gpu_coredump *error = 1047 container_of(error_ref, typeof(*error), ref); 1048 1049 while (error->gt) { 1050 struct intel_gt_coredump *gt = error->gt; 1051 1052 error->gt = gt->next; 1053 cleanup_gt(gt); 1054 } 1055 1056 kfree(error->overlay); 1057 1058 cleanup_params(error); 1059 1060 err_free_sgl(error->sgl); 1061 kfree(error); 1062 } 1063 1064 static struct i915_vma_coredump * 1065 i915_vma_coredump_create(const struct intel_gt *gt, 1066 const struct i915_vma_resource *vma_res, 1067 struct i915_vma_compress *compress, 1068 const char *name) 1069 1070 { 1071 struct i915_ggtt *ggtt = gt->ggtt; 1072 const u64 slot = ggtt->error_capture.start; 1073 struct i915_vma_coredump *dst; 1074 struct sgt_iter iter; 1075 int ret; 1076 1077 might_sleep(); 1078 1079 if (!vma_res || !vma_res->bi.pages || !compress) 1080 return NULL; 1081 1082 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1083 if (!dst) 1084 return NULL; 1085 1086 if (!compress_start(compress)) { 1087 kfree(dst); 1088 return NULL; 1089 } 1090 1091 INIT_LIST_HEAD(&dst->page_list); 1092 strcpy(dst->name, name); 1093 dst->next = NULL; 1094 1095 dst->gtt_offset = vma_res->start; 1096 dst->gtt_size = vma_res->node_size; 1097 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1098 dst->unused = 0; 1099 1100 ret = -EINVAL; 1101 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1102 void __iomem *s; 1103 dma_addr_t dma; 1104 1105 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1106 mutex_lock(&ggtt->error_mutex); 1107 if (ggtt->vm.raw_insert_page) 1108 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot, 1109 I915_CACHE_NONE, 0); 1110 else 1111 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1112 I915_CACHE_NONE, 0); 1113 mb(); 1114 1115 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1116 ret = compress_page(compress, 1117 (void __force *)s, dst, 1118 true); 1119 io_mapping_unmap(s); 1120 1121 mb(); 1122 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1123 mutex_unlock(&ggtt->error_mutex); 1124 if (ret) 1125 break; 1126 } 1127 } else if (vma_res->bi.lmem) { 1128 struct intel_memory_region *mem = vma_res->mr; 1129 dma_addr_t dma; 1130 1131 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1132 void __iomem *s; 1133 1134 s = io_mapping_map_wc(&mem->iomap, 1135 dma - mem->region.start, 1136 PAGE_SIZE); 1137 ret = compress_page(compress, 1138 (void __force *)s, dst, 1139 true); 1140 io_mapping_unmap(s); 1141 if (ret) 1142 break; 1143 } 1144 } else { 1145 struct page *page; 1146 1147 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1148 void *s; 1149 1150 drm_clflush_pages(&page, 1); 1151 1152 s = kmap(page); 1153 ret = compress_page(compress, s, dst, false); 1154 kunmap(page); 1155 1156 drm_clflush_pages(&page, 1); 1157 1158 if (ret) 1159 break; 1160 } 1161 } 1162 1163 if (ret || compress_flush(compress, dst)) { 1164 struct page *page, *n; 1165 1166 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1167 list_del_init(&page->lru); 1168 pool_free(&compress->pool, page_address(page)); 1169 } 1170 1171 kfree(dst); 1172 dst = NULL; 1173 } 1174 compress_finish(compress); 1175 1176 return dst; 1177 } 1178 1179 static void gt_record_fences(struct intel_gt_coredump *gt) 1180 { 1181 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1182 struct intel_uncore *uncore = gt->_gt->uncore; 1183 int i; 1184 1185 if (GRAPHICS_VER(uncore->i915) >= 6) { 1186 for (i = 0; i < ggtt->num_fences; i++) 1187 gt->fence[i] = 1188 intel_uncore_read64(uncore, 1189 FENCE_REG_GEN6_LO(i)); 1190 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1191 for (i = 0; i < ggtt->num_fences; i++) 1192 gt->fence[i] = 1193 intel_uncore_read64(uncore, 1194 FENCE_REG_965_LO(i)); 1195 } else { 1196 for (i = 0; i < ggtt->num_fences; i++) 1197 gt->fence[i] = 1198 intel_uncore_read(uncore, FENCE_REG(i)); 1199 } 1200 gt->nfence = i; 1201 } 1202 1203 static void engine_record_registers(struct intel_engine_coredump *ee) 1204 { 1205 const struct intel_engine_cs *engine = ee->engine; 1206 struct drm_i915_private *i915 = engine->i915; 1207 1208 if (GRAPHICS_VER(i915) >= 6) { 1209 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1210 1211 if (GRAPHICS_VER(i915) >= 12) 1212 ee->fault_reg = intel_uncore_read(engine->uncore, 1213 GEN12_RING_FAULT_REG); 1214 else if (GRAPHICS_VER(i915) >= 8) 1215 ee->fault_reg = intel_uncore_read(engine->uncore, 1216 GEN8_RING_FAULT_REG); 1217 else 1218 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1219 } 1220 1221 if (GRAPHICS_VER(i915) >= 4) { 1222 ee->esr = ENGINE_READ(engine, RING_ESR); 1223 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1224 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1225 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1226 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1227 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1228 ee->ccid = ENGINE_READ(engine, CCID); 1229 if (GRAPHICS_VER(i915) >= 8) { 1230 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1231 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1232 } 1233 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1234 } else { 1235 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1236 ee->ipeir = ENGINE_READ(engine, IPEIR); 1237 ee->ipehr = ENGINE_READ(engine, IPEHR); 1238 } 1239 1240 if (GRAPHICS_VER(i915) >= 11) { 1241 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); 1242 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); 1243 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); 1244 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); 1245 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); 1246 ee->nopid = ENGINE_READ(engine, RING_NOPID); 1247 ee->excc = ENGINE_READ(engine, RING_EXCC); 1248 } 1249 1250 intel_engine_get_instdone(engine, &ee->instdone); 1251 1252 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1253 ee->acthd = intel_engine_get_active_head(engine); 1254 ee->start = ENGINE_READ(engine, RING_START); 1255 ee->head = ENGINE_READ(engine, RING_HEAD); 1256 ee->tail = ENGINE_READ(engine, RING_TAIL); 1257 ee->ctl = ENGINE_READ(engine, RING_CTL); 1258 if (GRAPHICS_VER(i915) > 2) 1259 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1260 1261 if (!HWS_NEEDS_PHYSICAL(i915)) { 1262 i915_reg_t mmio; 1263 1264 if (GRAPHICS_VER(i915) == 7) { 1265 switch (engine->id) { 1266 default: 1267 MISSING_CASE(engine->id); 1268 fallthrough; 1269 case RCS0: 1270 mmio = RENDER_HWS_PGA_GEN7; 1271 break; 1272 case BCS0: 1273 mmio = BLT_HWS_PGA_GEN7; 1274 break; 1275 case VCS0: 1276 mmio = BSD_HWS_PGA_GEN7; 1277 break; 1278 case VECS0: 1279 mmio = VEBOX_HWS_PGA_GEN7; 1280 break; 1281 } 1282 } else if (GRAPHICS_VER(engine->i915) == 6) { 1283 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1284 } else { 1285 /* XXX: gen8 returns to sanity */ 1286 mmio = RING_HWS_PGA(engine->mmio_base); 1287 } 1288 1289 ee->hws = intel_uncore_read(engine->uncore, mmio); 1290 } 1291 1292 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1293 1294 if (HAS_PPGTT(i915)) { 1295 int i; 1296 1297 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1298 1299 if (GRAPHICS_VER(i915) == 6) { 1300 ee->vm_info.pp_dir_base = 1301 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1302 } else if (GRAPHICS_VER(i915) == 7) { 1303 ee->vm_info.pp_dir_base = 1304 ENGINE_READ(engine, RING_PP_DIR_BASE); 1305 } else if (GRAPHICS_VER(i915) >= 8) { 1306 u32 base = engine->mmio_base; 1307 1308 for (i = 0; i < 4; i++) { 1309 ee->vm_info.pdp[i] = 1310 intel_uncore_read(engine->uncore, 1311 GEN8_RING_PDP_UDW(base, i)); 1312 ee->vm_info.pdp[i] <<= 32; 1313 ee->vm_info.pdp[i] |= 1314 intel_uncore_read(engine->uncore, 1315 GEN8_RING_PDP_LDW(base, i)); 1316 } 1317 } 1318 } 1319 } 1320 1321 static void record_request(const struct i915_request *request, 1322 struct i915_request_coredump *erq) 1323 { 1324 erq->flags = request->fence.flags; 1325 erq->context = request->fence.context; 1326 erq->seqno = request->fence.seqno; 1327 erq->sched_attr = request->sched.attr; 1328 erq->head = request->head; 1329 erq->tail = request->tail; 1330 1331 erq->pid = 0; 1332 rcu_read_lock(); 1333 if (!intel_context_is_closed(request->context)) { 1334 const struct i915_gem_context *ctx; 1335 1336 ctx = rcu_dereference(request->context->gem_context); 1337 if (ctx) 1338 erq->pid = pid_nr(ctx->pid); 1339 } 1340 rcu_read_unlock(); 1341 } 1342 1343 static void engine_record_execlists(struct intel_engine_coredump *ee) 1344 { 1345 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1346 struct i915_request * const *port = el->active; 1347 unsigned int n = 0; 1348 1349 while (*port) 1350 record_request(*port++, &ee->execlist[n++]); 1351 1352 ee->num_ports = n; 1353 } 1354 1355 static bool record_context(struct i915_gem_context_coredump *e, 1356 const struct i915_request *rq) 1357 { 1358 struct i915_gem_context *ctx; 1359 struct task_struct *task; 1360 bool simulated; 1361 1362 rcu_read_lock(); 1363 ctx = rcu_dereference(rq->context->gem_context); 1364 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1365 ctx = NULL; 1366 rcu_read_unlock(); 1367 if (!ctx) 1368 return true; 1369 1370 rcu_read_lock(); 1371 task = pid_task(ctx->pid, PIDTYPE_PID); 1372 if (task) { 1373 strcpy(e->comm, task->comm); 1374 e->pid = task->pid; 1375 } 1376 rcu_read_unlock(); 1377 1378 e->sched_attr = ctx->sched; 1379 e->guilty = atomic_read(&ctx->guilty_count); 1380 e->active = atomic_read(&ctx->active_count); 1381 1382 e->total_runtime = intel_context_get_total_runtime_ns(rq->context); 1383 e->avg_runtime = intel_context_get_avg_runtime_ns(rq->context); 1384 1385 simulated = i915_gem_context_no_error_capture(ctx); 1386 1387 i915_gem_context_put(ctx); 1388 return simulated; 1389 } 1390 1391 struct intel_engine_capture_vma { 1392 struct intel_engine_capture_vma *next; 1393 struct i915_vma_resource *vma_res; 1394 char name[16]; 1395 bool lockdep_cookie; 1396 }; 1397 1398 static struct intel_engine_capture_vma * 1399 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1400 struct i915_vma_resource *vma_res, 1401 gfp_t gfp, const char *name) 1402 { 1403 struct intel_engine_capture_vma *c; 1404 1405 if (!vma_res) 1406 return next; 1407 1408 c = kmalloc(sizeof(*c), gfp); 1409 if (!c) 1410 return next; 1411 1412 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1413 kfree(c); 1414 return next; 1415 } 1416 1417 strcpy(c->name, name); 1418 c->vma_res = i915_vma_resource_get(vma_res); 1419 1420 c->next = next; 1421 return c; 1422 } 1423 1424 static struct intel_engine_capture_vma * 1425 capture_vma(struct intel_engine_capture_vma *next, 1426 struct i915_vma *vma, 1427 const char *name, 1428 gfp_t gfp) 1429 { 1430 if (!vma) 1431 return next; 1432 1433 /* 1434 * If the vma isn't pinned, then the vma should be snapshotted 1435 * to a struct i915_vma_snapshot at command submission time. 1436 * Not here. 1437 */ 1438 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1439 return next; 1440 1441 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1442 1443 return next; 1444 } 1445 1446 static struct intel_engine_capture_vma * 1447 capture_user(struct intel_engine_capture_vma *capture, 1448 const struct i915_request *rq, 1449 gfp_t gfp) 1450 { 1451 struct i915_capture_list *c; 1452 1453 for (c = rq->capture_list; c; c = c->next) 1454 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1455 "user"); 1456 1457 return capture; 1458 } 1459 1460 static void add_vma(struct intel_engine_coredump *ee, 1461 struct i915_vma_coredump *vma) 1462 { 1463 if (vma) { 1464 vma->next = ee->vma; 1465 ee->vma = vma; 1466 } 1467 } 1468 1469 static struct i915_vma_coredump * 1470 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1471 const char *name, struct i915_vma_compress *compress) 1472 { 1473 struct i915_vma_coredump *ret = NULL; 1474 struct i915_vma_resource *vma_res; 1475 bool lockdep_cookie; 1476 1477 if (!vma) 1478 return NULL; 1479 1480 vma_res = vma->resource; 1481 1482 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1483 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1484 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1485 } 1486 1487 return ret; 1488 } 1489 1490 static void add_vma_coredump(struct intel_engine_coredump *ee, 1491 const struct intel_gt *gt, 1492 struct i915_vma *vma, 1493 const char *name, 1494 struct i915_vma_compress *compress) 1495 { 1496 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1497 } 1498 1499 struct intel_engine_coredump * 1500 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1501 { 1502 struct intel_engine_coredump *ee; 1503 1504 ee = kzalloc(sizeof(*ee), gfp); 1505 if (!ee) 1506 return NULL; 1507 1508 ee->engine = engine; 1509 1510 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1511 engine_record_registers(ee); 1512 engine_record_execlists(ee); 1513 } 1514 1515 return ee; 1516 } 1517 1518 struct intel_engine_capture_vma * 1519 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1520 struct i915_request *rq, 1521 gfp_t gfp) 1522 { 1523 struct intel_engine_capture_vma *vma = NULL; 1524 1525 ee->simulated |= record_context(&ee->context, rq); 1526 if (ee->simulated) 1527 return NULL; 1528 1529 /* 1530 * We need to copy these to an anonymous buffer 1531 * as the simplest method to avoid being overwritten 1532 * by userspace. 1533 */ 1534 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1535 vma = capture_user(vma, rq, gfp); 1536 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1537 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1538 1539 ee->rq_head = rq->head; 1540 ee->rq_post = rq->postfix; 1541 ee->rq_tail = rq->tail; 1542 1543 return vma; 1544 } 1545 1546 void 1547 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1548 struct intel_engine_capture_vma *capture, 1549 struct i915_vma_compress *compress) 1550 { 1551 const struct intel_engine_cs *engine = ee->engine; 1552 1553 while (capture) { 1554 struct intel_engine_capture_vma *this = capture; 1555 struct i915_vma_resource *vma_res = this->vma_res; 1556 1557 add_vma(ee, 1558 i915_vma_coredump_create(engine->gt, vma_res, 1559 compress, this->name)); 1560 1561 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1562 i915_vma_resource_put(vma_res); 1563 1564 capture = this->next; 1565 kfree(this); 1566 } 1567 1568 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1569 "HW Status", compress); 1570 1571 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1572 "WA context", compress); 1573 } 1574 1575 static struct intel_engine_coredump * 1576 capture_engine(struct intel_engine_cs *engine, 1577 struct i915_vma_compress *compress, 1578 u32 dump_flags) 1579 { 1580 struct intel_engine_capture_vma *capture = NULL; 1581 struct intel_engine_coredump *ee; 1582 struct intel_context *ce; 1583 struct i915_request *rq = NULL; 1584 unsigned long flags; 1585 1586 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1587 if (!ee) 1588 return NULL; 1589 1590 ce = intel_engine_get_hung_context(engine); 1591 if (ce) { 1592 intel_engine_clear_hung_context(engine); 1593 rq = intel_context_find_active_request(ce); 1594 if (!rq || !i915_request_started(rq)) 1595 goto no_request_capture; 1596 } else { 1597 /* 1598 * Getting here with GuC enabled means it is a forced error capture 1599 * with no actual hang. So, no need to attempt the execlist search. 1600 */ 1601 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1602 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1603 rq = intel_engine_execlist_find_hung_request(engine); 1604 spin_unlock_irqrestore(&engine->sched_engine->lock, 1605 flags); 1606 } 1607 } 1608 if (rq) 1609 rq = i915_request_get_rcu(rq); 1610 1611 if (!rq) 1612 goto no_request_capture; 1613 1614 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1615 if (!capture) { 1616 i915_request_put(rq); 1617 goto no_request_capture; 1618 } 1619 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1620 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1621 1622 intel_engine_coredump_add_vma(ee, capture, compress); 1623 i915_request_put(rq); 1624 1625 return ee; 1626 1627 no_request_capture: 1628 kfree(ee); 1629 return NULL; 1630 } 1631 1632 static void 1633 gt_record_engines(struct intel_gt_coredump *gt, 1634 intel_engine_mask_t engine_mask, 1635 struct i915_vma_compress *compress, 1636 u32 dump_flags) 1637 { 1638 struct intel_engine_cs *engine; 1639 enum intel_engine_id id; 1640 1641 for_each_engine(engine, gt->_gt, id) { 1642 struct intel_engine_coredump *ee; 1643 1644 /* Refill our page pool before entering atomic section */ 1645 pool_refill(&compress->pool, ALLOW_FAIL); 1646 1647 ee = capture_engine(engine, compress, dump_flags); 1648 if (!ee) 1649 continue; 1650 1651 ee->hung = engine->mask & engine_mask; 1652 1653 gt->simulated |= ee->simulated; 1654 if (ee->simulated) { 1655 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1656 intel_guc_capture_free_node(ee); 1657 kfree(ee); 1658 continue; 1659 } 1660 1661 ee->next = gt->engine; 1662 gt->engine = ee; 1663 } 1664 } 1665 1666 static struct intel_uc_coredump * 1667 gt_record_uc(struct intel_gt_coredump *gt, 1668 struct i915_vma_compress *compress) 1669 { 1670 const struct intel_uc *uc = >->_gt->uc; 1671 struct intel_uc_coredump *error_uc; 1672 1673 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1674 if (!error_uc) 1675 return NULL; 1676 1677 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1678 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1679 1680 /* Non-default firmware paths will be specified by the modparam. 1681 * As modparams are generally accesible from the userspace make 1682 * explicit copies of the firmware paths. 1683 */ 1684 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1685 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1686 error_uc->guc_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1687 "GuC log buffer", compress); 1688 1689 return error_uc; 1690 } 1691 1692 /* Capture display registers. */ 1693 static void gt_record_display_regs(struct intel_gt_coredump *gt) 1694 { 1695 struct intel_uncore *uncore = gt->_gt->uncore; 1696 struct drm_i915_private *i915 = uncore->i915; 1697 1698 if (GRAPHICS_VER(i915) >= 6) 1699 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1700 1701 if (GRAPHICS_VER(i915) >= 8) 1702 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1703 else if (IS_VALLEYVIEW(i915)) 1704 gt->ier = intel_uncore_read(uncore, VLV_IER); 1705 else if (HAS_PCH_SPLIT(i915)) 1706 gt->ier = intel_uncore_read(uncore, DEIER); 1707 else if (GRAPHICS_VER(i915) == 2) 1708 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1709 else 1710 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1711 } 1712 1713 /* Capture all other registers that GuC doesn't capture. */ 1714 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1715 { 1716 struct intel_uncore *uncore = gt->_gt->uncore; 1717 struct drm_i915_private *i915 = uncore->i915; 1718 int i; 1719 1720 if (IS_VALLEYVIEW(i915)) { 1721 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1722 gt->ngtier = 1; 1723 } else if (GRAPHICS_VER(i915) >= 11) { 1724 gt->gtier[0] = 1725 intel_uncore_read(uncore, 1726 GEN11_RENDER_COPY_INTR_ENABLE); 1727 gt->gtier[1] = 1728 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1729 gt->gtier[2] = 1730 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1731 gt->gtier[3] = 1732 intel_uncore_read(uncore, 1733 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1734 gt->gtier[4] = 1735 intel_uncore_read(uncore, 1736 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1737 gt->gtier[5] = 1738 intel_uncore_read(uncore, 1739 GEN11_GUNIT_CSME_INTR_ENABLE); 1740 gt->ngtier = 6; 1741 } else if (GRAPHICS_VER(i915) >= 8) { 1742 for (i = 0; i < 4; i++) 1743 gt->gtier[i] = 1744 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1745 gt->ngtier = 4; 1746 } else if (HAS_PCH_SPLIT(i915)) { 1747 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1748 gt->ngtier = 1; 1749 } 1750 1751 gt->eir = intel_uncore_read(uncore, EIR); 1752 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1753 } 1754 1755 /* 1756 * Capture all registers that relate to workload submission. 1757 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1758 */ 1759 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1760 { 1761 struct intel_uncore *uncore = gt->_gt->uncore; 1762 struct drm_i915_private *i915 = uncore->i915; 1763 int i; 1764 1765 /* 1766 * General organization 1767 * 1. Registers specific to a single generation 1768 * 2. Registers which belong to multiple generations 1769 * 3. Feature specific registers. 1770 * 4. Everything else 1771 * Please try to follow the order. 1772 */ 1773 1774 /* 1: Registers specific to a single generation */ 1775 if (IS_VALLEYVIEW(i915)) 1776 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1777 1778 if (GRAPHICS_VER(i915) == 7) 1779 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1780 1781 if (GRAPHICS_VER(i915) >= 12) { 1782 gt->fault_data0 = intel_uncore_read(uncore, 1783 GEN12_FAULT_TLB_DATA0); 1784 gt->fault_data1 = intel_uncore_read(uncore, 1785 GEN12_FAULT_TLB_DATA1); 1786 } else if (GRAPHICS_VER(i915) >= 8) { 1787 gt->fault_data0 = intel_uncore_read(uncore, 1788 GEN8_FAULT_TLB_DATA0); 1789 gt->fault_data1 = intel_uncore_read(uncore, 1790 GEN8_FAULT_TLB_DATA1); 1791 } 1792 1793 if (GRAPHICS_VER(i915) == 6) { 1794 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1795 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1796 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1797 } 1798 1799 /* 2: Registers which belong to multiple generations */ 1800 if (GRAPHICS_VER(i915) >= 7) 1801 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1802 1803 if (GRAPHICS_VER(i915) >= 6) { 1804 if (GRAPHICS_VER(i915) < 12) { 1805 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1806 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1807 } 1808 } 1809 1810 /* 3: Feature specific registers */ 1811 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1812 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1813 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1814 } 1815 1816 if (IS_GRAPHICS_VER(i915, 8, 11)) 1817 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1818 1819 if (GRAPHICS_VER(i915) == 12) 1820 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1821 1822 if (GRAPHICS_VER(i915) >= 12) { 1823 for (i = 0; i < I915_MAX_SFC; i++) { 1824 /* 1825 * SFC_DONE resides in the VD forcewake domain, so it 1826 * only exists if the corresponding VCS engine is 1827 * present. 1828 */ 1829 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1830 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1831 continue; 1832 1833 gt->sfc_done[i] = 1834 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1835 } 1836 1837 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1838 } 1839 } 1840 1841 static void gt_record_info(struct intel_gt_coredump *gt) 1842 { 1843 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1844 } 1845 1846 /* 1847 * Generate a semi-unique error code. The code is not meant to have meaning, The 1848 * code's only purpose is to try to prevent false duplicated bug reports by 1849 * grossly estimating a GPU error state. 1850 * 1851 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1852 * the hang if we could strip the GTT offset information from it. 1853 * 1854 * It's only a small step better than a random number in its current form. 1855 */ 1856 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1857 { 1858 /* 1859 * IPEHR would be an ideal way to detect errors, as it's the gross 1860 * measure of "the command that hung." However, has some very common 1861 * synchronization commands which almost always appear in the case 1862 * strictly a client bug. Use instdone to differentiate those some. 1863 */ 1864 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1865 } 1866 1867 static const char *error_msg(struct i915_gpu_coredump *error) 1868 { 1869 struct intel_engine_coredump *first = NULL; 1870 unsigned int hung_classes = 0; 1871 struct intel_gt_coredump *gt; 1872 int len; 1873 1874 for (gt = error->gt; gt; gt = gt->next) { 1875 struct intel_engine_coredump *cs; 1876 1877 for (cs = gt->engine; cs; cs = cs->next) { 1878 if (cs->hung) { 1879 hung_classes |= BIT(cs->engine->uabi_class); 1880 if (!first) 1881 first = cs; 1882 } 1883 } 1884 } 1885 1886 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1887 "GPU HANG: ecode %d:%x:%08x", 1888 GRAPHICS_VER(error->i915), hung_classes, 1889 generate_ecode(first)); 1890 if (first && first->context.pid) { 1891 /* Just show the first executing process, more is confusing */ 1892 len += scnprintf(error->error_msg + len, 1893 sizeof(error->error_msg) - len, 1894 ", in %s [%d]", 1895 first->context.comm, first->context.pid); 1896 } 1897 1898 return error->error_msg; 1899 } 1900 1901 static void capture_gen(struct i915_gpu_coredump *error) 1902 { 1903 struct drm_i915_private *i915 = error->i915; 1904 1905 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1906 error->suspended = i915->runtime_pm.suspended; 1907 1908 error->iommu = i915_vtd_active(i915); 1909 error->reset_count = i915_reset_count(&i915->gpu_error); 1910 error->suspend_count = i915->suspend_count; 1911 1912 i915_params_copy(&error->params, &i915->params); 1913 memcpy(&error->device_info, 1914 INTEL_INFO(i915), 1915 sizeof(error->device_info)); 1916 memcpy(&error->runtime_info, 1917 RUNTIME_INFO(i915), 1918 sizeof(error->runtime_info)); 1919 error->driver_caps = i915->caps; 1920 } 1921 1922 struct i915_gpu_coredump * 1923 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1924 { 1925 struct i915_gpu_coredump *error; 1926 1927 if (!i915->params.error_capture) 1928 return NULL; 1929 1930 error = kzalloc(sizeof(*error), gfp); 1931 if (!error) 1932 return NULL; 1933 1934 kref_init(&error->ref); 1935 error->i915 = i915; 1936 1937 error->time = ktime_get_real(); 1938 error->boottime = ktime_get_boottime(); 1939 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1940 error->capture = jiffies; 1941 1942 capture_gen(error); 1943 1944 return error; 1945 } 1946 1947 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1948 1949 struct intel_gt_coredump * 1950 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 1951 { 1952 struct intel_gt_coredump *gc; 1953 1954 gc = kzalloc(sizeof(*gc), gfp); 1955 if (!gc) 1956 return NULL; 1957 1958 gc->_gt = gt; 1959 gc->awake = intel_gt_pm_is_awake(gt); 1960 1961 gt_record_display_regs(gc); 1962 gt_record_global_nonguc_regs(gc); 1963 1964 /* 1965 * GuC dumps global, eng-class and eng-instance registers 1966 * (that can change as part of engine state during execution) 1967 * before an engine is reset due to a hung context. 1968 * GuC captures and reports all three groups of registers 1969 * together as a single set before the engine is reset. 1970 * Thus, if GuC triggered the context reset we retrieve 1971 * the register values as part of gt_record_engines. 1972 */ 1973 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 1974 gt_record_global_regs(gc); 1975 1976 gt_record_fences(gc); 1977 1978 return gc; 1979 } 1980 1981 struct i915_vma_compress * 1982 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1983 { 1984 struct i915_vma_compress *compress; 1985 1986 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1987 if (!compress) 1988 return NULL; 1989 1990 if (!compress_init(compress)) { 1991 kfree(compress); 1992 return NULL; 1993 } 1994 1995 return compress; 1996 } 1997 1998 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1999 struct i915_vma_compress *compress) 2000 { 2001 if (!compress) 2002 return; 2003 2004 compress_fini(compress); 2005 kfree(compress); 2006 } 2007 2008 static struct i915_gpu_coredump * 2009 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2010 { 2011 struct drm_i915_private *i915 = gt->i915; 2012 struct i915_gpu_coredump *error; 2013 2014 /* Check if GPU capture has been disabled */ 2015 error = READ_ONCE(i915->gpu_error.first_error); 2016 if (IS_ERR(error)) 2017 return error; 2018 2019 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 2020 if (!error) 2021 return ERR_PTR(-ENOMEM); 2022 2023 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2024 if (error->gt) { 2025 struct i915_vma_compress *compress; 2026 2027 compress = i915_vma_capture_prepare(error->gt); 2028 if (!compress) { 2029 kfree(error->gt); 2030 kfree(error); 2031 return ERR_PTR(-ENOMEM); 2032 } 2033 2034 if (INTEL_INFO(i915)->has_gt_uc) { 2035 error->gt->uc = gt_record_uc(error->gt, compress); 2036 if (error->gt->uc) { 2037 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2038 error->gt->uc->is_guc_capture = true; 2039 else 2040 GEM_BUG_ON(error->gt->uc->is_guc_capture); 2041 } 2042 } 2043 2044 gt_record_info(error->gt); 2045 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2046 2047 2048 i915_vma_capture_finish(error->gt, compress); 2049 2050 error->simulated |= error->gt->simulated; 2051 } 2052 2053 error->overlay = intel_overlay_capture_error_state(i915); 2054 2055 return error; 2056 } 2057 2058 struct i915_gpu_coredump * 2059 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2060 { 2061 static DEFINE_MUTEX(capture_mutex); 2062 int ret = mutex_lock_interruptible(&capture_mutex); 2063 struct i915_gpu_coredump *dump; 2064 2065 if (ret) 2066 return ERR_PTR(ret); 2067 2068 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2069 mutex_unlock(&capture_mutex); 2070 2071 return dump; 2072 } 2073 2074 void i915_error_state_store(struct i915_gpu_coredump *error) 2075 { 2076 struct drm_i915_private *i915; 2077 static bool warned; 2078 2079 if (IS_ERR_OR_NULL(error)) 2080 return; 2081 2082 i915 = error->i915; 2083 drm_info(&i915->drm, "%s\n", error_msg(error)); 2084 2085 if (error->simulated || 2086 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2087 return; 2088 2089 i915_gpu_coredump_get(error); 2090 2091 if (!xchg(&warned, true) && 2092 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 2093 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 2094 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 2095 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 2096 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 2097 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 2098 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 2099 i915->drm.primary->index); 2100 } 2101 } 2102 2103 /** 2104 * i915_capture_error_state - capture an error record for later analysis 2105 * @gt: intel_gt which originated the hang 2106 * @engine_mask: hung engines 2107 * 2108 * 2109 * Should be called when an error is detected (either a hang or an error 2110 * interrupt) to capture error state from the time of the error. Fills 2111 * out a structure which becomes available in debugfs for user level tools 2112 * to pick up. 2113 */ 2114 void i915_capture_error_state(struct intel_gt *gt, 2115 intel_engine_mask_t engine_mask, u32 dump_flags) 2116 { 2117 struct i915_gpu_coredump *error; 2118 2119 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2120 if (IS_ERR(error)) { 2121 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2122 return; 2123 } 2124 2125 i915_error_state_store(error); 2126 i915_gpu_coredump_put(error); 2127 } 2128 2129 struct i915_gpu_coredump * 2130 i915_first_error_state(struct drm_i915_private *i915) 2131 { 2132 struct i915_gpu_coredump *error; 2133 2134 spin_lock_irq(&i915->gpu_error.lock); 2135 error = i915->gpu_error.first_error; 2136 if (!IS_ERR_OR_NULL(error)) 2137 i915_gpu_coredump_get(error); 2138 spin_unlock_irq(&i915->gpu_error.lock); 2139 2140 return error; 2141 } 2142 2143 void i915_reset_error_state(struct drm_i915_private *i915) 2144 { 2145 struct i915_gpu_coredump *error; 2146 2147 spin_lock_irq(&i915->gpu_error.lock); 2148 error = i915->gpu_error.first_error; 2149 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2150 i915->gpu_error.first_error = NULL; 2151 spin_unlock_irq(&i915->gpu_error.lock); 2152 2153 if (!IS_ERR_OR_NULL(error)) 2154 i915_gpu_coredump_put(error); 2155 } 2156 2157 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2158 { 2159 spin_lock_irq(&i915->gpu_error.lock); 2160 if (!i915->gpu_error.first_error) 2161 i915->gpu_error.first_error = ERR_PTR(err); 2162 spin_unlock_irq(&i915->gpu_error.lock); 2163 } 2164