1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 #include <linux/mm.h> 39 #include <linux/pagevec.h> 40 41 #include "i915_request.h" 42 #include "i915_selftest.h" 43 #include "i915_timeline.h" 44 45 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 46 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 47 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 48 49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 51 52 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 53 54 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 55 56 #define I915_FENCE_REG_NONE -1 57 #define I915_MAX_NUM_FENCES 32 58 /* 32 fences + sign bit for FENCE_REG_NONE */ 59 #define I915_MAX_NUM_FENCE_BITS 6 60 61 struct drm_i915_file_private; 62 struct drm_i915_fence_reg; 63 struct i915_vma; 64 65 typedef u32 gen6_pte_t; 66 typedef u64 gen8_pte_t; 67 typedef u64 gen8_pde_t; 68 typedef u64 gen8_ppgtt_pdpe_t; 69 typedef u64 gen8_ppgtt_pml4e_t; 70 71 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 72 73 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 74 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 75 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 76 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 77 #define GEN6_PTE_CACHE_LLC (2 << 1) 78 #define GEN6_PTE_UNCACHED (1 << 1) 79 #define GEN6_PTE_VALID (1 << 0) 80 81 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 82 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 83 #define I915_PDES 512 84 #define I915_PDE_MASK (I915_PDES - 1) 85 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 86 87 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 88 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 89 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 90 #define GEN6_PDE_SHIFT 22 91 #define GEN6_PDE_VALID (1 << 0) 92 93 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 94 95 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 96 #define BYT_PTE_WRITEABLE (1 << 1) 97 98 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 99 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 100 */ 101 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 102 (((bits) & 0x8) << (11 - 3))) 103 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 104 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 105 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 106 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 107 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 108 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 109 #define HSW_PTE_UNCACHED (0) 110 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 111 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 112 113 /* GEN8 32b style address is defined as a 3 level page table: 114 * 31:30 | 29:21 | 20:12 | 11:0 115 * PDPE | PDE | PTE | offset 116 * The difference as compared to normal x86 3 level page table is the PDPEs are 117 * programmed via register. 118 */ 119 #define GEN8_3LVL_PDPES 4 120 #define GEN8_PDE_SHIFT 21 121 #define GEN8_PDE_MASK 0x1ff 122 #define GEN8_PTE_SHIFT 12 123 #define GEN8_PTE_MASK 0x1ff 124 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 125 126 /* GEN8 48b style address is defined as a 4 level page table: 127 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 128 * PML4E | PDPE | PDE | PTE | offset 129 */ 130 #define GEN8_PML4ES_PER_PML4 512 131 #define GEN8_PML4E_SHIFT 39 132 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 133 #define GEN8_PDPE_SHIFT 30 134 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 135 * tables */ 136 #define GEN8_PDPE_MASK 0x1ff 137 138 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 139 #define PPAT_CACHED_PDE 0 /* WB LLC */ 140 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 141 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 142 143 #define CHV_PPAT_SNOOP (1<<6) 144 #define GEN8_PPAT_AGE(x) ((x)<<4) 145 #define GEN8_PPAT_LLCeLLC (3<<2) 146 #define GEN8_PPAT_LLCELLC (2<<2) 147 #define GEN8_PPAT_LLC (1<<2) 148 #define GEN8_PPAT_WB (3<<0) 149 #define GEN8_PPAT_WT (2<<0) 150 #define GEN8_PPAT_WC (1<<0) 151 #define GEN8_PPAT_UC (0<<0) 152 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 153 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 154 155 #define GEN8_PPAT_GET_CA(x) ((x) & 3) 156 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 157 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 158 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 159 160 #define GEN8_PDE_IPS_64K BIT(11) 161 #define GEN8_PDE_PS_2M BIT(7) 162 163 struct sg_table; 164 165 struct intel_rotation_info { 166 struct intel_rotation_plane_info { 167 /* tiles */ 168 unsigned int width, height, stride, offset; 169 } plane[2]; 170 } __packed; 171 172 struct intel_partial_info { 173 u64 offset; 174 unsigned int size; 175 } __packed; 176 177 enum i915_ggtt_view_type { 178 I915_GGTT_VIEW_NORMAL = 0, 179 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 180 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 181 }; 182 183 static inline void assert_i915_gem_gtt_types(void) 184 { 185 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 186 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 187 188 /* As we encode the size of each branch inside the union into its type, 189 * we have to be careful that each branch has a unique size. 190 */ 191 switch ((enum i915_ggtt_view_type)0) { 192 case I915_GGTT_VIEW_NORMAL: 193 case I915_GGTT_VIEW_PARTIAL: 194 case I915_GGTT_VIEW_ROTATED: 195 /* gcc complains if these are identical cases */ 196 break; 197 } 198 } 199 200 struct i915_ggtt_view { 201 enum i915_ggtt_view_type type; 202 union { 203 /* Members need to contain no holes/padding */ 204 struct intel_partial_info partial; 205 struct intel_rotation_info rotated; 206 }; 207 }; 208 209 enum i915_cache_level; 210 211 struct i915_vma; 212 213 struct i915_page_dma { 214 struct page *page; 215 int order; 216 union { 217 dma_addr_t daddr; 218 219 /* For gen6/gen7 only. This is the offset in the GGTT 220 * where the page directory entries for PPGTT begin 221 */ 222 u32 ggtt_offset; 223 }; 224 }; 225 226 #define px_base(px) (&(px)->base) 227 #define px_dma(px) (px_base(px)->daddr) 228 229 struct i915_page_table { 230 struct i915_page_dma base; 231 unsigned int used_ptes; 232 }; 233 234 struct i915_page_directory { 235 struct i915_page_dma base; 236 237 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 238 unsigned int used_pdes; 239 }; 240 241 struct i915_page_directory_pointer { 242 struct i915_page_dma base; 243 struct i915_page_directory **page_directory; 244 unsigned int used_pdpes; 245 }; 246 247 struct i915_pml4 { 248 struct i915_page_dma base; 249 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 250 }; 251 252 struct i915_vma_ops { 253 /* Map an object into an address space with the given cache flags. */ 254 int (*bind_vma)(struct i915_vma *vma, 255 enum i915_cache_level cache_level, 256 u32 flags); 257 /* 258 * Unmap an object from an address space. This usually consists of 259 * setting the valid PTE entries to a reserved scratch page. 260 */ 261 void (*unbind_vma)(struct i915_vma *vma); 262 263 int (*set_pages)(struct i915_vma *vma); 264 void (*clear_pages)(struct i915_vma *vma); 265 }; 266 267 struct pagestash { 268 spinlock_t lock; 269 struct pagevec pvec; 270 }; 271 272 struct i915_address_space { 273 struct drm_mm mm; 274 struct drm_i915_private *i915; 275 struct device *dma; 276 /* Every address space belongs to a struct file - except for the global 277 * GTT that is owned by the driver (and so @file is set to NULL). In 278 * principle, no information should leak from one context to another 279 * (or between files/processes etc) unless explicitly shared by the 280 * owner. Tracking the owner is important in order to free up per-file 281 * objects along with the file, to aide resource tracking, and to 282 * assign blame. 283 */ 284 struct drm_i915_file_private *file; 285 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 286 u64 reserved; /* size addr space reserved */ 287 288 bool closed; 289 290 struct mutex mutex; /* protects vma and our lists */ 291 292 struct i915_page_dma scratch_page; 293 struct i915_page_table *scratch_pt; 294 struct i915_page_directory *scratch_pd; 295 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 296 297 /** 298 * List of objects currently involved in rendering. 299 * 300 * Includes buffers having the contents of their GPU caches 301 * flushed, not necessarily primitives. last_read_req 302 * represents when the rendering involved will be completed. 303 * 304 * A reference is held on the buffer while on this list. 305 */ 306 struct list_head active_list; 307 308 /** 309 * LRU list of objects which are not in the ringbuffer and 310 * are ready to unbind, but are still in the GTT. 311 * 312 * last_read_req is NULL while an object is in this list. 313 * 314 * A reference is not held on the buffer while on this list, 315 * as merely being GTT-bound shouldn't prevent its being 316 * freed, and we'll pull it off the list in the free path. 317 */ 318 struct list_head inactive_list; 319 320 /** 321 * List of vma that have been unbound. 322 * 323 * A reference is not held on the buffer while on this list. 324 */ 325 struct list_head unbound_list; 326 327 struct pagestash free_pages; 328 329 /* Global GTT */ 330 bool is_ggtt:1; 331 332 /* Some systems require uncached updates of the page directories */ 333 bool pt_kmap_wc:1; 334 335 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 336 bool has_read_only:1; 337 338 /* FIXME: Need a more generic return type */ 339 gen6_pte_t (*pte_encode)(dma_addr_t addr, 340 enum i915_cache_level level, 341 u32 flags); /* Create a valid PTE */ 342 /* flags for pte_encode */ 343 #define PTE_READ_ONLY (1<<0) 344 int (*allocate_va_range)(struct i915_address_space *vm, 345 u64 start, u64 length); 346 void (*clear_range)(struct i915_address_space *vm, 347 u64 start, u64 length); 348 void (*insert_page)(struct i915_address_space *vm, 349 dma_addr_t addr, 350 u64 offset, 351 enum i915_cache_level cache_level, 352 u32 flags); 353 void (*insert_entries)(struct i915_address_space *vm, 354 struct i915_vma *vma, 355 enum i915_cache_level cache_level, 356 u32 flags); 357 void (*cleanup)(struct i915_address_space *vm); 358 359 struct i915_vma_ops vma_ops; 360 361 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 362 I915_SELFTEST_DECLARE(bool scrub_64K); 363 }; 364 365 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 366 367 static inline bool 368 i915_vm_is_48bit(const struct i915_address_space *vm) 369 { 370 return (vm->total - 1) >> 32; 371 } 372 373 static inline bool 374 i915_vm_has_scratch_64K(struct i915_address_space *vm) 375 { 376 return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K); 377 } 378 379 /* The Graphics Translation Table is the way in which GEN hardware translates a 380 * Graphics Virtual Address into a Physical Address. In addition to the normal 381 * collateral associated with any va->pa translations GEN hardware also has a 382 * portion of the GTT which can be mapped by the CPU and remain both coherent 383 * and correct (in cases like swizzling). That region is referred to as GMADR in 384 * the spec. 385 */ 386 struct i915_ggtt { 387 struct i915_address_space vm; 388 389 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 390 struct resource gmadr; /* GMADR resource */ 391 resource_size_t mappable_end; /* End offset that we can CPU map */ 392 393 /** "Graphics Stolen Memory" holds the global PTEs */ 394 void __iomem *gsm; 395 void (*invalidate)(struct drm_i915_private *dev_priv); 396 397 bool do_idle_maps; 398 399 int mtrr; 400 401 u32 pin_bias; 402 403 struct drm_mm_node error_capture; 404 }; 405 406 struct i915_hw_ppgtt { 407 struct i915_address_space vm; 408 struct kref ref; 409 410 unsigned long pd_dirty_rings; 411 union { 412 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 413 struct i915_page_directory_pointer pdp; /* GEN8+ */ 414 struct i915_page_directory pd; /* GEN6-7 */ 415 }; 416 417 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 418 }; 419 420 struct gen6_hw_ppgtt { 421 struct i915_hw_ppgtt base; 422 423 struct i915_vma *vma; 424 gen6_pte_t __iomem *pd_addr; 425 gen6_pte_t scratch_pte; 426 427 unsigned int pin_count; 428 bool scan_for_unused_pt; 429 }; 430 431 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base) 432 433 static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base) 434 { 435 BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base)); 436 return __to_gen6_ppgtt(base); 437 } 438 439 /* 440 * gen6_for_each_pde() iterates over every pde from start until start+length. 441 * If start and start+length are not perfectly divisible, the macro will round 442 * down and up as needed. Start=0 and length=2G effectively iterates over 443 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 444 * so each of the other parameters should preferably be a simple variable, or 445 * at most an lvalue with no side-effects! 446 */ 447 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 448 for (iter = gen6_pde_index(start); \ 449 length > 0 && iter < I915_PDES && \ 450 (pt = (pd)->page_table[iter], true); \ 451 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 452 temp = min(temp - start, length); \ 453 start += temp, length -= temp; }), ++iter) 454 455 #define gen6_for_all_pdes(pt, pd, iter) \ 456 for (iter = 0; \ 457 iter < I915_PDES && \ 458 (pt = (pd)->page_table[iter], true); \ 459 ++iter) 460 461 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 462 { 463 const u32 mask = NUM_PTE(pde_shift) - 1; 464 465 return (address >> PAGE_SHIFT) & mask; 466 } 467 468 /* Helper to counts the number of PTEs within the given length. This count 469 * does not cross a page table boundary, so the max value would be 470 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 471 */ 472 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 473 { 474 const u64 mask = ~((1ULL << pde_shift) - 1); 475 u64 end; 476 477 GEM_BUG_ON(length == 0); 478 GEM_BUG_ON(offset_in_page(addr | length)); 479 480 end = addr + length; 481 482 if ((addr & mask) != (end & mask)) 483 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 484 485 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 486 } 487 488 static inline u32 i915_pde_index(u64 addr, u32 shift) 489 { 490 return (addr >> shift) & I915_PDE_MASK; 491 } 492 493 static inline u32 gen6_pte_index(u32 addr) 494 { 495 return i915_pte_index(addr, GEN6_PDE_SHIFT); 496 } 497 498 static inline u32 gen6_pte_count(u32 addr, u32 length) 499 { 500 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 501 } 502 503 static inline u32 gen6_pde_index(u32 addr) 504 { 505 return i915_pde_index(addr, GEN6_PDE_SHIFT); 506 } 507 508 static inline unsigned int 509 i915_pdpes_per_pdp(const struct i915_address_space *vm) 510 { 511 if (i915_vm_is_48bit(vm)) 512 return GEN8_PML4ES_PER_PML4; 513 514 return GEN8_3LVL_PDPES; 515 } 516 517 /* Equivalent to the gen6 version, For each pde iterates over every pde 518 * between from start until start + length. On gen8+ it simply iterates 519 * over every page directory entry in a page directory. 520 */ 521 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 522 for (iter = gen8_pde_index(start); \ 523 length > 0 && iter < I915_PDES && \ 524 (pt = (pd)->page_table[iter], true); \ 525 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 526 temp = min(temp - start, length); \ 527 start += temp, length -= temp; }), ++iter) 528 529 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 530 for (iter = gen8_pdpe_index(start); \ 531 length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 532 (pd = (pdp)->page_directory[iter], true); \ 533 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 534 temp = min(temp - start, length); \ 535 start += temp, length -= temp; }), ++iter) 536 537 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 538 for (iter = gen8_pml4e_index(start); \ 539 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 540 (pdp = (pml4)->pdps[iter], true); \ 541 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 542 temp = min(temp - start, length); \ 543 start += temp, length -= temp; }), ++iter) 544 545 static inline u32 gen8_pte_index(u64 address) 546 { 547 return i915_pte_index(address, GEN8_PDE_SHIFT); 548 } 549 550 static inline u32 gen8_pde_index(u64 address) 551 { 552 return i915_pde_index(address, GEN8_PDE_SHIFT); 553 } 554 555 static inline u32 gen8_pdpe_index(u64 address) 556 { 557 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 558 } 559 560 static inline u32 gen8_pml4e_index(u64 address) 561 { 562 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 563 } 564 565 static inline u64 gen8_pte_count(u64 address, u64 length) 566 { 567 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 568 } 569 570 static inline dma_addr_t 571 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 572 { 573 return px_dma(ppgtt->pdp.page_directory[n]); 574 } 575 576 static inline struct i915_ggtt * 577 i915_vm_to_ggtt(struct i915_address_space *vm) 578 { 579 GEM_BUG_ON(!i915_is_ggtt(vm)); 580 return container_of(vm, struct i915_ggtt, vm); 581 } 582 583 #define INTEL_MAX_PPAT_ENTRIES 8 584 #define INTEL_PPAT_PERFECT_MATCH (~0U) 585 586 struct intel_ppat; 587 588 struct intel_ppat_entry { 589 struct intel_ppat *ppat; 590 struct kref ref; 591 u8 value; 592 }; 593 594 struct intel_ppat { 595 struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 596 DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 597 DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 598 unsigned int max_entries; 599 u8 clear_value; 600 /* 601 * Return a score to show how two PPAT values match, 602 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 603 */ 604 unsigned int (*match)(u8 src, u8 dst); 605 void (*update_hw)(struct drm_i915_private *i915); 606 607 struct drm_i915_private *i915; 608 }; 609 610 const struct intel_ppat_entry * 611 intel_ppat_get(struct drm_i915_private *i915, u8 value); 612 void intel_ppat_put(const struct intel_ppat_entry *entry); 613 614 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 615 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 616 617 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 618 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 619 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 620 void i915_ggtt_enable_guc(struct drm_i915_private *i915); 621 void i915_ggtt_disable_guc(struct drm_i915_private *i915); 622 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 623 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 624 625 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 626 void i915_ppgtt_release(struct kref *kref); 627 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 628 struct drm_i915_file_private *fpriv); 629 void i915_ppgtt_close(struct i915_address_space *vm); 630 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 631 { 632 if (ppgtt) 633 kref_get(&ppgtt->ref); 634 } 635 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 636 { 637 if (ppgtt) 638 kref_put(&ppgtt->ref, i915_ppgtt_release); 639 } 640 641 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base); 642 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base); 643 644 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 645 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 646 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 647 648 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 649 struct sg_table *pages); 650 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 651 struct sg_table *pages); 652 653 int i915_gem_gtt_reserve(struct i915_address_space *vm, 654 struct drm_mm_node *node, 655 u64 size, u64 offset, unsigned long color, 656 unsigned int flags); 657 658 int i915_gem_gtt_insert(struct i915_address_space *vm, 659 struct drm_mm_node *node, 660 u64 size, u64 alignment, unsigned long color, 661 u64 start, u64 end, unsigned int flags); 662 663 /* Flags used by pin/bind&friends. */ 664 #define PIN_NONBLOCK BIT_ULL(0) 665 #define PIN_MAPPABLE BIT_ULL(1) 666 #define PIN_ZONE_4G BIT_ULL(2) 667 #define PIN_NONFAULT BIT_ULL(3) 668 #define PIN_NOEVICT BIT_ULL(4) 669 670 #define PIN_MBZ BIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */ 671 #define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */ 672 #define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */ 673 #define PIN_UPDATE BIT_ULL(8) 674 675 #define PIN_HIGH BIT_ULL(9) 676 #define PIN_OFFSET_BIAS BIT_ULL(10) 677 #define PIN_OFFSET_FIXED BIT_ULL(11) 678 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 679 680 #endif 681