1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 39 #include "i915_gem_request.h" 40 41 #define I915_FENCE_REG_NONE -1 42 #define I915_MAX_NUM_FENCES 32 43 /* 32 fences + sign bit for FENCE_REG_NONE */ 44 #define I915_MAX_NUM_FENCE_BITS 6 45 46 struct drm_i915_file_private; 47 struct drm_i915_fence_reg; 48 49 typedef uint32_t gen6_pte_t; 50 typedef uint64_t gen8_pte_t; 51 typedef uint64_t gen8_pde_t; 52 typedef uint64_t gen8_ppgtt_pdpe_t; 53 typedef uint64_t gen8_ppgtt_pml4e_t; 54 55 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 56 57 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 58 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 59 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 60 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 61 #define GEN6_PTE_CACHE_LLC (2 << 1) 62 #define GEN6_PTE_UNCACHED (1 << 1) 63 #define GEN6_PTE_VALID (1 << 0) 64 65 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 66 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 67 #define I915_PDES 512 68 #define I915_PDE_MASK (I915_PDES - 1) 69 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 70 71 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 72 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 73 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 74 #define GEN6_PDE_SHIFT 22 75 #define GEN6_PDE_VALID (1 << 0) 76 77 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 78 79 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 80 #define BYT_PTE_WRITEABLE (1 << 1) 81 82 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 83 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 84 */ 85 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 86 (((bits) & 0x8) << (11 - 3))) 87 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 88 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 89 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 90 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 91 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 92 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 93 #define HSW_PTE_UNCACHED (0) 94 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 95 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 96 97 /* GEN8 legacy style address is defined as a 3 level page table: 98 * 31:30 | 29:21 | 20:12 | 11:0 99 * PDPE | PDE | PTE | offset 100 * The difference as compared to normal x86 3 level page table is the PDPEs are 101 * programmed via register. 102 * 103 * GEN8 48b legacy style address is defined as a 4 level page table: 104 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 105 * PML4E | PDPE | PDE | PTE | offset 106 */ 107 #define GEN8_PML4ES_PER_PML4 512 108 #define GEN8_PML4E_SHIFT 39 109 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 110 #define GEN8_PDPE_SHIFT 30 111 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 112 * tables */ 113 #define GEN8_PDPE_MASK 0x1ff 114 #define GEN8_PDE_SHIFT 21 115 #define GEN8_PDE_MASK 0x1ff 116 #define GEN8_PTE_SHIFT 12 117 #define GEN8_PTE_MASK 0x1ff 118 #define GEN8_LEGACY_PDPES 4 119 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 120 121 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 122 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 123 124 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 125 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 126 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 127 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 128 129 #define CHV_PPAT_SNOOP (1<<6) 130 #define GEN8_PPAT_AGE(x) (x<<4) 131 #define GEN8_PPAT_LLCeLLC (3<<2) 132 #define GEN8_PPAT_LLCELLC (2<<2) 133 #define GEN8_PPAT_LLC (1<<2) 134 #define GEN8_PPAT_WB (3<<0) 135 #define GEN8_PPAT_WT (2<<0) 136 #define GEN8_PPAT_WC (1<<0) 137 #define GEN8_PPAT_UC (0<<0) 138 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 139 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 140 141 enum i915_ggtt_view_type { 142 I915_GGTT_VIEW_NORMAL = 0, 143 I915_GGTT_VIEW_ROTATED, 144 I915_GGTT_VIEW_PARTIAL, 145 }; 146 147 struct intel_rotation_info { 148 struct { 149 /* tiles */ 150 unsigned int width, height, stride, offset; 151 } plane[2]; 152 }; 153 154 struct i915_ggtt_view { 155 enum i915_ggtt_view_type type; 156 157 union { 158 struct { 159 u64 offset; 160 unsigned int size; 161 } partial; 162 struct intel_rotation_info rotated; 163 } params; 164 }; 165 166 extern const struct i915_ggtt_view i915_ggtt_view_normal; 167 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 168 169 enum i915_cache_level; 170 171 /** 172 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 173 * VMA's presence cannot be guaranteed before binding, or after unbinding the 174 * object into/from the address space. 175 * 176 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 177 * will always be <= an objects lifetime. So object refcounting should cover us. 178 */ 179 struct i915_vma { 180 struct drm_mm_node node; 181 struct drm_i915_gem_object *obj; 182 struct i915_address_space *vm; 183 struct drm_i915_fence_reg *fence; 184 struct sg_table *pages; 185 void __iomem *iomap; 186 u64 size; 187 u64 display_alignment; 188 189 unsigned int flags; 190 /** 191 * How many users have pinned this object in GTT space. The following 192 * users can each hold at most one reference: pwrite/pread, execbuffer 193 * (objects are not allowed multiple times for the same batchbuffer), 194 * and the framebuffer code. When switching/pageflipping, the 195 * framebuffer code has at most two buffers pinned per crtc. 196 * 197 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 198 * bits with absolutely no headroom. So use 4 bits. 199 */ 200 #define I915_VMA_PIN_MASK 0xf 201 #define I915_VMA_PIN_OVERFLOW BIT(5) 202 203 /** Flags and address space this VMA is bound to */ 204 #define I915_VMA_GLOBAL_BIND BIT(6) 205 #define I915_VMA_LOCAL_BIND BIT(7) 206 #define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND | I915_VMA_PIN_OVERFLOW) 207 208 #define I915_VMA_GGTT BIT(8) 209 #define I915_VMA_CAN_FENCE BIT(9) 210 #define I915_VMA_CLOSED BIT(10) 211 212 unsigned int active; 213 struct i915_gem_active last_read[I915_NUM_ENGINES]; 214 struct i915_gem_active last_write; 215 struct i915_gem_active last_fence; 216 217 /** 218 * Support different GGTT views into the same object. 219 * This means there can be multiple VMA mappings per object and per VM. 220 * i915_ggtt_view_type is used to distinguish between those entries. 221 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 222 * assumed in GEM functions which take no ggtt view parameter. 223 */ 224 struct i915_ggtt_view ggtt_view; 225 226 /** This object's place on the active/inactive lists */ 227 struct list_head vm_link; 228 229 struct list_head obj_link; /* Link in the object's VMA list */ 230 struct rb_node obj_node; 231 232 /** This vma's place in the batchbuffer or on the eviction list */ 233 struct list_head exec_list; 234 235 /** 236 * Used for performing relocations during execbuffer insertion. 237 */ 238 struct hlist_node exec_node; 239 unsigned long exec_handle; 240 struct drm_i915_gem_exec_object2 *exec_entry; 241 }; 242 243 struct i915_vma * 244 i915_vma_create(struct drm_i915_gem_object *obj, 245 struct i915_address_space *vm, 246 const struct i915_ggtt_view *view); 247 void i915_vma_unpin_and_release(struct i915_vma **p_vma); 248 249 static inline bool i915_vma_is_ggtt(const struct i915_vma *vma) 250 { 251 return vma->flags & I915_VMA_GGTT; 252 } 253 254 static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma) 255 { 256 return vma->flags & I915_VMA_CAN_FENCE; 257 } 258 259 static inline bool i915_vma_is_closed(const struct i915_vma *vma) 260 { 261 return vma->flags & I915_VMA_CLOSED; 262 } 263 264 static inline unsigned int i915_vma_get_active(const struct i915_vma *vma) 265 { 266 return vma->active; 267 } 268 269 static inline bool i915_vma_is_active(const struct i915_vma *vma) 270 { 271 return i915_vma_get_active(vma); 272 } 273 274 static inline void i915_vma_set_active(struct i915_vma *vma, 275 unsigned int engine) 276 { 277 vma->active |= BIT(engine); 278 } 279 280 static inline void i915_vma_clear_active(struct i915_vma *vma, 281 unsigned int engine) 282 { 283 vma->active &= ~BIT(engine); 284 } 285 286 static inline bool i915_vma_has_active_engine(const struct i915_vma *vma, 287 unsigned int engine) 288 { 289 return vma->active & BIT(engine); 290 } 291 292 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) 293 { 294 GEM_BUG_ON(!i915_vma_is_ggtt(vma)); 295 GEM_BUG_ON(!vma->node.allocated); 296 GEM_BUG_ON(upper_32_bits(vma->node.start)); 297 GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1)); 298 return lower_32_bits(vma->node.start); 299 } 300 301 struct i915_page_dma { 302 struct page *page; 303 union { 304 dma_addr_t daddr; 305 306 /* For gen6/gen7 only. This is the offset in the GGTT 307 * where the page directory entries for PPGTT begin 308 */ 309 uint32_t ggtt_offset; 310 }; 311 }; 312 313 #define px_base(px) (&(px)->base) 314 #define px_page(px) (px_base(px)->page) 315 #define px_dma(px) (px_base(px)->daddr) 316 317 struct i915_page_table { 318 struct i915_page_dma base; 319 320 unsigned long *used_ptes; 321 }; 322 323 struct i915_page_directory { 324 struct i915_page_dma base; 325 326 unsigned long *used_pdes; 327 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 328 }; 329 330 struct i915_page_directory_pointer { 331 struct i915_page_dma base; 332 333 unsigned long *used_pdpes; 334 struct i915_page_directory **page_directory; 335 }; 336 337 struct i915_pml4 { 338 struct i915_page_dma base; 339 340 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 341 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 342 }; 343 344 struct i915_address_space { 345 struct drm_mm mm; 346 struct i915_gem_timeline timeline; 347 struct drm_device *dev; 348 /* Every address space belongs to a struct file - except for the global 349 * GTT that is owned by the driver (and so @file is set to NULL). In 350 * principle, no information should leak from one context to another 351 * (or between files/processes etc) unless explicitly shared by the 352 * owner. Tracking the owner is important in order to free up per-file 353 * objects along with the file, to aide resource tracking, and to 354 * assign blame. 355 */ 356 struct drm_i915_file_private *file; 357 struct list_head global_link; 358 u64 start; /* Start offset always 0 for dri2 */ 359 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 360 361 bool closed; 362 363 struct i915_page_dma scratch_page; 364 struct i915_page_table *scratch_pt; 365 struct i915_page_directory *scratch_pd; 366 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 367 368 /** 369 * List of objects currently involved in rendering. 370 * 371 * Includes buffers having the contents of their GPU caches 372 * flushed, not necessarily primitives. last_read_req 373 * represents when the rendering involved will be completed. 374 * 375 * A reference is held on the buffer while on this list. 376 */ 377 struct list_head active_list; 378 379 /** 380 * LRU list of objects which are not in the ringbuffer and 381 * are ready to unbind, but are still in the GTT. 382 * 383 * last_read_req is NULL while an object is in this list. 384 * 385 * A reference is not held on the buffer while on this list, 386 * as merely being GTT-bound shouldn't prevent its being 387 * freed, and we'll pull it off the list in the free path. 388 */ 389 struct list_head inactive_list; 390 391 /** 392 * List of vma that have been unbound. 393 * 394 * A reference is not held on the buffer while on this list. 395 */ 396 struct list_head unbound_list; 397 398 /* FIXME: Need a more generic return type */ 399 gen6_pte_t (*pte_encode)(dma_addr_t addr, 400 enum i915_cache_level level, 401 u32 flags); /* Create a valid PTE */ 402 /* flags for pte_encode */ 403 #define PTE_READ_ONLY (1<<0) 404 int (*allocate_va_range)(struct i915_address_space *vm, 405 uint64_t start, 406 uint64_t length); 407 void (*clear_range)(struct i915_address_space *vm, 408 uint64_t start, 409 uint64_t length); 410 void (*insert_page)(struct i915_address_space *vm, 411 dma_addr_t addr, 412 uint64_t offset, 413 enum i915_cache_level cache_level, 414 u32 flags); 415 void (*insert_entries)(struct i915_address_space *vm, 416 struct sg_table *st, 417 uint64_t start, 418 enum i915_cache_level cache_level, u32 flags); 419 void (*cleanup)(struct i915_address_space *vm); 420 /** Unmap an object from an address space. This usually consists of 421 * setting the valid PTE entries to a reserved scratch page. */ 422 void (*unbind_vma)(struct i915_vma *vma); 423 /* Map an object into an address space with the given cache flags. */ 424 int (*bind_vma)(struct i915_vma *vma, 425 enum i915_cache_level cache_level, 426 u32 flags); 427 }; 428 429 #define i915_is_ggtt(V) (!(V)->file) 430 431 /* The Graphics Translation Table is the way in which GEN hardware translates a 432 * Graphics Virtual Address into a Physical Address. In addition to the normal 433 * collateral associated with any va->pa translations GEN hardware also has a 434 * portion of the GTT which can be mapped by the CPU and remain both coherent 435 * and correct (in cases like swizzling). That region is referred to as GMADR in 436 * the spec. 437 */ 438 struct i915_ggtt { 439 struct i915_address_space base; 440 struct io_mapping mappable; /* Mapping to our CPU mappable region */ 441 442 size_t stolen_size; /* Total size of stolen memory */ 443 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 444 size_t stolen_reserved_base; 445 size_t stolen_reserved_size; 446 u64 mappable_end; /* End offset that we can CPU map */ 447 phys_addr_t mappable_base; /* PA of our GMADR */ 448 449 /** "Graphics Stolen Memory" holds the global PTEs */ 450 void __iomem *gsm; 451 452 bool do_idle_maps; 453 454 int mtrr; 455 456 struct drm_mm_node error_capture; 457 }; 458 459 struct i915_hw_ppgtt { 460 struct i915_address_space base; 461 struct kref ref; 462 struct drm_mm_node node; 463 unsigned long pd_dirty_rings; 464 union { 465 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 466 struct i915_page_directory_pointer pdp; /* GEN8+ */ 467 struct i915_page_directory pd; /* GEN6-7 */ 468 }; 469 470 gen6_pte_t __iomem *pd_addr; 471 472 int (*enable)(struct i915_hw_ppgtt *ppgtt); 473 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 474 struct drm_i915_gem_request *req); 475 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 476 }; 477 478 /* 479 * gen6_for_each_pde() iterates over every pde from start until start+length. 480 * If start and start+length are not perfectly divisible, the macro will round 481 * down and up as needed. Start=0 and length=2G effectively iterates over 482 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 483 * so each of the other parameters should preferably be a simple variable, or 484 * at most an lvalue with no side-effects! 485 */ 486 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 487 for (iter = gen6_pde_index(start); \ 488 length > 0 && iter < I915_PDES && \ 489 (pt = (pd)->page_table[iter], true); \ 490 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 491 temp = min(temp - start, length); \ 492 start += temp, length -= temp; }), ++iter) 493 494 #define gen6_for_all_pdes(pt, pd, iter) \ 495 for (iter = 0; \ 496 iter < I915_PDES && \ 497 (pt = (pd)->page_table[iter], true); \ 498 ++iter) 499 500 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 501 { 502 const uint32_t mask = NUM_PTE(pde_shift) - 1; 503 504 return (address >> PAGE_SHIFT) & mask; 505 } 506 507 /* Helper to counts the number of PTEs within the given length. This count 508 * does not cross a page table boundary, so the max value would be 509 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 510 */ 511 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 512 uint32_t pde_shift) 513 { 514 const uint64_t mask = ~((1ULL << pde_shift) - 1); 515 uint64_t end; 516 517 WARN_ON(length == 0); 518 WARN_ON(offset_in_page(addr|length)); 519 520 end = addr + length; 521 522 if ((addr & mask) != (end & mask)) 523 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 524 525 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 526 } 527 528 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 529 { 530 return (addr >> shift) & I915_PDE_MASK; 531 } 532 533 static inline uint32_t gen6_pte_index(uint32_t addr) 534 { 535 return i915_pte_index(addr, GEN6_PDE_SHIFT); 536 } 537 538 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 539 { 540 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 541 } 542 543 static inline uint32_t gen6_pde_index(uint32_t addr) 544 { 545 return i915_pde_index(addr, GEN6_PDE_SHIFT); 546 } 547 548 /* Equivalent to the gen6 version, For each pde iterates over every pde 549 * between from start until start + length. On gen8+ it simply iterates 550 * over every page directory entry in a page directory. 551 */ 552 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 553 for (iter = gen8_pde_index(start); \ 554 length > 0 && iter < I915_PDES && \ 555 (pt = (pd)->page_table[iter], true); \ 556 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 557 temp = min(temp - start, length); \ 558 start += temp, length -= temp; }), ++iter) 559 560 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 561 for (iter = gen8_pdpe_index(start); \ 562 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 563 (pd = (pdp)->page_directory[iter], true); \ 564 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 565 temp = min(temp - start, length); \ 566 start += temp, length -= temp; }), ++iter) 567 568 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 569 for (iter = gen8_pml4e_index(start); \ 570 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 571 (pdp = (pml4)->pdps[iter], true); \ 572 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 573 temp = min(temp - start, length); \ 574 start += temp, length -= temp; }), ++iter) 575 576 static inline uint32_t gen8_pte_index(uint64_t address) 577 { 578 return i915_pte_index(address, GEN8_PDE_SHIFT); 579 } 580 581 static inline uint32_t gen8_pde_index(uint64_t address) 582 { 583 return i915_pde_index(address, GEN8_PDE_SHIFT); 584 } 585 586 static inline uint32_t gen8_pdpe_index(uint64_t address) 587 { 588 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 589 } 590 591 static inline uint32_t gen8_pml4e_index(uint64_t address) 592 { 593 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 594 } 595 596 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 597 { 598 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 599 } 600 601 static inline dma_addr_t 602 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 603 { 604 return test_bit(n, ppgtt->pdp.used_pdpes) ? 605 px_dma(ppgtt->pdp.page_directory[n]) : 606 px_dma(ppgtt->base.scratch_pd); 607 } 608 609 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 610 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 611 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 612 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 613 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 614 615 int i915_ppgtt_init_hw(struct drm_device *dev); 616 void i915_ppgtt_release(struct kref *kref); 617 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 618 struct drm_i915_file_private *fpriv, 619 const char *name); 620 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 621 { 622 if (ppgtt) 623 kref_get(&ppgtt->ref); 624 } 625 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 626 { 627 if (ppgtt) 628 kref_put(&ppgtt->ref, i915_ppgtt_release); 629 } 630 631 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 632 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 633 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 634 635 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 636 struct sg_table *pages); 637 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 638 struct sg_table *pages); 639 640 /* Flags used by pin/bind&friends. */ 641 #define PIN_NONBLOCK BIT(0) 642 #define PIN_MAPPABLE BIT(1) 643 #define PIN_ZONE_4G BIT(2) 644 #define PIN_NONFAULT BIT(3) 645 646 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 647 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 648 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 649 #define PIN_UPDATE BIT(8) 650 651 #define PIN_HIGH BIT(9) 652 #define PIN_OFFSET_BIAS BIT(10) 653 #define PIN_OFFSET_FIXED BIT(11) 654 #define PIN_OFFSET_MASK (~4095) 655 656 int __i915_vma_do_pin(struct i915_vma *vma, 657 u64 size, u64 alignment, u64 flags); 658 static inline int __must_check 659 i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) 660 { 661 BUILD_BUG_ON(PIN_MBZ != I915_VMA_PIN_OVERFLOW); 662 BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); 663 BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND); 664 665 /* Pin early to prevent the shrinker/eviction logic from destroying 666 * our vma as we insert and bind. 667 */ 668 if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0)) 669 return 0; 670 671 return __i915_vma_do_pin(vma, size, alignment, flags); 672 } 673 674 static inline int i915_vma_pin_count(const struct i915_vma *vma) 675 { 676 return vma->flags & I915_VMA_PIN_MASK; 677 } 678 679 static inline bool i915_vma_is_pinned(const struct i915_vma *vma) 680 { 681 return i915_vma_pin_count(vma); 682 } 683 684 static inline void __i915_vma_pin(struct i915_vma *vma) 685 { 686 vma->flags++; 687 GEM_BUG_ON(vma->flags & I915_VMA_PIN_OVERFLOW); 688 } 689 690 static inline void __i915_vma_unpin(struct i915_vma *vma) 691 { 692 GEM_BUG_ON(!i915_vma_is_pinned(vma)); 693 vma->flags--; 694 } 695 696 static inline void i915_vma_unpin(struct i915_vma *vma) 697 { 698 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); 699 __i915_vma_unpin(vma); 700 } 701 702 /** 703 * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture 704 * @vma: VMA to iomap 705 * 706 * The passed in VMA has to be pinned in the global GTT mappable region. 707 * An extra pinning of the VMA is acquired for the return iomapping, 708 * the caller must call i915_vma_unpin_iomap to relinquish the pinning 709 * after the iomapping is no longer required. 710 * 711 * Callers must hold the struct_mutex. 712 * 713 * Returns a valid iomapped pointer or ERR_PTR. 714 */ 715 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); 716 #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) 717 718 /** 719 * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap 720 * @vma: VMA to unpin 721 * 722 * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). 723 * 724 * Callers must hold the struct_mutex. This function is only valid to be 725 * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). 726 */ 727 static inline void i915_vma_unpin_iomap(struct i915_vma *vma) 728 { 729 lockdep_assert_held(&vma->vm->dev->struct_mutex); 730 GEM_BUG_ON(vma->iomap == NULL); 731 i915_vma_unpin(vma); 732 } 733 734 static inline struct page *i915_vma_first_page(struct i915_vma *vma) 735 { 736 GEM_BUG_ON(!vma->pages); 737 return sg_page(vma->pages->sgl); 738 } 739 740 #endif 741