1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 #include <linux/mm.h> 39 #include <linux/pagevec.h> 40 41 #include "i915_gem_timeline.h" 42 #include "i915_gem_request.h" 43 #include "i915_selftest.h" 44 45 #define I915_GTT_PAGE_SIZE 4096UL 46 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 47 48 #define I915_FENCE_REG_NONE -1 49 #define I915_MAX_NUM_FENCES 32 50 /* 32 fences + sign bit for FENCE_REG_NONE */ 51 #define I915_MAX_NUM_FENCE_BITS 6 52 53 struct drm_i915_file_private; 54 struct drm_i915_fence_reg; 55 56 typedef u32 gen6_pte_t; 57 typedef u64 gen8_pte_t; 58 typedef u64 gen8_pde_t; 59 typedef u64 gen8_ppgtt_pdpe_t; 60 typedef u64 gen8_ppgtt_pml4e_t; 61 62 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 63 64 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 65 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 66 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 67 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 68 #define GEN6_PTE_CACHE_LLC (2 << 1) 69 #define GEN6_PTE_UNCACHED (1 << 1) 70 #define GEN6_PTE_VALID (1 << 0) 71 72 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 73 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 74 #define I915_PDES 512 75 #define I915_PDE_MASK (I915_PDES - 1) 76 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 77 78 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 79 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 80 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 81 #define GEN6_PDE_SHIFT 22 82 #define GEN6_PDE_VALID (1 << 0) 83 84 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 85 86 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 87 #define BYT_PTE_WRITEABLE (1 << 1) 88 89 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 90 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 91 */ 92 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 93 (((bits) & 0x8) << (11 - 3))) 94 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 95 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 96 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 97 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 98 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 99 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 100 #define HSW_PTE_UNCACHED (0) 101 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 102 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 103 104 /* GEN8 32b style address is defined as a 3 level page table: 105 * 31:30 | 29:21 | 20:12 | 11:0 106 * PDPE | PDE | PTE | offset 107 * The difference as compared to normal x86 3 level page table is the PDPEs are 108 * programmed via register. 109 */ 110 #define GEN8_3LVL_PDPES 4 111 #define GEN8_PDE_SHIFT 21 112 #define GEN8_PDE_MASK 0x1ff 113 #define GEN8_PTE_SHIFT 12 114 #define GEN8_PTE_MASK 0x1ff 115 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 116 117 /* GEN8 48b style address is defined as a 4 level page table: 118 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 119 * PML4E | PDPE | PDE | PTE | offset 120 */ 121 #define GEN8_PML4ES_PER_PML4 512 122 #define GEN8_PML4E_SHIFT 39 123 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 124 #define GEN8_PDPE_SHIFT 30 125 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 126 * tables */ 127 #define GEN8_PDPE_MASK 0x1ff 128 129 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 130 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 131 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 132 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 133 134 #define CHV_PPAT_SNOOP (1<<6) 135 #define GEN8_PPAT_AGE(x) (x<<4) 136 #define GEN8_PPAT_LLCeLLC (3<<2) 137 #define GEN8_PPAT_LLCELLC (2<<2) 138 #define GEN8_PPAT_LLC (1<<2) 139 #define GEN8_PPAT_WB (3<<0) 140 #define GEN8_PPAT_WT (2<<0) 141 #define GEN8_PPAT_WC (1<<0) 142 #define GEN8_PPAT_UC (0<<0) 143 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 144 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 145 146 struct sg_table; 147 148 struct intel_rotation_info { 149 struct intel_rotation_plane_info { 150 /* tiles */ 151 unsigned int width, height, stride, offset; 152 } plane[2]; 153 } __packed; 154 155 static inline void assert_intel_rotation_info_is_packed(void) 156 { 157 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 158 } 159 160 struct intel_partial_info { 161 u64 offset; 162 unsigned int size; 163 } __packed; 164 165 static inline void assert_intel_partial_info_is_packed(void) 166 { 167 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 168 } 169 170 enum i915_ggtt_view_type { 171 I915_GGTT_VIEW_NORMAL = 0, 172 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 173 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 174 }; 175 176 static inline void assert_i915_ggtt_view_type_is_unique(void) 177 { 178 /* As we encode the size of each branch inside the union into its type, 179 * we have to be careful that each branch has a unique size. 180 */ 181 switch ((enum i915_ggtt_view_type)0) { 182 case I915_GGTT_VIEW_NORMAL: 183 case I915_GGTT_VIEW_PARTIAL: 184 case I915_GGTT_VIEW_ROTATED: 185 /* gcc complains if these are identical cases */ 186 break; 187 } 188 } 189 190 struct i915_ggtt_view { 191 enum i915_ggtt_view_type type; 192 union { 193 /* Members need to contain no holes/padding */ 194 struct intel_partial_info partial; 195 struct intel_rotation_info rotated; 196 }; 197 }; 198 199 enum i915_cache_level; 200 201 struct i915_vma; 202 203 struct i915_page_dma { 204 struct page *page; 205 union { 206 dma_addr_t daddr; 207 208 /* For gen6/gen7 only. This is the offset in the GGTT 209 * where the page directory entries for PPGTT begin 210 */ 211 u32 ggtt_offset; 212 }; 213 }; 214 215 #define px_base(px) (&(px)->base) 216 #define px_page(px) (px_base(px)->page) 217 #define px_dma(px) (px_base(px)->daddr) 218 219 struct i915_page_table { 220 struct i915_page_dma base; 221 unsigned int used_ptes; 222 }; 223 224 struct i915_page_directory { 225 struct i915_page_dma base; 226 227 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 228 unsigned int used_pdes; 229 }; 230 231 struct i915_page_directory_pointer { 232 struct i915_page_dma base; 233 struct i915_page_directory **page_directory; 234 unsigned int used_pdpes; 235 }; 236 237 struct i915_pml4 { 238 struct i915_page_dma base; 239 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 240 }; 241 242 struct i915_address_space { 243 struct drm_mm mm; 244 struct i915_gem_timeline timeline; 245 struct drm_i915_private *i915; 246 struct device *dma; 247 /* Every address space belongs to a struct file - except for the global 248 * GTT that is owned by the driver (and so @file is set to NULL). In 249 * principle, no information should leak from one context to another 250 * (or between files/processes etc) unless explicitly shared by the 251 * owner. Tracking the owner is important in order to free up per-file 252 * objects along with the file, to aide resource tracking, and to 253 * assign blame. 254 */ 255 struct drm_i915_file_private *file; 256 struct list_head global_link; 257 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 258 u64 reserved; /* size addr space reserved */ 259 260 bool closed; 261 262 struct i915_page_dma scratch_page; 263 struct i915_page_table *scratch_pt; 264 struct i915_page_directory *scratch_pd; 265 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 266 267 /** 268 * List of objects currently involved in rendering. 269 * 270 * Includes buffers having the contents of their GPU caches 271 * flushed, not necessarily primitives. last_read_req 272 * represents when the rendering involved will be completed. 273 * 274 * A reference is held on the buffer while on this list. 275 */ 276 struct list_head active_list; 277 278 /** 279 * LRU list of objects which are not in the ringbuffer and 280 * are ready to unbind, but are still in the GTT. 281 * 282 * last_read_req is NULL while an object is in this list. 283 * 284 * A reference is not held on the buffer while on this list, 285 * as merely being GTT-bound shouldn't prevent its being 286 * freed, and we'll pull it off the list in the free path. 287 */ 288 struct list_head inactive_list; 289 290 /** 291 * List of vma that have been unbound. 292 * 293 * A reference is not held on the buffer while on this list. 294 */ 295 struct list_head unbound_list; 296 297 struct pagevec free_pages; 298 bool pt_kmap_wc; 299 300 /* FIXME: Need a more generic return type */ 301 gen6_pte_t (*pte_encode)(dma_addr_t addr, 302 enum i915_cache_level level, 303 u32 flags); /* Create a valid PTE */ 304 /* flags for pte_encode */ 305 #define PTE_READ_ONLY (1<<0) 306 int (*allocate_va_range)(struct i915_address_space *vm, 307 u64 start, u64 length); 308 void (*clear_range)(struct i915_address_space *vm, 309 u64 start, u64 length); 310 void (*insert_page)(struct i915_address_space *vm, 311 dma_addr_t addr, 312 u64 offset, 313 enum i915_cache_level cache_level, 314 u32 flags); 315 void (*insert_entries)(struct i915_address_space *vm, 316 struct sg_table *st, 317 u64 start, 318 enum i915_cache_level cache_level, 319 u32 flags); 320 void (*cleanup)(struct i915_address_space *vm); 321 /** Unmap an object from an address space. This usually consists of 322 * setting the valid PTE entries to a reserved scratch page. */ 323 void (*unbind_vma)(struct i915_vma *vma); 324 /* Map an object into an address space with the given cache flags. */ 325 int (*bind_vma)(struct i915_vma *vma, 326 enum i915_cache_level cache_level, 327 u32 flags); 328 329 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 330 }; 331 332 #define i915_is_ggtt(V) (!(V)->file) 333 334 static inline bool 335 i915_vm_is_48bit(const struct i915_address_space *vm) 336 { 337 return (vm->total - 1) >> 32; 338 } 339 340 /* The Graphics Translation Table is the way in which GEN hardware translates a 341 * Graphics Virtual Address into a Physical Address. In addition to the normal 342 * collateral associated with any va->pa translations GEN hardware also has a 343 * portion of the GTT which can be mapped by the CPU and remain both coherent 344 * and correct (in cases like swizzling). That region is referred to as GMADR in 345 * the spec. 346 */ 347 struct i915_ggtt { 348 struct i915_address_space base; 349 struct io_mapping mappable; /* Mapping to our CPU mappable region */ 350 351 phys_addr_t mappable_base; /* PA of our GMADR */ 352 u64 mappable_end; /* End offset that we can CPU map */ 353 354 /* Stolen memory is segmented in hardware with different portions 355 * offlimits to certain functions. 356 * 357 * The drm_mm is initialised to the total accessible range, as found 358 * from the PCI config. On Broadwell+, this is further restricted to 359 * avoid the first page! The upper end of stolen memory is reserved for 360 * hardware functions and similarly removed from the accessible range. 361 */ 362 u32 stolen_size; /* Total size of stolen memory */ 363 u32 stolen_usable_size; /* Total size minus reserved ranges */ 364 u32 stolen_reserved_base; 365 u32 stolen_reserved_size; 366 367 /** "Graphics Stolen Memory" holds the global PTEs */ 368 void __iomem *gsm; 369 void (*invalidate)(struct drm_i915_private *dev_priv); 370 371 bool do_idle_maps; 372 373 int mtrr; 374 375 struct drm_mm_node error_capture; 376 }; 377 378 struct i915_hw_ppgtt { 379 struct i915_address_space base; 380 struct kref ref; 381 struct drm_mm_node node; 382 unsigned long pd_dirty_rings; 383 union { 384 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 385 struct i915_page_directory_pointer pdp; /* GEN8+ */ 386 struct i915_page_directory pd; /* GEN6-7 */ 387 }; 388 389 gen6_pte_t __iomem *pd_addr; 390 391 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 392 struct drm_i915_gem_request *req); 393 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 394 }; 395 396 /* 397 * gen6_for_each_pde() iterates over every pde from start until start+length. 398 * If start and start+length are not perfectly divisible, the macro will round 399 * down and up as needed. Start=0 and length=2G effectively iterates over 400 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 401 * so each of the other parameters should preferably be a simple variable, or 402 * at most an lvalue with no side-effects! 403 */ 404 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 405 for (iter = gen6_pde_index(start); \ 406 length > 0 && iter < I915_PDES && \ 407 (pt = (pd)->page_table[iter], true); \ 408 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 409 temp = min(temp - start, length); \ 410 start += temp, length -= temp; }), ++iter) 411 412 #define gen6_for_all_pdes(pt, pd, iter) \ 413 for (iter = 0; \ 414 iter < I915_PDES && \ 415 (pt = (pd)->page_table[iter], true); \ 416 ++iter) 417 418 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 419 { 420 const u32 mask = NUM_PTE(pde_shift) - 1; 421 422 return (address >> PAGE_SHIFT) & mask; 423 } 424 425 /* Helper to counts the number of PTEs within the given length. This count 426 * does not cross a page table boundary, so the max value would be 427 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 428 */ 429 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 430 { 431 const u64 mask = ~((1ULL << pde_shift) - 1); 432 u64 end; 433 434 WARN_ON(length == 0); 435 WARN_ON(offset_in_page(addr|length)); 436 437 end = addr + length; 438 439 if ((addr & mask) != (end & mask)) 440 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 441 442 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 443 } 444 445 static inline u32 i915_pde_index(u64 addr, u32 shift) 446 { 447 return (addr >> shift) & I915_PDE_MASK; 448 } 449 450 static inline u32 gen6_pte_index(u32 addr) 451 { 452 return i915_pte_index(addr, GEN6_PDE_SHIFT); 453 } 454 455 static inline u32 gen6_pte_count(u32 addr, u32 length) 456 { 457 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 458 } 459 460 static inline u32 gen6_pde_index(u32 addr) 461 { 462 return i915_pde_index(addr, GEN6_PDE_SHIFT); 463 } 464 465 static inline unsigned int 466 i915_pdpes_per_pdp(const struct i915_address_space *vm) 467 { 468 if (i915_vm_is_48bit(vm)) 469 return GEN8_PML4ES_PER_PML4; 470 471 return GEN8_3LVL_PDPES; 472 } 473 474 /* Equivalent to the gen6 version, For each pde iterates over every pde 475 * between from start until start + length. On gen8+ it simply iterates 476 * over every page directory entry in a page directory. 477 */ 478 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 479 for (iter = gen8_pde_index(start); \ 480 length > 0 && iter < I915_PDES && \ 481 (pt = (pd)->page_table[iter], true); \ 482 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 483 temp = min(temp - start, length); \ 484 start += temp, length -= temp; }), ++iter) 485 486 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 487 for (iter = gen8_pdpe_index(start); \ 488 length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 489 (pd = (pdp)->page_directory[iter], true); \ 490 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 491 temp = min(temp - start, length); \ 492 start += temp, length -= temp; }), ++iter) 493 494 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 495 for (iter = gen8_pml4e_index(start); \ 496 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 497 (pdp = (pml4)->pdps[iter], true); \ 498 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 499 temp = min(temp - start, length); \ 500 start += temp, length -= temp; }), ++iter) 501 502 static inline u32 gen8_pte_index(u64 address) 503 { 504 return i915_pte_index(address, GEN8_PDE_SHIFT); 505 } 506 507 static inline u32 gen8_pde_index(u64 address) 508 { 509 return i915_pde_index(address, GEN8_PDE_SHIFT); 510 } 511 512 static inline u32 gen8_pdpe_index(u64 address) 513 { 514 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 515 } 516 517 static inline u32 gen8_pml4e_index(u64 address) 518 { 519 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 520 } 521 522 static inline u64 gen8_pte_count(u64 address, u64 length) 523 { 524 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 525 } 526 527 static inline dma_addr_t 528 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 529 { 530 return px_dma(ppgtt->pdp.page_directory[n]); 531 } 532 533 static inline struct i915_ggtt * 534 i915_vm_to_ggtt(struct i915_address_space *vm) 535 { 536 GEM_BUG_ON(!i915_is_ggtt(vm)); 537 return container_of(vm, struct i915_ggtt, base); 538 } 539 540 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 541 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 542 543 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 544 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 545 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 546 void i915_ggtt_enable_guc(struct drm_i915_private *i915); 547 void i915_ggtt_disable_guc(struct drm_i915_private *i915); 548 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 549 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 550 551 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 552 void i915_ppgtt_release(struct kref *kref); 553 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 554 struct drm_i915_file_private *fpriv, 555 const char *name); 556 void i915_ppgtt_close(struct i915_address_space *vm); 557 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 558 { 559 if (ppgtt) 560 kref_get(&ppgtt->ref); 561 } 562 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 563 { 564 if (ppgtt) 565 kref_put(&ppgtt->ref, i915_ppgtt_release); 566 } 567 568 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 569 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 570 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 571 572 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 573 struct sg_table *pages); 574 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 575 struct sg_table *pages); 576 577 int i915_gem_gtt_reserve(struct i915_address_space *vm, 578 struct drm_mm_node *node, 579 u64 size, u64 offset, unsigned long color, 580 unsigned int flags); 581 582 int i915_gem_gtt_insert(struct i915_address_space *vm, 583 struct drm_mm_node *node, 584 u64 size, u64 alignment, unsigned long color, 585 u64 start, u64 end, unsigned int flags); 586 587 /* Flags used by pin/bind&friends. */ 588 #define PIN_NONBLOCK BIT(0) 589 #define PIN_MAPPABLE BIT(1) 590 #define PIN_ZONE_4G BIT(2) 591 #define PIN_NONFAULT BIT(3) 592 #define PIN_NOEVICT BIT(4) 593 594 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 595 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 596 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 597 #define PIN_UPDATE BIT(8) 598 599 #define PIN_HIGH BIT(9) 600 #define PIN_OFFSET_BIAS BIT(10) 601 #define PIN_OFFSET_FIXED BIT(11) 602 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 603 604 #endif 605