1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 #include <linux/mm.h> 39 #include <linux/pagevec.h> 40 41 #include "i915_request.h" 42 #include "i915_selftest.h" 43 #include "i915_timeline.h" 44 45 #define I915_GTT_PAGE_SIZE_4K BIT(12) 46 #define I915_GTT_PAGE_SIZE_64K BIT(16) 47 #define I915_GTT_PAGE_SIZE_2M BIT(21) 48 49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 51 52 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 53 54 #define I915_FENCE_REG_NONE -1 55 #define I915_MAX_NUM_FENCES 32 56 /* 32 fences + sign bit for FENCE_REG_NONE */ 57 #define I915_MAX_NUM_FENCE_BITS 6 58 59 struct drm_i915_file_private; 60 struct drm_i915_fence_reg; 61 struct i915_vma; 62 63 typedef u32 gen6_pte_t; 64 typedef u64 gen8_pte_t; 65 typedef u64 gen8_pde_t; 66 typedef u64 gen8_ppgtt_pdpe_t; 67 typedef u64 gen8_ppgtt_pml4e_t; 68 69 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 70 71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 72 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 73 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 74 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 75 #define GEN6_PTE_CACHE_LLC (2 << 1) 76 #define GEN6_PTE_UNCACHED (1 << 1) 77 #define GEN6_PTE_VALID (1 << 0) 78 79 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 80 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 81 #define I915_PDES 512 82 #define I915_PDE_MASK (I915_PDES - 1) 83 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 84 85 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 86 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 87 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 88 #define GEN6_PDE_SHIFT 22 89 #define GEN6_PDE_VALID (1 << 0) 90 91 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 92 93 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 94 #define BYT_PTE_WRITEABLE (1 << 1) 95 96 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 97 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 98 */ 99 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 100 (((bits) & 0x8) << (11 - 3))) 101 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 102 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 103 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 104 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 105 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 106 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 107 #define HSW_PTE_UNCACHED (0) 108 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 109 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 110 111 /* GEN8 32b style address is defined as a 3 level page table: 112 * 31:30 | 29:21 | 20:12 | 11:0 113 * PDPE | PDE | PTE | offset 114 * The difference as compared to normal x86 3 level page table is the PDPEs are 115 * programmed via register. 116 */ 117 #define GEN8_3LVL_PDPES 4 118 #define GEN8_PDE_SHIFT 21 119 #define GEN8_PDE_MASK 0x1ff 120 #define GEN8_PTE_SHIFT 12 121 #define GEN8_PTE_MASK 0x1ff 122 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 123 124 /* GEN8 48b style address is defined as a 4 level page table: 125 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 126 * PML4E | PDPE | PDE | PTE | offset 127 */ 128 #define GEN8_PML4ES_PER_PML4 512 129 #define GEN8_PML4E_SHIFT 39 130 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 131 #define GEN8_PDPE_SHIFT 30 132 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 133 * tables */ 134 #define GEN8_PDPE_MASK 0x1ff 135 136 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 137 #define PPAT_CACHED_PDE 0 /* WB LLC */ 138 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 139 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 140 141 #define CHV_PPAT_SNOOP (1<<6) 142 #define GEN8_PPAT_AGE(x) ((x)<<4) 143 #define GEN8_PPAT_LLCeLLC (3<<2) 144 #define GEN8_PPAT_LLCELLC (2<<2) 145 #define GEN8_PPAT_LLC (1<<2) 146 #define GEN8_PPAT_WB (3<<0) 147 #define GEN8_PPAT_WT (2<<0) 148 #define GEN8_PPAT_WC (1<<0) 149 #define GEN8_PPAT_UC (0<<0) 150 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 151 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 152 153 #define GEN8_PPAT_GET_CA(x) ((x) & 3) 154 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 155 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 156 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 157 158 #define GEN8_PDE_IPS_64K BIT(11) 159 #define GEN8_PDE_PS_2M BIT(7) 160 161 struct sg_table; 162 163 struct intel_rotation_info { 164 struct intel_rotation_plane_info { 165 /* tiles */ 166 unsigned int width, height, stride, offset; 167 } plane[2]; 168 } __packed; 169 170 static inline void assert_intel_rotation_info_is_packed(void) 171 { 172 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 173 } 174 175 struct intel_partial_info { 176 u64 offset; 177 unsigned int size; 178 } __packed; 179 180 static inline void assert_intel_partial_info_is_packed(void) 181 { 182 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 183 } 184 185 enum i915_ggtt_view_type { 186 I915_GGTT_VIEW_NORMAL = 0, 187 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 188 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 189 }; 190 191 static inline void assert_i915_ggtt_view_type_is_unique(void) 192 { 193 /* As we encode the size of each branch inside the union into its type, 194 * we have to be careful that each branch has a unique size. 195 */ 196 switch ((enum i915_ggtt_view_type)0) { 197 case I915_GGTT_VIEW_NORMAL: 198 case I915_GGTT_VIEW_PARTIAL: 199 case I915_GGTT_VIEW_ROTATED: 200 /* gcc complains if these are identical cases */ 201 break; 202 } 203 } 204 205 struct i915_ggtt_view { 206 enum i915_ggtt_view_type type; 207 union { 208 /* Members need to contain no holes/padding */ 209 struct intel_partial_info partial; 210 struct intel_rotation_info rotated; 211 }; 212 }; 213 214 enum i915_cache_level; 215 216 struct i915_vma; 217 218 struct i915_page_dma { 219 struct page *page; 220 int order; 221 union { 222 dma_addr_t daddr; 223 224 /* For gen6/gen7 only. This is the offset in the GGTT 225 * where the page directory entries for PPGTT begin 226 */ 227 u32 ggtt_offset; 228 }; 229 }; 230 231 #define px_base(px) (&(px)->base) 232 #define px_page(px) (px_base(px)->page) 233 #define px_dma(px) (px_base(px)->daddr) 234 235 struct i915_page_table { 236 struct i915_page_dma base; 237 unsigned int used_ptes; 238 }; 239 240 struct i915_page_directory { 241 struct i915_page_dma base; 242 243 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 244 unsigned int used_pdes; 245 }; 246 247 struct i915_page_directory_pointer { 248 struct i915_page_dma base; 249 struct i915_page_directory **page_directory; 250 unsigned int used_pdpes; 251 }; 252 253 struct i915_pml4 { 254 struct i915_page_dma base; 255 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 256 }; 257 258 struct i915_vma_ops { 259 /* Map an object into an address space with the given cache flags. */ 260 int (*bind_vma)(struct i915_vma *vma, 261 enum i915_cache_level cache_level, 262 u32 flags); 263 /* 264 * Unmap an object from an address space. This usually consists of 265 * setting the valid PTE entries to a reserved scratch page. 266 */ 267 void (*unbind_vma)(struct i915_vma *vma); 268 269 int (*set_pages)(struct i915_vma *vma); 270 void (*clear_pages)(struct i915_vma *vma); 271 }; 272 273 struct i915_address_space { 274 struct drm_mm mm; 275 struct drm_i915_private *i915; 276 struct device *dma; 277 /* Every address space belongs to a struct file - except for the global 278 * GTT that is owned by the driver (and so @file is set to NULL). In 279 * principle, no information should leak from one context to another 280 * (or between files/processes etc) unless explicitly shared by the 281 * owner. Tracking the owner is important in order to free up per-file 282 * objects along with the file, to aide resource tracking, and to 283 * assign blame. 284 */ 285 struct drm_i915_file_private *file; 286 struct list_head global_link; 287 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 288 u64 reserved; /* size addr space reserved */ 289 290 bool closed; 291 292 struct i915_page_dma scratch_page; 293 struct i915_page_table *scratch_pt; 294 struct i915_page_directory *scratch_pd; 295 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 296 297 /** 298 * List of objects currently involved in rendering. 299 * 300 * Includes buffers having the contents of their GPU caches 301 * flushed, not necessarily primitives. last_read_req 302 * represents when the rendering involved will be completed. 303 * 304 * A reference is held on the buffer while on this list. 305 */ 306 struct list_head active_list; 307 308 /** 309 * LRU list of objects which are not in the ringbuffer and 310 * are ready to unbind, but are still in the GTT. 311 * 312 * last_read_req is NULL while an object is in this list. 313 * 314 * A reference is not held on the buffer while on this list, 315 * as merely being GTT-bound shouldn't prevent its being 316 * freed, and we'll pull it off the list in the free path. 317 */ 318 struct list_head inactive_list; 319 320 /** 321 * List of vma that have been unbound. 322 * 323 * A reference is not held on the buffer while on this list. 324 */ 325 struct list_head unbound_list; 326 327 struct pagevec free_pages; 328 bool pt_kmap_wc; 329 330 /* FIXME: Need a more generic return type */ 331 gen6_pte_t (*pte_encode)(dma_addr_t addr, 332 enum i915_cache_level level, 333 u32 flags); /* Create a valid PTE */ 334 /* flags for pte_encode */ 335 #define PTE_READ_ONLY (1<<0) 336 int (*allocate_va_range)(struct i915_address_space *vm, 337 u64 start, u64 length); 338 void (*clear_range)(struct i915_address_space *vm, 339 u64 start, u64 length); 340 void (*insert_page)(struct i915_address_space *vm, 341 dma_addr_t addr, 342 u64 offset, 343 enum i915_cache_level cache_level, 344 u32 flags); 345 void (*insert_entries)(struct i915_address_space *vm, 346 struct i915_vma *vma, 347 enum i915_cache_level cache_level, 348 u32 flags); 349 void (*cleanup)(struct i915_address_space *vm); 350 351 struct i915_vma_ops vma_ops; 352 353 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 354 I915_SELFTEST_DECLARE(bool scrub_64K); 355 }; 356 357 #define i915_is_ggtt(V) (!(V)->file) 358 359 static inline bool 360 i915_vm_is_48bit(const struct i915_address_space *vm) 361 { 362 return (vm->total - 1) >> 32; 363 } 364 365 static inline bool 366 i915_vm_has_scratch_64K(struct i915_address_space *vm) 367 { 368 return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K); 369 } 370 371 /* The Graphics Translation Table is the way in which GEN hardware translates a 372 * Graphics Virtual Address into a Physical Address. In addition to the normal 373 * collateral associated with any va->pa translations GEN hardware also has a 374 * portion of the GTT which can be mapped by the CPU and remain both coherent 375 * and correct (in cases like swizzling). That region is referred to as GMADR in 376 * the spec. 377 */ 378 struct i915_ggtt { 379 struct i915_address_space vm; 380 381 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 382 struct resource gmadr; /* GMADR resource */ 383 resource_size_t mappable_end; /* End offset that we can CPU map */ 384 385 /** "Graphics Stolen Memory" holds the global PTEs */ 386 void __iomem *gsm; 387 void (*invalidate)(struct drm_i915_private *dev_priv); 388 389 bool do_idle_maps; 390 391 int mtrr; 392 393 struct drm_mm_node error_capture; 394 }; 395 396 struct i915_hw_ppgtt { 397 struct i915_address_space vm; 398 struct kref ref; 399 400 unsigned long pd_dirty_rings; 401 union { 402 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 403 struct i915_page_directory_pointer pdp; /* GEN8+ */ 404 struct i915_page_directory pd; /* GEN6-7 */ 405 }; 406 407 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 408 }; 409 410 struct gen6_hw_ppgtt { 411 struct i915_hw_ppgtt base; 412 413 struct i915_vma *vma; 414 gen6_pte_t __iomem *pd_addr; 415 gen6_pte_t scratch_pte; 416 417 unsigned int pin_count; 418 bool scan_for_unused_pt; 419 }; 420 421 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base) 422 423 static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base) 424 { 425 BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base)); 426 return __to_gen6_ppgtt(base); 427 } 428 429 /* 430 * gen6_for_each_pde() iterates over every pde from start until start+length. 431 * If start and start+length are not perfectly divisible, the macro will round 432 * down and up as needed. Start=0 and length=2G effectively iterates over 433 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 434 * so each of the other parameters should preferably be a simple variable, or 435 * at most an lvalue with no side-effects! 436 */ 437 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 438 for (iter = gen6_pde_index(start); \ 439 length > 0 && iter < I915_PDES && \ 440 (pt = (pd)->page_table[iter], true); \ 441 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 442 temp = min(temp - start, length); \ 443 start += temp, length -= temp; }), ++iter) 444 445 #define gen6_for_all_pdes(pt, pd, iter) \ 446 for (iter = 0; \ 447 iter < I915_PDES && \ 448 (pt = (pd)->page_table[iter], true); \ 449 ++iter) 450 451 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 452 { 453 const u32 mask = NUM_PTE(pde_shift) - 1; 454 455 return (address >> PAGE_SHIFT) & mask; 456 } 457 458 /* Helper to counts the number of PTEs within the given length. This count 459 * does not cross a page table boundary, so the max value would be 460 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 461 */ 462 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 463 { 464 const u64 mask = ~((1ULL << pde_shift) - 1); 465 u64 end; 466 467 GEM_BUG_ON(length == 0); 468 GEM_BUG_ON(offset_in_page(addr | length)); 469 470 end = addr + length; 471 472 if ((addr & mask) != (end & mask)) 473 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 474 475 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 476 } 477 478 static inline u32 i915_pde_index(u64 addr, u32 shift) 479 { 480 return (addr >> shift) & I915_PDE_MASK; 481 } 482 483 static inline u32 gen6_pte_index(u32 addr) 484 { 485 return i915_pte_index(addr, GEN6_PDE_SHIFT); 486 } 487 488 static inline u32 gen6_pte_count(u32 addr, u32 length) 489 { 490 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 491 } 492 493 static inline u32 gen6_pde_index(u32 addr) 494 { 495 return i915_pde_index(addr, GEN6_PDE_SHIFT); 496 } 497 498 static inline unsigned int 499 i915_pdpes_per_pdp(const struct i915_address_space *vm) 500 { 501 if (i915_vm_is_48bit(vm)) 502 return GEN8_PML4ES_PER_PML4; 503 504 return GEN8_3LVL_PDPES; 505 } 506 507 /* Equivalent to the gen6 version, For each pde iterates over every pde 508 * between from start until start + length. On gen8+ it simply iterates 509 * over every page directory entry in a page directory. 510 */ 511 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 512 for (iter = gen8_pde_index(start); \ 513 length > 0 && iter < I915_PDES && \ 514 (pt = (pd)->page_table[iter], true); \ 515 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 516 temp = min(temp - start, length); \ 517 start += temp, length -= temp; }), ++iter) 518 519 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 520 for (iter = gen8_pdpe_index(start); \ 521 length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 522 (pd = (pdp)->page_directory[iter], true); \ 523 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 524 temp = min(temp - start, length); \ 525 start += temp, length -= temp; }), ++iter) 526 527 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 528 for (iter = gen8_pml4e_index(start); \ 529 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 530 (pdp = (pml4)->pdps[iter], true); \ 531 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 532 temp = min(temp - start, length); \ 533 start += temp, length -= temp; }), ++iter) 534 535 static inline u32 gen8_pte_index(u64 address) 536 { 537 return i915_pte_index(address, GEN8_PDE_SHIFT); 538 } 539 540 static inline u32 gen8_pde_index(u64 address) 541 { 542 return i915_pde_index(address, GEN8_PDE_SHIFT); 543 } 544 545 static inline u32 gen8_pdpe_index(u64 address) 546 { 547 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 548 } 549 550 static inline u32 gen8_pml4e_index(u64 address) 551 { 552 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 553 } 554 555 static inline u64 gen8_pte_count(u64 address, u64 length) 556 { 557 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 558 } 559 560 static inline dma_addr_t 561 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 562 { 563 return px_dma(ppgtt->pdp.page_directory[n]); 564 } 565 566 static inline struct i915_ggtt * 567 i915_vm_to_ggtt(struct i915_address_space *vm) 568 { 569 GEM_BUG_ON(!i915_is_ggtt(vm)); 570 return container_of(vm, struct i915_ggtt, vm); 571 } 572 573 #define INTEL_MAX_PPAT_ENTRIES 8 574 #define INTEL_PPAT_PERFECT_MATCH (~0U) 575 576 struct intel_ppat; 577 578 struct intel_ppat_entry { 579 struct intel_ppat *ppat; 580 struct kref ref; 581 u8 value; 582 }; 583 584 struct intel_ppat { 585 struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 586 DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 587 DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 588 unsigned int max_entries; 589 u8 clear_value; 590 /* 591 * Return a score to show how two PPAT values match, 592 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 593 */ 594 unsigned int (*match)(u8 src, u8 dst); 595 void (*update_hw)(struct drm_i915_private *i915); 596 597 struct drm_i915_private *i915; 598 }; 599 600 const struct intel_ppat_entry * 601 intel_ppat_get(struct drm_i915_private *i915, u8 value); 602 void intel_ppat_put(const struct intel_ppat_entry *entry); 603 604 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 605 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 606 607 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 608 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 609 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 610 void i915_ggtt_enable_guc(struct drm_i915_private *i915); 611 void i915_ggtt_disable_guc(struct drm_i915_private *i915); 612 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 613 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 614 615 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 616 void i915_ppgtt_release(struct kref *kref); 617 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 618 struct drm_i915_file_private *fpriv, 619 const char *name); 620 void i915_ppgtt_close(struct i915_address_space *vm); 621 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 622 { 623 if (ppgtt) 624 kref_get(&ppgtt->ref); 625 } 626 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 627 { 628 if (ppgtt) 629 kref_put(&ppgtt->ref, i915_ppgtt_release); 630 } 631 632 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base); 633 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base); 634 635 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 636 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 637 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 638 639 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 640 struct sg_table *pages); 641 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 642 struct sg_table *pages); 643 644 int i915_gem_gtt_reserve(struct i915_address_space *vm, 645 struct drm_mm_node *node, 646 u64 size, u64 offset, unsigned long color, 647 unsigned int flags); 648 649 int i915_gem_gtt_insert(struct i915_address_space *vm, 650 struct drm_mm_node *node, 651 u64 size, u64 alignment, unsigned long color, 652 u64 start, u64 end, unsigned int flags); 653 654 /* Flags used by pin/bind&friends. */ 655 #define PIN_NONBLOCK BIT(0) 656 #define PIN_MAPPABLE BIT(1) 657 #define PIN_ZONE_4G BIT(2) 658 #define PIN_NONFAULT BIT(3) 659 #define PIN_NOEVICT BIT(4) 660 661 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 662 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 663 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 664 #define PIN_UPDATE BIT(8) 665 666 #define PIN_HIGH BIT(9) 667 #define PIN_OFFSET_BIAS BIT(10) 668 #define PIN_OFFSET_FIXED BIT(11) 669 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 670 671 #endif 672