1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 struct drm_i915_file_private; 38 39 typedef uint32_t gen6_pte_t; 40 typedef uint64_t gen8_pte_t; 41 typedef uint64_t gen8_pde_t; 42 typedef uint64_t gen8_ppgtt_pdpe_t; 43 typedef uint64_t gen8_ppgtt_pml4e_t; 44 45 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 46 47 48 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 49 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 51 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 52 #define GEN6_PTE_CACHE_LLC (2 << 1) 53 #define GEN6_PTE_UNCACHED (1 << 1) 54 #define GEN6_PTE_VALID (1 << 0) 55 56 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 57 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 58 #define I915_PDES 512 59 #define I915_PDE_MASK (I915_PDES - 1) 60 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 61 62 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 63 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 64 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 65 #define GEN6_PDE_SHIFT 22 66 #define GEN6_PDE_VALID (1 << 0) 67 68 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 69 70 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 71 #define BYT_PTE_WRITEABLE (1 << 1) 72 73 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 74 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 75 */ 76 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 77 (((bits) & 0x8) << (11 - 3))) 78 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 79 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 80 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 81 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 82 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 83 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 84 #define HSW_PTE_UNCACHED (0) 85 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 86 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 87 88 /* GEN8 legacy style address is defined as a 3 level page table: 89 * 31:30 | 29:21 | 20:12 | 11:0 90 * PDPE | PDE | PTE | offset 91 * The difference as compared to normal x86 3 level page table is the PDPEs are 92 * programmed via register. 93 * 94 * GEN8 48b legacy style address is defined as a 4 level page table: 95 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 96 * PML4E | PDPE | PDE | PTE | offset 97 */ 98 #define GEN8_PML4ES_PER_PML4 512 99 #define GEN8_PML4E_SHIFT 39 100 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 101 #define GEN8_PDPE_SHIFT 30 102 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 103 * tables */ 104 #define GEN8_PDPE_MASK 0x1ff 105 #define GEN8_PDE_SHIFT 21 106 #define GEN8_PDE_MASK 0x1ff 107 #define GEN8_PTE_SHIFT 12 108 #define GEN8_PTE_MASK 0x1ff 109 #define GEN8_LEGACY_PDPES 4 110 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 111 112 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 113 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 114 115 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 116 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 117 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 118 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 119 120 #define CHV_PPAT_SNOOP (1<<6) 121 #define GEN8_PPAT_AGE(x) (x<<4) 122 #define GEN8_PPAT_LLCeLLC (3<<2) 123 #define GEN8_PPAT_LLCELLC (2<<2) 124 #define GEN8_PPAT_LLC (1<<2) 125 #define GEN8_PPAT_WB (3<<0) 126 #define GEN8_PPAT_WT (2<<0) 127 #define GEN8_PPAT_WC (1<<0) 128 #define GEN8_PPAT_UC (0<<0) 129 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 130 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 131 132 enum i915_ggtt_view_type { 133 I915_GGTT_VIEW_NORMAL = 0, 134 I915_GGTT_VIEW_ROTATED, 135 I915_GGTT_VIEW_PARTIAL, 136 }; 137 138 struct intel_rotation_info { 139 unsigned int height; 140 unsigned int pitch; 141 uint32_t pixel_format; 142 uint64_t fb_modifier; 143 unsigned int width_pages, height_pages; 144 uint64_t size; 145 }; 146 147 struct i915_ggtt_view { 148 enum i915_ggtt_view_type type; 149 150 union { 151 struct { 152 u64 offset; 153 unsigned int size; 154 } partial; 155 } params; 156 157 struct sg_table *pages; 158 159 union { 160 struct intel_rotation_info rotation_info; 161 }; 162 }; 163 164 extern const struct i915_ggtt_view i915_ggtt_view_normal; 165 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 166 167 enum i915_cache_level; 168 169 /** 170 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 171 * VMA's presence cannot be guaranteed before binding, or after unbinding the 172 * object into/from the address space. 173 * 174 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 175 * will always be <= an objects lifetime. So object refcounting should cover us. 176 */ 177 struct i915_vma { 178 struct drm_mm_node node; 179 struct drm_i915_gem_object *obj; 180 struct i915_address_space *vm; 181 182 /** Flags and address space this VMA is bound to */ 183 #define GLOBAL_BIND (1<<0) 184 #define LOCAL_BIND (1<<1) 185 unsigned int bound : 4; 186 187 /** 188 * Support different GGTT views into the same object. 189 * This means there can be multiple VMA mappings per object and per VM. 190 * i915_ggtt_view_type is used to distinguish between those entries. 191 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 192 * assumed in GEM functions which take no ggtt view parameter. 193 */ 194 struct i915_ggtt_view ggtt_view; 195 196 /** This object's place on the active/inactive lists */ 197 struct list_head mm_list; 198 199 struct list_head vma_link; /* Link in the object's VMA list */ 200 201 /** This vma's place in the batchbuffer or on the eviction list */ 202 struct list_head exec_list; 203 204 /** 205 * Used for performing relocations during execbuffer insertion. 206 */ 207 struct hlist_node exec_node; 208 unsigned long exec_handle; 209 struct drm_i915_gem_exec_object2 *exec_entry; 210 211 /** 212 * How many users have pinned this object in GTT space. The following 213 * users can each hold at most one reference: pwrite/pread, execbuffer 214 * (objects are not allowed multiple times for the same batchbuffer), 215 * and the framebuffer code. When switching/pageflipping, the 216 * framebuffer code has at most two buffers pinned per crtc. 217 * 218 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 219 * bits with absolutely no headroom. So use 4 bits. */ 220 unsigned int pin_count:4; 221 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 222 }; 223 224 struct i915_page_dma { 225 struct page *page; 226 union { 227 dma_addr_t daddr; 228 229 /* For gen6/gen7 only. This is the offset in the GGTT 230 * where the page directory entries for PPGTT begin 231 */ 232 uint32_t ggtt_offset; 233 }; 234 }; 235 236 #define px_base(px) (&(px)->base) 237 #define px_page(px) (px_base(px)->page) 238 #define px_dma(px) (px_base(px)->daddr) 239 240 struct i915_page_scratch { 241 struct i915_page_dma base; 242 }; 243 244 struct i915_page_table { 245 struct i915_page_dma base; 246 247 unsigned long *used_ptes; 248 }; 249 250 struct i915_page_directory { 251 struct i915_page_dma base; 252 253 unsigned long *used_pdes; 254 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 255 }; 256 257 struct i915_page_directory_pointer { 258 struct i915_page_dma base; 259 260 unsigned long *used_pdpes; 261 struct i915_page_directory **page_directory; 262 }; 263 264 struct i915_pml4 { 265 struct i915_page_dma base; 266 267 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 268 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 269 }; 270 271 struct i915_address_space { 272 struct drm_mm mm; 273 struct drm_device *dev; 274 struct list_head global_link; 275 u64 start; /* Start offset always 0 for dri2 */ 276 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 277 278 struct i915_page_scratch *scratch_page; 279 struct i915_page_table *scratch_pt; 280 struct i915_page_directory *scratch_pd; 281 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 282 283 /** 284 * List of objects currently involved in rendering. 285 * 286 * Includes buffers having the contents of their GPU caches 287 * flushed, not necessarily primitives. last_read_req 288 * represents when the rendering involved will be completed. 289 * 290 * A reference is held on the buffer while on this list. 291 */ 292 struct list_head active_list; 293 294 /** 295 * LRU list of objects which are not in the ringbuffer and 296 * are ready to unbind, but are still in the GTT. 297 * 298 * last_read_req is NULL while an object is in this list. 299 * 300 * A reference is not held on the buffer while on this list, 301 * as merely being GTT-bound shouldn't prevent its being 302 * freed, and we'll pull it off the list in the free path. 303 */ 304 struct list_head inactive_list; 305 306 /* FIXME: Need a more generic return type */ 307 gen6_pte_t (*pte_encode)(dma_addr_t addr, 308 enum i915_cache_level level, 309 bool valid, u32 flags); /* Create a valid PTE */ 310 /* flags for pte_encode */ 311 #define PTE_READ_ONLY (1<<0) 312 int (*allocate_va_range)(struct i915_address_space *vm, 313 uint64_t start, 314 uint64_t length); 315 void (*clear_range)(struct i915_address_space *vm, 316 uint64_t start, 317 uint64_t length, 318 bool use_scratch); 319 void (*insert_entries)(struct i915_address_space *vm, 320 struct sg_table *st, 321 uint64_t start, 322 enum i915_cache_level cache_level, u32 flags); 323 void (*cleanup)(struct i915_address_space *vm); 324 /** Unmap an object from an address space. This usually consists of 325 * setting the valid PTE entries to a reserved scratch page. */ 326 void (*unbind_vma)(struct i915_vma *vma); 327 /* Map an object into an address space with the given cache flags. */ 328 int (*bind_vma)(struct i915_vma *vma, 329 enum i915_cache_level cache_level, 330 u32 flags); 331 }; 332 333 /* The Graphics Translation Table is the way in which GEN hardware translates a 334 * Graphics Virtual Address into a Physical Address. In addition to the normal 335 * collateral associated with any va->pa translations GEN hardware also has a 336 * portion of the GTT which can be mapped by the CPU and remain both coherent 337 * and correct (in cases like swizzling). That region is referred to as GMADR in 338 * the spec. 339 */ 340 struct i915_gtt { 341 struct i915_address_space base; 342 343 size_t stolen_size; /* Total size of stolen memory */ 344 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 345 u64 mappable_end; /* End offset that we can CPU map */ 346 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 347 phys_addr_t mappable_base; /* PA of our GMADR */ 348 349 /** "Graphics Stolen Memory" holds the global PTEs */ 350 void __iomem *gsm; 351 352 bool do_idle_maps; 353 354 int mtrr; 355 356 /* global gtt ops */ 357 int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total, 358 size_t *stolen, phys_addr_t *mappable_base, 359 u64 *mappable_end); 360 }; 361 362 struct i915_hw_ppgtt { 363 struct i915_address_space base; 364 struct kref ref; 365 struct drm_mm_node node; 366 unsigned long pd_dirty_rings; 367 union { 368 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 369 struct i915_page_directory_pointer pdp; /* GEN8+ */ 370 struct i915_page_directory pd; /* GEN6-7 */ 371 }; 372 373 struct drm_i915_file_private *file_priv; 374 375 gen6_pte_t __iomem *pd_addr; 376 377 int (*enable)(struct i915_hw_ppgtt *ppgtt); 378 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 379 struct drm_i915_gem_request *req); 380 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 381 }; 382 383 /* For each pde iterates over every pde between from start until start + length. 384 * If start, and start+length are not perfectly divisible, the macro will round 385 * down, and up as needed. The macro modifies pde, start, and length. Dev is 386 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, 387 * and length = 2G effectively iterates over every PDE in the system. 388 * 389 * XXX: temp is not actually needed, but it saves doing the ALIGN operation. 390 */ 391 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ 392 for (iter = gen6_pde_index(start); \ 393 pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 394 iter++, \ 395 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ 396 temp = min_t(unsigned, temp, length), \ 397 start += temp, length -= temp) 398 399 #define gen6_for_all_pdes(pt, ppgtt, iter) \ 400 for (iter = 0; \ 401 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ 402 iter++) 403 404 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 405 { 406 const uint32_t mask = NUM_PTE(pde_shift) - 1; 407 408 return (address >> PAGE_SHIFT) & mask; 409 } 410 411 /* Helper to counts the number of PTEs within the given length. This count 412 * does not cross a page table boundary, so the max value would be 413 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 414 */ 415 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 416 uint32_t pde_shift) 417 { 418 const uint64_t mask = ~((1 << pde_shift) - 1); 419 uint64_t end; 420 421 WARN_ON(length == 0); 422 WARN_ON(offset_in_page(addr|length)); 423 424 end = addr + length; 425 426 if ((addr & mask) != (end & mask)) 427 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 428 429 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 430 } 431 432 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 433 { 434 return (addr >> shift) & I915_PDE_MASK; 435 } 436 437 static inline uint32_t gen6_pte_index(uint32_t addr) 438 { 439 return i915_pte_index(addr, GEN6_PDE_SHIFT); 440 } 441 442 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 443 { 444 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 445 } 446 447 static inline uint32_t gen6_pde_index(uint32_t addr) 448 { 449 return i915_pde_index(addr, GEN6_PDE_SHIFT); 450 } 451 452 /* Equivalent to the gen6 version, For each pde iterates over every pde 453 * between from start until start + length. On gen8+ it simply iterates 454 * over every page directory entry in a page directory. 455 */ 456 #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ 457 for (iter = gen8_pde_index(start); \ 458 pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 459 iter++, \ 460 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ 461 temp = min(temp, length), \ 462 start += temp, length -= temp) 463 464 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ 465 for (iter = gen8_pdpe_index(start); \ 466 pd = (pdp)->page_directory[iter], \ 467 length > 0 && (iter < I915_PDPES_PER_PDP(dev)); \ 468 iter++, \ 469 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ 470 temp = min(temp, length), \ 471 start += temp, length -= temp) 472 473 #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter) \ 474 for (iter = gen8_pml4e_index(start); \ 475 pdp = (pml4)->pdps[iter], \ 476 length > 0 && iter < GEN8_PML4ES_PER_PML4; \ 477 iter++, \ 478 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start, \ 479 temp = min(temp, length), \ 480 start += temp, length -= temp) 481 482 static inline uint32_t gen8_pte_index(uint64_t address) 483 { 484 return i915_pte_index(address, GEN8_PDE_SHIFT); 485 } 486 487 static inline uint32_t gen8_pde_index(uint64_t address) 488 { 489 return i915_pde_index(address, GEN8_PDE_SHIFT); 490 } 491 492 static inline uint32_t gen8_pdpe_index(uint64_t address) 493 { 494 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 495 } 496 497 static inline uint32_t gen8_pml4e_index(uint64_t address) 498 { 499 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 500 } 501 502 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 503 { 504 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 505 } 506 507 static inline dma_addr_t 508 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 509 { 510 return test_bit(n, ppgtt->pdp.used_pdpes) ? 511 px_dma(ppgtt->pdp.page_directory[n]) : 512 px_dma(ppgtt->base.scratch_pd); 513 } 514 515 int i915_gem_gtt_init(struct drm_device *dev); 516 void i915_gem_init_global_gtt(struct drm_device *dev); 517 void i915_global_gtt_cleanup(struct drm_device *dev); 518 519 520 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 521 int i915_ppgtt_init_hw(struct drm_device *dev); 522 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); 523 void i915_ppgtt_release(struct kref *kref); 524 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 525 struct drm_i915_file_private *fpriv); 526 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 527 { 528 if (ppgtt) 529 kref_get(&ppgtt->ref); 530 } 531 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 532 { 533 if (ppgtt) 534 kref_put(&ppgtt->ref, i915_ppgtt_release); 535 } 536 537 void i915_check_and_clear_faults(struct drm_device *dev); 538 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 539 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 540 541 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 542 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 543 544 static inline bool 545 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 546 const struct i915_ggtt_view *b) 547 { 548 if (WARN_ON(!a || !b)) 549 return false; 550 551 if (a->type != b->type) 552 return false; 553 if (a->type == I915_GGTT_VIEW_PARTIAL) 554 return !memcmp(&a->params, &b->params, sizeof(a->params)); 555 return true; 556 } 557 558 size_t 559 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 560 const struct i915_ggtt_view *view); 561 562 #endif 563