1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 #include <linux/mm.h> 39 #include <linux/pagevec.h> 40 41 #include "gt/intel_reset.h" 42 #include "i915_request.h" 43 #include "i915_selftest.h" 44 #include "i915_timeline.h" 45 46 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 47 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 48 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 49 50 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 51 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 52 53 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 54 55 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 56 57 #define I915_FENCE_REG_NONE -1 58 #define I915_MAX_NUM_FENCES 32 59 /* 32 fences + sign bit for FENCE_REG_NONE */ 60 #define I915_MAX_NUM_FENCE_BITS 6 61 62 struct drm_i915_file_private; 63 struct drm_i915_fence_reg; 64 struct i915_vma; 65 66 typedef u32 gen6_pte_t; 67 typedef u64 gen8_pte_t; 68 typedef u64 gen8_pde_t; 69 typedef u64 gen8_ppgtt_pdpe_t; 70 typedef u64 gen8_ppgtt_pml4e_t; 71 72 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 73 74 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 75 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 76 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 77 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 78 #define GEN6_PTE_CACHE_LLC (2 << 1) 79 #define GEN6_PTE_UNCACHED (1 << 1) 80 #define GEN6_PTE_VALID (1 << 0) 81 82 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 83 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 84 #define I915_PDES 512 85 #define I915_PDE_MASK (I915_PDES - 1) 86 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 87 88 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 89 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 90 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 91 #define GEN6_PDE_SHIFT 22 92 #define GEN6_PDE_VALID (1 << 0) 93 94 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 95 96 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 97 #define BYT_PTE_WRITEABLE (1 << 1) 98 99 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 100 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 101 */ 102 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 103 (((bits) & 0x8) << (11 - 3))) 104 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 105 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 106 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 107 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 108 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 109 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 110 #define HSW_PTE_UNCACHED (0) 111 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 112 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 113 114 /* GEN8 32b style address is defined as a 3 level page table: 115 * 31:30 | 29:21 | 20:12 | 11:0 116 * PDPE | PDE | PTE | offset 117 * The difference as compared to normal x86 3 level page table is the PDPEs are 118 * programmed via register. 119 */ 120 #define GEN8_3LVL_PDPES 4 121 #define GEN8_PDE_SHIFT 21 122 #define GEN8_PDE_MASK 0x1ff 123 #define GEN8_PTE_SHIFT 12 124 #define GEN8_PTE_MASK 0x1ff 125 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 126 127 /* GEN8 48b style address is defined as a 4 level page table: 128 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 129 * PML4E | PDPE | PDE | PTE | offset 130 */ 131 #define GEN8_PML4ES_PER_PML4 512 132 #define GEN8_PML4E_SHIFT 39 133 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 134 #define GEN8_PDPE_SHIFT 30 135 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 136 * tables */ 137 #define GEN8_PDPE_MASK 0x1ff 138 139 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 140 #define PPAT_CACHED_PDE 0 /* WB LLC */ 141 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 142 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 143 144 #define CHV_PPAT_SNOOP (1<<6) 145 #define GEN8_PPAT_AGE(x) ((x)<<4) 146 #define GEN8_PPAT_LLCeLLC (3<<2) 147 #define GEN8_PPAT_LLCELLC (2<<2) 148 #define GEN8_PPAT_LLC (1<<2) 149 #define GEN8_PPAT_WB (3<<0) 150 #define GEN8_PPAT_WT (2<<0) 151 #define GEN8_PPAT_WC (1<<0) 152 #define GEN8_PPAT_UC (0<<0) 153 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 154 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 155 156 #define GEN8_PPAT_GET_CA(x) ((x) & 3) 157 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 158 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 159 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 160 161 #define GEN8_PDE_IPS_64K BIT(11) 162 #define GEN8_PDE_PS_2M BIT(7) 163 164 struct sg_table; 165 166 struct intel_remapped_plane_info { 167 /* in gtt pages */ 168 unsigned int width, height, stride, offset; 169 } __packed; 170 171 struct intel_remapped_info { 172 struct intel_remapped_plane_info plane[2]; 173 unsigned int unused_mbz; 174 } __packed; 175 176 struct intel_rotation_info { 177 struct intel_remapped_plane_info plane[2]; 178 } __packed; 179 180 struct intel_partial_info { 181 u64 offset; 182 unsigned int size; 183 } __packed; 184 185 enum i915_ggtt_view_type { 186 I915_GGTT_VIEW_NORMAL = 0, 187 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 188 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 189 I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info), 190 }; 191 192 static inline void assert_i915_gem_gtt_types(void) 193 { 194 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 195 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 196 BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int)); 197 198 /* Check that rotation/remapped shares offsets for simplicity */ 199 BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) != 200 offsetof(struct intel_rotation_info, plane[0])); 201 BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) != 202 offsetofend(struct intel_rotation_info, plane[1])); 203 204 /* As we encode the size of each branch inside the union into its type, 205 * we have to be careful that each branch has a unique size. 206 */ 207 switch ((enum i915_ggtt_view_type)0) { 208 case I915_GGTT_VIEW_NORMAL: 209 case I915_GGTT_VIEW_PARTIAL: 210 case I915_GGTT_VIEW_ROTATED: 211 case I915_GGTT_VIEW_REMAPPED: 212 /* gcc complains if these are identical cases */ 213 break; 214 } 215 } 216 217 struct i915_ggtt_view { 218 enum i915_ggtt_view_type type; 219 union { 220 /* Members need to contain no holes/padding */ 221 struct intel_partial_info partial; 222 struct intel_rotation_info rotated; 223 struct intel_remapped_info remapped; 224 }; 225 }; 226 227 enum i915_cache_level; 228 229 struct i915_vma; 230 231 struct i915_page_dma { 232 struct page *page; 233 union { 234 dma_addr_t daddr; 235 236 /* For gen6/gen7 only. This is the offset in the GGTT 237 * where the page directory entries for PPGTT begin 238 */ 239 u32 ggtt_offset; 240 }; 241 }; 242 243 #define px_base(px) (&(px)->base) 244 #define px_dma(px) (px_base(px)->daddr) 245 246 struct i915_page_table { 247 struct i915_page_dma base; 248 unsigned int used_ptes; 249 }; 250 251 struct i915_page_directory { 252 struct i915_page_dma base; 253 254 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 255 unsigned int used_pdes; 256 }; 257 258 struct i915_page_directory_pointer { 259 struct i915_page_dma base; 260 struct i915_page_directory **page_directory; 261 unsigned int used_pdpes; 262 }; 263 264 struct i915_pml4 { 265 struct i915_page_dma base; 266 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 267 }; 268 269 struct i915_vma_ops { 270 /* Map an object into an address space with the given cache flags. */ 271 int (*bind_vma)(struct i915_vma *vma, 272 enum i915_cache_level cache_level, 273 u32 flags); 274 /* 275 * Unmap an object from an address space. This usually consists of 276 * setting the valid PTE entries to a reserved scratch page. 277 */ 278 void (*unbind_vma)(struct i915_vma *vma); 279 280 int (*set_pages)(struct i915_vma *vma); 281 void (*clear_pages)(struct i915_vma *vma); 282 }; 283 284 struct pagestash { 285 spinlock_t lock; 286 struct pagevec pvec; 287 }; 288 289 struct i915_address_space { 290 struct drm_mm mm; 291 struct drm_i915_private *i915; 292 struct device *dma; 293 /* Every address space belongs to a struct file - except for the global 294 * GTT that is owned by the driver (and so @file is set to NULL). In 295 * principle, no information should leak from one context to another 296 * (or between files/processes etc) unless explicitly shared by the 297 * owner. Tracking the owner is important in order to free up per-file 298 * objects along with the file, to aide resource tracking, and to 299 * assign blame. 300 */ 301 struct drm_i915_file_private *file; 302 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 303 u64 reserved; /* size addr space reserved */ 304 305 bool closed; 306 307 struct mutex mutex; /* protects vma and our lists */ 308 #define VM_CLASS_GGTT 0 309 #define VM_CLASS_PPGTT 1 310 311 u64 scratch_pte; 312 int scratch_order; 313 struct i915_page_dma scratch_page; 314 struct i915_page_table *scratch_pt; 315 struct i915_page_directory *scratch_pd; 316 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 317 318 /** 319 * List of vma currently bound. 320 */ 321 struct list_head bound_list; 322 323 /** 324 * List of vma that are not unbound. 325 */ 326 struct list_head unbound_list; 327 328 struct pagestash free_pages; 329 330 /* Global GTT */ 331 bool is_ggtt:1; 332 333 /* Some systems require uncached updates of the page directories */ 334 bool pt_kmap_wc:1; 335 336 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 337 bool has_read_only:1; 338 339 u64 (*pte_encode)(dma_addr_t addr, 340 enum i915_cache_level level, 341 u32 flags); /* Create a valid PTE */ 342 #define PTE_READ_ONLY (1<<0) 343 344 int (*allocate_va_range)(struct i915_address_space *vm, 345 u64 start, u64 length); 346 void (*clear_range)(struct i915_address_space *vm, 347 u64 start, u64 length); 348 void (*insert_page)(struct i915_address_space *vm, 349 dma_addr_t addr, 350 u64 offset, 351 enum i915_cache_level cache_level, 352 u32 flags); 353 void (*insert_entries)(struct i915_address_space *vm, 354 struct i915_vma *vma, 355 enum i915_cache_level cache_level, 356 u32 flags); 357 void (*cleanup)(struct i915_address_space *vm); 358 359 struct i915_vma_ops vma_ops; 360 361 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 362 I915_SELFTEST_DECLARE(bool scrub_64K); 363 }; 364 365 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 366 367 static inline bool 368 i915_vm_is_4lvl(const struct i915_address_space *vm) 369 { 370 return (vm->total - 1) >> 32; 371 } 372 373 static inline bool 374 i915_vm_has_scratch_64K(struct i915_address_space *vm) 375 { 376 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 377 } 378 379 /* The Graphics Translation Table is the way in which GEN hardware translates a 380 * Graphics Virtual Address into a Physical Address. In addition to the normal 381 * collateral associated with any va->pa translations GEN hardware also has a 382 * portion of the GTT which can be mapped by the CPU and remain both coherent 383 * and correct (in cases like swizzling). That region is referred to as GMADR in 384 * the spec. 385 */ 386 struct i915_ggtt { 387 struct i915_address_space vm; 388 389 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 390 struct resource gmadr; /* GMADR resource */ 391 resource_size_t mappable_end; /* End offset that we can CPU map */ 392 393 /** "Graphics Stolen Memory" holds the global PTEs */ 394 void __iomem *gsm; 395 void (*invalidate)(struct drm_i915_private *dev_priv); 396 397 bool do_idle_maps; 398 399 int mtrr; 400 401 u32 pin_bias; 402 403 struct drm_mm_node error_capture; 404 struct drm_mm_node uc_fw; 405 }; 406 407 struct i915_hw_ppgtt { 408 struct i915_address_space vm; 409 struct kref ref; 410 411 intel_engine_mask_t pd_dirty_engines; 412 union { 413 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 414 struct i915_page_directory_pointer pdp; /* GEN8+ */ 415 struct i915_page_directory pd; /* GEN6-7 */ 416 }; 417 }; 418 419 struct gen6_hw_ppgtt { 420 struct i915_hw_ppgtt base; 421 422 struct i915_vma *vma; 423 gen6_pte_t __iomem *pd_addr; 424 425 unsigned int pin_count; 426 bool scan_for_unused_pt; 427 428 struct gen6_ppgtt_cleanup_work *work; 429 }; 430 431 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base) 432 433 static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base) 434 { 435 BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base)); 436 return __to_gen6_ppgtt(base); 437 } 438 439 /* 440 * gen6_for_each_pde() iterates over every pde from start until start+length. 441 * If start and start+length are not perfectly divisible, the macro will round 442 * down and up as needed. Start=0 and length=2G effectively iterates over 443 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 444 * so each of the other parameters should preferably be a simple variable, or 445 * at most an lvalue with no side-effects! 446 */ 447 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 448 for (iter = gen6_pde_index(start); \ 449 length > 0 && iter < I915_PDES && \ 450 (pt = (pd)->page_table[iter], true); \ 451 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 452 temp = min(temp - start, length); \ 453 start += temp, length -= temp; }), ++iter) 454 455 #define gen6_for_all_pdes(pt, pd, iter) \ 456 for (iter = 0; \ 457 iter < I915_PDES && \ 458 (pt = (pd)->page_table[iter], true); \ 459 ++iter) 460 461 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 462 { 463 const u32 mask = NUM_PTE(pde_shift) - 1; 464 465 return (address >> PAGE_SHIFT) & mask; 466 } 467 468 /* Helper to counts the number of PTEs within the given length. This count 469 * does not cross a page table boundary, so the max value would be 470 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 471 */ 472 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 473 { 474 const u64 mask = ~((1ULL << pde_shift) - 1); 475 u64 end; 476 477 GEM_BUG_ON(length == 0); 478 GEM_BUG_ON(offset_in_page(addr | length)); 479 480 end = addr + length; 481 482 if ((addr & mask) != (end & mask)) 483 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 484 485 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 486 } 487 488 static inline u32 i915_pde_index(u64 addr, u32 shift) 489 { 490 return (addr >> shift) & I915_PDE_MASK; 491 } 492 493 static inline u32 gen6_pte_index(u32 addr) 494 { 495 return i915_pte_index(addr, GEN6_PDE_SHIFT); 496 } 497 498 static inline u32 gen6_pte_count(u32 addr, u32 length) 499 { 500 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 501 } 502 503 static inline u32 gen6_pde_index(u32 addr) 504 { 505 return i915_pde_index(addr, GEN6_PDE_SHIFT); 506 } 507 508 static inline unsigned int 509 i915_pdpes_per_pdp(const struct i915_address_space *vm) 510 { 511 if (i915_vm_is_4lvl(vm)) 512 return GEN8_PML4ES_PER_PML4; 513 514 return GEN8_3LVL_PDPES; 515 } 516 517 /* Equivalent to the gen6 version, For each pde iterates over every pde 518 * between from start until start + length. On gen8+ it simply iterates 519 * over every page directory entry in a page directory. 520 */ 521 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 522 for (iter = gen8_pde_index(start); \ 523 length > 0 && iter < I915_PDES && \ 524 (pt = (pd)->page_table[iter], true); \ 525 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 526 temp = min(temp - start, length); \ 527 start += temp, length -= temp; }), ++iter) 528 529 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 530 for (iter = gen8_pdpe_index(start); \ 531 length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 532 (pd = (pdp)->page_directory[iter], true); \ 533 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 534 temp = min(temp - start, length); \ 535 start += temp, length -= temp; }), ++iter) 536 537 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 538 for (iter = gen8_pml4e_index(start); \ 539 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 540 (pdp = (pml4)->pdps[iter], true); \ 541 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 542 temp = min(temp - start, length); \ 543 start += temp, length -= temp; }), ++iter) 544 545 static inline u32 gen8_pte_index(u64 address) 546 { 547 return i915_pte_index(address, GEN8_PDE_SHIFT); 548 } 549 550 static inline u32 gen8_pde_index(u64 address) 551 { 552 return i915_pde_index(address, GEN8_PDE_SHIFT); 553 } 554 555 static inline u32 gen8_pdpe_index(u64 address) 556 { 557 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 558 } 559 560 static inline u32 gen8_pml4e_index(u64 address) 561 { 562 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 563 } 564 565 static inline u64 gen8_pte_count(u64 address, u64 length) 566 { 567 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 568 } 569 570 static inline dma_addr_t 571 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 572 { 573 return px_dma(ppgtt->pdp.page_directory[n]); 574 } 575 576 static inline struct i915_ggtt * 577 i915_vm_to_ggtt(struct i915_address_space *vm) 578 { 579 GEM_BUG_ON(!i915_is_ggtt(vm)); 580 return container_of(vm, struct i915_ggtt, vm); 581 } 582 583 #define INTEL_MAX_PPAT_ENTRIES 8 584 #define INTEL_PPAT_PERFECT_MATCH (~0U) 585 586 struct intel_ppat; 587 588 struct intel_ppat_entry { 589 struct intel_ppat *ppat; 590 struct kref ref; 591 u8 value; 592 }; 593 594 struct intel_ppat { 595 struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 596 DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 597 DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 598 unsigned int max_entries; 599 u8 clear_value; 600 /* 601 * Return a score to show how two PPAT values match, 602 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 603 */ 604 unsigned int (*match)(u8 src, u8 dst); 605 void (*update_hw)(struct drm_i915_private *i915); 606 607 struct drm_i915_private *i915; 608 }; 609 610 const struct intel_ppat_entry * 611 intel_ppat_get(struct drm_i915_private *i915, u8 value); 612 void intel_ppat_put(const struct intel_ppat_entry *entry); 613 614 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 615 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 616 617 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 618 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 619 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 620 void i915_ggtt_enable_guc(struct drm_i915_private *i915); 621 void i915_ggtt_disable_guc(struct drm_i915_private *i915); 622 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 623 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 624 625 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 626 627 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv); 628 void i915_ppgtt_release(struct kref *kref); 629 630 static inline struct i915_hw_ppgtt *i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 631 { 632 kref_get(&ppgtt->ref); 633 return ppgtt; 634 } 635 636 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 637 { 638 if (ppgtt) 639 kref_put(&ppgtt->ref, i915_ppgtt_release); 640 } 641 642 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base); 643 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base); 644 void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base); 645 646 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 647 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 648 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 649 650 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 651 struct sg_table *pages); 652 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 653 struct sg_table *pages); 654 655 int i915_gem_gtt_reserve(struct i915_address_space *vm, 656 struct drm_mm_node *node, 657 u64 size, u64 offset, unsigned long color, 658 unsigned int flags); 659 660 int i915_gem_gtt_insert(struct i915_address_space *vm, 661 struct drm_mm_node *node, 662 u64 size, u64 alignment, unsigned long color, 663 u64 start, u64 end, unsigned int flags); 664 665 /* Flags used by pin/bind&friends. */ 666 #define PIN_NONBLOCK BIT_ULL(0) 667 #define PIN_NONFAULT BIT_ULL(1) 668 #define PIN_NOEVICT BIT_ULL(2) 669 #define PIN_MAPPABLE BIT_ULL(3) 670 #define PIN_ZONE_4G BIT_ULL(4) 671 #define PIN_HIGH BIT_ULL(5) 672 #define PIN_OFFSET_BIAS BIT_ULL(6) 673 #define PIN_OFFSET_FIXED BIT_ULL(7) 674 675 #define PIN_MBZ BIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */ 676 #define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */ 677 #define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */ 678 #define PIN_UPDATE BIT_ULL(11) 679 680 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 681 682 #endif 683