1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 39 struct drm_i915_file_private; 40 41 typedef uint32_t gen6_pte_t; 42 typedef uint64_t gen8_pte_t; 43 typedef uint64_t gen8_pde_t; 44 typedef uint64_t gen8_ppgtt_pdpe_t; 45 typedef uint64_t gen8_ppgtt_pml4e_t; 46 47 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 48 49 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 50 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 51 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 52 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 53 #define GEN6_PTE_CACHE_LLC (2 << 1) 54 #define GEN6_PTE_UNCACHED (1 << 1) 55 #define GEN6_PTE_VALID (1 << 0) 56 57 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 58 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 59 #define I915_PDES 512 60 #define I915_PDE_MASK (I915_PDES - 1) 61 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 62 63 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 64 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 65 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 66 #define GEN6_PDE_SHIFT 22 67 #define GEN6_PDE_VALID (1 << 0) 68 69 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 70 71 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 72 #define BYT_PTE_WRITEABLE (1 << 1) 73 74 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 75 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 76 */ 77 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 78 (((bits) & 0x8) << (11 - 3))) 79 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 80 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 81 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 82 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 83 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 84 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 85 #define HSW_PTE_UNCACHED (0) 86 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 87 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 88 89 /* GEN8 legacy style address is defined as a 3 level page table: 90 * 31:30 | 29:21 | 20:12 | 11:0 91 * PDPE | PDE | PTE | offset 92 * The difference as compared to normal x86 3 level page table is the PDPEs are 93 * programmed via register. 94 * 95 * GEN8 48b legacy style address is defined as a 4 level page table: 96 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 97 * PML4E | PDPE | PDE | PTE | offset 98 */ 99 #define GEN8_PML4ES_PER_PML4 512 100 #define GEN8_PML4E_SHIFT 39 101 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 102 #define GEN8_PDPE_SHIFT 30 103 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 104 * tables */ 105 #define GEN8_PDPE_MASK 0x1ff 106 #define GEN8_PDE_SHIFT 21 107 #define GEN8_PDE_MASK 0x1ff 108 #define GEN8_PTE_SHIFT 12 109 #define GEN8_PTE_MASK 0x1ff 110 #define GEN8_LEGACY_PDPES 4 111 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 112 113 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 114 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 115 116 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 117 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 118 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 119 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 120 121 #define CHV_PPAT_SNOOP (1<<6) 122 #define GEN8_PPAT_AGE(x) (x<<4) 123 #define GEN8_PPAT_LLCeLLC (3<<2) 124 #define GEN8_PPAT_LLCELLC (2<<2) 125 #define GEN8_PPAT_LLC (1<<2) 126 #define GEN8_PPAT_WB (3<<0) 127 #define GEN8_PPAT_WT (2<<0) 128 #define GEN8_PPAT_WC (1<<0) 129 #define GEN8_PPAT_UC (0<<0) 130 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 131 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 132 133 enum i915_ggtt_view_type { 134 I915_GGTT_VIEW_NORMAL = 0, 135 I915_GGTT_VIEW_ROTATED, 136 I915_GGTT_VIEW_PARTIAL, 137 }; 138 139 struct intel_rotation_info { 140 unsigned int uv_offset; 141 uint32_t pixel_format; 142 unsigned int uv_start_page; 143 struct { 144 /* tiles */ 145 unsigned int width, height; 146 } plane[2]; 147 }; 148 149 struct i915_ggtt_view { 150 enum i915_ggtt_view_type type; 151 152 union { 153 struct { 154 u64 offset; 155 unsigned int size; 156 } partial; 157 struct intel_rotation_info rotated; 158 } params; 159 160 struct sg_table *pages; 161 }; 162 163 extern const struct i915_ggtt_view i915_ggtt_view_normal; 164 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 165 166 enum i915_cache_level; 167 168 /** 169 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 170 * VMA's presence cannot be guaranteed before binding, or after unbinding the 171 * object into/from the address space. 172 * 173 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 174 * will always be <= an objects lifetime. So object refcounting should cover us. 175 */ 176 struct i915_vma { 177 struct drm_mm_node node; 178 struct drm_i915_gem_object *obj; 179 struct i915_address_space *vm; 180 void __iomem *iomap; 181 182 /** Flags and address space this VMA is bound to */ 183 #define GLOBAL_BIND (1<<0) 184 #define LOCAL_BIND (1<<1) 185 unsigned int bound : 4; 186 bool is_ggtt : 1; 187 188 /** 189 * Support different GGTT views into the same object. 190 * This means there can be multiple VMA mappings per object and per VM. 191 * i915_ggtt_view_type is used to distinguish between those entries. 192 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 193 * assumed in GEM functions which take no ggtt view parameter. 194 */ 195 struct i915_ggtt_view ggtt_view; 196 197 /** This object's place on the active/inactive lists */ 198 struct list_head vm_link; 199 200 struct list_head obj_link; /* Link in the object's VMA list */ 201 202 /** This vma's place in the batchbuffer or on the eviction list */ 203 struct list_head exec_list; 204 205 /** 206 * Used for performing relocations during execbuffer insertion. 207 */ 208 struct hlist_node exec_node; 209 unsigned long exec_handle; 210 struct drm_i915_gem_exec_object2 *exec_entry; 211 212 /** 213 * How many users have pinned this object in GTT space. The following 214 * users can each hold at most one reference: pwrite/pread, execbuffer 215 * (objects are not allowed multiple times for the same batchbuffer), 216 * and the framebuffer code. When switching/pageflipping, the 217 * framebuffer code has at most two buffers pinned per crtc. 218 * 219 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 220 * bits with absolutely no headroom. So use 4 bits. */ 221 unsigned int pin_count:4; 222 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 223 }; 224 225 struct i915_page_dma { 226 struct page *page; 227 union { 228 dma_addr_t daddr; 229 230 /* For gen6/gen7 only. This is the offset in the GGTT 231 * where the page directory entries for PPGTT begin 232 */ 233 uint32_t ggtt_offset; 234 }; 235 }; 236 237 #define px_base(px) (&(px)->base) 238 #define px_page(px) (px_base(px)->page) 239 #define px_dma(px) (px_base(px)->daddr) 240 241 struct i915_page_scratch { 242 struct i915_page_dma base; 243 }; 244 245 struct i915_page_table { 246 struct i915_page_dma base; 247 248 unsigned long *used_ptes; 249 }; 250 251 struct i915_page_directory { 252 struct i915_page_dma base; 253 254 unsigned long *used_pdes; 255 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 256 }; 257 258 struct i915_page_directory_pointer { 259 struct i915_page_dma base; 260 261 unsigned long *used_pdpes; 262 struct i915_page_directory **page_directory; 263 }; 264 265 struct i915_pml4 { 266 struct i915_page_dma base; 267 268 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 269 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 270 }; 271 272 struct i915_address_space { 273 struct drm_mm mm; 274 struct drm_device *dev; 275 struct list_head global_link; 276 u64 start; /* Start offset always 0 for dri2 */ 277 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 278 279 bool is_ggtt; 280 281 struct i915_page_scratch *scratch_page; 282 struct i915_page_table *scratch_pt; 283 struct i915_page_directory *scratch_pd; 284 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 285 286 /** 287 * List of objects currently involved in rendering. 288 * 289 * Includes buffers having the contents of their GPU caches 290 * flushed, not necessarily primitives. last_read_req 291 * represents when the rendering involved will be completed. 292 * 293 * A reference is held on the buffer while on this list. 294 */ 295 struct list_head active_list; 296 297 /** 298 * LRU list of objects which are not in the ringbuffer and 299 * are ready to unbind, but are still in the GTT. 300 * 301 * last_read_req is NULL while an object is in this list. 302 * 303 * A reference is not held on the buffer while on this list, 304 * as merely being GTT-bound shouldn't prevent its being 305 * freed, and we'll pull it off the list in the free path. 306 */ 307 struct list_head inactive_list; 308 309 /* FIXME: Need a more generic return type */ 310 gen6_pte_t (*pte_encode)(dma_addr_t addr, 311 enum i915_cache_level level, 312 bool valid, u32 flags); /* Create a valid PTE */ 313 /* flags for pte_encode */ 314 #define PTE_READ_ONLY (1<<0) 315 int (*allocate_va_range)(struct i915_address_space *vm, 316 uint64_t start, 317 uint64_t length); 318 void (*clear_range)(struct i915_address_space *vm, 319 uint64_t start, 320 uint64_t length, 321 bool use_scratch); 322 void (*insert_page)(struct i915_address_space *vm, 323 dma_addr_t addr, 324 uint64_t offset, 325 enum i915_cache_level cache_level, 326 u32 flags); 327 void (*insert_entries)(struct i915_address_space *vm, 328 struct sg_table *st, 329 uint64_t start, 330 enum i915_cache_level cache_level, u32 flags); 331 void (*cleanup)(struct i915_address_space *vm); 332 /** Unmap an object from an address space. This usually consists of 333 * setting the valid PTE entries to a reserved scratch page. */ 334 void (*unbind_vma)(struct i915_vma *vma); 335 /* Map an object into an address space with the given cache flags. */ 336 int (*bind_vma)(struct i915_vma *vma, 337 enum i915_cache_level cache_level, 338 u32 flags); 339 }; 340 341 #define i915_is_ggtt(V) ((V)->is_ggtt) 342 343 /* The Graphics Translation Table is the way in which GEN hardware translates a 344 * Graphics Virtual Address into a Physical Address. In addition to the normal 345 * collateral associated with any va->pa translations GEN hardware also has a 346 * portion of the GTT which can be mapped by the CPU and remain both coherent 347 * and correct (in cases like swizzling). That region is referred to as GMADR in 348 * the spec. 349 */ 350 struct i915_ggtt { 351 struct i915_address_space base; 352 353 size_t stolen_size; /* Total size of stolen memory */ 354 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 355 size_t stolen_reserved_base; 356 size_t stolen_reserved_size; 357 size_t size; /* Total size of Global GTT */ 358 u64 mappable_end; /* End offset that we can CPU map */ 359 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 360 phys_addr_t mappable_base; /* PA of our GMADR */ 361 362 /** "Graphics Stolen Memory" holds the global PTEs */ 363 void __iomem *gsm; 364 365 bool do_idle_maps; 366 367 int mtrr; 368 369 int (*probe)(struct i915_ggtt *ggtt); 370 }; 371 372 struct i915_hw_ppgtt { 373 struct i915_address_space base; 374 struct kref ref; 375 struct drm_mm_node node; 376 unsigned long pd_dirty_rings; 377 union { 378 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 379 struct i915_page_directory_pointer pdp; /* GEN8+ */ 380 struct i915_page_directory pd; /* GEN6-7 */ 381 }; 382 383 struct drm_i915_file_private *file_priv; 384 385 gen6_pte_t __iomem *pd_addr; 386 387 int (*enable)(struct i915_hw_ppgtt *ppgtt); 388 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 389 struct drm_i915_gem_request *req); 390 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 391 }; 392 393 /* 394 * gen6_for_each_pde() iterates over every pde from start until start+length. 395 * If start and start+length are not perfectly divisible, the macro will round 396 * down and up as needed. Start=0 and length=2G effectively iterates over 397 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 398 * so each of the other parameters should preferably be a simple variable, or 399 * at most an lvalue with no side-effects! 400 */ 401 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 402 for (iter = gen6_pde_index(start); \ 403 length > 0 && iter < I915_PDES && \ 404 (pt = (pd)->page_table[iter], true); \ 405 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 406 temp = min(temp - start, length); \ 407 start += temp, length -= temp; }), ++iter) 408 409 #define gen6_for_all_pdes(pt, pd, iter) \ 410 for (iter = 0; \ 411 iter < I915_PDES && \ 412 (pt = (pd)->page_table[iter], true); \ 413 ++iter) 414 415 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 416 { 417 const uint32_t mask = NUM_PTE(pde_shift) - 1; 418 419 return (address >> PAGE_SHIFT) & mask; 420 } 421 422 /* Helper to counts the number of PTEs within the given length. This count 423 * does not cross a page table boundary, so the max value would be 424 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 425 */ 426 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 427 uint32_t pde_shift) 428 { 429 const uint64_t mask = ~((1ULL << pde_shift) - 1); 430 uint64_t end; 431 432 WARN_ON(length == 0); 433 WARN_ON(offset_in_page(addr|length)); 434 435 end = addr + length; 436 437 if ((addr & mask) != (end & mask)) 438 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 439 440 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 441 } 442 443 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 444 { 445 return (addr >> shift) & I915_PDE_MASK; 446 } 447 448 static inline uint32_t gen6_pte_index(uint32_t addr) 449 { 450 return i915_pte_index(addr, GEN6_PDE_SHIFT); 451 } 452 453 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 454 { 455 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 456 } 457 458 static inline uint32_t gen6_pde_index(uint32_t addr) 459 { 460 return i915_pde_index(addr, GEN6_PDE_SHIFT); 461 } 462 463 /* Equivalent to the gen6 version, For each pde iterates over every pde 464 * between from start until start + length. On gen8+ it simply iterates 465 * over every page directory entry in a page directory. 466 */ 467 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 468 for (iter = gen8_pde_index(start); \ 469 length > 0 && iter < I915_PDES && \ 470 (pt = (pd)->page_table[iter], true); \ 471 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 472 temp = min(temp - start, length); \ 473 start += temp, length -= temp; }), ++iter) 474 475 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 476 for (iter = gen8_pdpe_index(start); \ 477 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 478 (pd = (pdp)->page_directory[iter], true); \ 479 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 480 temp = min(temp - start, length); \ 481 start += temp, length -= temp; }), ++iter) 482 483 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 484 for (iter = gen8_pml4e_index(start); \ 485 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 486 (pdp = (pml4)->pdps[iter], true); \ 487 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 488 temp = min(temp - start, length); \ 489 start += temp, length -= temp; }), ++iter) 490 491 static inline uint32_t gen8_pte_index(uint64_t address) 492 { 493 return i915_pte_index(address, GEN8_PDE_SHIFT); 494 } 495 496 static inline uint32_t gen8_pde_index(uint64_t address) 497 { 498 return i915_pde_index(address, GEN8_PDE_SHIFT); 499 } 500 501 static inline uint32_t gen8_pdpe_index(uint64_t address) 502 { 503 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 504 } 505 506 static inline uint32_t gen8_pml4e_index(uint64_t address) 507 { 508 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 509 } 510 511 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 512 { 513 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 514 } 515 516 static inline dma_addr_t 517 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 518 { 519 return test_bit(n, ppgtt->pdp.used_pdpes) ? 520 px_dma(ppgtt->pdp.page_directory[n]) : 521 px_dma(ppgtt->base.scratch_pd); 522 } 523 524 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 525 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 526 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 527 void i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 528 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 529 530 int i915_ppgtt_init_hw(struct drm_device *dev); 531 void i915_ppgtt_release(struct kref *kref); 532 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 533 struct drm_i915_file_private *fpriv); 534 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 535 { 536 if (ppgtt) 537 kref_get(&ppgtt->ref); 538 } 539 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 540 { 541 if (ppgtt) 542 kref_put(&ppgtt->ref, i915_ppgtt_release); 543 } 544 545 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 546 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 547 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 548 549 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 550 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 551 552 static inline bool 553 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 554 const struct i915_ggtt_view *b) 555 { 556 if (WARN_ON(!a || !b)) 557 return false; 558 559 if (a->type != b->type) 560 return false; 561 if (a->type != I915_GGTT_VIEW_NORMAL) 562 return !memcmp(&a->params, &b->params, sizeof(a->params)); 563 return true; 564 } 565 566 size_t 567 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 568 const struct i915_ggtt_view *view); 569 570 /** 571 * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture 572 * @vma: VMA to iomap 573 * 574 * The passed in VMA has to be pinned in the global GTT mappable region. 575 * An extra pinning of the VMA is acquired for the return iomapping, 576 * the caller must call i915_vma_unpin_iomap to relinquish the pinning 577 * after the iomapping is no longer required. 578 * 579 * Callers must hold the struct_mutex. 580 * 581 * Returns a valid iomapped pointer or ERR_PTR. 582 */ 583 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); 584 #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) 585 586 /** 587 * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap 588 * @vma: VMA to unpin 589 * 590 * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). 591 * 592 * Callers must hold the struct_mutex. This function is only valid to be 593 * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). 594 */ 595 static inline void i915_vma_unpin_iomap(struct i915_vma *vma) 596 { 597 lockdep_assert_held(&vma->vm->dev->struct_mutex); 598 GEM_BUG_ON(vma->pin_count == 0); 599 GEM_BUG_ON(vma->iomap == NULL); 600 vma->pin_count--; 601 } 602 603 #endif 604