1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 struct drm_i915_file_private; 38 39 typedef uint32_t gen6_pte_t; 40 typedef uint64_t gen8_pte_t; 41 typedef uint64_t gen8_pde_t; 42 typedef uint64_t gen8_ppgtt_pdpe_t; 43 typedef uint64_t gen8_ppgtt_pml4e_t; 44 45 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 46 47 48 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 49 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 51 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 52 #define GEN6_PTE_CACHE_LLC (2 << 1) 53 #define GEN6_PTE_UNCACHED (1 << 1) 54 #define GEN6_PTE_VALID (1 << 0) 55 56 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 57 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 58 #define I915_PDES 512 59 #define I915_PDE_MASK (I915_PDES - 1) 60 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 61 62 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 63 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 64 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 65 #define GEN6_PDE_SHIFT 22 66 #define GEN6_PDE_VALID (1 << 0) 67 68 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 69 70 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 71 #define BYT_PTE_WRITEABLE (1 << 1) 72 73 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 74 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 75 */ 76 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 77 (((bits) & 0x8) << (11 - 3))) 78 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 79 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 80 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 81 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 82 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 83 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 84 #define HSW_PTE_UNCACHED (0) 85 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 86 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 87 88 /* GEN8 legacy style address is defined as a 3 level page table: 89 * 31:30 | 29:21 | 20:12 | 11:0 90 * PDPE | PDE | PTE | offset 91 * The difference as compared to normal x86 3 level page table is the PDPEs are 92 * programmed via register. 93 * 94 * GEN8 48b legacy style address is defined as a 4 level page table: 95 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 96 * PML4E | PDPE | PDE | PTE | offset 97 */ 98 #define GEN8_PML4ES_PER_PML4 512 99 #define GEN8_PML4E_SHIFT 39 100 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 101 #define GEN8_PDPE_SHIFT 30 102 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 103 * tables */ 104 #define GEN8_PDPE_MASK 0x1ff 105 #define GEN8_PDE_SHIFT 21 106 #define GEN8_PDE_MASK 0x1ff 107 #define GEN8_PTE_SHIFT 12 108 #define GEN8_PTE_MASK 0x1ff 109 #define GEN8_LEGACY_PDPES 4 110 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 111 112 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 113 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 114 115 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 116 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 117 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 118 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 119 120 #define CHV_PPAT_SNOOP (1<<6) 121 #define GEN8_PPAT_AGE(x) (x<<4) 122 #define GEN8_PPAT_LLCeLLC (3<<2) 123 #define GEN8_PPAT_LLCELLC (2<<2) 124 #define GEN8_PPAT_LLC (1<<2) 125 #define GEN8_PPAT_WB (3<<0) 126 #define GEN8_PPAT_WT (2<<0) 127 #define GEN8_PPAT_WC (1<<0) 128 #define GEN8_PPAT_UC (0<<0) 129 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 130 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 131 132 enum i915_ggtt_view_type { 133 I915_GGTT_VIEW_NORMAL = 0, 134 I915_GGTT_VIEW_ROTATED, 135 I915_GGTT_VIEW_PARTIAL, 136 }; 137 138 struct intel_rotation_info { 139 unsigned int height; 140 unsigned int pitch; 141 unsigned int uv_offset; 142 uint32_t pixel_format; 143 uint64_t fb_modifier; 144 unsigned int width_pages, height_pages; 145 uint64_t size; 146 unsigned int width_pages_uv, height_pages_uv; 147 uint64_t size_uv; 148 }; 149 150 struct i915_ggtt_view { 151 enum i915_ggtt_view_type type; 152 153 union { 154 struct { 155 u64 offset; 156 unsigned int size; 157 } partial; 158 } params; 159 160 struct sg_table *pages; 161 162 union { 163 struct intel_rotation_info rotation_info; 164 }; 165 }; 166 167 extern const struct i915_ggtt_view i915_ggtt_view_normal; 168 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 169 170 enum i915_cache_level; 171 172 /** 173 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 174 * VMA's presence cannot be guaranteed before binding, or after unbinding the 175 * object into/from the address space. 176 * 177 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 178 * will always be <= an objects lifetime. So object refcounting should cover us. 179 */ 180 struct i915_vma { 181 struct drm_mm_node node; 182 struct drm_i915_gem_object *obj; 183 struct i915_address_space *vm; 184 185 /** Flags and address space this VMA is bound to */ 186 #define GLOBAL_BIND (1<<0) 187 #define LOCAL_BIND (1<<1) 188 unsigned int bound : 4; 189 190 /** 191 * Support different GGTT views into the same object. 192 * This means there can be multiple VMA mappings per object and per VM. 193 * i915_ggtt_view_type is used to distinguish between those entries. 194 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 195 * assumed in GEM functions which take no ggtt view parameter. 196 */ 197 struct i915_ggtt_view ggtt_view; 198 199 /** This object's place on the active/inactive lists */ 200 struct list_head mm_list; 201 202 struct list_head vma_link; /* Link in the object's VMA list */ 203 204 /** This vma's place in the batchbuffer or on the eviction list */ 205 struct list_head exec_list; 206 207 /** 208 * Used for performing relocations during execbuffer insertion. 209 */ 210 struct hlist_node exec_node; 211 unsigned long exec_handle; 212 struct drm_i915_gem_exec_object2 *exec_entry; 213 214 /** 215 * How many users have pinned this object in GTT space. The following 216 * users can each hold at most one reference: pwrite/pread, execbuffer 217 * (objects are not allowed multiple times for the same batchbuffer), 218 * and the framebuffer code. When switching/pageflipping, the 219 * framebuffer code has at most two buffers pinned per crtc. 220 * 221 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 222 * bits with absolutely no headroom. So use 4 bits. */ 223 unsigned int pin_count:4; 224 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 225 }; 226 227 struct i915_page_dma { 228 struct page *page; 229 union { 230 dma_addr_t daddr; 231 232 /* For gen6/gen7 only. This is the offset in the GGTT 233 * where the page directory entries for PPGTT begin 234 */ 235 uint32_t ggtt_offset; 236 }; 237 }; 238 239 #define px_base(px) (&(px)->base) 240 #define px_page(px) (px_base(px)->page) 241 #define px_dma(px) (px_base(px)->daddr) 242 243 struct i915_page_scratch { 244 struct i915_page_dma base; 245 }; 246 247 struct i915_page_table { 248 struct i915_page_dma base; 249 250 unsigned long *used_ptes; 251 }; 252 253 struct i915_page_directory { 254 struct i915_page_dma base; 255 256 unsigned long *used_pdes; 257 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 258 }; 259 260 struct i915_page_directory_pointer { 261 struct i915_page_dma base; 262 263 unsigned long *used_pdpes; 264 struct i915_page_directory **page_directory; 265 }; 266 267 struct i915_pml4 { 268 struct i915_page_dma base; 269 270 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 271 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 272 }; 273 274 struct i915_address_space { 275 struct drm_mm mm; 276 struct drm_device *dev; 277 struct list_head global_link; 278 u64 start; /* Start offset always 0 for dri2 */ 279 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 280 281 struct i915_page_scratch *scratch_page; 282 struct i915_page_table *scratch_pt; 283 struct i915_page_directory *scratch_pd; 284 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 285 286 /** 287 * List of objects currently involved in rendering. 288 * 289 * Includes buffers having the contents of their GPU caches 290 * flushed, not necessarily primitives. last_read_req 291 * represents when the rendering involved will be completed. 292 * 293 * A reference is held on the buffer while on this list. 294 */ 295 struct list_head active_list; 296 297 /** 298 * LRU list of objects which are not in the ringbuffer and 299 * are ready to unbind, but are still in the GTT. 300 * 301 * last_read_req is NULL while an object is in this list. 302 * 303 * A reference is not held on the buffer while on this list, 304 * as merely being GTT-bound shouldn't prevent its being 305 * freed, and we'll pull it off the list in the free path. 306 */ 307 struct list_head inactive_list; 308 309 /* FIXME: Need a more generic return type */ 310 gen6_pte_t (*pte_encode)(dma_addr_t addr, 311 enum i915_cache_level level, 312 bool valid, u32 flags); /* Create a valid PTE */ 313 /* flags for pte_encode */ 314 #define PTE_READ_ONLY (1<<0) 315 int (*allocate_va_range)(struct i915_address_space *vm, 316 uint64_t start, 317 uint64_t length); 318 void (*clear_range)(struct i915_address_space *vm, 319 uint64_t start, 320 uint64_t length, 321 bool use_scratch); 322 void (*insert_entries)(struct i915_address_space *vm, 323 struct sg_table *st, 324 uint64_t start, 325 enum i915_cache_level cache_level, u32 flags); 326 void (*cleanup)(struct i915_address_space *vm); 327 /** Unmap an object from an address space. This usually consists of 328 * setting the valid PTE entries to a reserved scratch page. */ 329 void (*unbind_vma)(struct i915_vma *vma); 330 /* Map an object into an address space with the given cache flags. */ 331 int (*bind_vma)(struct i915_vma *vma, 332 enum i915_cache_level cache_level, 333 u32 flags); 334 }; 335 336 /* The Graphics Translation Table is the way in which GEN hardware translates a 337 * Graphics Virtual Address into a Physical Address. In addition to the normal 338 * collateral associated with any va->pa translations GEN hardware also has a 339 * portion of the GTT which can be mapped by the CPU and remain both coherent 340 * and correct (in cases like swizzling). That region is referred to as GMADR in 341 * the spec. 342 */ 343 struct i915_gtt { 344 struct i915_address_space base; 345 346 size_t stolen_size; /* Total size of stolen memory */ 347 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 348 u64 mappable_end; /* End offset that we can CPU map */ 349 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 350 phys_addr_t mappable_base; /* PA of our GMADR */ 351 352 /** "Graphics Stolen Memory" holds the global PTEs */ 353 void __iomem *gsm; 354 355 bool do_idle_maps; 356 357 int mtrr; 358 359 /* global gtt ops */ 360 int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total, 361 size_t *stolen, phys_addr_t *mappable_base, 362 u64 *mappable_end); 363 }; 364 365 struct i915_hw_ppgtt { 366 struct i915_address_space base; 367 struct kref ref; 368 struct drm_mm_node node; 369 unsigned long pd_dirty_rings; 370 union { 371 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 372 struct i915_page_directory_pointer pdp; /* GEN8+ */ 373 struct i915_page_directory pd; /* GEN6-7 */ 374 }; 375 376 struct drm_i915_file_private *file_priv; 377 378 gen6_pte_t __iomem *pd_addr; 379 380 int (*enable)(struct i915_hw_ppgtt *ppgtt); 381 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 382 struct drm_i915_gem_request *req); 383 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 384 }; 385 386 /* For each pde iterates over every pde between from start until start + length. 387 * If start, and start+length are not perfectly divisible, the macro will round 388 * down, and up as needed. The macro modifies pde, start, and length. Dev is 389 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, 390 * and length = 2G effectively iterates over every PDE in the system. 391 * 392 * XXX: temp is not actually needed, but it saves doing the ALIGN operation. 393 */ 394 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ 395 for (iter = gen6_pde_index(start); \ 396 pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 397 iter++, \ 398 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ 399 temp = min_t(unsigned, temp, length), \ 400 start += temp, length -= temp) 401 402 #define gen6_for_all_pdes(pt, ppgtt, iter) \ 403 for (iter = 0; \ 404 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ 405 iter++) 406 407 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 408 { 409 const uint32_t mask = NUM_PTE(pde_shift) - 1; 410 411 return (address >> PAGE_SHIFT) & mask; 412 } 413 414 /* Helper to counts the number of PTEs within the given length. This count 415 * does not cross a page table boundary, so the max value would be 416 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 417 */ 418 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 419 uint32_t pde_shift) 420 { 421 const uint64_t mask = ~((1 << pde_shift) - 1); 422 uint64_t end; 423 424 WARN_ON(length == 0); 425 WARN_ON(offset_in_page(addr|length)); 426 427 end = addr + length; 428 429 if ((addr & mask) != (end & mask)) 430 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 431 432 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 433 } 434 435 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 436 { 437 return (addr >> shift) & I915_PDE_MASK; 438 } 439 440 static inline uint32_t gen6_pte_index(uint32_t addr) 441 { 442 return i915_pte_index(addr, GEN6_PDE_SHIFT); 443 } 444 445 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 446 { 447 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 448 } 449 450 static inline uint32_t gen6_pde_index(uint32_t addr) 451 { 452 return i915_pde_index(addr, GEN6_PDE_SHIFT); 453 } 454 455 /* Equivalent to the gen6 version, For each pde iterates over every pde 456 * between from start until start + length. On gen8+ it simply iterates 457 * over every page directory entry in a page directory. 458 */ 459 #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ 460 for (iter = gen8_pde_index(start); \ 461 pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 462 iter++, \ 463 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ 464 temp = min(temp, length), \ 465 start += temp, length -= temp) 466 467 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ 468 for (iter = gen8_pdpe_index(start); \ 469 pd = (pdp)->page_directory[iter], \ 470 length > 0 && (iter < I915_PDPES_PER_PDP(dev)); \ 471 iter++, \ 472 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ 473 temp = min(temp, length), \ 474 start += temp, length -= temp) 475 476 #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter) \ 477 for (iter = gen8_pml4e_index(start); \ 478 pdp = (pml4)->pdps[iter], \ 479 length > 0 && iter < GEN8_PML4ES_PER_PML4; \ 480 iter++, \ 481 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start, \ 482 temp = min(temp, length), \ 483 start += temp, length -= temp) 484 485 static inline uint32_t gen8_pte_index(uint64_t address) 486 { 487 return i915_pte_index(address, GEN8_PDE_SHIFT); 488 } 489 490 static inline uint32_t gen8_pde_index(uint64_t address) 491 { 492 return i915_pde_index(address, GEN8_PDE_SHIFT); 493 } 494 495 static inline uint32_t gen8_pdpe_index(uint64_t address) 496 { 497 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 498 } 499 500 static inline uint32_t gen8_pml4e_index(uint64_t address) 501 { 502 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 503 } 504 505 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 506 { 507 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 508 } 509 510 static inline dma_addr_t 511 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 512 { 513 return test_bit(n, ppgtt->pdp.used_pdpes) ? 514 px_dma(ppgtt->pdp.page_directory[n]) : 515 px_dma(ppgtt->base.scratch_pd); 516 } 517 518 int i915_gem_gtt_init(struct drm_device *dev); 519 void i915_gem_init_global_gtt(struct drm_device *dev); 520 void i915_global_gtt_cleanup(struct drm_device *dev); 521 522 523 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 524 int i915_ppgtt_init_hw(struct drm_device *dev); 525 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); 526 void i915_ppgtt_release(struct kref *kref); 527 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 528 struct drm_i915_file_private *fpriv); 529 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 530 { 531 if (ppgtt) 532 kref_get(&ppgtt->ref); 533 } 534 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 535 { 536 if (ppgtt) 537 kref_put(&ppgtt->ref, i915_ppgtt_release); 538 } 539 540 void i915_check_and_clear_faults(struct drm_device *dev); 541 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 542 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 543 544 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 545 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 546 547 static inline bool 548 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 549 const struct i915_ggtt_view *b) 550 { 551 if (WARN_ON(!a || !b)) 552 return false; 553 554 if (a->type != b->type) 555 return false; 556 if (a->type == I915_GGTT_VIEW_PARTIAL) 557 return !memcmp(&a->params, &b->params, sizeof(a->params)); 558 return true; 559 } 560 561 size_t 562 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 563 const struct i915_ggtt_view *view); 564 565 #endif 566