1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Please try to maintain the following order within this file unless it makes
24  * sense to do otherwise. From top to bottom:
25  * 1. typedefs
26  * 2. #defines, and macros
27  * 3. structure definitions
28  * 4. function prototypes
29  *
30  * Within each section, please try to order by generation in ascending order,
31  * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
32  */
33 
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
36 
37 #include <linux/io-mapping.h>
38 #include <linux/mm.h>
39 
40 #include "i915_gem_timeline.h"
41 #include "i915_gem_request.h"
42 
43 #define I915_GTT_PAGE_SIZE 4096UL
44 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
45 
46 #define I915_FENCE_REG_NONE -1
47 #define I915_MAX_NUM_FENCES 32
48 /* 32 fences + sign bit for FENCE_REG_NONE */
49 #define I915_MAX_NUM_FENCE_BITS 6
50 
51 struct drm_i915_file_private;
52 struct drm_i915_fence_reg;
53 
54 typedef uint32_t gen6_pte_t;
55 typedef uint64_t gen8_pte_t;
56 typedef uint64_t gen8_pde_t;
57 typedef uint64_t gen8_ppgtt_pdpe_t;
58 typedef uint64_t gen8_ppgtt_pml4e_t;
59 
60 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
61 
62 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
63 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
64 #define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
65 #define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
66 #define GEN6_PTE_CACHE_LLC		(2 << 1)
67 #define GEN6_PTE_UNCACHED		(1 << 1)
68 #define GEN6_PTE_VALID			(1 << 0)
69 
70 #define I915_PTES(pte_len)		(PAGE_SIZE / (pte_len))
71 #define I915_PTE_MASK(pte_len)		(I915_PTES(pte_len) - 1)
72 #define I915_PDES			512
73 #define I915_PDE_MASK			(I915_PDES - 1)
74 #define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))
75 
76 #define GEN6_PTES			I915_PTES(sizeof(gen6_pte_t))
77 #define GEN6_PD_SIZE		        (I915_PDES * PAGE_SIZE)
78 #define GEN6_PD_ALIGN			(PAGE_SIZE * 16)
79 #define GEN6_PDE_SHIFT			22
80 #define GEN6_PDE_VALID			(1 << 0)
81 
82 #define GEN7_PTE_CACHE_L3_LLC		(3 << 1)
83 
84 #define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
85 #define BYT_PTE_WRITEABLE		(1 << 1)
86 
87 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
88  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
89  */
90 #define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
91 					 (((bits) & 0x8) << (11 - 3)))
92 #define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
93 #define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
94 #define HSW_WB_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x8)
95 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
96 #define HSW_WT_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x7)
97 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
98 #define HSW_PTE_UNCACHED		(0)
99 #define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
100 #define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)
101 
102 /* GEN8 legacy style address is defined as a 3 level page table:
103  * 31:30 | 29:21 | 20:12 |  11:0
104  * PDPE  |  PDE  |  PTE  | offset
105  * The difference as compared to normal x86 3 level page table is the PDPEs are
106  * programmed via register.
107  *
108  * GEN8 48b legacy style address is defined as a 4 level page table:
109  * 47:39 | 38:30 | 29:21 | 20:12 |  11:0
110  * PML4E | PDPE  |  PDE  |  PTE  | offset
111  */
112 #define GEN8_PML4ES_PER_PML4		512
113 #define GEN8_PML4E_SHIFT		39
114 #define GEN8_PML4E_MASK			(GEN8_PML4ES_PER_PML4 - 1)
115 #define GEN8_PDPE_SHIFT			30
116 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
117  * tables */
118 #define GEN8_PDPE_MASK			0x1ff
119 #define GEN8_PDE_SHIFT			21
120 #define GEN8_PDE_MASK			0x1ff
121 #define GEN8_PTE_SHIFT			12
122 #define GEN8_PTE_MASK			0x1ff
123 #define GEN8_LEGACY_PDPES		4
124 #define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))
125 
126 #define I915_PDPES_PER_PDP(dev_priv)	(USES_FULL_48BIT_PPGTT(dev_priv) ?\
127 					GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
128 
129 #define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
130 #define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
131 #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
132 #define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
133 
134 #define CHV_PPAT_SNOOP			(1<<6)
135 #define GEN8_PPAT_AGE(x)		(x<<4)
136 #define GEN8_PPAT_LLCeLLC		(3<<2)
137 #define GEN8_PPAT_LLCELLC		(2<<2)
138 #define GEN8_PPAT_LLC			(1<<2)
139 #define GEN8_PPAT_WB			(3<<0)
140 #define GEN8_PPAT_WT			(2<<0)
141 #define GEN8_PPAT_WC			(1<<0)
142 #define GEN8_PPAT_UC			(0<<0)
143 #define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
144 #define GEN8_PPAT(i, x)			((uint64_t) (x) << ((i) * 8))
145 
146 struct sg_table;
147 
148 struct intel_rotation_info {
149 	struct intel_rotation_plane_info {
150 		/* tiles */
151 		unsigned int width, height, stride, offset;
152 	} plane[2];
153 } __packed;
154 
155 static inline void assert_intel_rotation_info_is_packed(void)
156 {
157 	BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
158 }
159 
160 struct intel_partial_info {
161 	u64 offset;
162 	unsigned int size;
163 } __packed;
164 
165 static inline void assert_intel_partial_info_is_packed(void)
166 {
167 	BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
168 }
169 
170 enum i915_ggtt_view_type {
171 	I915_GGTT_VIEW_NORMAL = 0,
172 	I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
173 	I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
174 };
175 
176 static inline void assert_i915_ggtt_view_type_is_unique(void)
177 {
178 	/* As we encode the size of each branch inside the union into its type,
179 	 * we have to be careful that each branch has a unique size.
180 	 */
181 	switch ((enum i915_ggtt_view_type)0) {
182 	case I915_GGTT_VIEW_NORMAL:
183 	case I915_GGTT_VIEW_PARTIAL:
184 	case I915_GGTT_VIEW_ROTATED:
185 		/* gcc complains if these are identical cases */
186 		break;
187 	}
188 }
189 
190 struct i915_ggtt_view {
191 	enum i915_ggtt_view_type type;
192 	union {
193 		/* Members need to contain no holes/padding */
194 		struct intel_partial_info partial;
195 		struct intel_rotation_info rotated;
196 	};
197 };
198 
199 enum i915_cache_level;
200 
201 struct i915_vma;
202 
203 struct i915_page_dma {
204 	struct page *page;
205 	union {
206 		dma_addr_t daddr;
207 
208 		/* For gen6/gen7 only. This is the offset in the GGTT
209 		 * where the page directory entries for PPGTT begin
210 		 */
211 		uint32_t ggtt_offset;
212 	};
213 };
214 
215 #define px_base(px) (&(px)->base)
216 #define px_page(px) (px_base(px)->page)
217 #define px_dma(px) (px_base(px)->daddr)
218 
219 struct i915_page_table {
220 	struct i915_page_dma base;
221 
222 	unsigned long *used_ptes;
223 };
224 
225 struct i915_page_directory {
226 	struct i915_page_dma base;
227 
228 	unsigned long *used_pdes;
229 	struct i915_page_table *page_table[I915_PDES]; /* PDEs */
230 };
231 
232 struct i915_page_directory_pointer {
233 	struct i915_page_dma base;
234 
235 	unsigned long *used_pdpes;
236 	struct i915_page_directory **page_directory;
237 };
238 
239 struct i915_pml4 {
240 	struct i915_page_dma base;
241 
242 	DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
243 	struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
244 };
245 
246 struct i915_address_space {
247 	struct drm_mm mm;
248 	struct i915_gem_timeline timeline;
249 	struct drm_i915_private *i915;
250 	/* Every address space belongs to a struct file - except for the global
251 	 * GTT that is owned by the driver (and so @file is set to NULL). In
252 	 * principle, no information should leak from one context to another
253 	 * (or between files/processes etc) unless explicitly shared by the
254 	 * owner. Tracking the owner is important in order to free up per-file
255 	 * objects along with the file, to aide resource tracking, and to
256 	 * assign blame.
257 	 */
258 	struct drm_i915_file_private *file;
259 	struct list_head global_link;
260 	u64 start;		/* Start offset always 0 for dri2 */
261 	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */
262 
263 	bool closed;
264 
265 	struct i915_page_dma scratch_page;
266 	struct i915_page_table *scratch_pt;
267 	struct i915_page_directory *scratch_pd;
268 	struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
269 
270 	/**
271 	 * List of objects currently involved in rendering.
272 	 *
273 	 * Includes buffers having the contents of their GPU caches
274 	 * flushed, not necessarily primitives. last_read_req
275 	 * represents when the rendering involved will be completed.
276 	 *
277 	 * A reference is held on the buffer while on this list.
278 	 */
279 	struct list_head active_list;
280 
281 	/**
282 	 * LRU list of objects which are not in the ringbuffer and
283 	 * are ready to unbind, but are still in the GTT.
284 	 *
285 	 * last_read_req is NULL while an object is in this list.
286 	 *
287 	 * A reference is not held on the buffer while on this list,
288 	 * as merely being GTT-bound shouldn't prevent its being
289 	 * freed, and we'll pull it off the list in the free path.
290 	 */
291 	struct list_head inactive_list;
292 
293 	/**
294 	 * List of vma that have been unbound.
295 	 *
296 	 * A reference is not held on the buffer while on this list.
297 	 */
298 	struct list_head unbound_list;
299 
300 	/* FIXME: Need a more generic return type */
301 	gen6_pte_t (*pte_encode)(dma_addr_t addr,
302 				 enum i915_cache_level level,
303 				 u32 flags); /* Create a valid PTE */
304 	/* flags for pte_encode */
305 #define PTE_READ_ONLY	(1<<0)
306 	int (*allocate_va_range)(struct i915_address_space *vm,
307 				 uint64_t start,
308 				 uint64_t length);
309 	void (*clear_range)(struct i915_address_space *vm,
310 			    uint64_t start,
311 			    uint64_t length);
312 	void (*insert_page)(struct i915_address_space *vm,
313 			    dma_addr_t addr,
314 			    uint64_t offset,
315 			    enum i915_cache_level cache_level,
316 			    u32 flags);
317 	void (*insert_entries)(struct i915_address_space *vm,
318 			       struct sg_table *st,
319 			       uint64_t start,
320 			       enum i915_cache_level cache_level, u32 flags);
321 	void (*cleanup)(struct i915_address_space *vm);
322 	/** Unmap an object from an address space. This usually consists of
323 	 * setting the valid PTE entries to a reserved scratch page. */
324 	void (*unbind_vma)(struct i915_vma *vma);
325 	/* Map an object into an address space with the given cache flags. */
326 	int (*bind_vma)(struct i915_vma *vma,
327 			enum i915_cache_level cache_level,
328 			u32 flags);
329 };
330 
331 #define i915_is_ggtt(V) (!(V)->file)
332 
333 /* The Graphics Translation Table is the way in which GEN hardware translates a
334  * Graphics Virtual Address into a Physical Address. In addition to the normal
335  * collateral associated with any va->pa translations GEN hardware also has a
336  * portion of the GTT which can be mapped by the CPU and remain both coherent
337  * and correct (in cases like swizzling). That region is referred to as GMADR in
338  * the spec.
339  */
340 struct i915_ggtt {
341 	struct i915_address_space base;
342 	struct io_mapping mappable;	/* Mapping to our CPU mappable region */
343 
344 	phys_addr_t mappable_base;	/* PA of our GMADR */
345 	u64 mappable_end;		/* End offset that we can CPU map */
346 
347 	/* Stolen memory is segmented in hardware with different portions
348 	 * offlimits to certain functions.
349 	 *
350 	 * The drm_mm is initialised to the total accessible range, as found
351 	 * from the PCI config. On Broadwell+, this is further restricted to
352 	 * avoid the first page! The upper end of stolen memory is reserved for
353 	 * hardware functions and similarly removed from the accessible range.
354 	 */
355 	u32 stolen_size;		/* Total size of stolen memory */
356 	u32 stolen_usable_size;	/* Total size minus reserved ranges */
357 	u32 stolen_reserved_base;
358 	u32 stolen_reserved_size;
359 
360 	/** "Graphics Stolen Memory" holds the global PTEs */
361 	void __iomem *gsm;
362 	void (*invalidate)(struct drm_i915_private *dev_priv);
363 
364 	bool do_idle_maps;
365 
366 	int mtrr;
367 
368 	struct drm_mm_node error_capture;
369 };
370 
371 struct i915_hw_ppgtt {
372 	struct i915_address_space base;
373 	struct kref ref;
374 	struct drm_mm_node node;
375 	unsigned long pd_dirty_rings;
376 	union {
377 		struct i915_pml4 pml4;		/* GEN8+ & 48b PPGTT */
378 		struct i915_page_directory_pointer pdp;	/* GEN8+ */
379 		struct i915_page_directory pd;		/* GEN6-7 */
380 	};
381 
382 	gen6_pte_t __iomem *pd_addr;
383 
384 	int (*enable)(struct i915_hw_ppgtt *ppgtt);
385 	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
386 			 struct drm_i915_gem_request *req);
387 	void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
388 };
389 
390 /*
391  * gen6_for_each_pde() iterates over every pde from start until start+length.
392  * If start and start+length are not perfectly divisible, the macro will round
393  * down and up as needed. Start=0 and length=2G effectively iterates over
394  * every PDE in the system. The macro modifies ALL its parameters except 'pd',
395  * so each of the other parameters should preferably be a simple variable, or
396  * at most an lvalue with no side-effects!
397  */
398 #define gen6_for_each_pde(pt, pd, start, length, iter)			\
399 	for (iter = gen6_pde_index(start);				\
400 	     length > 0 && iter < I915_PDES &&				\
401 		(pt = (pd)->page_table[iter], true);			\
402 	     ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT);		\
403 		    temp = min(temp - start, length);			\
404 		    start += temp, length -= temp; }), ++iter)
405 
406 #define gen6_for_all_pdes(pt, pd, iter)					\
407 	for (iter = 0;							\
408 	     iter < I915_PDES &&					\
409 		(pt = (pd)->page_table[iter], true);			\
410 	     ++iter)
411 
412 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
413 {
414 	const uint32_t mask = NUM_PTE(pde_shift) - 1;
415 
416 	return (address >> PAGE_SHIFT) & mask;
417 }
418 
419 /* Helper to counts the number of PTEs within the given length. This count
420  * does not cross a page table boundary, so the max value would be
421  * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
422 */
423 static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
424 				      uint32_t pde_shift)
425 {
426 	const uint64_t mask = ~((1ULL << pde_shift) - 1);
427 	uint64_t end;
428 
429 	WARN_ON(length == 0);
430 	WARN_ON(offset_in_page(addr|length));
431 
432 	end = addr + length;
433 
434 	if ((addr & mask) != (end & mask))
435 		return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
436 
437 	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
438 }
439 
440 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
441 {
442 	return (addr >> shift) & I915_PDE_MASK;
443 }
444 
445 static inline uint32_t gen6_pte_index(uint32_t addr)
446 {
447 	return i915_pte_index(addr, GEN6_PDE_SHIFT);
448 }
449 
450 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
451 {
452 	return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
453 }
454 
455 static inline uint32_t gen6_pde_index(uint32_t addr)
456 {
457 	return i915_pde_index(addr, GEN6_PDE_SHIFT);
458 }
459 
460 /* Equivalent to the gen6 version, For each pde iterates over every pde
461  * between from start until start + length. On gen8+ it simply iterates
462  * over every page directory entry in a page directory.
463  */
464 #define gen8_for_each_pde(pt, pd, start, length, iter)			\
465 	for (iter = gen8_pde_index(start);				\
466 	     length > 0 && iter < I915_PDES &&				\
467 		(pt = (pd)->page_table[iter], true);			\
468 	     ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT);		\
469 		    temp = min(temp - start, length);			\
470 		    start += temp, length -= temp; }), ++iter)
471 
472 #define gen8_for_each_pdpe(pd, pdp, start, length, iter)		\
473 	for (iter = gen8_pdpe_index(start);				\
474 	     length > 0 && iter < I915_PDPES_PER_PDP(dev) &&		\
475 		(pd = (pdp)->page_directory[iter], true);		\
476 	     ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT);	\
477 		    temp = min(temp - start, length);			\
478 		    start += temp, length -= temp; }), ++iter)
479 
480 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter)		\
481 	for (iter = gen8_pml4e_index(start);				\
482 	     length > 0 && iter < GEN8_PML4ES_PER_PML4 &&		\
483 		(pdp = (pml4)->pdps[iter], true);			\
484 	     ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT);	\
485 		    temp = min(temp - start, length);			\
486 		    start += temp, length -= temp; }), ++iter)
487 
488 static inline uint32_t gen8_pte_index(uint64_t address)
489 {
490 	return i915_pte_index(address, GEN8_PDE_SHIFT);
491 }
492 
493 static inline uint32_t gen8_pde_index(uint64_t address)
494 {
495 	return i915_pde_index(address, GEN8_PDE_SHIFT);
496 }
497 
498 static inline uint32_t gen8_pdpe_index(uint64_t address)
499 {
500 	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
501 }
502 
503 static inline uint32_t gen8_pml4e_index(uint64_t address)
504 {
505 	return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
506 }
507 
508 static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
509 {
510 	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
511 }
512 
513 static inline dma_addr_t
514 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
515 {
516 	return test_bit(n, ppgtt->pdp.used_pdpes) ?
517 		px_dma(ppgtt->pdp.page_directory[n]) :
518 		px_dma(ppgtt->base.scratch_pd);
519 }
520 
521 static inline struct i915_ggtt *
522 i915_vm_to_ggtt(struct i915_address_space *vm)
523 {
524 	GEM_BUG_ON(!i915_is_ggtt(vm));
525 	return container_of(vm, struct i915_ggtt, base);
526 }
527 
528 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
529 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
530 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
531 void i915_ggtt_enable_guc(struct drm_i915_private *i915);
532 void i915_ggtt_disable_guc(struct drm_i915_private *i915);
533 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
534 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
535 
536 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
537 void i915_ppgtt_release(struct kref *kref);
538 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
539 					struct drm_i915_file_private *fpriv,
540 					const char *name);
541 void i915_ppgtt_close(struct i915_address_space *vm);
542 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
543 {
544 	if (ppgtt)
545 		kref_get(&ppgtt->ref);
546 }
547 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
548 {
549 	if (ppgtt)
550 		kref_put(&ppgtt->ref, i915_ppgtt_release);
551 }
552 
553 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
554 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
555 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
556 
557 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
558 					    struct sg_table *pages);
559 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
560 			       struct sg_table *pages);
561 
562 int i915_gem_gtt_reserve(struct i915_address_space *vm,
563 			 struct drm_mm_node *node,
564 			 u64 size, u64 offset, unsigned long color,
565 			 unsigned int flags);
566 
567 int i915_gem_gtt_insert(struct i915_address_space *vm,
568 			struct drm_mm_node *node,
569 			u64 size, u64 alignment, unsigned long color,
570 			u64 start, u64 end, unsigned int flags);
571 
572 /* Flags used by pin/bind&friends. */
573 #define PIN_NONBLOCK		BIT(0)
574 #define PIN_MAPPABLE		BIT(1)
575 #define PIN_ZONE_4G		BIT(2)
576 #define PIN_NONFAULT		BIT(3)
577 
578 #define PIN_MBZ			BIT(5) /* I915_VMA_PIN_OVERFLOW */
579 #define PIN_GLOBAL		BIT(6) /* I915_VMA_GLOBAL_BIND */
580 #define PIN_USER		BIT(7) /* I915_VMA_LOCAL_BIND */
581 #define PIN_UPDATE		BIT(8)
582 
583 #define PIN_HIGH		BIT(9)
584 #define PIN_OFFSET_BIAS		BIT(10)
585 #define PIN_OFFSET_FIXED	BIT(11)
586 #define PIN_OFFSET_MASK		(-I915_GTT_PAGE_SIZE)
587 
588 #endif
589