1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 typedef uint32_t gen6_gtt_pte_t; 38 typedef uint64_t gen8_gtt_pte_t; 39 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; 40 41 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 42 43 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) 44 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 45 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 46 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 47 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 48 #define GEN6_PTE_CACHE_LLC (2 << 1) 49 #define GEN6_PTE_UNCACHED (1 << 1) 50 #define GEN6_PTE_VALID (1 << 0) 51 52 #define GEN6_PPGTT_PD_ENTRIES 512 53 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) 54 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 55 #define GEN6_PDE_VALID (1 << 0) 56 57 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 58 59 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 60 #define BYT_PTE_WRITEABLE (1 << 1) 61 62 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 63 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 64 */ 65 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 66 (((bits) & 0x8) << (11 - 3))) 67 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 68 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 69 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 70 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 71 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 72 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 73 #define HSW_PTE_UNCACHED (0) 74 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 75 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 76 77 /* GEN8 legacy style address is defined as a 3 level page table: 78 * 31:30 | 29:21 | 20:12 | 11:0 79 * PDPE | PDE | PTE | offset 80 * The difference as compared to normal x86 3 level page table is the PDPEs are 81 * programmed via register. 82 */ 83 #define GEN8_PDPE_SHIFT 30 84 #define GEN8_PDPE_MASK 0x3 85 #define GEN8_PDE_SHIFT 21 86 #define GEN8_PDE_MASK 0x1ff 87 #define GEN8_PTE_SHIFT 12 88 #define GEN8_PTE_MASK 0x1ff 89 #define GEN8_LEGACY_PDPS 4 90 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) 91 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) 92 93 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 94 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 95 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 96 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 97 98 #define CHV_PPAT_SNOOP (1<<6) 99 #define GEN8_PPAT_AGE(x) (x<<4) 100 #define GEN8_PPAT_LLCeLLC (3<<2) 101 #define GEN8_PPAT_LLCELLC (2<<2) 102 #define GEN8_PPAT_LLC (1<<2) 103 #define GEN8_PPAT_WB (3<<0) 104 #define GEN8_PPAT_WT (2<<0) 105 #define GEN8_PPAT_WC (1<<0) 106 #define GEN8_PPAT_UC (0<<0) 107 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 108 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 109 110 enum i915_cache_level; 111 /** 112 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 113 * VMA's presence cannot be guaranteed before binding, or after unbinding the 114 * object into/from the address space. 115 * 116 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 117 * will always be <= an objects lifetime. So object refcounting should cover us. 118 */ 119 struct i915_vma { 120 struct drm_mm_node node; 121 struct drm_i915_gem_object *obj; 122 struct i915_address_space *vm; 123 124 /** This object's place on the active/inactive lists */ 125 struct list_head mm_list; 126 127 struct list_head vma_link; /* Link in the object's VMA list */ 128 129 /** This vma's place in the batchbuffer or on the eviction list */ 130 struct list_head exec_list; 131 132 /** 133 * Used for performing relocations during execbuffer insertion. 134 */ 135 struct hlist_node exec_node; 136 unsigned long exec_handle; 137 struct drm_i915_gem_exec_object2 *exec_entry; 138 139 /** 140 * How many users have pinned this object in GTT space. The following 141 * users can each hold at most one reference: pwrite/pread, pin_ioctl 142 * (via user_pin_count), execbuffer (objects are not allowed multiple 143 * times for the same batchbuffer), and the framebuffer code. When 144 * switching/pageflipping, the framebuffer code has at most two buffers 145 * pinned per crtc. 146 * 147 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 148 * bits with absolutely no headroom. So use 4 bits. */ 149 unsigned int pin_count:4; 150 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 151 152 /** Unmap an object from an address space. This usually consists of 153 * setting the valid PTE entries to a reserved scratch page. */ 154 void (*unbind_vma)(struct i915_vma *vma); 155 /* Map an object into an address space with the given cache flags. */ 156 #define GLOBAL_BIND (1<<0) 157 #define PTE_READ_ONLY (1<<1) 158 void (*bind_vma)(struct i915_vma *vma, 159 enum i915_cache_level cache_level, 160 u32 flags); 161 }; 162 163 struct i915_address_space { 164 struct drm_mm mm; 165 struct drm_device *dev; 166 struct list_head global_link; 167 unsigned long start; /* Start offset always 0 for dri2 */ 168 size_t total; /* size addr space maps (ex. 2GB for ggtt) */ 169 170 struct { 171 dma_addr_t addr; 172 struct page *page; 173 } scratch; 174 175 /** 176 * List of objects currently involved in rendering. 177 * 178 * Includes buffers having the contents of their GPU caches 179 * flushed, not necessarily primitives. last_rendering_seqno 180 * represents when the rendering involved will be completed. 181 * 182 * A reference is held on the buffer while on this list. 183 */ 184 struct list_head active_list; 185 186 /** 187 * LRU list of objects which are not in the ringbuffer and 188 * are ready to unbind, but are still in the GTT. 189 * 190 * last_rendering_seqno is 0 while an object is in this list. 191 * 192 * A reference is not held on the buffer while on this list, 193 * as merely being GTT-bound shouldn't prevent its being 194 * freed, and we'll pull it off the list in the free path. 195 */ 196 struct list_head inactive_list; 197 198 /* FIXME: Need a more generic return type */ 199 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 200 enum i915_cache_level level, 201 bool valid, u32 flags); /* Create a valid PTE */ 202 void (*clear_range)(struct i915_address_space *vm, 203 uint64_t start, 204 uint64_t length, 205 bool use_scratch); 206 void (*insert_entries)(struct i915_address_space *vm, 207 struct sg_table *st, 208 uint64_t start, 209 enum i915_cache_level cache_level, u32 flags); 210 void (*cleanup)(struct i915_address_space *vm); 211 }; 212 213 /* The Graphics Translation Table is the way in which GEN hardware translates a 214 * Graphics Virtual Address into a Physical Address. In addition to the normal 215 * collateral associated with any va->pa translations GEN hardware also has a 216 * portion of the GTT which can be mapped by the CPU and remain both coherent 217 * and correct (in cases like swizzling). That region is referred to as GMADR in 218 * the spec. 219 */ 220 struct i915_gtt { 221 struct i915_address_space base; 222 size_t stolen_size; /* Total size of stolen memory */ 223 224 unsigned long mappable_end; /* End offset that we can CPU map */ 225 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 226 phys_addr_t mappable_base; /* PA of our GMADR */ 227 228 /** "Graphics Stolen Memory" holds the global PTEs */ 229 void __iomem *gsm; 230 231 bool do_idle_maps; 232 233 int mtrr; 234 235 /* global gtt ops */ 236 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 237 size_t *stolen, phys_addr_t *mappable_base, 238 unsigned long *mappable_end); 239 }; 240 241 struct i915_hw_ppgtt { 242 struct i915_address_space base; 243 struct kref ref; 244 struct drm_mm_node node; 245 unsigned num_pd_entries; 246 unsigned num_pd_pages; /* gen8+ */ 247 union { 248 struct page **pt_pages; 249 struct page **gen8_pt_pages[GEN8_LEGACY_PDPS]; 250 }; 251 struct page *pd_pages; 252 union { 253 uint32_t pd_offset; 254 dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS]; 255 }; 256 union { 257 dma_addr_t *pt_dma_addr; 258 dma_addr_t *gen8_pt_dma_addr[4]; 259 }; 260 261 struct intel_context *ctx; 262 263 int (*enable)(struct i915_hw_ppgtt *ppgtt); 264 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 265 struct intel_engine_cs *ring, 266 bool synchronous); 267 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 268 }; 269 270 int i915_gem_gtt_init(struct drm_device *dev); 271 void i915_gem_init_global_gtt(struct drm_device *dev); 272 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 273 unsigned long mappable_end, unsigned long end); 274 275 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 276 277 void i915_check_and_clear_faults(struct drm_device *dev); 278 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 279 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 280 281 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 282 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 283 284 #endif 285