1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 #include <linux/kref.h> 39 #include <linux/mm.h> 40 #include <linux/pagevec.h> 41 #include <linux/workqueue.h> 42 43 #include <drm/drm_mm.h> 44 45 #include "gt/intel_reset.h" 46 #include "i915_gem_fence_reg.h" 47 #include "i915_request.h" 48 #include "i915_scatterlist.h" 49 #include "i915_selftest.h" 50 #include "gt/intel_timeline.h" 51 52 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 53 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 54 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 55 56 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 57 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 58 59 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 60 61 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 62 63 #define I915_FENCE_REG_NONE -1 64 #define I915_MAX_NUM_FENCES 32 65 /* 32 fences + sign bit for FENCE_REG_NONE */ 66 #define I915_MAX_NUM_FENCE_BITS 6 67 68 struct drm_i915_file_private; 69 struct drm_i915_gem_object; 70 struct i915_vma; 71 struct intel_gt; 72 73 typedef u32 gen6_pte_t; 74 typedef u64 gen8_pte_t; 75 76 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 77 78 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 79 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 80 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 81 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 82 #define GEN6_PTE_CACHE_LLC (2 << 1) 83 #define GEN6_PTE_UNCACHED (1 << 1) 84 #define GEN6_PTE_VALID (1 << 0) 85 86 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 87 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 88 #define I915_PDES 512 89 #define I915_PDE_MASK (I915_PDES - 1) 90 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 91 92 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 93 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 94 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 95 #define GEN6_PDE_SHIFT 22 96 #define GEN6_PDE_VALID (1 << 0) 97 98 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 99 100 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 101 #define BYT_PTE_WRITEABLE (1 << 1) 102 103 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 104 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 105 */ 106 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 107 (((bits) & 0x8) << (11 - 3))) 108 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 109 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 110 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 111 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 112 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 113 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 114 #define HSW_PTE_UNCACHED (0) 115 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 116 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 117 118 /* GEN8 32b style address is defined as a 3 level page table: 119 * 31:30 | 29:21 | 20:12 | 11:0 120 * PDPE | PDE | PTE | offset 121 * The difference as compared to normal x86 3 level page table is the PDPEs are 122 * programmed via register. 123 */ 124 #define GEN8_3LVL_PDPES 4 125 #define GEN8_PDE_SHIFT 21 126 #define GEN8_PDE_MASK 0x1ff 127 #define GEN8_PTE_MASK 0x1ff 128 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 129 130 /* GEN8 48b style address is defined as a 4 level page table: 131 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 132 * PML4E | PDPE | PDE | PTE | offset 133 */ 134 #define GEN8_PML4ES_PER_PML4 512 135 #define GEN8_PML4E_SHIFT 39 136 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 137 #define GEN8_PDPE_SHIFT 30 138 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 139 * tables */ 140 #define GEN8_PDPE_MASK 0x1ff 141 142 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 143 #define PPAT_CACHED_PDE 0 /* WB LLC */ 144 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 145 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 146 147 #define CHV_PPAT_SNOOP (1<<6) 148 #define GEN8_PPAT_AGE(x) ((x)<<4) 149 #define GEN8_PPAT_LLCeLLC (3<<2) 150 #define GEN8_PPAT_LLCELLC (2<<2) 151 #define GEN8_PPAT_LLC (1<<2) 152 #define GEN8_PPAT_WB (3<<0) 153 #define GEN8_PPAT_WT (2<<0) 154 #define GEN8_PPAT_WC (1<<0) 155 #define GEN8_PPAT_UC (0<<0) 156 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 157 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 158 159 #define GEN8_PDE_IPS_64K BIT(11) 160 #define GEN8_PDE_PS_2M BIT(7) 161 162 #define for_each_sgt_dma(__dmap, __iter, __sgt) \ 163 __for_each_sgt_dma(__dmap, __iter, __sgt, I915_GTT_PAGE_SIZE) 164 165 struct intel_remapped_plane_info { 166 /* in gtt pages */ 167 unsigned int width, height, stride, offset; 168 } __packed; 169 170 struct intel_remapped_info { 171 struct intel_remapped_plane_info plane[2]; 172 unsigned int unused_mbz; 173 } __packed; 174 175 struct intel_rotation_info { 176 struct intel_remapped_plane_info plane[2]; 177 } __packed; 178 179 struct intel_partial_info { 180 u64 offset; 181 unsigned int size; 182 } __packed; 183 184 enum i915_ggtt_view_type { 185 I915_GGTT_VIEW_NORMAL = 0, 186 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 187 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 188 I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info), 189 }; 190 191 static inline void assert_i915_gem_gtt_types(void) 192 { 193 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 194 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 195 BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int)); 196 197 /* Check that rotation/remapped shares offsets for simplicity */ 198 BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) != 199 offsetof(struct intel_rotation_info, plane[0])); 200 BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) != 201 offsetofend(struct intel_rotation_info, plane[1])); 202 203 /* As we encode the size of each branch inside the union into its type, 204 * we have to be careful that each branch has a unique size. 205 */ 206 switch ((enum i915_ggtt_view_type)0) { 207 case I915_GGTT_VIEW_NORMAL: 208 case I915_GGTT_VIEW_PARTIAL: 209 case I915_GGTT_VIEW_ROTATED: 210 case I915_GGTT_VIEW_REMAPPED: 211 /* gcc complains if these are identical cases */ 212 break; 213 } 214 } 215 216 struct i915_ggtt_view { 217 enum i915_ggtt_view_type type; 218 union { 219 /* Members need to contain no holes/padding */ 220 struct intel_partial_info partial; 221 struct intel_rotation_info rotated; 222 struct intel_remapped_info remapped; 223 }; 224 }; 225 226 enum i915_cache_level; 227 228 struct i915_vma; 229 230 struct i915_page_dma { 231 struct page *page; 232 union { 233 dma_addr_t daddr; 234 235 /* For gen6/gen7 only. This is the offset in the GGTT 236 * where the page directory entries for PPGTT begin 237 */ 238 u32 ggtt_offset; 239 }; 240 }; 241 242 struct i915_page_table { 243 struct i915_page_dma base; 244 atomic_t used; 245 }; 246 247 struct i915_page_directory { 248 struct i915_page_table pt; 249 spinlock_t lock; 250 void *entry[512]; 251 }; 252 253 #define __px_choose_expr(x, type, expr, other) \ 254 __builtin_choose_expr( \ 255 __builtin_types_compatible_p(typeof(x), type) || \ 256 __builtin_types_compatible_p(typeof(x), const type), \ 257 ({ type __x = (type)(x); expr; }), \ 258 other) 259 260 #define px_base(px) \ 261 __px_choose_expr(px, struct i915_page_dma *, __x, \ 262 __px_choose_expr(px, struct i915_page_table *, &__x->base, \ 263 __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \ 264 (void)0))) 265 #define px_dma(px) (px_base(px)->daddr) 266 267 #define px_pt(px) \ 268 __px_choose_expr(px, struct i915_page_table *, __x, \ 269 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 270 (void)0)) 271 #define px_used(px) (&px_pt(px)->used) 272 273 struct i915_vma_ops { 274 /* Map an object into an address space with the given cache flags. */ 275 int (*bind_vma)(struct i915_vma *vma, 276 enum i915_cache_level cache_level, 277 u32 flags); 278 /* 279 * Unmap an object from an address space. This usually consists of 280 * setting the valid PTE entries to a reserved scratch page. 281 */ 282 void (*unbind_vma)(struct i915_vma *vma); 283 284 int (*set_pages)(struct i915_vma *vma); 285 void (*clear_pages)(struct i915_vma *vma); 286 }; 287 288 struct pagestash { 289 spinlock_t lock; 290 struct pagevec pvec; 291 }; 292 293 struct i915_address_space { 294 struct kref ref; 295 struct rcu_work rcu; 296 297 struct drm_mm mm; 298 struct intel_gt *gt; 299 struct drm_i915_private *i915; 300 struct device *dma; 301 /* Every address space belongs to a struct file - except for the global 302 * GTT that is owned by the driver (and so @file is set to NULL). In 303 * principle, no information should leak from one context to another 304 * (or between files/processes etc) unless explicitly shared by the 305 * owner. Tracking the owner is important in order to free up per-file 306 * objects along with the file, to aide resource tracking, and to 307 * assign blame. 308 */ 309 struct drm_i915_file_private *file; 310 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 311 u64 reserved; /* size addr space reserved */ 312 313 bool closed; 314 315 struct mutex mutex; /* protects vma and our lists */ 316 #define VM_CLASS_GGTT 0 317 #define VM_CLASS_PPGTT 1 318 319 u64 scratch_pte; 320 int scratch_order; 321 struct i915_page_dma scratch_page; 322 struct i915_page_dma scratch_pt; 323 struct i915_page_dma scratch_pd; 324 struct i915_page_dma scratch_pdp; /* GEN8+ & 48b PPGTT */ 325 unsigned int top; 326 327 /** 328 * List of vma currently bound. 329 */ 330 struct list_head bound_list; 331 332 /** 333 * List of vma that are not unbound. 334 */ 335 struct list_head unbound_list; 336 337 struct pagestash free_pages; 338 339 /* Global GTT */ 340 bool is_ggtt:1; 341 342 /* Some systems require uncached updates of the page directories */ 343 bool pt_kmap_wc:1; 344 345 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 346 bool has_read_only:1; 347 348 u64 (*pte_encode)(dma_addr_t addr, 349 enum i915_cache_level level, 350 u32 flags); /* Create a valid PTE */ 351 #define PTE_READ_ONLY (1<<0) 352 353 int (*allocate_va_range)(struct i915_address_space *vm, 354 u64 start, u64 length); 355 void (*clear_range)(struct i915_address_space *vm, 356 u64 start, u64 length); 357 void (*insert_page)(struct i915_address_space *vm, 358 dma_addr_t addr, 359 u64 offset, 360 enum i915_cache_level cache_level, 361 u32 flags); 362 void (*insert_entries)(struct i915_address_space *vm, 363 struct i915_vma *vma, 364 enum i915_cache_level cache_level, 365 u32 flags); 366 void (*cleanup)(struct i915_address_space *vm); 367 368 struct i915_vma_ops vma_ops; 369 370 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 371 I915_SELFTEST_DECLARE(bool scrub_64K); 372 }; 373 374 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 375 376 static inline bool 377 i915_vm_is_4lvl(const struct i915_address_space *vm) 378 { 379 return (vm->total - 1) >> 32; 380 } 381 382 static inline bool 383 i915_vm_has_scratch_64K(struct i915_address_space *vm) 384 { 385 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 386 } 387 388 /* The Graphics Translation Table is the way in which GEN hardware translates a 389 * Graphics Virtual Address into a Physical Address. In addition to the normal 390 * collateral associated with any va->pa translations GEN hardware also has a 391 * portion of the GTT which can be mapped by the CPU and remain both coherent 392 * and correct (in cases like swizzling). That region is referred to as GMADR in 393 * the spec. 394 */ 395 struct i915_ggtt { 396 struct i915_address_space vm; 397 398 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 399 struct resource gmadr; /* GMADR resource */ 400 resource_size_t mappable_end; /* End offset that we can CPU map */ 401 402 /** "Graphics Stolen Memory" holds the global PTEs */ 403 void __iomem *gsm; 404 void (*invalidate)(struct i915_ggtt *ggtt); 405 406 bool do_idle_maps; 407 408 int mtrr; 409 410 u32 pin_bias; 411 412 unsigned int num_fences; 413 struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; 414 struct list_head fence_list; 415 416 /** List of all objects in gtt_space, currently mmaped by userspace. 417 * All objects within this list must also be on bound_list. 418 */ 419 struct list_head userfault_list; 420 421 /* Manual runtime pm autosuspend delay for user GGTT mmaps */ 422 struct intel_wakeref_auto userfault_wakeref; 423 424 struct drm_mm_node error_capture; 425 struct drm_mm_node uc_fw; 426 }; 427 428 struct i915_ppgtt { 429 struct i915_address_space vm; 430 431 intel_engine_mask_t pd_dirty_engines; 432 struct i915_page_directory *pd; 433 }; 434 435 struct gen6_ppgtt { 436 struct i915_ppgtt base; 437 438 struct i915_vma *vma; 439 gen6_pte_t __iomem *pd_addr; 440 441 unsigned int pin_count; 442 bool scan_for_unused_pt; 443 }; 444 445 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_ppgtt, base) 446 447 static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base) 448 { 449 BUILD_BUG_ON(offsetof(struct gen6_ppgtt, base)); 450 return __to_gen6_ppgtt(base); 451 } 452 453 /* 454 * gen6_for_each_pde() iterates over every pde from start until start+length. 455 * If start and start+length are not perfectly divisible, the macro will round 456 * down and up as needed. Start=0 and length=2G effectively iterates over 457 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 458 * so each of the other parameters should preferably be a simple variable, or 459 * at most an lvalue with no side-effects! 460 */ 461 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 462 for (iter = gen6_pde_index(start); \ 463 length > 0 && iter < I915_PDES && \ 464 (pt = i915_pt_entry(pd, iter), true); \ 465 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 466 temp = min(temp - start, length); \ 467 start += temp, length -= temp; }), ++iter) 468 469 #define gen6_for_all_pdes(pt, pd, iter) \ 470 for (iter = 0; \ 471 iter < I915_PDES && \ 472 (pt = i915_pt_entry(pd, iter), true); \ 473 ++iter) 474 475 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 476 { 477 const u32 mask = NUM_PTE(pde_shift) - 1; 478 479 return (address >> PAGE_SHIFT) & mask; 480 } 481 482 /* Helper to counts the number of PTEs within the given length. This count 483 * does not cross a page table boundary, so the max value would be 484 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 485 */ 486 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 487 { 488 const u64 mask = ~((1ULL << pde_shift) - 1); 489 u64 end; 490 491 GEM_BUG_ON(length == 0); 492 GEM_BUG_ON(offset_in_page(addr | length)); 493 494 end = addr + length; 495 496 if ((addr & mask) != (end & mask)) 497 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 498 499 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 500 } 501 502 static inline u32 i915_pde_index(u64 addr, u32 shift) 503 { 504 return (addr >> shift) & I915_PDE_MASK; 505 } 506 507 static inline u32 gen6_pte_index(u32 addr) 508 { 509 return i915_pte_index(addr, GEN6_PDE_SHIFT); 510 } 511 512 static inline u32 gen6_pte_count(u32 addr, u32 length) 513 { 514 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 515 } 516 517 static inline u32 gen6_pde_index(u32 addr) 518 { 519 return i915_pde_index(addr, GEN6_PDE_SHIFT); 520 } 521 522 static inline unsigned int 523 i915_pdpes_per_pdp(const struct i915_address_space *vm) 524 { 525 if (i915_vm_is_4lvl(vm)) 526 return GEN8_PML4ES_PER_PML4; 527 528 return GEN8_3LVL_PDPES; 529 } 530 531 static inline struct i915_page_table * 532 i915_pt_entry(const struct i915_page_directory * const pd, 533 const unsigned short n) 534 { 535 return pd->entry[n]; 536 } 537 538 static inline struct i915_page_directory * 539 i915_pd_entry(const struct i915_page_directory * const pdp, 540 const unsigned short n) 541 { 542 return pdp->entry[n]; 543 } 544 545 static inline struct i915_page_directory * 546 i915_pdp_entry(const struct i915_page_directory * const pml4, 547 const unsigned short n) 548 { 549 return pml4->entry[n]; 550 } 551 552 /* Equivalent to the gen6 version, For each pde iterates over every pde 553 * between from start until start + length. On gen8+ it simply iterates 554 * over every page directory entry in a page directory. 555 */ 556 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 557 for (iter = gen8_pde_index(start); \ 558 length > 0 && iter < I915_PDES && \ 559 (pt = i915_pt_entry(pd, iter), true); \ 560 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 561 temp = min(temp - start, length); \ 562 start += temp, length -= temp; }), ++iter) 563 564 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 565 for (iter = gen8_pdpe_index(start); \ 566 length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 567 (pd = i915_pd_entry(pdp, iter), true); \ 568 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 569 temp = min(temp - start, length); \ 570 start += temp, length -= temp; }), ++iter) 571 572 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 573 for (iter = gen8_pml4e_index(start); \ 574 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 575 (pdp = i915_pdp_entry(pml4, iter), true); \ 576 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 577 temp = min(temp - start, length); \ 578 start += temp, length -= temp; }), ++iter) 579 580 static inline u32 gen8_pte_index(u64 address) 581 { 582 return i915_pte_index(address, GEN8_PDE_SHIFT); 583 } 584 585 static inline u32 gen8_pde_index(u64 address) 586 { 587 return i915_pde_index(address, GEN8_PDE_SHIFT); 588 } 589 590 static inline u32 gen8_pdpe_index(u64 address) 591 { 592 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 593 } 594 595 static inline u32 gen8_pml4e_index(u64 address) 596 { 597 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 598 } 599 600 static inline u64 gen8_pte_count(u64 address, u64 length) 601 { 602 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 603 } 604 605 static inline dma_addr_t 606 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 607 { 608 struct i915_page_dma *pt = ppgtt->pd->entry[n]; 609 610 return px_dma(pt); 611 } 612 613 static inline struct i915_ggtt * 614 i915_vm_to_ggtt(struct i915_address_space *vm) 615 { 616 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 617 GEM_BUG_ON(!i915_is_ggtt(vm)); 618 return container_of(vm, struct i915_ggtt, vm); 619 } 620 621 static inline struct i915_ppgtt * 622 i915_vm_to_ppgtt(struct i915_address_space *vm) 623 { 624 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 625 GEM_BUG_ON(i915_is_ggtt(vm)); 626 return container_of(vm, struct i915_ppgtt, vm); 627 } 628 629 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 630 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 631 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 632 void i915_ggtt_enable_guc(struct drm_i915_private *i915); 633 void i915_ggtt_disable_guc(struct drm_i915_private *i915); 634 int i915_init_ggtt(struct drm_i915_private *dev_priv); 635 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 636 637 int i915_ppgtt_init_hw(struct intel_gt *gt); 638 639 struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv); 640 641 static inline struct i915_address_space * 642 i915_vm_get(struct i915_address_space *vm) 643 { 644 kref_get(&vm->ref); 645 return vm; 646 } 647 648 void i915_vm_release(struct kref *kref); 649 650 static inline void i915_vm_put(struct i915_address_space *vm) 651 { 652 kref_put(&vm->ref, i915_vm_release); 653 } 654 655 int gen6_ppgtt_pin(struct i915_ppgtt *base); 656 void gen6_ppgtt_unpin(struct i915_ppgtt *base); 657 void gen6_ppgtt_unpin_all(struct i915_ppgtt *base); 658 659 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 660 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 661 662 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 663 struct sg_table *pages); 664 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 665 struct sg_table *pages); 666 667 int i915_gem_gtt_reserve(struct i915_address_space *vm, 668 struct drm_mm_node *node, 669 u64 size, u64 offset, unsigned long color, 670 unsigned int flags); 671 672 int i915_gem_gtt_insert(struct i915_address_space *vm, 673 struct drm_mm_node *node, 674 u64 size, u64 alignment, unsigned long color, 675 u64 start, u64 end, unsigned int flags); 676 677 /* Flags used by pin/bind&friends. */ 678 #define PIN_NONBLOCK BIT_ULL(0) 679 #define PIN_NONFAULT BIT_ULL(1) 680 #define PIN_NOEVICT BIT_ULL(2) 681 #define PIN_MAPPABLE BIT_ULL(3) 682 #define PIN_ZONE_4G BIT_ULL(4) 683 #define PIN_HIGH BIT_ULL(5) 684 #define PIN_OFFSET_BIAS BIT_ULL(6) 685 #define PIN_OFFSET_FIXED BIT_ULL(7) 686 687 #define PIN_MBZ BIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */ 688 #define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */ 689 #define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */ 690 #define PIN_UPDATE BIT_ULL(11) 691 692 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 693 694 #endif 695