1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 39 #include "i915_gem_request.h" 40 41 struct drm_i915_file_private; 42 43 typedef uint32_t gen6_pte_t; 44 typedef uint64_t gen8_pte_t; 45 typedef uint64_t gen8_pde_t; 46 typedef uint64_t gen8_ppgtt_pdpe_t; 47 typedef uint64_t gen8_ppgtt_pml4e_t; 48 49 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 50 51 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 52 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 53 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 54 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 55 #define GEN6_PTE_CACHE_LLC (2 << 1) 56 #define GEN6_PTE_UNCACHED (1 << 1) 57 #define GEN6_PTE_VALID (1 << 0) 58 59 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 60 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 61 #define I915_PDES 512 62 #define I915_PDE_MASK (I915_PDES - 1) 63 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 64 65 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 66 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 67 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 68 #define GEN6_PDE_SHIFT 22 69 #define GEN6_PDE_VALID (1 << 0) 70 71 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 72 73 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 74 #define BYT_PTE_WRITEABLE (1 << 1) 75 76 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 77 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 78 */ 79 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 80 (((bits) & 0x8) << (11 - 3))) 81 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 82 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 83 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 84 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 85 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 86 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 87 #define HSW_PTE_UNCACHED (0) 88 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 89 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 90 91 /* GEN8 legacy style address is defined as a 3 level page table: 92 * 31:30 | 29:21 | 20:12 | 11:0 93 * PDPE | PDE | PTE | offset 94 * The difference as compared to normal x86 3 level page table is the PDPEs are 95 * programmed via register. 96 * 97 * GEN8 48b legacy style address is defined as a 4 level page table: 98 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 99 * PML4E | PDPE | PDE | PTE | offset 100 */ 101 #define GEN8_PML4ES_PER_PML4 512 102 #define GEN8_PML4E_SHIFT 39 103 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 104 #define GEN8_PDPE_SHIFT 30 105 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 106 * tables */ 107 #define GEN8_PDPE_MASK 0x1ff 108 #define GEN8_PDE_SHIFT 21 109 #define GEN8_PDE_MASK 0x1ff 110 #define GEN8_PTE_SHIFT 12 111 #define GEN8_PTE_MASK 0x1ff 112 #define GEN8_LEGACY_PDPES 4 113 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 114 115 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 116 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 117 118 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 119 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 120 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 121 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 122 123 #define CHV_PPAT_SNOOP (1<<6) 124 #define GEN8_PPAT_AGE(x) (x<<4) 125 #define GEN8_PPAT_LLCeLLC (3<<2) 126 #define GEN8_PPAT_LLCELLC (2<<2) 127 #define GEN8_PPAT_LLC (1<<2) 128 #define GEN8_PPAT_WB (3<<0) 129 #define GEN8_PPAT_WT (2<<0) 130 #define GEN8_PPAT_WC (1<<0) 131 #define GEN8_PPAT_UC (0<<0) 132 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 133 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 134 135 enum i915_ggtt_view_type { 136 I915_GGTT_VIEW_NORMAL = 0, 137 I915_GGTT_VIEW_ROTATED, 138 I915_GGTT_VIEW_PARTIAL, 139 }; 140 141 struct intel_rotation_info { 142 unsigned int uv_offset; 143 uint32_t pixel_format; 144 unsigned int uv_start_page; 145 struct { 146 /* tiles */ 147 unsigned int width, height; 148 } plane[2]; 149 }; 150 151 struct i915_ggtt_view { 152 enum i915_ggtt_view_type type; 153 154 union { 155 struct { 156 u64 offset; 157 unsigned int size; 158 } partial; 159 struct intel_rotation_info rotated; 160 } params; 161 162 struct sg_table *pages; 163 }; 164 165 extern const struct i915_ggtt_view i915_ggtt_view_normal; 166 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 167 168 enum i915_cache_level; 169 170 /** 171 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 172 * VMA's presence cannot be guaranteed before binding, or after unbinding the 173 * object into/from the address space. 174 * 175 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 176 * will always be <= an objects lifetime. So object refcounting should cover us. 177 */ 178 struct i915_vma { 179 struct drm_mm_node node; 180 struct drm_i915_gem_object *obj; 181 struct i915_address_space *vm; 182 void __iomem *iomap; 183 u64 size; 184 185 unsigned int active; 186 struct i915_gem_active last_read[I915_NUM_ENGINES]; 187 188 /** Flags and address space this VMA is bound to */ 189 #define GLOBAL_BIND (1<<0) 190 #define LOCAL_BIND (1<<1) 191 unsigned int bound : 4; 192 bool is_ggtt : 1; 193 bool closed : 1; 194 195 /** 196 * Support different GGTT views into the same object. 197 * This means there can be multiple VMA mappings per object and per VM. 198 * i915_ggtt_view_type is used to distinguish between those entries. 199 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 200 * assumed in GEM functions which take no ggtt view parameter. 201 */ 202 struct i915_ggtt_view ggtt_view; 203 204 /** This object's place on the active/inactive lists */ 205 struct list_head vm_link; 206 207 struct list_head obj_link; /* Link in the object's VMA list */ 208 209 /** This vma's place in the batchbuffer or on the eviction list */ 210 struct list_head exec_list; 211 212 /** 213 * Used for performing relocations during execbuffer insertion. 214 */ 215 struct hlist_node exec_node; 216 unsigned long exec_handle; 217 struct drm_i915_gem_exec_object2 *exec_entry; 218 219 /** 220 * How many users have pinned this object in GTT space. The following 221 * users can each hold at most one reference: pwrite/pread, execbuffer 222 * (objects are not allowed multiple times for the same batchbuffer), 223 * and the framebuffer code. When switching/pageflipping, the 224 * framebuffer code has at most two buffers pinned per crtc. 225 * 226 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 227 * bits with absolutely no headroom. So use 4 bits. */ 228 unsigned int pin_count:4; 229 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 230 }; 231 232 static inline unsigned int i915_vma_get_active(const struct i915_vma *vma) 233 { 234 return vma->active; 235 } 236 237 static inline bool i915_vma_is_active(const struct i915_vma *vma) 238 { 239 return i915_vma_get_active(vma); 240 } 241 242 static inline void i915_vma_set_active(struct i915_vma *vma, 243 unsigned int engine) 244 { 245 vma->active |= BIT(engine); 246 } 247 248 static inline void i915_vma_clear_active(struct i915_vma *vma, 249 unsigned int engine) 250 { 251 vma->active &= ~BIT(engine); 252 } 253 254 static inline bool i915_vma_has_active_engine(const struct i915_vma *vma, 255 unsigned int engine) 256 { 257 return vma->active & BIT(engine); 258 } 259 260 struct i915_page_dma { 261 struct page *page; 262 union { 263 dma_addr_t daddr; 264 265 /* For gen6/gen7 only. This is the offset in the GGTT 266 * where the page directory entries for PPGTT begin 267 */ 268 uint32_t ggtt_offset; 269 }; 270 }; 271 272 #define px_base(px) (&(px)->base) 273 #define px_page(px) (px_base(px)->page) 274 #define px_dma(px) (px_base(px)->daddr) 275 276 struct i915_page_scratch { 277 struct i915_page_dma base; 278 }; 279 280 struct i915_page_table { 281 struct i915_page_dma base; 282 283 unsigned long *used_ptes; 284 }; 285 286 struct i915_page_directory { 287 struct i915_page_dma base; 288 289 unsigned long *used_pdes; 290 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 291 }; 292 293 struct i915_page_directory_pointer { 294 struct i915_page_dma base; 295 296 unsigned long *used_pdpes; 297 struct i915_page_directory **page_directory; 298 }; 299 300 struct i915_pml4 { 301 struct i915_page_dma base; 302 303 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 304 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 305 }; 306 307 struct i915_address_space { 308 struct drm_mm mm; 309 struct drm_device *dev; 310 /* Every address space belongs to a struct file - except for the global 311 * GTT that is owned by the driver (and so @file is set to NULL). In 312 * principle, no information should leak from one context to another 313 * (or between files/processes etc) unless explicitly shared by the 314 * owner. Tracking the owner is important in order to free up per-file 315 * objects along with the file, to aide resource tracking, and to 316 * assign blame. 317 */ 318 struct drm_i915_file_private *file; 319 struct list_head global_link; 320 u64 start; /* Start offset always 0 for dri2 */ 321 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 322 323 bool closed; 324 325 struct i915_page_scratch *scratch_page; 326 struct i915_page_table *scratch_pt; 327 struct i915_page_directory *scratch_pd; 328 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 329 330 /** 331 * List of objects currently involved in rendering. 332 * 333 * Includes buffers having the contents of their GPU caches 334 * flushed, not necessarily primitives. last_read_req 335 * represents when the rendering involved will be completed. 336 * 337 * A reference is held on the buffer while on this list. 338 */ 339 struct list_head active_list; 340 341 /** 342 * LRU list of objects which are not in the ringbuffer and 343 * are ready to unbind, but are still in the GTT. 344 * 345 * last_read_req is NULL while an object is in this list. 346 * 347 * A reference is not held on the buffer while on this list, 348 * as merely being GTT-bound shouldn't prevent its being 349 * freed, and we'll pull it off the list in the free path. 350 */ 351 struct list_head inactive_list; 352 353 /** 354 * List of vma that have been unbound. 355 * 356 * A reference is not held on the buffer while on this list. 357 */ 358 struct list_head unbound_list; 359 360 /* FIXME: Need a more generic return type */ 361 gen6_pte_t (*pte_encode)(dma_addr_t addr, 362 enum i915_cache_level level, 363 bool valid, u32 flags); /* Create a valid PTE */ 364 /* flags for pte_encode */ 365 #define PTE_READ_ONLY (1<<0) 366 int (*allocate_va_range)(struct i915_address_space *vm, 367 uint64_t start, 368 uint64_t length); 369 void (*clear_range)(struct i915_address_space *vm, 370 uint64_t start, 371 uint64_t length, 372 bool use_scratch); 373 void (*insert_page)(struct i915_address_space *vm, 374 dma_addr_t addr, 375 uint64_t offset, 376 enum i915_cache_level cache_level, 377 u32 flags); 378 void (*insert_entries)(struct i915_address_space *vm, 379 struct sg_table *st, 380 uint64_t start, 381 enum i915_cache_level cache_level, u32 flags); 382 void (*cleanup)(struct i915_address_space *vm); 383 /** Unmap an object from an address space. This usually consists of 384 * setting the valid PTE entries to a reserved scratch page. */ 385 void (*unbind_vma)(struct i915_vma *vma); 386 /* Map an object into an address space with the given cache flags. */ 387 int (*bind_vma)(struct i915_vma *vma, 388 enum i915_cache_level cache_level, 389 u32 flags); 390 }; 391 392 #define i915_is_ggtt(V) (!(V)->file) 393 394 /* The Graphics Translation Table is the way in which GEN hardware translates a 395 * Graphics Virtual Address into a Physical Address. In addition to the normal 396 * collateral associated with any va->pa translations GEN hardware also has a 397 * portion of the GTT which can be mapped by the CPU and remain both coherent 398 * and correct (in cases like swizzling). That region is referred to as GMADR in 399 * the spec. 400 */ 401 struct i915_ggtt { 402 struct i915_address_space base; 403 404 size_t stolen_size; /* Total size of stolen memory */ 405 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 406 size_t stolen_reserved_base; 407 size_t stolen_reserved_size; 408 u64 mappable_end; /* End offset that we can CPU map */ 409 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 410 phys_addr_t mappable_base; /* PA of our GMADR */ 411 412 /** "Graphics Stolen Memory" holds the global PTEs */ 413 void __iomem *gsm; 414 415 bool do_idle_maps; 416 417 int mtrr; 418 }; 419 420 struct i915_hw_ppgtt { 421 struct i915_address_space base; 422 struct kref ref; 423 struct drm_mm_node node; 424 unsigned long pd_dirty_rings; 425 union { 426 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 427 struct i915_page_directory_pointer pdp; /* GEN8+ */ 428 struct i915_page_directory pd; /* GEN6-7 */ 429 }; 430 431 gen6_pte_t __iomem *pd_addr; 432 433 int (*enable)(struct i915_hw_ppgtt *ppgtt); 434 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 435 struct drm_i915_gem_request *req); 436 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 437 }; 438 439 /* 440 * gen6_for_each_pde() iterates over every pde from start until start+length. 441 * If start and start+length are not perfectly divisible, the macro will round 442 * down and up as needed. Start=0 and length=2G effectively iterates over 443 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 444 * so each of the other parameters should preferably be a simple variable, or 445 * at most an lvalue with no side-effects! 446 */ 447 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 448 for (iter = gen6_pde_index(start); \ 449 length > 0 && iter < I915_PDES && \ 450 (pt = (pd)->page_table[iter], true); \ 451 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 452 temp = min(temp - start, length); \ 453 start += temp, length -= temp; }), ++iter) 454 455 #define gen6_for_all_pdes(pt, pd, iter) \ 456 for (iter = 0; \ 457 iter < I915_PDES && \ 458 (pt = (pd)->page_table[iter], true); \ 459 ++iter) 460 461 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 462 { 463 const uint32_t mask = NUM_PTE(pde_shift) - 1; 464 465 return (address >> PAGE_SHIFT) & mask; 466 } 467 468 /* Helper to counts the number of PTEs within the given length. This count 469 * does not cross a page table boundary, so the max value would be 470 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 471 */ 472 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 473 uint32_t pde_shift) 474 { 475 const uint64_t mask = ~((1ULL << pde_shift) - 1); 476 uint64_t end; 477 478 WARN_ON(length == 0); 479 WARN_ON(offset_in_page(addr|length)); 480 481 end = addr + length; 482 483 if ((addr & mask) != (end & mask)) 484 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 485 486 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 487 } 488 489 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 490 { 491 return (addr >> shift) & I915_PDE_MASK; 492 } 493 494 static inline uint32_t gen6_pte_index(uint32_t addr) 495 { 496 return i915_pte_index(addr, GEN6_PDE_SHIFT); 497 } 498 499 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 500 { 501 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 502 } 503 504 static inline uint32_t gen6_pde_index(uint32_t addr) 505 { 506 return i915_pde_index(addr, GEN6_PDE_SHIFT); 507 } 508 509 /* Equivalent to the gen6 version, For each pde iterates over every pde 510 * between from start until start + length. On gen8+ it simply iterates 511 * over every page directory entry in a page directory. 512 */ 513 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 514 for (iter = gen8_pde_index(start); \ 515 length > 0 && iter < I915_PDES && \ 516 (pt = (pd)->page_table[iter], true); \ 517 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 518 temp = min(temp - start, length); \ 519 start += temp, length -= temp; }), ++iter) 520 521 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 522 for (iter = gen8_pdpe_index(start); \ 523 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 524 (pd = (pdp)->page_directory[iter], true); \ 525 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 526 temp = min(temp - start, length); \ 527 start += temp, length -= temp; }), ++iter) 528 529 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 530 for (iter = gen8_pml4e_index(start); \ 531 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 532 (pdp = (pml4)->pdps[iter], true); \ 533 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 534 temp = min(temp - start, length); \ 535 start += temp, length -= temp; }), ++iter) 536 537 static inline uint32_t gen8_pte_index(uint64_t address) 538 { 539 return i915_pte_index(address, GEN8_PDE_SHIFT); 540 } 541 542 static inline uint32_t gen8_pde_index(uint64_t address) 543 { 544 return i915_pde_index(address, GEN8_PDE_SHIFT); 545 } 546 547 static inline uint32_t gen8_pdpe_index(uint64_t address) 548 { 549 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 550 } 551 552 static inline uint32_t gen8_pml4e_index(uint64_t address) 553 { 554 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 555 } 556 557 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 558 { 559 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 560 } 561 562 static inline dma_addr_t 563 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 564 { 565 return test_bit(n, ppgtt->pdp.used_pdpes) ? 566 px_dma(ppgtt->pdp.page_directory[n]) : 567 px_dma(ppgtt->base.scratch_pd); 568 } 569 570 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 571 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 572 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 573 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 574 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 575 576 int i915_ppgtt_init_hw(struct drm_device *dev); 577 void i915_ppgtt_release(struct kref *kref); 578 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 579 struct drm_i915_file_private *fpriv); 580 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 581 { 582 if (ppgtt) 583 kref_get(&ppgtt->ref); 584 } 585 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 586 { 587 if (ppgtt) 588 kref_put(&ppgtt->ref, i915_ppgtt_release); 589 } 590 591 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 592 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 593 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 594 595 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 596 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 597 598 static inline bool 599 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 600 const struct i915_ggtt_view *b) 601 { 602 if (WARN_ON(!a || !b)) 603 return false; 604 605 if (a->type != b->type) 606 return false; 607 if (a->type != I915_GGTT_VIEW_NORMAL) 608 return !memcmp(&a->params, &b->params, sizeof(a->params)); 609 return true; 610 } 611 612 static inline int i915_vma_pin_count(const struct i915_vma *vma) 613 { 614 return vma->pin_count; 615 } 616 617 static inline bool i915_vma_is_pinned(const struct i915_vma *vma) 618 { 619 return i915_vma_pin_count(vma); 620 } 621 622 static inline void __i915_vma_pin(struct i915_vma *vma) 623 { 624 vma->pin_count++; 625 GEM_BUG_ON(!i915_vma_is_pinned(vma)); 626 } 627 628 static inline void __i915_vma_unpin(struct i915_vma *vma) 629 { 630 GEM_BUG_ON(!i915_vma_is_pinned(vma)); 631 vma->pin_count--; 632 } 633 634 static inline void i915_vma_unpin(struct i915_vma *vma) 635 { 636 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); 637 __i915_vma_unpin(vma); 638 } 639 640 /** 641 * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture 642 * @vma: VMA to iomap 643 * 644 * The passed in VMA has to be pinned in the global GTT mappable region. 645 * An extra pinning of the VMA is acquired for the return iomapping, 646 * the caller must call i915_vma_unpin_iomap to relinquish the pinning 647 * after the iomapping is no longer required. 648 * 649 * Callers must hold the struct_mutex. 650 * 651 * Returns a valid iomapped pointer or ERR_PTR. 652 */ 653 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); 654 #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) 655 656 /** 657 * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap 658 * @vma: VMA to unpin 659 * 660 * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). 661 * 662 * Callers must hold the struct_mutex. This function is only valid to be 663 * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). 664 */ 665 static inline void i915_vma_unpin_iomap(struct i915_vma *vma) 666 { 667 lockdep_assert_held(&vma->vm->dev->struct_mutex); 668 GEM_BUG_ON(vma->iomap == NULL); 669 i915_vma_unpin(vma); 670 } 671 672 #endif 673