10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 378ef8561fSChris Wilson #include <linux/io-mapping.h> 38b42fe9caSJoonas Lahtinen #include <linux/mm.h> 398448661dSChris Wilson #include <linux/pagevec.h> 408ef8561fSChris Wilson 41b42fe9caSJoonas Lahtinen #include "i915_gem_timeline.h" 42b0decaf7SChris Wilson #include "i915_gem_request.h" 438448661dSChris Wilson #include "i915_selftest.h" 44b0decaf7SChris Wilson 452a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE_4K BIT(12) 462a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE_64K BIT(16) 472a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE_2M BIT(21) 482a9654b2SMatthew Auld 492a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 502a9654b2SMatthew Auld #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 512a9654b2SMatthew Auld 52f51455d4SChris Wilson #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 53f51455d4SChris Wilson 5449ef5294SChris Wilson #define I915_FENCE_REG_NONE -1 5549ef5294SChris Wilson #define I915_MAX_NUM_FENCES 32 5649ef5294SChris Wilson /* 32 fences + sign bit for FENCE_REG_NONE */ 5749ef5294SChris Wilson #define I915_MAX_NUM_FENCE_BITS 6 5849ef5294SChris Wilson 594d884705SDaniel Vetter struct drm_i915_file_private; 6049ef5294SChris Wilson struct drm_i915_fence_reg; 614d884705SDaniel Vetter 6275c7b0b8SChris Wilson typedef u32 gen6_pte_t; 6375c7b0b8SChris Wilson typedef u64 gen8_pte_t; 6475c7b0b8SChris Wilson typedef u64 gen8_pde_t; 6575c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pdpe_t; 6675c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pml4e_t; 670260c420SBen Widawsky 6872e96d64SJoonas Lahtinen #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 690260c420SBen Widawsky 700260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 710260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 720260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 730260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 740260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 750260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 760260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 770260c420SBen Widawsky 78dd19674bSChris Wilson #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 7907749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 8007749ef3SMichel Thierry #define I915_PDES 512 8107749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 82678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 8307749ef3SMichel Thierry 8407749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 8507749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 860260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 87678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 880260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 890260c420SBen Widawsky 900260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 910260c420SBen Widawsky 920260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 930260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 940260c420SBen Widawsky 950260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 960260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 970260c420SBen Widawsky */ 980260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 990260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 1000260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 1010260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 1020260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 1030260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 1040260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 1050260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1060260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 1070260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1080260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1090260c420SBen Widawsky 110e7167769SMika Kuoppala /* GEN8 32b style address is defined as a 3 level page table: 1110260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 1120260c420SBen Widawsky * PDPE | PDE | PTE | offset 1130260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 1140260c420SBen Widawsky * programmed via register. 115e7167769SMika Kuoppala */ 116e7167769SMika Kuoppala #define GEN8_3LVL_PDPES 4 117e7167769SMika Kuoppala #define GEN8_PDE_SHIFT 21 118e7167769SMika Kuoppala #define GEN8_PDE_MASK 0x1ff 119e7167769SMika Kuoppala #define GEN8_PTE_SHIFT 12 120e7167769SMika Kuoppala #define GEN8_PTE_MASK 0x1ff 121e7167769SMika Kuoppala #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 122e7167769SMika Kuoppala 123e7167769SMika Kuoppala /* GEN8 48b style address is defined as a 4 level page table: 12481ba8aefSMichel Thierry * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 12581ba8aefSMichel Thierry * PML4E | PDPE | PDE | PTE | offset 1260260c420SBen Widawsky */ 12781ba8aefSMichel Thierry #define GEN8_PML4ES_PER_PML4 512 12881ba8aefSMichel Thierry #define GEN8_PML4E_SHIFT 39 129762d9936SMichel Thierry #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 1300260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 13181ba8aefSMichel Thierry /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 13281ba8aefSMichel Thierry * tables */ 13381ba8aefSMichel Thierry #define GEN8_PDPE_MASK 0x1ff 1340260c420SBen Widawsky 135c095b97cSZhi Wang #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 136c095b97cSZhi Wang #define PPAT_CACHED_PDE 0 /* WB LLC */ 137c095b97cSZhi Wang #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 138c095b97cSZhi Wang #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 1390260c420SBen Widawsky 140ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1411790625bSMichal Wajdeczko #define GEN8_PPAT_AGE(x) ((x)<<4) 1420260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1430260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1440260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1450260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1460260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1470260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1480260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1490260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 15075c7b0b8SChris Wilson #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1510260c420SBen Widawsky 1524395890aSZhi Wang #define GEN8_PPAT_GET_CA(x) ((x) & 3) 1534395890aSZhi Wang #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 1544395890aSZhi Wang #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 1554395890aSZhi Wang #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 1564395890aSZhi Wang 157b42fe9caSJoonas Lahtinen struct sg_table; 158b42fe9caSJoonas Lahtinen 15950470bb0STvrtko Ursulin struct intel_rotation_info { 1607ff19c56SChris Wilson struct intel_rotation_plane_info { 1611663b9d6SVille Syrjälä /* tiles */ 1626687c906SVille Syrjälä unsigned int width, height, stride, offset; 1631663b9d6SVille Syrjälä } plane[2]; 1648d9046adSChris Wilson } __packed; 1658d9046adSChris Wilson 1668d9046adSChris Wilson static inline void assert_intel_rotation_info_is_packed(void) 1678d9046adSChris Wilson { 1688d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 1698d9046adSChris Wilson } 170fe14d5f4STvrtko Ursulin 1717ff19c56SChris Wilson struct intel_partial_info { 1727ff19c56SChris Wilson u64 offset; 1737ff19c56SChris Wilson unsigned int size; 1748d9046adSChris Wilson } __packed; 1758d9046adSChris Wilson 1768d9046adSChris Wilson static inline void assert_intel_partial_info_is_packed(void) 1778d9046adSChris Wilson { 1788d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 1798d9046adSChris Wilson } 1807ff19c56SChris Wilson 181992e418dSChris Wilson enum i915_ggtt_view_type { 182992e418dSChris Wilson I915_GGTT_VIEW_NORMAL = 0, 183992e418dSChris Wilson I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 184992e418dSChris Wilson I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 185992e418dSChris Wilson }; 186992e418dSChris Wilson 187992e418dSChris Wilson static inline void assert_i915_ggtt_view_type_is_unique(void) 188992e418dSChris Wilson { 189992e418dSChris Wilson /* As we encode the size of each branch inside the union into its type, 190992e418dSChris Wilson * we have to be careful that each branch has a unique size. 191992e418dSChris Wilson */ 192992e418dSChris Wilson switch ((enum i915_ggtt_view_type)0) { 193992e418dSChris Wilson case I915_GGTT_VIEW_NORMAL: 194992e418dSChris Wilson case I915_GGTT_VIEW_PARTIAL: 195992e418dSChris Wilson case I915_GGTT_VIEW_ROTATED: 196992e418dSChris Wilson /* gcc complains if these are identical cases */ 197992e418dSChris Wilson break; 198992e418dSChris Wilson } 199992e418dSChris Wilson } 200992e418dSChris Wilson 201fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 202fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 2038bd7ef16SJoonas Lahtinen union { 204992e418dSChris Wilson /* Members need to contain no holes/padding */ 2057ff19c56SChris Wilson struct intel_partial_info partial; 2067723f47dSVille Syrjälä struct intel_rotation_info rotated; 2078bab1193SChris Wilson }; 208fe14d5f4STvrtko Ursulin }; 209fe14d5f4STvrtko Ursulin 2100260c420SBen Widawsky enum i915_cache_level; 211fe14d5f4STvrtko Ursulin 212b42fe9caSJoonas Lahtinen struct i915_vma; 213bde13ebdSChris Wilson 21444159ddbSMika Kuoppala struct i915_page_dma { 215d7b3de91SBen Widawsky struct page *page; 21644159ddbSMika Kuoppala union { 2177324cc04SBen Widawsky dma_addr_t daddr; 218678d96fbSBen Widawsky 21944159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 22044159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 22144159ddbSMika Kuoppala */ 22275c7b0b8SChris Wilson u32 ggtt_offset; 22344159ddbSMika Kuoppala }; 22444159ddbSMika Kuoppala }; 22544159ddbSMika Kuoppala 226567047beSMika Kuoppala #define px_base(px) (&(px)->base) 227567047beSMika Kuoppala #define px_page(px) (px_base(px)->page) 228567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 229567047beSMika Kuoppala 23044159ddbSMika Kuoppala struct i915_page_table { 23144159ddbSMika Kuoppala struct i915_page_dma base; 232dd19674bSChris Wilson unsigned int used_ptes; 233d7b3de91SBen Widawsky }; 234d7b3de91SBen Widawsky 235ec565b3cSMichel Thierry struct i915_page_directory { 23644159ddbSMika Kuoppala struct i915_page_dma base; 2377324cc04SBen Widawsky 238ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 239fe52e37fSChris Wilson unsigned int used_pdes; 240d7b3de91SBen Widawsky }; 241d7b3de91SBen Widawsky 242ec565b3cSMichel Thierry struct i915_page_directory_pointer { 2436ac18502SMichel Thierry struct i915_page_dma base; 2446ac18502SMichel Thierry struct i915_page_directory **page_directory; 245e2b763caSChris Wilson unsigned int used_pdpes; 246d7b3de91SBen Widawsky }; 247d7b3de91SBen Widawsky 24881ba8aefSMichel Thierry struct i915_pml4 { 24981ba8aefSMichel Thierry struct i915_page_dma base; 25081ba8aefSMichel Thierry struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 25181ba8aefSMichel Thierry }; 25281ba8aefSMichel Thierry 2530260c420SBen Widawsky struct i915_address_space { 2540260c420SBen Widawsky struct drm_mm mm; 25580b204bcSChris Wilson struct i915_gem_timeline timeline; 25649d73912SChris Wilson struct drm_i915_private *i915; 2578448661dSChris Wilson struct device *dma; 2582bfa996eSChris Wilson /* Every address space belongs to a struct file - except for the global 2592bfa996eSChris Wilson * GTT that is owned by the driver (and so @file is set to NULL). In 2602bfa996eSChris Wilson * principle, no information should leak from one context to another 2612bfa996eSChris Wilson * (or between files/processes etc) unless explicitly shared by the 2622bfa996eSChris Wilson * owner. Tracking the owner is important in order to free up per-file 2632bfa996eSChris Wilson * objects along with the file, to aide resource tracking, and to 2642bfa996eSChris Wilson * assign blame. 2652bfa996eSChris Wilson */ 2662bfa996eSChris Wilson struct drm_i915_file_private *file; 2670260c420SBen Widawsky struct list_head global_link; 268c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 269ff8f7975SWeinan Li u64 reserved; /* size addr space reserved */ 2700260c420SBen Widawsky 27150e046b6SChris Wilson bool closed; 27250e046b6SChris Wilson 2738bcdd0f7SChris Wilson struct i915_page_dma scratch_page; 27479ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 27579ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 27669ab76fdSMichel Thierry struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 2770260c420SBen Widawsky 2780260c420SBen Widawsky /** 2790260c420SBen Widawsky * List of objects currently involved in rendering. 2800260c420SBen Widawsky * 2810260c420SBen Widawsky * Includes buffers having the contents of their GPU caches 28297b2a6a1SJohn Harrison * flushed, not necessarily primitives. last_read_req 2830260c420SBen Widawsky * represents when the rendering involved will be completed. 2840260c420SBen Widawsky * 2850260c420SBen Widawsky * A reference is held on the buffer while on this list. 2860260c420SBen Widawsky */ 2870260c420SBen Widawsky struct list_head active_list; 2880260c420SBen Widawsky 2890260c420SBen Widawsky /** 2900260c420SBen Widawsky * LRU list of objects which are not in the ringbuffer and 2910260c420SBen Widawsky * are ready to unbind, but are still in the GTT. 2920260c420SBen Widawsky * 29397b2a6a1SJohn Harrison * last_read_req is NULL while an object is in this list. 2940260c420SBen Widawsky * 2950260c420SBen Widawsky * A reference is not held on the buffer while on this list, 2960260c420SBen Widawsky * as merely being GTT-bound shouldn't prevent its being 2970260c420SBen Widawsky * freed, and we'll pull it off the list in the free path. 2980260c420SBen Widawsky */ 2990260c420SBen Widawsky struct list_head inactive_list; 3000260c420SBen Widawsky 30150e046b6SChris Wilson /** 30250e046b6SChris Wilson * List of vma that have been unbound. 30350e046b6SChris Wilson * 30450e046b6SChris Wilson * A reference is not held on the buffer while on this list. 30550e046b6SChris Wilson */ 30650e046b6SChris Wilson struct list_head unbound_list; 30750e046b6SChris Wilson 3088448661dSChris Wilson struct pagevec free_pages; 3098448661dSChris Wilson bool pt_kmap_wc; 3108448661dSChris Wilson 3110260c420SBen Widawsky /* FIXME: Need a more generic return type */ 31207749ef3SMichel Thierry gen6_pte_t (*pte_encode)(dma_addr_t addr, 3130260c420SBen Widawsky enum i915_cache_level level, 3144fb84d99SMichał Winiarski u32 flags); /* Create a valid PTE */ 315f329f5f6SDaniel Vetter /* flags for pte_encode */ 316f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 317678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 31875c7b0b8SChris Wilson u64 start, u64 length); 3190260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 32075c7b0b8SChris Wilson u64 start, u64 length); 321d6473f56SChris Wilson void (*insert_page)(struct i915_address_space *vm, 322d6473f56SChris Wilson dma_addr_t addr, 32375c7b0b8SChris Wilson u64 offset, 324d6473f56SChris Wilson enum i915_cache_level cache_level, 325d6473f56SChris Wilson u32 flags); 3260260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 3274a234c5fSMatthew Auld struct i915_vma *vma, 32875c7b0b8SChris Wilson enum i915_cache_level cache_level, 32975c7b0b8SChris Wilson u32 flags); 3300260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 331777dc5bbSDaniel Vetter /** Unmap an object from an address space. This usually consists of 332777dc5bbSDaniel Vetter * setting the valid PTE entries to a reserved scratch page. */ 333777dc5bbSDaniel Vetter void (*unbind_vma)(struct i915_vma *vma); 334777dc5bbSDaniel Vetter /* Map an object into an address space with the given cache flags. */ 33570b9f6f8SDaniel Vetter int (*bind_vma)(struct i915_vma *vma, 336777dc5bbSDaniel Vetter enum i915_cache_level cache_level, 337777dc5bbSDaniel Vetter u32 flags); 338fa3f46afSMatthew Auld int (*set_pages)(struct i915_vma *vma); 339fa3f46afSMatthew Auld void (*clear_pages)(struct i915_vma *vma); 3408448661dSChris Wilson 3418448661dSChris Wilson I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 3420260c420SBen Widawsky }; 3430260c420SBen Widawsky 3442bfa996eSChris Wilson #define i915_is_ggtt(V) (!(V)->file) 345596c5923SChris Wilson 3463e490042SMika Kuoppala static inline bool 3473e490042SMika Kuoppala i915_vm_is_48bit(const struct i915_address_space *vm) 3483e490042SMika Kuoppala { 3493e490042SMika Kuoppala return (vm->total - 1) >> 32; 3503e490042SMika Kuoppala } 3513e490042SMika Kuoppala 3520260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3530260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3540260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3550260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3560260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3570260c420SBen Widawsky * the spec. 3580260c420SBen Widawsky */ 35962106b4fSJoonas Lahtinen struct i915_ggtt { 3600260c420SBen Widawsky struct i915_address_space base; 361f7bbe788SChris Wilson struct io_mapping mappable; /* Mapping to our CPU mappable region */ 3620260c420SBen Widawsky 363edd1f2feSChris Wilson phys_addr_t mappable_base; /* PA of our GMADR */ 364edd1f2feSChris Wilson u64 mappable_end; /* End offset that we can CPU map */ 365edd1f2feSChris Wilson 3663c6b29b2SPaulo Zanoni /* Stolen memory is segmented in hardware with different portions 3673c6b29b2SPaulo Zanoni * offlimits to certain functions. 3683c6b29b2SPaulo Zanoni * 3693c6b29b2SPaulo Zanoni * The drm_mm is initialised to the total accessible range, as found 3703c6b29b2SPaulo Zanoni * from the PCI config. On Broadwell+, this is further restricted to 3713c6b29b2SPaulo Zanoni * avoid the first page! The upper end of stolen memory is reserved for 3723c6b29b2SPaulo Zanoni * hardware functions and similarly removed from the accessible range. 3733c6b29b2SPaulo Zanoni */ 374edd1f2feSChris Wilson u32 stolen_size; /* Total size of stolen memory */ 375edd1f2feSChris Wilson u32 stolen_usable_size; /* Total size minus reserved ranges */ 376edd1f2feSChris Wilson u32 stolen_reserved_base; 377edd1f2feSChris Wilson u32 stolen_reserved_size; 3780260c420SBen Widawsky 3790260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3800260c420SBen Widawsky void __iomem *gsm; 3817c3f86b6SChris Wilson void (*invalidate)(struct drm_i915_private *dev_priv); 3820260c420SBen Widawsky 3830260c420SBen Widawsky bool do_idle_maps; 3840260c420SBen Widawsky 3850260c420SBen Widawsky int mtrr; 38695374d75SChris Wilson 38795374d75SChris Wilson struct drm_mm_node error_capture; 3880260c420SBen Widawsky }; 3890260c420SBen Widawsky 3900260c420SBen Widawsky struct i915_hw_ppgtt { 3910260c420SBen Widawsky struct i915_address_space base; 3920260c420SBen Widawsky struct kref ref; 3930260c420SBen Widawsky struct drm_mm_node node; 394563222a7SBen Widawsky unsigned long pd_dirty_rings; 3950260c420SBen Widawsky union { 39681ba8aefSMichel Thierry struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 39781ba8aefSMichel Thierry struct i915_page_directory_pointer pdp; /* GEN8+ */ 39881ba8aefSMichel Thierry struct i915_page_directory pd; /* GEN6-7 */ 399d7b3de91SBen Widawsky }; 4000260c420SBen Widawsky 401678d96fbSBen Widawsky gen6_pte_t __iomem *pd_addr; 402678d96fbSBen Widawsky 4030260c420SBen Widawsky int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 404e85b26dcSJohn Harrison struct drm_i915_gem_request *req); 4050260c420SBen Widawsky void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 4060260c420SBen Widawsky }; 4070260c420SBen Widawsky 408731f74c5SDave Gordon /* 409731f74c5SDave Gordon * gen6_for_each_pde() iterates over every pde from start until start+length. 410731f74c5SDave Gordon * If start and start+length are not perfectly divisible, the macro will round 411731f74c5SDave Gordon * down and up as needed. Start=0 and length=2G effectively iterates over 412731f74c5SDave Gordon * every PDE in the system. The macro modifies ALL its parameters except 'pd', 413731f74c5SDave Gordon * so each of the other parameters should preferably be a simple variable, or 414731f74c5SDave Gordon * at most an lvalue with no side-effects! 415678d96fbSBen Widawsky */ 416731f74c5SDave Gordon #define gen6_for_each_pde(pt, pd, start, length, iter) \ 417fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 418731f74c5SDave Gordon length > 0 && iter < I915_PDES && \ 419731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 420731f74c5SDave Gordon ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 421731f74c5SDave Gordon temp = min(temp - start, length); \ 422731f74c5SDave Gordon start += temp, length -= temp; }), ++iter) 423678d96fbSBen Widawsky 424731f74c5SDave Gordon #define gen6_for_all_pdes(pt, pd, iter) \ 42509942c65SMichel Thierry for (iter = 0; \ 426731f74c5SDave Gordon iter < I915_PDES && \ 427731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 428731f74c5SDave Gordon ++iter) 42909942c65SMichel Thierry 43075c7b0b8SChris Wilson static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 431678d96fbSBen Widawsky { 43275c7b0b8SChris Wilson const u32 mask = NUM_PTE(pde_shift) - 1; 433678d96fbSBen Widawsky 434678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 435678d96fbSBen Widawsky } 436678d96fbSBen Widawsky 437678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 438678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 439678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 440678d96fbSBen Widawsky */ 44175c7b0b8SChris Wilson static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 442678d96fbSBen Widawsky { 44375c7b0b8SChris Wilson const u64 mask = ~((1ULL << pde_shift) - 1); 44475c7b0b8SChris Wilson u64 end; 445678d96fbSBen Widawsky 446678d96fbSBen Widawsky WARN_ON(length == 0); 447678d96fbSBen Widawsky WARN_ON(offset_in_page(addr|length)); 448678d96fbSBen Widawsky 449678d96fbSBen Widawsky end = addr + length; 450678d96fbSBen Widawsky 451678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 452678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 453678d96fbSBen Widawsky 454678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 455678d96fbSBen Widawsky } 456678d96fbSBen Widawsky 45775c7b0b8SChris Wilson static inline u32 i915_pde_index(u64 addr, u32 shift) 458678d96fbSBen Widawsky { 459678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 460678d96fbSBen Widawsky } 461678d96fbSBen Widawsky 46275c7b0b8SChris Wilson static inline u32 gen6_pte_index(u32 addr) 463678d96fbSBen Widawsky { 464678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 465678d96fbSBen Widawsky } 466678d96fbSBen Widawsky 46775c7b0b8SChris Wilson static inline u32 gen6_pte_count(u32 addr, u32 length) 468678d96fbSBen Widawsky { 469678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 470678d96fbSBen Widawsky } 471678d96fbSBen Widawsky 47275c7b0b8SChris Wilson static inline u32 gen6_pde_index(u32 addr) 473678d96fbSBen Widawsky { 474678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 475678d96fbSBen Widawsky } 476678d96fbSBen Widawsky 4773e490042SMika Kuoppala static inline unsigned int 4783e490042SMika Kuoppala i915_pdpes_per_pdp(const struct i915_address_space *vm) 4793e490042SMika Kuoppala { 4803e490042SMika Kuoppala if (i915_vm_is_48bit(vm)) 4813e490042SMika Kuoppala return GEN8_PML4ES_PER_PML4; 4823e490042SMika Kuoppala 483e7167769SMika Kuoppala return GEN8_3LVL_PDPES; 4843e490042SMika Kuoppala } 4853e490042SMika Kuoppala 4869271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4879271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4889271d959SMichel Thierry * over every page directory entry in a page directory. 4899271d959SMichel Thierry */ 490e8ebd8e2SDave Gordon #define gen8_for_each_pde(pt, pd, start, length, iter) \ 4919271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 492e8ebd8e2SDave Gordon length > 0 && iter < I915_PDES && \ 493e8ebd8e2SDave Gordon (pt = (pd)->page_table[iter], true); \ 494e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 495e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 496e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4979271d959SMichel Thierry 498e8ebd8e2SDave Gordon #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 4999271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 5003e490042SMika Kuoppala length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 501e8ebd8e2SDave Gordon (pd = (pdp)->page_directory[iter], true); \ 502e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 503e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 504e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 5059271d959SMichel Thierry 506e8ebd8e2SDave Gordon #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 507762d9936SMichel Thierry for (iter = gen8_pml4e_index(start); \ 508e8ebd8e2SDave Gordon length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 509e8ebd8e2SDave Gordon (pdp = (pml4)->pdps[iter], true); \ 510e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 511e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 512e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 513762d9936SMichel Thierry 51475c7b0b8SChris Wilson static inline u32 gen8_pte_index(u64 address) 5159271d959SMichel Thierry { 5169271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 5179271d959SMichel Thierry } 5189271d959SMichel Thierry 51975c7b0b8SChris Wilson static inline u32 gen8_pde_index(u64 address) 5209271d959SMichel Thierry { 5219271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 5229271d959SMichel Thierry } 5239271d959SMichel Thierry 52475c7b0b8SChris Wilson static inline u32 gen8_pdpe_index(u64 address) 5259271d959SMichel Thierry { 5269271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 5279271d959SMichel Thierry } 5289271d959SMichel Thierry 52975c7b0b8SChris Wilson static inline u32 gen8_pml4e_index(u64 address) 5309271d959SMichel Thierry { 531762d9936SMichel Thierry return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 5329271d959SMichel Thierry } 5339271d959SMichel Thierry 53475c7b0b8SChris Wilson static inline u64 gen8_pte_count(u64 address, u64 length) 53533c8819fSMichel Thierry { 53633c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 53733c8819fSMichel Thierry } 53833c8819fSMichel Thierry 539d852c7bfSMika Kuoppala static inline dma_addr_t 540d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 541d852c7bfSMika Kuoppala { 542fe52e37fSChris Wilson return px_dma(ppgtt->pdp.page_directory[n]); 543d852c7bfSMika Kuoppala } 544d852c7bfSMika Kuoppala 545b42fe9caSJoonas Lahtinen static inline struct i915_ggtt * 546b42fe9caSJoonas Lahtinen i915_vm_to_ggtt(struct i915_address_space *vm) 547b42fe9caSJoonas Lahtinen { 548b42fe9caSJoonas Lahtinen GEM_BUG_ON(!i915_is_ggtt(vm)); 549b42fe9caSJoonas Lahtinen return container_of(vm, struct i915_ggtt, base); 550b42fe9caSJoonas Lahtinen } 551b42fe9caSJoonas Lahtinen 5524395890aSZhi Wang #define INTEL_MAX_PPAT_ENTRIES 8 5534395890aSZhi Wang #define INTEL_PPAT_PERFECT_MATCH (~0U) 5544395890aSZhi Wang 5554395890aSZhi Wang struct intel_ppat; 5564395890aSZhi Wang 5574395890aSZhi Wang struct intel_ppat_entry { 5584395890aSZhi Wang struct intel_ppat *ppat; 5594395890aSZhi Wang struct kref ref; 5604395890aSZhi Wang u8 value; 5614395890aSZhi Wang }; 5624395890aSZhi Wang 5634395890aSZhi Wang struct intel_ppat { 5644395890aSZhi Wang struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 5654395890aSZhi Wang DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 5664395890aSZhi Wang DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 5674395890aSZhi Wang unsigned int max_entries; 5684395890aSZhi Wang u8 clear_value; 5694395890aSZhi Wang /* 5704395890aSZhi Wang * Return a score to show how two PPAT values match, 5714395890aSZhi Wang * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 5724395890aSZhi Wang */ 5734395890aSZhi Wang unsigned int (*match)(u8 src, u8 dst); 5744395890aSZhi Wang void (*update_hw)(struct drm_i915_private *i915); 5754395890aSZhi Wang 5764395890aSZhi Wang struct drm_i915_private *i915; 5774395890aSZhi Wang }; 5784395890aSZhi Wang 5794395890aSZhi Wang const struct intel_ppat_entry * 5804395890aSZhi Wang intel_ppat_get(struct drm_i915_private *i915, u8 value); 5814395890aSZhi Wang void intel_ppat_put(const struct intel_ppat_entry *entry); 5824395890aSZhi Wang 5836cde9a02SChris Wilson int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 5846cde9a02SChris Wilson void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 5856cde9a02SChris Wilson 58697d6d7abSChris Wilson int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 58797d6d7abSChris Wilson int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 58897d6d7abSChris Wilson int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 5897c3f86b6SChris Wilson void i915_ggtt_enable_guc(struct drm_i915_private *i915); 5907c3f86b6SChris Wilson void i915_ggtt_disable_guc(struct drm_i915_private *i915); 591f6b9d5caSChris Wilson int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 59297d6d7abSChris Wilson void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 593ee960be7SDaniel Vetter 594c6be607aSTvrtko Ursulin int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 595ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 5962bfa996eSChris Wilson struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 59780b204bcSChris Wilson struct drm_i915_file_private *fpriv, 59880b204bcSChris Wilson const char *name); 5990c7eeda1SChris Wilson void i915_ppgtt_close(struct i915_address_space *vm); 600ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 601ee960be7SDaniel Vetter { 602ee960be7SDaniel Vetter if (ppgtt) 603ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 604ee960be7SDaniel Vetter } 605ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 606ee960be7SDaniel Vetter { 607ee960be7SDaniel Vetter if (ppgtt) 608ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 609ee960be7SDaniel Vetter } 6100260c420SBen Widawsky 611dc97997aSChris Wilson void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 612275a991cSTvrtko Ursulin void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 613275a991cSTvrtko Ursulin void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 6140260c420SBen Widawsky 61503ac84f1SChris Wilson int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 61603ac84f1SChris Wilson struct sg_table *pages); 61703ac84f1SChris Wilson void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 61803ac84f1SChris Wilson struct sg_table *pages); 6190260c420SBen Widawsky 620625d988aSChris Wilson int i915_gem_gtt_reserve(struct i915_address_space *vm, 621625d988aSChris Wilson struct drm_mm_node *node, 622625d988aSChris Wilson u64 size, u64 offset, unsigned long color, 623625d988aSChris Wilson unsigned int flags); 624625d988aSChris Wilson 625e007b19dSChris Wilson int i915_gem_gtt_insert(struct i915_address_space *vm, 626e007b19dSChris Wilson struct drm_mm_node *node, 627e007b19dSChris Wilson u64 size, u64 alignment, unsigned long color, 628e007b19dSChris Wilson u64 start, u64 end, unsigned int flags); 629e007b19dSChris Wilson 63059bfa124SChris Wilson /* Flags used by pin/bind&friends. */ 631305bc234SChris Wilson #define PIN_NONBLOCK BIT(0) 632305bc234SChris Wilson #define PIN_MAPPABLE BIT(1) 633305bc234SChris Wilson #define PIN_ZONE_4G BIT(2) 63482118877SChris Wilson #define PIN_NONFAULT BIT(3) 635616d9ceeSChris Wilson #define PIN_NOEVICT BIT(4) 636305bc234SChris Wilson 637305bc234SChris Wilson #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 638305bc234SChris Wilson #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 639305bc234SChris Wilson #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 640305bc234SChris Wilson #define PIN_UPDATE BIT(8) 641305bc234SChris Wilson 642305bc234SChris Wilson #define PIN_HIGH BIT(9) 643305bc234SChris Wilson #define PIN_OFFSET_BIAS BIT(10) 644305bc234SChris Wilson #define PIN_OFFSET_FIXED BIT(11) 645f51455d4SChris Wilson #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 64659bfa124SChris Wilson 6470260c420SBen Widawsky #endif 648