10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 378ef8561fSChris Wilson #include <linux/io-mapping.h> 38b42fe9caSJoonas Lahtinen #include <linux/mm.h> 398448661dSChris Wilson #include <linux/pagevec.h> 408ef8561fSChris Wilson 41b42fe9caSJoonas Lahtinen #include "i915_gem_timeline.h" 42e61e0f51SChris Wilson 43e61e0f51SChris Wilson #include "i915_request.h" 448448661dSChris Wilson #include "i915_selftest.h" 45b0decaf7SChris Wilson 462a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE_4K BIT(12) 472a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE_64K BIT(16) 482a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE_2M BIT(21) 492a9654b2SMatthew Auld 502a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 512a9654b2SMatthew Auld #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 522a9654b2SMatthew Auld 53f51455d4SChris Wilson #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 54f51455d4SChris Wilson 5549ef5294SChris Wilson #define I915_FENCE_REG_NONE -1 5649ef5294SChris Wilson #define I915_MAX_NUM_FENCES 32 5749ef5294SChris Wilson /* 32 fences + sign bit for FENCE_REG_NONE */ 5849ef5294SChris Wilson #define I915_MAX_NUM_FENCE_BITS 6 5949ef5294SChris Wilson 604d884705SDaniel Vetter struct drm_i915_file_private; 6149ef5294SChris Wilson struct drm_i915_fence_reg; 624d884705SDaniel Vetter 6375c7b0b8SChris Wilson typedef u32 gen6_pte_t; 6475c7b0b8SChris Wilson typedef u64 gen8_pte_t; 6575c7b0b8SChris Wilson typedef u64 gen8_pde_t; 6675c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pdpe_t; 6775c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pml4e_t; 680260c420SBen Widawsky 6972e96d64SJoonas Lahtinen #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 700260c420SBen Widawsky 710260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 720260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 730260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 740260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 750260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 760260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 770260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 780260c420SBen Widawsky 79dd19674bSChris Wilson #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 8007749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 8107749ef3SMichel Thierry #define I915_PDES 512 8207749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 83678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 8407749ef3SMichel Thierry 8507749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 8607749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 870260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 88678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 890260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 900260c420SBen Widawsky 910260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 920260c420SBen Widawsky 930260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 940260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 950260c420SBen Widawsky 960260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 970260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 980260c420SBen Widawsky */ 990260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 1000260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 1010260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 1020260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 1030260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 1040260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 1050260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 1060260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1070260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 1080260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1090260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1100260c420SBen Widawsky 111e7167769SMika Kuoppala /* GEN8 32b style address is defined as a 3 level page table: 1120260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 1130260c420SBen Widawsky * PDPE | PDE | PTE | offset 1140260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 1150260c420SBen Widawsky * programmed via register. 116e7167769SMika Kuoppala */ 117e7167769SMika Kuoppala #define GEN8_3LVL_PDPES 4 118e7167769SMika Kuoppala #define GEN8_PDE_SHIFT 21 119e7167769SMika Kuoppala #define GEN8_PDE_MASK 0x1ff 120e7167769SMika Kuoppala #define GEN8_PTE_SHIFT 12 121e7167769SMika Kuoppala #define GEN8_PTE_MASK 0x1ff 122e7167769SMika Kuoppala #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 123e7167769SMika Kuoppala 124e7167769SMika Kuoppala /* GEN8 48b style address is defined as a 4 level page table: 12581ba8aefSMichel Thierry * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 12681ba8aefSMichel Thierry * PML4E | PDPE | PDE | PTE | offset 1270260c420SBen Widawsky */ 12881ba8aefSMichel Thierry #define GEN8_PML4ES_PER_PML4 512 12981ba8aefSMichel Thierry #define GEN8_PML4E_SHIFT 39 130762d9936SMichel Thierry #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 1310260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 13281ba8aefSMichel Thierry /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 13381ba8aefSMichel Thierry * tables */ 13481ba8aefSMichel Thierry #define GEN8_PDPE_MASK 0x1ff 1350260c420SBen Widawsky 136c095b97cSZhi Wang #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 137c095b97cSZhi Wang #define PPAT_CACHED_PDE 0 /* WB LLC */ 138c095b97cSZhi Wang #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 139c095b97cSZhi Wang #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 1400260c420SBen Widawsky 141ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1421790625bSMichal Wajdeczko #define GEN8_PPAT_AGE(x) ((x)<<4) 1430260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1440260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1450260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1460260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1470260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1480260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1490260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1500260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 15175c7b0b8SChris Wilson #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1520260c420SBen Widawsky 1534395890aSZhi Wang #define GEN8_PPAT_GET_CA(x) ((x) & 3) 1544395890aSZhi Wang #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 1554395890aSZhi Wang #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 1564395890aSZhi Wang #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 1574395890aSZhi Wang 15817a00cf7SMatthew Auld #define GEN8_PDE_IPS_64K BIT(11) 1590a03852eSMatthew Auld #define GEN8_PDE_PS_2M BIT(7) 1600a03852eSMatthew Auld 161b42fe9caSJoonas Lahtinen struct sg_table; 162b42fe9caSJoonas Lahtinen 16350470bb0STvrtko Ursulin struct intel_rotation_info { 1647ff19c56SChris Wilson struct intel_rotation_plane_info { 1651663b9d6SVille Syrjälä /* tiles */ 1666687c906SVille Syrjälä unsigned int width, height, stride, offset; 1671663b9d6SVille Syrjälä } plane[2]; 1688d9046adSChris Wilson } __packed; 1698d9046adSChris Wilson 1708d9046adSChris Wilson static inline void assert_intel_rotation_info_is_packed(void) 1718d9046adSChris Wilson { 1728d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 1738d9046adSChris Wilson } 174fe14d5f4STvrtko Ursulin 1757ff19c56SChris Wilson struct intel_partial_info { 1767ff19c56SChris Wilson u64 offset; 1777ff19c56SChris Wilson unsigned int size; 1788d9046adSChris Wilson } __packed; 1798d9046adSChris Wilson 1808d9046adSChris Wilson static inline void assert_intel_partial_info_is_packed(void) 1818d9046adSChris Wilson { 1828d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 1838d9046adSChris Wilson } 1847ff19c56SChris Wilson 185992e418dSChris Wilson enum i915_ggtt_view_type { 186992e418dSChris Wilson I915_GGTT_VIEW_NORMAL = 0, 187992e418dSChris Wilson I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 188992e418dSChris Wilson I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 189992e418dSChris Wilson }; 190992e418dSChris Wilson 191992e418dSChris Wilson static inline void assert_i915_ggtt_view_type_is_unique(void) 192992e418dSChris Wilson { 193992e418dSChris Wilson /* As we encode the size of each branch inside the union into its type, 194992e418dSChris Wilson * we have to be careful that each branch has a unique size. 195992e418dSChris Wilson */ 196992e418dSChris Wilson switch ((enum i915_ggtt_view_type)0) { 197992e418dSChris Wilson case I915_GGTT_VIEW_NORMAL: 198992e418dSChris Wilson case I915_GGTT_VIEW_PARTIAL: 199992e418dSChris Wilson case I915_GGTT_VIEW_ROTATED: 200992e418dSChris Wilson /* gcc complains if these are identical cases */ 201992e418dSChris Wilson break; 202992e418dSChris Wilson } 203992e418dSChris Wilson } 204992e418dSChris Wilson 205fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 206fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 2078bd7ef16SJoonas Lahtinen union { 208992e418dSChris Wilson /* Members need to contain no holes/padding */ 2097ff19c56SChris Wilson struct intel_partial_info partial; 2107723f47dSVille Syrjälä struct intel_rotation_info rotated; 2118bab1193SChris Wilson }; 212fe14d5f4STvrtko Ursulin }; 213fe14d5f4STvrtko Ursulin 2140260c420SBen Widawsky enum i915_cache_level; 215fe14d5f4STvrtko Ursulin 216b42fe9caSJoonas Lahtinen struct i915_vma; 217bde13ebdSChris Wilson 21844159ddbSMika Kuoppala struct i915_page_dma { 219d7b3de91SBen Widawsky struct page *page; 220aa095871SMatthew Auld int order; 22144159ddbSMika Kuoppala union { 2227324cc04SBen Widawsky dma_addr_t daddr; 223678d96fbSBen Widawsky 22444159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 22544159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 22644159ddbSMika Kuoppala */ 22775c7b0b8SChris Wilson u32 ggtt_offset; 22844159ddbSMika Kuoppala }; 22944159ddbSMika Kuoppala }; 23044159ddbSMika Kuoppala 231567047beSMika Kuoppala #define px_base(px) (&(px)->base) 232567047beSMika Kuoppala #define px_page(px) (px_base(px)->page) 233567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 234567047beSMika Kuoppala 23544159ddbSMika Kuoppala struct i915_page_table { 23644159ddbSMika Kuoppala struct i915_page_dma base; 237dd19674bSChris Wilson unsigned int used_ptes; 238d7b3de91SBen Widawsky }; 239d7b3de91SBen Widawsky 240ec565b3cSMichel Thierry struct i915_page_directory { 24144159ddbSMika Kuoppala struct i915_page_dma base; 2427324cc04SBen Widawsky 243ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 244fe52e37fSChris Wilson unsigned int used_pdes; 245d7b3de91SBen Widawsky }; 246d7b3de91SBen Widawsky 247ec565b3cSMichel Thierry struct i915_page_directory_pointer { 2486ac18502SMichel Thierry struct i915_page_dma base; 2496ac18502SMichel Thierry struct i915_page_directory **page_directory; 250e2b763caSChris Wilson unsigned int used_pdpes; 251d7b3de91SBen Widawsky }; 252d7b3de91SBen Widawsky 25381ba8aefSMichel Thierry struct i915_pml4 { 25481ba8aefSMichel Thierry struct i915_page_dma base; 25581ba8aefSMichel Thierry struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 25681ba8aefSMichel Thierry }; 25781ba8aefSMichel Thierry 2580260c420SBen Widawsky struct i915_address_space { 2590260c420SBen Widawsky struct drm_mm mm; 26080b204bcSChris Wilson struct i915_gem_timeline timeline; 26149d73912SChris Wilson struct drm_i915_private *i915; 2628448661dSChris Wilson struct device *dma; 2632bfa996eSChris Wilson /* Every address space belongs to a struct file - except for the global 2642bfa996eSChris Wilson * GTT that is owned by the driver (and so @file is set to NULL). In 2652bfa996eSChris Wilson * principle, no information should leak from one context to another 2662bfa996eSChris Wilson * (or between files/processes etc) unless explicitly shared by the 2672bfa996eSChris Wilson * owner. Tracking the owner is important in order to free up per-file 2682bfa996eSChris Wilson * objects along with the file, to aide resource tracking, and to 2692bfa996eSChris Wilson * assign blame. 2702bfa996eSChris Wilson */ 2712bfa996eSChris Wilson struct drm_i915_file_private *file; 2720260c420SBen Widawsky struct list_head global_link; 273c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 274ff8f7975SWeinan Li u64 reserved; /* size addr space reserved */ 2750260c420SBen Widawsky 27650e046b6SChris Wilson bool closed; 27750e046b6SChris Wilson 2788bcdd0f7SChris Wilson struct i915_page_dma scratch_page; 27979ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 28079ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 28169ab76fdSMichel Thierry struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 2820260c420SBen Widawsky 2830260c420SBen Widawsky /** 2840260c420SBen Widawsky * List of objects currently involved in rendering. 2850260c420SBen Widawsky * 2860260c420SBen Widawsky * Includes buffers having the contents of their GPU caches 28797b2a6a1SJohn Harrison * flushed, not necessarily primitives. last_read_req 2880260c420SBen Widawsky * represents when the rendering involved will be completed. 2890260c420SBen Widawsky * 2900260c420SBen Widawsky * A reference is held on the buffer while on this list. 2910260c420SBen Widawsky */ 2920260c420SBen Widawsky struct list_head active_list; 2930260c420SBen Widawsky 2940260c420SBen Widawsky /** 2950260c420SBen Widawsky * LRU list of objects which are not in the ringbuffer and 2960260c420SBen Widawsky * are ready to unbind, but are still in the GTT. 2970260c420SBen Widawsky * 29897b2a6a1SJohn Harrison * last_read_req is NULL while an object is in this list. 2990260c420SBen Widawsky * 3000260c420SBen Widawsky * A reference is not held on the buffer while on this list, 3010260c420SBen Widawsky * as merely being GTT-bound shouldn't prevent its being 3020260c420SBen Widawsky * freed, and we'll pull it off the list in the free path. 3030260c420SBen Widawsky */ 3040260c420SBen Widawsky struct list_head inactive_list; 3050260c420SBen Widawsky 30650e046b6SChris Wilson /** 30750e046b6SChris Wilson * List of vma that have been unbound. 30850e046b6SChris Wilson * 30950e046b6SChris Wilson * A reference is not held on the buffer while on this list. 31050e046b6SChris Wilson */ 31150e046b6SChris Wilson struct list_head unbound_list; 31250e046b6SChris Wilson 3138448661dSChris Wilson struct pagevec free_pages; 3148448661dSChris Wilson bool pt_kmap_wc; 3158448661dSChris Wilson 3160260c420SBen Widawsky /* FIXME: Need a more generic return type */ 31707749ef3SMichel Thierry gen6_pte_t (*pte_encode)(dma_addr_t addr, 3180260c420SBen Widawsky enum i915_cache_level level, 3194fb84d99SMichał Winiarski u32 flags); /* Create a valid PTE */ 320f329f5f6SDaniel Vetter /* flags for pte_encode */ 321f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 322678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 32375c7b0b8SChris Wilson u64 start, u64 length); 3240260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 32575c7b0b8SChris Wilson u64 start, u64 length); 326d6473f56SChris Wilson void (*insert_page)(struct i915_address_space *vm, 327d6473f56SChris Wilson dma_addr_t addr, 32875c7b0b8SChris Wilson u64 offset, 329d6473f56SChris Wilson enum i915_cache_level cache_level, 330d6473f56SChris Wilson u32 flags); 3310260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 3324a234c5fSMatthew Auld struct i915_vma *vma, 33375c7b0b8SChris Wilson enum i915_cache_level cache_level, 33475c7b0b8SChris Wilson u32 flags); 3350260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 336777dc5bbSDaniel Vetter /** Unmap an object from an address space. This usually consists of 337777dc5bbSDaniel Vetter * setting the valid PTE entries to a reserved scratch page. */ 338777dc5bbSDaniel Vetter void (*unbind_vma)(struct i915_vma *vma); 339777dc5bbSDaniel Vetter /* Map an object into an address space with the given cache flags. */ 34070b9f6f8SDaniel Vetter int (*bind_vma)(struct i915_vma *vma, 341777dc5bbSDaniel Vetter enum i915_cache_level cache_level, 342777dc5bbSDaniel Vetter u32 flags); 343fa3f46afSMatthew Auld int (*set_pages)(struct i915_vma *vma); 344fa3f46afSMatthew Auld void (*clear_pages)(struct i915_vma *vma); 3458448661dSChris Wilson 3468448661dSChris Wilson I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 3470260c420SBen Widawsky }; 3480260c420SBen Widawsky 3492bfa996eSChris Wilson #define i915_is_ggtt(V) (!(V)->file) 350596c5923SChris Wilson 3513e490042SMika Kuoppala static inline bool 3523e490042SMika Kuoppala i915_vm_is_48bit(const struct i915_address_space *vm) 3533e490042SMika Kuoppala { 3543e490042SMika Kuoppala return (vm->total - 1) >> 32; 3553e490042SMika Kuoppala } 3563e490042SMika Kuoppala 35717a00cf7SMatthew Auld static inline bool 35817a00cf7SMatthew Auld i915_vm_has_scratch_64K(struct i915_address_space *vm) 35917a00cf7SMatthew Auld { 36017a00cf7SMatthew Auld return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K); 36117a00cf7SMatthew Auld } 36217a00cf7SMatthew Auld 3630260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3640260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3650260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3660260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3670260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3680260c420SBen Widawsky * the spec. 3690260c420SBen Widawsky */ 37062106b4fSJoonas Lahtinen struct i915_ggtt { 3710260c420SBen Widawsky struct i915_address_space base; 3720260c420SBen Widawsky 37373ebd503SMatthew Auld struct io_mapping iomap; /* Mapping to our CPU mappable region */ 37473ebd503SMatthew Auld struct resource gmadr; /* GMADR resource */ 375b7128ef1SMatthew Auld resource_size_t mappable_end; /* End offset that we can CPU map */ 376edd1f2feSChris Wilson 3770260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3780260c420SBen Widawsky void __iomem *gsm; 3797c3f86b6SChris Wilson void (*invalidate)(struct drm_i915_private *dev_priv); 3800260c420SBen Widawsky 3810260c420SBen Widawsky bool do_idle_maps; 3820260c420SBen Widawsky 3830260c420SBen Widawsky int mtrr; 38495374d75SChris Wilson 38595374d75SChris Wilson struct drm_mm_node error_capture; 3860260c420SBen Widawsky }; 3870260c420SBen Widawsky 3880260c420SBen Widawsky struct i915_hw_ppgtt { 3890260c420SBen Widawsky struct i915_address_space base; 3900260c420SBen Widawsky struct kref ref; 3910260c420SBen Widawsky struct drm_mm_node node; 392563222a7SBen Widawsky unsigned long pd_dirty_rings; 3930260c420SBen Widawsky union { 39481ba8aefSMichel Thierry struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 39581ba8aefSMichel Thierry struct i915_page_directory_pointer pdp; /* GEN8+ */ 39681ba8aefSMichel Thierry struct i915_page_directory pd; /* GEN6-7 */ 397d7b3de91SBen Widawsky }; 3980260c420SBen Widawsky 399678d96fbSBen Widawsky gen6_pte_t __iomem *pd_addr; 400678d96fbSBen Widawsky 4010260c420SBen Widawsky int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 402e61e0f51SChris Wilson struct i915_request *rq); 4030260c420SBen Widawsky void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 4040260c420SBen Widawsky }; 4050260c420SBen Widawsky 406731f74c5SDave Gordon /* 407731f74c5SDave Gordon * gen6_for_each_pde() iterates over every pde from start until start+length. 408731f74c5SDave Gordon * If start and start+length are not perfectly divisible, the macro will round 409731f74c5SDave Gordon * down and up as needed. Start=0 and length=2G effectively iterates over 410731f74c5SDave Gordon * every PDE in the system. The macro modifies ALL its parameters except 'pd', 411731f74c5SDave Gordon * so each of the other parameters should preferably be a simple variable, or 412731f74c5SDave Gordon * at most an lvalue with no side-effects! 413678d96fbSBen Widawsky */ 414731f74c5SDave Gordon #define gen6_for_each_pde(pt, pd, start, length, iter) \ 415fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 416731f74c5SDave Gordon length > 0 && iter < I915_PDES && \ 417731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 418731f74c5SDave Gordon ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 419731f74c5SDave Gordon temp = min(temp - start, length); \ 420731f74c5SDave Gordon start += temp, length -= temp; }), ++iter) 421678d96fbSBen Widawsky 422731f74c5SDave Gordon #define gen6_for_all_pdes(pt, pd, iter) \ 42309942c65SMichel Thierry for (iter = 0; \ 424731f74c5SDave Gordon iter < I915_PDES && \ 425731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 426731f74c5SDave Gordon ++iter) 42709942c65SMichel Thierry 42875c7b0b8SChris Wilson static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 429678d96fbSBen Widawsky { 43075c7b0b8SChris Wilson const u32 mask = NUM_PTE(pde_shift) - 1; 431678d96fbSBen Widawsky 432678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 433678d96fbSBen Widawsky } 434678d96fbSBen Widawsky 435678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 436678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 437678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 438678d96fbSBen Widawsky */ 43975c7b0b8SChris Wilson static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 440678d96fbSBen Widawsky { 44175c7b0b8SChris Wilson const u64 mask = ~((1ULL << pde_shift) - 1); 44275c7b0b8SChris Wilson u64 end; 443678d96fbSBen Widawsky 444678d96fbSBen Widawsky WARN_ON(length == 0); 445678d96fbSBen Widawsky WARN_ON(offset_in_page(addr|length)); 446678d96fbSBen Widawsky 447678d96fbSBen Widawsky end = addr + length; 448678d96fbSBen Widawsky 449678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 450678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 451678d96fbSBen Widawsky 452678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 453678d96fbSBen Widawsky } 454678d96fbSBen Widawsky 45575c7b0b8SChris Wilson static inline u32 i915_pde_index(u64 addr, u32 shift) 456678d96fbSBen Widawsky { 457678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 458678d96fbSBen Widawsky } 459678d96fbSBen Widawsky 46075c7b0b8SChris Wilson static inline u32 gen6_pte_index(u32 addr) 461678d96fbSBen Widawsky { 462678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 463678d96fbSBen Widawsky } 464678d96fbSBen Widawsky 46575c7b0b8SChris Wilson static inline u32 gen6_pte_count(u32 addr, u32 length) 466678d96fbSBen Widawsky { 467678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 468678d96fbSBen Widawsky } 469678d96fbSBen Widawsky 47075c7b0b8SChris Wilson static inline u32 gen6_pde_index(u32 addr) 471678d96fbSBen Widawsky { 472678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 473678d96fbSBen Widawsky } 474678d96fbSBen Widawsky 4753e490042SMika Kuoppala static inline unsigned int 4763e490042SMika Kuoppala i915_pdpes_per_pdp(const struct i915_address_space *vm) 4773e490042SMika Kuoppala { 4783e490042SMika Kuoppala if (i915_vm_is_48bit(vm)) 4793e490042SMika Kuoppala return GEN8_PML4ES_PER_PML4; 4803e490042SMika Kuoppala 481e7167769SMika Kuoppala return GEN8_3LVL_PDPES; 4823e490042SMika Kuoppala } 4833e490042SMika Kuoppala 4849271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4859271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4869271d959SMichel Thierry * over every page directory entry in a page directory. 4879271d959SMichel Thierry */ 488e8ebd8e2SDave Gordon #define gen8_for_each_pde(pt, pd, start, length, iter) \ 4899271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 490e8ebd8e2SDave Gordon length > 0 && iter < I915_PDES && \ 491e8ebd8e2SDave Gordon (pt = (pd)->page_table[iter], true); \ 492e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 493e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 494e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4959271d959SMichel Thierry 496e8ebd8e2SDave Gordon #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 4979271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 4983e490042SMika Kuoppala length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 499e8ebd8e2SDave Gordon (pd = (pdp)->page_directory[iter], true); \ 500e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 501e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 502e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 5039271d959SMichel Thierry 504e8ebd8e2SDave Gordon #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 505762d9936SMichel Thierry for (iter = gen8_pml4e_index(start); \ 506e8ebd8e2SDave Gordon length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 507e8ebd8e2SDave Gordon (pdp = (pml4)->pdps[iter], true); \ 508e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 509e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 510e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 511762d9936SMichel Thierry 51275c7b0b8SChris Wilson static inline u32 gen8_pte_index(u64 address) 5139271d959SMichel Thierry { 5149271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 5159271d959SMichel Thierry } 5169271d959SMichel Thierry 51775c7b0b8SChris Wilson static inline u32 gen8_pde_index(u64 address) 5189271d959SMichel Thierry { 5199271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 5209271d959SMichel Thierry } 5219271d959SMichel Thierry 52275c7b0b8SChris Wilson static inline u32 gen8_pdpe_index(u64 address) 5239271d959SMichel Thierry { 5249271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 5259271d959SMichel Thierry } 5269271d959SMichel Thierry 52775c7b0b8SChris Wilson static inline u32 gen8_pml4e_index(u64 address) 5289271d959SMichel Thierry { 529762d9936SMichel Thierry return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 5309271d959SMichel Thierry } 5319271d959SMichel Thierry 53275c7b0b8SChris Wilson static inline u64 gen8_pte_count(u64 address, u64 length) 53333c8819fSMichel Thierry { 53433c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 53533c8819fSMichel Thierry } 53633c8819fSMichel Thierry 537d852c7bfSMika Kuoppala static inline dma_addr_t 538d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 539d852c7bfSMika Kuoppala { 540fe52e37fSChris Wilson return px_dma(ppgtt->pdp.page_directory[n]); 541d852c7bfSMika Kuoppala } 542d852c7bfSMika Kuoppala 543b42fe9caSJoonas Lahtinen static inline struct i915_ggtt * 544b42fe9caSJoonas Lahtinen i915_vm_to_ggtt(struct i915_address_space *vm) 545b42fe9caSJoonas Lahtinen { 546b42fe9caSJoonas Lahtinen GEM_BUG_ON(!i915_is_ggtt(vm)); 547b42fe9caSJoonas Lahtinen return container_of(vm, struct i915_ggtt, base); 548b42fe9caSJoonas Lahtinen } 549b42fe9caSJoonas Lahtinen 5504395890aSZhi Wang #define INTEL_MAX_PPAT_ENTRIES 8 5514395890aSZhi Wang #define INTEL_PPAT_PERFECT_MATCH (~0U) 5524395890aSZhi Wang 5534395890aSZhi Wang struct intel_ppat; 5544395890aSZhi Wang 5554395890aSZhi Wang struct intel_ppat_entry { 5564395890aSZhi Wang struct intel_ppat *ppat; 5574395890aSZhi Wang struct kref ref; 5584395890aSZhi Wang u8 value; 5594395890aSZhi Wang }; 5604395890aSZhi Wang 5614395890aSZhi Wang struct intel_ppat { 5624395890aSZhi Wang struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 5634395890aSZhi Wang DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 5644395890aSZhi Wang DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 5654395890aSZhi Wang unsigned int max_entries; 5664395890aSZhi Wang u8 clear_value; 5674395890aSZhi Wang /* 5684395890aSZhi Wang * Return a score to show how two PPAT values match, 5694395890aSZhi Wang * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 5704395890aSZhi Wang */ 5714395890aSZhi Wang unsigned int (*match)(u8 src, u8 dst); 5724395890aSZhi Wang void (*update_hw)(struct drm_i915_private *i915); 5734395890aSZhi Wang 5744395890aSZhi Wang struct drm_i915_private *i915; 5754395890aSZhi Wang }; 5764395890aSZhi Wang 5774395890aSZhi Wang const struct intel_ppat_entry * 5784395890aSZhi Wang intel_ppat_get(struct drm_i915_private *i915, u8 value); 5794395890aSZhi Wang void intel_ppat_put(const struct intel_ppat_entry *entry); 5804395890aSZhi Wang 5816cde9a02SChris Wilson int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 5826cde9a02SChris Wilson void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 5836cde9a02SChris Wilson 58497d6d7abSChris Wilson int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 58597d6d7abSChris Wilson int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 58697d6d7abSChris Wilson int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 5877c3f86b6SChris Wilson void i915_ggtt_enable_guc(struct drm_i915_private *i915); 5887c3f86b6SChris Wilson void i915_ggtt_disable_guc(struct drm_i915_private *i915); 589f6b9d5caSChris Wilson int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 59097d6d7abSChris Wilson void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 591ee960be7SDaniel Vetter 592c6be607aSTvrtko Ursulin int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 593ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 5942bfa996eSChris Wilson struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 59580b204bcSChris Wilson struct drm_i915_file_private *fpriv, 59680b204bcSChris Wilson const char *name); 5970c7eeda1SChris Wilson void i915_ppgtt_close(struct i915_address_space *vm); 598ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 599ee960be7SDaniel Vetter { 600ee960be7SDaniel Vetter if (ppgtt) 601ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 602ee960be7SDaniel Vetter } 603ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 604ee960be7SDaniel Vetter { 605ee960be7SDaniel Vetter if (ppgtt) 606ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 607ee960be7SDaniel Vetter } 6080260c420SBen Widawsky 609dc97997aSChris Wilson void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 610275a991cSTvrtko Ursulin void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 611275a991cSTvrtko Ursulin void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 6120260c420SBen Widawsky 61303ac84f1SChris Wilson int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 61403ac84f1SChris Wilson struct sg_table *pages); 61503ac84f1SChris Wilson void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 61603ac84f1SChris Wilson struct sg_table *pages); 6170260c420SBen Widawsky 618625d988aSChris Wilson int i915_gem_gtt_reserve(struct i915_address_space *vm, 619625d988aSChris Wilson struct drm_mm_node *node, 620625d988aSChris Wilson u64 size, u64 offset, unsigned long color, 621625d988aSChris Wilson unsigned int flags); 622625d988aSChris Wilson 623e007b19dSChris Wilson int i915_gem_gtt_insert(struct i915_address_space *vm, 624e007b19dSChris Wilson struct drm_mm_node *node, 625e007b19dSChris Wilson u64 size, u64 alignment, unsigned long color, 626e007b19dSChris Wilson u64 start, u64 end, unsigned int flags); 627e007b19dSChris Wilson 62859bfa124SChris Wilson /* Flags used by pin/bind&friends. */ 629305bc234SChris Wilson #define PIN_NONBLOCK BIT(0) 630305bc234SChris Wilson #define PIN_MAPPABLE BIT(1) 631305bc234SChris Wilson #define PIN_ZONE_4G BIT(2) 63282118877SChris Wilson #define PIN_NONFAULT BIT(3) 633616d9ceeSChris Wilson #define PIN_NOEVICT BIT(4) 634305bc234SChris Wilson 635305bc234SChris Wilson #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 636305bc234SChris Wilson #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 637305bc234SChris Wilson #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 638305bc234SChris Wilson #define PIN_UPDATE BIT(8) 639305bc234SChris Wilson 640305bc234SChris Wilson #define PIN_HIGH BIT(9) 641305bc234SChris Wilson #define PIN_OFFSET_BIAS BIT(10) 642305bc234SChris Wilson #define PIN_OFFSET_FIXED BIT(11) 643f51455d4SChris Wilson #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 64459bfa124SChris Wilson 6450260c420SBen Widawsky #endif 646