10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 378ef8561fSChris Wilson #include <linux/io-mapping.h> 38b42fe9caSJoonas Lahtinen #include <linux/mm.h> 398448661dSChris Wilson #include <linux/pagevec.h> 408ef8561fSChris Wilson 41e61e0f51SChris Wilson #include "i915_request.h" 42eb8d0f5aSChris Wilson #include "i915_reset.h" 438448661dSChris Wilson #include "i915_selftest.h" 44a89d1f92SChris Wilson #include "i915_timeline.h" 45b0decaf7SChris Wilson 469125963aSChris Wilson #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 479125963aSChris Wilson #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 489125963aSChris Wilson #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 492a9654b2SMatthew Auld 502a9654b2SMatthew Auld #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 512a9654b2SMatthew Auld #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 522a9654b2SMatthew Auld 536fc4e48fSChris Wilson #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 546fc4e48fSChris Wilson 55f51455d4SChris Wilson #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 56f51455d4SChris Wilson 5749ef5294SChris Wilson #define I915_FENCE_REG_NONE -1 5849ef5294SChris Wilson #define I915_MAX_NUM_FENCES 32 5949ef5294SChris Wilson /* 32 fences + sign bit for FENCE_REG_NONE */ 6049ef5294SChris Wilson #define I915_MAX_NUM_FENCE_BITS 6 6149ef5294SChris Wilson 624d884705SDaniel Vetter struct drm_i915_file_private; 6349ef5294SChris Wilson struct drm_i915_fence_reg; 6493f2cde2SChris Wilson struct i915_vma; 654d884705SDaniel Vetter 6675c7b0b8SChris Wilson typedef u32 gen6_pte_t; 6775c7b0b8SChris Wilson typedef u64 gen8_pte_t; 6875c7b0b8SChris Wilson typedef u64 gen8_pde_t; 6975c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pdpe_t; 7075c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pml4e_t; 710260c420SBen Widawsky 7282ad6443SChris Wilson #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 730260c420SBen Widawsky 740260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 750260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 760260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 770260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 780260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 790260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 800260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 810260c420SBen Widawsky 82dd19674bSChris Wilson #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 8307749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 8407749ef3SMichel Thierry #define I915_PDES 512 8507749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 86678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 8707749ef3SMichel Thierry 8807749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 8907749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 900260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 91678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 920260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 930260c420SBen Widawsky 940260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 950260c420SBen Widawsky 960260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 970260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 980260c420SBen Widawsky 990260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 1000260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 1010260c420SBen Widawsky */ 1020260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 1030260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 1040260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 1050260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 1060260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 1070260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 1080260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 1090260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1100260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 1110260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1120260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1130260c420SBen Widawsky 114e7167769SMika Kuoppala /* GEN8 32b style address is defined as a 3 level page table: 1150260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 1160260c420SBen Widawsky * PDPE | PDE | PTE | offset 1170260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 1180260c420SBen Widawsky * programmed via register. 119e7167769SMika Kuoppala */ 120e7167769SMika Kuoppala #define GEN8_3LVL_PDPES 4 121e7167769SMika Kuoppala #define GEN8_PDE_SHIFT 21 122e7167769SMika Kuoppala #define GEN8_PDE_MASK 0x1ff 123e7167769SMika Kuoppala #define GEN8_PTE_SHIFT 12 124e7167769SMika Kuoppala #define GEN8_PTE_MASK 0x1ff 125e7167769SMika Kuoppala #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 126e7167769SMika Kuoppala 127e7167769SMika Kuoppala /* GEN8 48b style address is defined as a 4 level page table: 12881ba8aefSMichel Thierry * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 12981ba8aefSMichel Thierry * PML4E | PDPE | PDE | PTE | offset 1300260c420SBen Widawsky */ 13181ba8aefSMichel Thierry #define GEN8_PML4ES_PER_PML4 512 13281ba8aefSMichel Thierry #define GEN8_PML4E_SHIFT 39 133762d9936SMichel Thierry #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 1340260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 13581ba8aefSMichel Thierry /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 13681ba8aefSMichel Thierry * tables */ 13781ba8aefSMichel Thierry #define GEN8_PDPE_MASK 0x1ff 1380260c420SBen Widawsky 139c095b97cSZhi Wang #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 140c095b97cSZhi Wang #define PPAT_CACHED_PDE 0 /* WB LLC */ 141c095b97cSZhi Wang #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 142c095b97cSZhi Wang #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 1430260c420SBen Widawsky 144ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1451790625bSMichal Wajdeczko #define GEN8_PPAT_AGE(x) ((x)<<4) 1460260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1470260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1480260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1490260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1500260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1510260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1520260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1530260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 15475c7b0b8SChris Wilson #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1550260c420SBen Widawsky 1564395890aSZhi Wang #define GEN8_PPAT_GET_CA(x) ((x) & 3) 1574395890aSZhi Wang #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 1584395890aSZhi Wang #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 1594395890aSZhi Wang #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 1604395890aSZhi Wang 16117a00cf7SMatthew Auld #define GEN8_PDE_IPS_64K BIT(11) 1620a03852eSMatthew Auld #define GEN8_PDE_PS_2M BIT(7) 1630a03852eSMatthew Auld 164b42fe9caSJoonas Lahtinen struct sg_table; 165b42fe9caSJoonas Lahtinen 16650470bb0STvrtko Ursulin struct intel_rotation_info { 1677ff19c56SChris Wilson struct intel_rotation_plane_info { 1681663b9d6SVille Syrjälä /* tiles */ 1696687c906SVille Syrjälä unsigned int width, height, stride, offset; 1701663b9d6SVille Syrjälä } plane[2]; 1718d9046adSChris Wilson } __packed; 1728d9046adSChris Wilson 1737ff19c56SChris Wilson struct intel_partial_info { 1747ff19c56SChris Wilson u64 offset; 1757ff19c56SChris Wilson unsigned int size; 1768d9046adSChris Wilson } __packed; 1778d9046adSChris Wilson 178992e418dSChris Wilson enum i915_ggtt_view_type { 179992e418dSChris Wilson I915_GGTT_VIEW_NORMAL = 0, 180992e418dSChris Wilson I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 181992e418dSChris Wilson I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 182992e418dSChris Wilson }; 183992e418dSChris Wilson 184ed11e415SVille Syrjälä static inline void assert_i915_gem_gtt_types(void) 185992e418dSChris Wilson { 186ed11e415SVille Syrjälä BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 187ed11e415SVille Syrjälä BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 188ed11e415SVille Syrjälä 189992e418dSChris Wilson /* As we encode the size of each branch inside the union into its type, 190992e418dSChris Wilson * we have to be careful that each branch has a unique size. 191992e418dSChris Wilson */ 192992e418dSChris Wilson switch ((enum i915_ggtt_view_type)0) { 193992e418dSChris Wilson case I915_GGTT_VIEW_NORMAL: 194992e418dSChris Wilson case I915_GGTT_VIEW_PARTIAL: 195992e418dSChris Wilson case I915_GGTT_VIEW_ROTATED: 196992e418dSChris Wilson /* gcc complains if these are identical cases */ 197992e418dSChris Wilson break; 198992e418dSChris Wilson } 199992e418dSChris Wilson } 200992e418dSChris Wilson 201fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 202fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 2038bd7ef16SJoonas Lahtinen union { 204992e418dSChris Wilson /* Members need to contain no holes/padding */ 2057ff19c56SChris Wilson struct intel_partial_info partial; 2067723f47dSVille Syrjälä struct intel_rotation_info rotated; 2078bab1193SChris Wilson }; 208fe14d5f4STvrtko Ursulin }; 209fe14d5f4STvrtko Ursulin 2100260c420SBen Widawsky enum i915_cache_level; 211fe14d5f4STvrtko Ursulin 212b42fe9caSJoonas Lahtinen struct i915_vma; 213bde13ebdSChris Wilson 21444159ddbSMika Kuoppala struct i915_page_dma { 215d7b3de91SBen Widawsky struct page *page; 216aa095871SMatthew Auld int order; 21744159ddbSMika Kuoppala union { 2187324cc04SBen Widawsky dma_addr_t daddr; 219678d96fbSBen Widawsky 22044159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 22144159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 22244159ddbSMika Kuoppala */ 22375c7b0b8SChris Wilson u32 ggtt_offset; 22444159ddbSMika Kuoppala }; 22544159ddbSMika Kuoppala }; 22644159ddbSMika Kuoppala 227567047beSMika Kuoppala #define px_base(px) (&(px)->base) 228567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 229567047beSMika Kuoppala 23044159ddbSMika Kuoppala struct i915_page_table { 23144159ddbSMika Kuoppala struct i915_page_dma base; 232dd19674bSChris Wilson unsigned int used_ptes; 233d7b3de91SBen Widawsky }; 234d7b3de91SBen Widawsky 235ec565b3cSMichel Thierry struct i915_page_directory { 23644159ddbSMika Kuoppala struct i915_page_dma base; 2377324cc04SBen Widawsky 238ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 239fe52e37fSChris Wilson unsigned int used_pdes; 240d7b3de91SBen Widawsky }; 241d7b3de91SBen Widawsky 242ec565b3cSMichel Thierry struct i915_page_directory_pointer { 2436ac18502SMichel Thierry struct i915_page_dma base; 2446ac18502SMichel Thierry struct i915_page_directory **page_directory; 245e2b763caSChris Wilson unsigned int used_pdpes; 246d7b3de91SBen Widawsky }; 247d7b3de91SBen Widawsky 24881ba8aefSMichel Thierry struct i915_pml4 { 24981ba8aefSMichel Thierry struct i915_page_dma base; 25081ba8aefSMichel Thierry struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 25181ba8aefSMichel Thierry }; 25281ba8aefSMichel Thierry 25393f2cde2SChris Wilson struct i915_vma_ops { 25493f2cde2SChris Wilson /* Map an object into an address space with the given cache flags. */ 25593f2cde2SChris Wilson int (*bind_vma)(struct i915_vma *vma, 25693f2cde2SChris Wilson enum i915_cache_level cache_level, 25793f2cde2SChris Wilson u32 flags); 25893f2cde2SChris Wilson /* 25993f2cde2SChris Wilson * Unmap an object from an address space. This usually consists of 26093f2cde2SChris Wilson * setting the valid PTE entries to a reserved scratch page. 26193f2cde2SChris Wilson */ 26293f2cde2SChris Wilson void (*unbind_vma)(struct i915_vma *vma); 26393f2cde2SChris Wilson 26493f2cde2SChris Wilson int (*set_pages)(struct i915_vma *vma); 26593f2cde2SChris Wilson void (*clear_pages)(struct i915_vma *vma); 26693f2cde2SChris Wilson }; 26793f2cde2SChris Wilson 26863fd659fSChris Wilson struct pagestash { 26963fd659fSChris Wilson spinlock_t lock; 27063fd659fSChris Wilson struct pagevec pvec; 27163fd659fSChris Wilson }; 27263fd659fSChris Wilson 2730260c420SBen Widawsky struct i915_address_space { 2740260c420SBen Widawsky struct drm_mm mm; 27549d73912SChris Wilson struct drm_i915_private *i915; 2768448661dSChris Wilson struct device *dma; 2772bfa996eSChris Wilson /* Every address space belongs to a struct file - except for the global 2782bfa996eSChris Wilson * GTT that is owned by the driver (and so @file is set to NULL). In 2792bfa996eSChris Wilson * principle, no information should leak from one context to another 2802bfa996eSChris Wilson * (or between files/processes etc) unless explicitly shared by the 2812bfa996eSChris Wilson * owner. Tracking the owner is important in order to free up per-file 2822bfa996eSChris Wilson * objects along with the file, to aide resource tracking, and to 2832bfa996eSChris Wilson * assign blame. 2842bfa996eSChris Wilson */ 2852bfa996eSChris Wilson struct drm_i915_file_private *file; 286c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 287ff8f7975SWeinan Li u64 reserved; /* size addr space reserved */ 2880260c420SBen Widawsky 28950e046b6SChris Wilson bool closed; 29050e046b6SChris Wilson 29119bb33c7SChris Wilson struct mutex mutex; /* protects vma and our lists */ 292305dc3f9SChris Wilson #define VM_CLASS_GGTT 0 293305dc3f9SChris Wilson #define VM_CLASS_PPGTT 1 29419bb33c7SChris Wilson 295daf3dc0fSChris Wilson u64 scratch_pte; 2968bcdd0f7SChris Wilson struct i915_page_dma scratch_page; 29779ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 29879ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 29969ab76fdSMichel Thierry struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 3000260c420SBen Widawsky 3010260c420SBen Widawsky /** 302499197dcSChris Wilson * List of vma currently bound. 3030260c420SBen Widawsky */ 304499197dcSChris Wilson struct list_head bound_list; 3050260c420SBen Widawsky 3060260c420SBen Widawsky /** 307499197dcSChris Wilson * List of vma that are not unbound. 30850e046b6SChris Wilson */ 30950e046b6SChris Wilson struct list_head unbound_list; 31050e046b6SChris Wilson 31163fd659fSChris Wilson struct pagestash free_pages; 312250f8c81SJon Bloomfield 31348e90504STvrtko Ursulin /* Global GTT */ 31448e90504STvrtko Ursulin bool is_ggtt:1; 31548e90504STvrtko Ursulin 316250f8c81SJon Bloomfield /* Some systems require uncached updates of the page directories */ 317250f8c81SJon Bloomfield bool pt_kmap_wc:1; 318250f8c81SJon Bloomfield 319250f8c81SJon Bloomfield /* Some systems support read-only mappings for GGTT and/or PPGTT */ 320250f8c81SJon Bloomfield bool has_read_only:1; 3218448661dSChris Wilson 322daf3dc0fSChris Wilson u64 (*pte_encode)(dma_addr_t addr, 3230260c420SBen Widawsky enum i915_cache_level level, 3244fb84d99SMichał Winiarski u32 flags); /* Create a valid PTE */ 325f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 326daf3dc0fSChris Wilson 327678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 32875c7b0b8SChris Wilson u64 start, u64 length); 3290260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 33075c7b0b8SChris Wilson u64 start, u64 length); 331d6473f56SChris Wilson void (*insert_page)(struct i915_address_space *vm, 332d6473f56SChris Wilson dma_addr_t addr, 33375c7b0b8SChris Wilson u64 offset, 334d6473f56SChris Wilson enum i915_cache_level cache_level, 335d6473f56SChris Wilson u32 flags); 3360260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 3374a234c5fSMatthew Auld struct i915_vma *vma, 33875c7b0b8SChris Wilson enum i915_cache_level cache_level, 33975c7b0b8SChris Wilson u32 flags); 3400260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 34193f2cde2SChris Wilson 34293f2cde2SChris Wilson struct i915_vma_ops vma_ops; 3438448661dSChris Wilson 3448448661dSChris Wilson I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 345f79401b4SMatthew Auld I915_SELFTEST_DECLARE(bool scrub_64K); 3460260c420SBen Widawsky }; 3470260c420SBen Widawsky 34848e90504STvrtko Ursulin #define i915_is_ggtt(vm) ((vm)->is_ggtt) 349596c5923SChris Wilson 3503e490042SMika Kuoppala static inline bool 3513e490042SMika Kuoppala i915_vm_is_48bit(const struct i915_address_space *vm) 3523e490042SMika Kuoppala { 3533e490042SMika Kuoppala return (vm->total - 1) >> 32; 3543e490042SMika Kuoppala } 3553e490042SMika Kuoppala 35617a00cf7SMatthew Auld static inline bool 35717a00cf7SMatthew Auld i915_vm_has_scratch_64K(struct i915_address_space *vm) 35817a00cf7SMatthew Auld { 35917a00cf7SMatthew Auld return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K); 36017a00cf7SMatthew Auld } 36117a00cf7SMatthew Auld 3620260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3630260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3640260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3650260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3660260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3670260c420SBen Widawsky * the spec. 3680260c420SBen Widawsky */ 36962106b4fSJoonas Lahtinen struct i915_ggtt { 37082ad6443SChris Wilson struct i915_address_space vm; 3710260c420SBen Widawsky 37273ebd503SMatthew Auld struct io_mapping iomap; /* Mapping to our CPU mappable region */ 37373ebd503SMatthew Auld struct resource gmadr; /* GMADR resource */ 374b7128ef1SMatthew Auld resource_size_t mappable_end; /* End offset that we can CPU map */ 375edd1f2feSChris Wilson 3760260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3770260c420SBen Widawsky void __iomem *gsm; 3787c3f86b6SChris Wilson void (*invalidate)(struct drm_i915_private *dev_priv); 3790260c420SBen Widawsky 3800260c420SBen Widawsky bool do_idle_maps; 3810260c420SBen Widawsky 3820260c420SBen Widawsky int mtrr; 38395374d75SChris Wilson 384dd18cedfSJakub Bartmiński u32 pin_bias; 385dd18cedfSJakub Bartmiński 38695374d75SChris Wilson struct drm_mm_node error_capture; 3870260c420SBen Widawsky }; 3880260c420SBen Widawsky 3890260c420SBen Widawsky struct i915_hw_ppgtt { 39082ad6443SChris Wilson struct i915_address_space vm; 3910260c420SBen Widawsky struct kref ref; 39235ac40d8SChris Wilson 393563222a7SBen Widawsky unsigned long pd_dirty_rings; 3940260c420SBen Widawsky union { 39581ba8aefSMichel Thierry struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 39681ba8aefSMichel Thierry struct i915_page_directory_pointer pdp; /* GEN8+ */ 39781ba8aefSMichel Thierry struct i915_page_directory pd; /* GEN6-7 */ 398d7b3de91SBen Widawsky }; 3990260c420SBen Widawsky }; 4000260c420SBen Widawsky 40135ac40d8SChris Wilson struct gen6_hw_ppgtt { 40235ac40d8SChris Wilson struct i915_hw_ppgtt base; 40335ac40d8SChris Wilson 404e9e7dc41SChris Wilson struct i915_vma *vma; 40535ac40d8SChris Wilson gen6_pte_t __iomem *pd_addr; 406a2bbf714SChris Wilson 407a2bbf714SChris Wilson unsigned int pin_count; 4084a192c7eSChris Wilson bool scan_for_unused_pt; 40935ac40d8SChris Wilson }; 41035ac40d8SChris Wilson 41135ac40d8SChris Wilson #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base) 41235ac40d8SChris Wilson 41335ac40d8SChris Wilson static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base) 41435ac40d8SChris Wilson { 41535ac40d8SChris Wilson BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base)); 41635ac40d8SChris Wilson return __to_gen6_ppgtt(base); 41735ac40d8SChris Wilson } 41835ac40d8SChris Wilson 419731f74c5SDave Gordon /* 420731f74c5SDave Gordon * gen6_for_each_pde() iterates over every pde from start until start+length. 421731f74c5SDave Gordon * If start and start+length are not perfectly divisible, the macro will round 422731f74c5SDave Gordon * down and up as needed. Start=0 and length=2G effectively iterates over 423731f74c5SDave Gordon * every PDE in the system. The macro modifies ALL its parameters except 'pd', 424731f74c5SDave Gordon * so each of the other parameters should preferably be a simple variable, or 425731f74c5SDave Gordon * at most an lvalue with no side-effects! 426678d96fbSBen Widawsky */ 427731f74c5SDave Gordon #define gen6_for_each_pde(pt, pd, start, length, iter) \ 428fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 429731f74c5SDave Gordon length > 0 && iter < I915_PDES && \ 430731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 431731f74c5SDave Gordon ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 432731f74c5SDave Gordon temp = min(temp - start, length); \ 433731f74c5SDave Gordon start += temp, length -= temp; }), ++iter) 434678d96fbSBen Widawsky 435731f74c5SDave Gordon #define gen6_for_all_pdes(pt, pd, iter) \ 43609942c65SMichel Thierry for (iter = 0; \ 437731f74c5SDave Gordon iter < I915_PDES && \ 438731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 439731f74c5SDave Gordon ++iter) 44009942c65SMichel Thierry 44175c7b0b8SChris Wilson static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 442678d96fbSBen Widawsky { 44375c7b0b8SChris Wilson const u32 mask = NUM_PTE(pde_shift) - 1; 444678d96fbSBen Widawsky 445678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 446678d96fbSBen Widawsky } 447678d96fbSBen Widawsky 448678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 449678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 450678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 451678d96fbSBen Widawsky */ 45275c7b0b8SChris Wilson static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 453678d96fbSBen Widawsky { 45475c7b0b8SChris Wilson const u64 mask = ~((1ULL << pde_shift) - 1); 45575c7b0b8SChris Wilson u64 end; 456678d96fbSBen Widawsky 457a0fbacb5SChris Wilson GEM_BUG_ON(length == 0); 458a0fbacb5SChris Wilson GEM_BUG_ON(offset_in_page(addr | length)); 459678d96fbSBen Widawsky 460678d96fbSBen Widawsky end = addr + length; 461678d96fbSBen Widawsky 462678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 463678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 464678d96fbSBen Widawsky 465678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 466678d96fbSBen Widawsky } 467678d96fbSBen Widawsky 46875c7b0b8SChris Wilson static inline u32 i915_pde_index(u64 addr, u32 shift) 469678d96fbSBen Widawsky { 470678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 471678d96fbSBen Widawsky } 472678d96fbSBen Widawsky 47375c7b0b8SChris Wilson static inline u32 gen6_pte_index(u32 addr) 474678d96fbSBen Widawsky { 475678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 476678d96fbSBen Widawsky } 477678d96fbSBen Widawsky 47875c7b0b8SChris Wilson static inline u32 gen6_pte_count(u32 addr, u32 length) 479678d96fbSBen Widawsky { 480678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 481678d96fbSBen Widawsky } 482678d96fbSBen Widawsky 48375c7b0b8SChris Wilson static inline u32 gen6_pde_index(u32 addr) 484678d96fbSBen Widawsky { 485678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 486678d96fbSBen Widawsky } 487678d96fbSBen Widawsky 4883e490042SMika Kuoppala static inline unsigned int 4893e490042SMika Kuoppala i915_pdpes_per_pdp(const struct i915_address_space *vm) 4903e490042SMika Kuoppala { 4913e490042SMika Kuoppala if (i915_vm_is_48bit(vm)) 4923e490042SMika Kuoppala return GEN8_PML4ES_PER_PML4; 4933e490042SMika Kuoppala 494e7167769SMika Kuoppala return GEN8_3LVL_PDPES; 4953e490042SMika Kuoppala } 4963e490042SMika Kuoppala 4979271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4989271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4999271d959SMichel Thierry * over every page directory entry in a page directory. 5009271d959SMichel Thierry */ 501e8ebd8e2SDave Gordon #define gen8_for_each_pde(pt, pd, start, length, iter) \ 5029271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 503e8ebd8e2SDave Gordon length > 0 && iter < I915_PDES && \ 504e8ebd8e2SDave Gordon (pt = (pd)->page_table[iter], true); \ 505e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 506e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 507e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 5089271d959SMichel Thierry 509e8ebd8e2SDave Gordon #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 5109271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 5113e490042SMika Kuoppala length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 512e8ebd8e2SDave Gordon (pd = (pdp)->page_directory[iter], true); \ 513e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 514e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 515e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 5169271d959SMichel Thierry 517e8ebd8e2SDave Gordon #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 518762d9936SMichel Thierry for (iter = gen8_pml4e_index(start); \ 519e8ebd8e2SDave Gordon length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 520e8ebd8e2SDave Gordon (pdp = (pml4)->pdps[iter], true); \ 521e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 522e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 523e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 524762d9936SMichel Thierry 52575c7b0b8SChris Wilson static inline u32 gen8_pte_index(u64 address) 5269271d959SMichel Thierry { 5279271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 5289271d959SMichel Thierry } 5299271d959SMichel Thierry 53075c7b0b8SChris Wilson static inline u32 gen8_pde_index(u64 address) 5319271d959SMichel Thierry { 5329271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 5339271d959SMichel Thierry } 5349271d959SMichel Thierry 53575c7b0b8SChris Wilson static inline u32 gen8_pdpe_index(u64 address) 5369271d959SMichel Thierry { 5379271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 5389271d959SMichel Thierry } 5399271d959SMichel Thierry 54075c7b0b8SChris Wilson static inline u32 gen8_pml4e_index(u64 address) 5419271d959SMichel Thierry { 542762d9936SMichel Thierry return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 5439271d959SMichel Thierry } 5449271d959SMichel Thierry 54575c7b0b8SChris Wilson static inline u64 gen8_pte_count(u64 address, u64 length) 54633c8819fSMichel Thierry { 54733c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 54833c8819fSMichel Thierry } 54933c8819fSMichel Thierry 550d852c7bfSMika Kuoppala static inline dma_addr_t 551d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 552d852c7bfSMika Kuoppala { 553fe52e37fSChris Wilson return px_dma(ppgtt->pdp.page_directory[n]); 554d852c7bfSMika Kuoppala } 555d852c7bfSMika Kuoppala 556b42fe9caSJoonas Lahtinen static inline struct i915_ggtt * 557b42fe9caSJoonas Lahtinen i915_vm_to_ggtt(struct i915_address_space *vm) 558b42fe9caSJoonas Lahtinen { 559b42fe9caSJoonas Lahtinen GEM_BUG_ON(!i915_is_ggtt(vm)); 56082ad6443SChris Wilson return container_of(vm, struct i915_ggtt, vm); 561b42fe9caSJoonas Lahtinen } 562b42fe9caSJoonas Lahtinen 5634395890aSZhi Wang #define INTEL_MAX_PPAT_ENTRIES 8 5644395890aSZhi Wang #define INTEL_PPAT_PERFECT_MATCH (~0U) 5654395890aSZhi Wang 5664395890aSZhi Wang struct intel_ppat; 5674395890aSZhi Wang 5684395890aSZhi Wang struct intel_ppat_entry { 5694395890aSZhi Wang struct intel_ppat *ppat; 5704395890aSZhi Wang struct kref ref; 5714395890aSZhi Wang u8 value; 5724395890aSZhi Wang }; 5734395890aSZhi Wang 5744395890aSZhi Wang struct intel_ppat { 5754395890aSZhi Wang struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 5764395890aSZhi Wang DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 5774395890aSZhi Wang DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 5784395890aSZhi Wang unsigned int max_entries; 5794395890aSZhi Wang u8 clear_value; 5804395890aSZhi Wang /* 5814395890aSZhi Wang * Return a score to show how two PPAT values match, 5824395890aSZhi Wang * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 5834395890aSZhi Wang */ 5844395890aSZhi Wang unsigned int (*match)(u8 src, u8 dst); 5854395890aSZhi Wang void (*update_hw)(struct drm_i915_private *i915); 5864395890aSZhi Wang 5874395890aSZhi Wang struct drm_i915_private *i915; 5884395890aSZhi Wang }; 5894395890aSZhi Wang 5904395890aSZhi Wang const struct intel_ppat_entry * 5914395890aSZhi Wang intel_ppat_get(struct drm_i915_private *i915, u8 value); 5924395890aSZhi Wang void intel_ppat_put(const struct intel_ppat_entry *entry); 5934395890aSZhi Wang 5946cde9a02SChris Wilson int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 5956cde9a02SChris Wilson void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 5966cde9a02SChris Wilson 59797d6d7abSChris Wilson int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 59897d6d7abSChris Wilson int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 59997d6d7abSChris Wilson int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 6007c3f86b6SChris Wilson void i915_ggtt_enable_guc(struct drm_i915_private *i915); 6017c3f86b6SChris Wilson void i915_ggtt_disable_guc(struct drm_i915_private *i915); 602f6b9d5caSChris Wilson int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 60397d6d7abSChris Wilson void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 604ee960be7SDaniel Vetter 605c6be607aSTvrtko Ursulin int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 606ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 6072bfa996eSChris Wilson struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 60863fd659fSChris Wilson struct drm_i915_file_private *fpriv); 6090c7eeda1SChris Wilson void i915_ppgtt_close(struct i915_address_space *vm); 610ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 611ee960be7SDaniel Vetter { 612ee960be7SDaniel Vetter if (ppgtt) 613ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 614ee960be7SDaniel Vetter } 615ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 616ee960be7SDaniel Vetter { 617ee960be7SDaniel Vetter if (ppgtt) 618ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 619ee960be7SDaniel Vetter } 6200260c420SBen Widawsky 621a2bbf714SChris Wilson int gen6_ppgtt_pin(struct i915_hw_ppgtt *base); 622a2bbf714SChris Wilson void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base); 623a2bbf714SChris Wilson 624dc97997aSChris Wilson void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 625275a991cSTvrtko Ursulin void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 626275a991cSTvrtko Ursulin void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 6270260c420SBen Widawsky 62803ac84f1SChris Wilson int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 62903ac84f1SChris Wilson struct sg_table *pages); 63003ac84f1SChris Wilson void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 63103ac84f1SChris Wilson struct sg_table *pages); 6320260c420SBen Widawsky 633625d988aSChris Wilson int i915_gem_gtt_reserve(struct i915_address_space *vm, 634625d988aSChris Wilson struct drm_mm_node *node, 635625d988aSChris Wilson u64 size, u64 offset, unsigned long color, 636625d988aSChris Wilson unsigned int flags); 637625d988aSChris Wilson 638e007b19dSChris Wilson int i915_gem_gtt_insert(struct i915_address_space *vm, 639e007b19dSChris Wilson struct drm_mm_node *node, 640e007b19dSChris Wilson u64 size, u64 alignment, unsigned long color, 641e007b19dSChris Wilson u64 start, u64 end, unsigned int flags); 642e007b19dSChris Wilson 64359bfa124SChris Wilson /* Flags used by pin/bind&friends. */ 64483b466b1SChris Wilson #define PIN_NONBLOCK BIT_ULL(0) 645b18fe4beSChris Wilson #define PIN_NONFAULT BIT_ULL(1) 646b18fe4beSChris Wilson #define PIN_NOEVICT BIT_ULL(2) 647b18fe4beSChris Wilson #define PIN_MAPPABLE BIT_ULL(3) 648b18fe4beSChris Wilson #define PIN_ZONE_4G BIT_ULL(4) 649b18fe4beSChris Wilson #define PIN_HIGH BIT_ULL(5) 650b18fe4beSChris Wilson #define PIN_OFFSET_BIAS BIT_ULL(6) 651b18fe4beSChris Wilson #define PIN_OFFSET_FIXED BIT_ULL(7) 652305bc234SChris Wilson 653b18fe4beSChris Wilson #define PIN_MBZ BIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */ 654b18fe4beSChris Wilson #define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */ 655b18fe4beSChris Wilson #define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */ 656b18fe4beSChris Wilson #define PIN_UPDATE BIT_ULL(11) 657305bc234SChris Wilson 658f51455d4SChris Wilson #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 65959bfa124SChris Wilson 6600260c420SBen Widawsky #endif 661