10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 378ef8561fSChris Wilson #include <linux/io-mapping.h> 38b42fe9caSJoonas Lahtinen #include <linux/mm.h> 398ef8561fSChris Wilson 40b42fe9caSJoonas Lahtinen #include "i915_gem_timeline.h" 41b0decaf7SChris Wilson #include "i915_gem_request.h" 42b0decaf7SChris Wilson 43f51455d4SChris Wilson #define I915_GTT_PAGE_SIZE 4096UL 44f51455d4SChris Wilson #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 45f51455d4SChris Wilson 4649ef5294SChris Wilson #define I915_FENCE_REG_NONE -1 4749ef5294SChris Wilson #define I915_MAX_NUM_FENCES 32 4849ef5294SChris Wilson /* 32 fences + sign bit for FENCE_REG_NONE */ 4949ef5294SChris Wilson #define I915_MAX_NUM_FENCE_BITS 6 5049ef5294SChris Wilson 514d884705SDaniel Vetter struct drm_i915_file_private; 5249ef5294SChris Wilson struct drm_i915_fence_reg; 534d884705SDaniel Vetter 5407749ef3SMichel Thierry typedef uint32_t gen6_pte_t; 5507749ef3SMichel Thierry typedef uint64_t gen8_pte_t; 5607749ef3SMichel Thierry typedef uint64_t gen8_pde_t; 57762d9936SMichel Thierry typedef uint64_t gen8_ppgtt_pdpe_t; 58762d9936SMichel Thierry typedef uint64_t gen8_ppgtt_pml4e_t; 590260c420SBen Widawsky 6072e96d64SJoonas Lahtinen #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 610260c420SBen Widawsky 620260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 630260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 640260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 650260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 660260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 670260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 680260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 690260c420SBen Widawsky 7007749ef3SMichel Thierry #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 7107749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 7207749ef3SMichel Thierry #define I915_PDES 512 7307749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 74678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 7507749ef3SMichel Thierry 7607749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 7707749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 780260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 79678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 800260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 810260c420SBen Widawsky 820260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 830260c420SBen Widawsky 840260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 850260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 860260c420SBen Widawsky 870260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 880260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 890260c420SBen Widawsky */ 900260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 910260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 920260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 930260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 940260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 950260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 960260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 970260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 980260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 990260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1000260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1010260c420SBen Widawsky 1020260c420SBen Widawsky /* GEN8 legacy style address is defined as a 3 level page table: 1030260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 1040260c420SBen Widawsky * PDPE | PDE | PTE | offset 1050260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 1060260c420SBen Widawsky * programmed via register. 10781ba8aefSMichel Thierry * 10881ba8aefSMichel Thierry * GEN8 48b legacy style address is defined as a 4 level page table: 10981ba8aefSMichel Thierry * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 11081ba8aefSMichel Thierry * PML4E | PDPE | PDE | PTE | offset 1110260c420SBen Widawsky */ 11281ba8aefSMichel Thierry #define GEN8_PML4ES_PER_PML4 512 11381ba8aefSMichel Thierry #define GEN8_PML4E_SHIFT 39 114762d9936SMichel Thierry #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 1150260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 11681ba8aefSMichel Thierry /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 11781ba8aefSMichel Thierry * tables */ 11881ba8aefSMichel Thierry #define GEN8_PDPE_MASK 0x1ff 1190260c420SBen Widawsky #define GEN8_PDE_SHIFT 21 1200260c420SBen Widawsky #define GEN8_PDE_MASK 0x1ff 1210260c420SBen Widawsky #define GEN8_PTE_SHIFT 12 1220260c420SBen Widawsky #define GEN8_PTE_MASK 0x1ff 12376643600SBen Widawsky #define GEN8_LEGACY_PDPES 4 12407749ef3SMichel Thierry #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 1250260c420SBen Widawsky 126275a991cSTvrtko Ursulin #define I915_PDPES_PER_PDP(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\ 12781ba8aefSMichel Thierry GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 1286ac18502SMichel Thierry 1290260c420SBen Widawsky #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 1300260c420SBen Widawsky #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 1310260c420SBen Widawsky #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 1320260c420SBen Widawsky #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 1330260c420SBen Widawsky 134ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1350260c420SBen Widawsky #define GEN8_PPAT_AGE(x) (x<<4) 1360260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1370260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1380260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1390260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1400260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1410260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1420260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1430260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1440260c420SBen Widawsky #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 1450260c420SBen Widawsky 146b42fe9caSJoonas Lahtinen struct sg_table; 147b42fe9caSJoonas Lahtinen 148fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type { 149fe14d5f4STvrtko Ursulin I915_GGTT_VIEW_NORMAL = 0, 1508bd7ef16SJoonas Lahtinen I915_GGTT_VIEW_ROTATED, 1518bd7ef16SJoonas Lahtinen I915_GGTT_VIEW_PARTIAL, 15250470bb0STvrtko Ursulin }; 15350470bb0STvrtko Ursulin 15450470bb0STvrtko Ursulin struct intel_rotation_info { 1557ff19c56SChris Wilson struct intel_rotation_plane_info { 1561663b9d6SVille Syrjälä /* tiles */ 1576687c906SVille Syrjälä unsigned int width, height, stride, offset; 1581663b9d6SVille Syrjälä } plane[2]; 1598d9046adSChris Wilson } __packed; 1608d9046adSChris Wilson 1618d9046adSChris Wilson static inline void assert_intel_rotation_info_is_packed(void) 1628d9046adSChris Wilson { 1638d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 1648d9046adSChris Wilson } 165fe14d5f4STvrtko Ursulin 1667ff19c56SChris Wilson struct intel_partial_info { 1677ff19c56SChris Wilson u64 offset; 1687ff19c56SChris Wilson unsigned int size; 1698d9046adSChris Wilson } __packed; 1708d9046adSChris Wilson 1718d9046adSChris Wilson static inline void assert_intel_partial_info_is_packed(void) 1728d9046adSChris Wilson { 1738d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 1748d9046adSChris Wilson } 1757ff19c56SChris Wilson 176fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 177fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 178fe14d5f4STvrtko Ursulin 1798bd7ef16SJoonas Lahtinen union { 1807ff19c56SChris Wilson struct intel_partial_info partial; 1817723f47dSVille Syrjälä struct intel_rotation_info rotated; 1828bd7ef16SJoonas Lahtinen } params; 183fe14d5f4STvrtko Ursulin }; 184fe14d5f4STvrtko Ursulin 185fe14d5f4STvrtko Ursulin extern const struct i915_ggtt_view i915_ggtt_view_normal; 1869abc4648SJoonas Lahtinen extern const struct i915_ggtt_view i915_ggtt_view_rotated; 187fe14d5f4STvrtko Ursulin 1880260c420SBen Widawsky enum i915_cache_level; 189fe14d5f4STvrtko Ursulin 190b42fe9caSJoonas Lahtinen struct i915_vma; 191bde13ebdSChris Wilson 19244159ddbSMika Kuoppala struct i915_page_dma { 193d7b3de91SBen Widawsky struct page *page; 19444159ddbSMika Kuoppala union { 1957324cc04SBen Widawsky dma_addr_t daddr; 196678d96fbSBen Widawsky 19744159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 19844159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 19944159ddbSMika Kuoppala */ 20044159ddbSMika Kuoppala uint32_t ggtt_offset; 20144159ddbSMika Kuoppala }; 20244159ddbSMika Kuoppala }; 20344159ddbSMika Kuoppala 204567047beSMika Kuoppala #define px_base(px) (&(px)->base) 205567047beSMika Kuoppala #define px_page(px) (px_base(px)->page) 206567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 207567047beSMika Kuoppala 20844159ddbSMika Kuoppala struct i915_page_table { 20944159ddbSMika Kuoppala struct i915_page_dma base; 21044159ddbSMika Kuoppala 211678d96fbSBen Widawsky unsigned long *used_ptes; 212d7b3de91SBen Widawsky }; 213d7b3de91SBen Widawsky 214ec565b3cSMichel Thierry struct i915_page_directory { 21544159ddbSMika Kuoppala struct i915_page_dma base; 2167324cc04SBen Widawsky 21733c8819fSMichel Thierry unsigned long *used_pdes; 218ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 219d7b3de91SBen Widawsky }; 220d7b3de91SBen Widawsky 221ec565b3cSMichel Thierry struct i915_page_directory_pointer { 2226ac18502SMichel Thierry struct i915_page_dma base; 2236ac18502SMichel Thierry 2246ac18502SMichel Thierry unsigned long *used_pdpes; 2256ac18502SMichel Thierry struct i915_page_directory **page_directory; 226d7b3de91SBen Widawsky }; 227d7b3de91SBen Widawsky 22881ba8aefSMichel Thierry struct i915_pml4 { 22981ba8aefSMichel Thierry struct i915_page_dma base; 23081ba8aefSMichel Thierry 23181ba8aefSMichel Thierry DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 23281ba8aefSMichel Thierry struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 23381ba8aefSMichel Thierry }; 23481ba8aefSMichel Thierry 2350260c420SBen Widawsky struct i915_address_space { 2360260c420SBen Widawsky struct drm_mm mm; 23780b204bcSChris Wilson struct i915_gem_timeline timeline; 23849d73912SChris Wilson struct drm_i915_private *i915; 2392bfa996eSChris Wilson /* Every address space belongs to a struct file - except for the global 2402bfa996eSChris Wilson * GTT that is owned by the driver (and so @file is set to NULL). In 2412bfa996eSChris Wilson * principle, no information should leak from one context to another 2422bfa996eSChris Wilson * (or between files/processes etc) unless explicitly shared by the 2432bfa996eSChris Wilson * owner. Tracking the owner is important in order to free up per-file 2442bfa996eSChris Wilson * objects along with the file, to aide resource tracking, and to 2452bfa996eSChris Wilson * assign blame. 2462bfa996eSChris Wilson */ 2472bfa996eSChris Wilson struct drm_i915_file_private *file; 2480260c420SBen Widawsky struct list_head global_link; 249c44ef60eSMika Kuoppala u64 start; /* Start offset always 0 for dri2 */ 250c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 2510260c420SBen Widawsky 25250e046b6SChris Wilson bool closed; 25350e046b6SChris Wilson 2548bcdd0f7SChris Wilson struct i915_page_dma scratch_page; 25579ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 25679ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 25769ab76fdSMichel Thierry struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 2580260c420SBen Widawsky 2590260c420SBen Widawsky /** 2600260c420SBen Widawsky * List of objects currently involved in rendering. 2610260c420SBen Widawsky * 2620260c420SBen Widawsky * Includes buffers having the contents of their GPU caches 26397b2a6a1SJohn Harrison * flushed, not necessarily primitives. last_read_req 2640260c420SBen Widawsky * represents when the rendering involved will be completed. 2650260c420SBen Widawsky * 2660260c420SBen Widawsky * A reference is held on the buffer while on this list. 2670260c420SBen Widawsky */ 2680260c420SBen Widawsky struct list_head active_list; 2690260c420SBen Widawsky 2700260c420SBen Widawsky /** 2710260c420SBen Widawsky * LRU list of objects which are not in the ringbuffer and 2720260c420SBen Widawsky * are ready to unbind, but are still in the GTT. 2730260c420SBen Widawsky * 27497b2a6a1SJohn Harrison * last_read_req is NULL while an object is in this list. 2750260c420SBen Widawsky * 2760260c420SBen Widawsky * A reference is not held on the buffer while on this list, 2770260c420SBen Widawsky * as merely being GTT-bound shouldn't prevent its being 2780260c420SBen Widawsky * freed, and we'll pull it off the list in the free path. 2790260c420SBen Widawsky */ 2800260c420SBen Widawsky struct list_head inactive_list; 2810260c420SBen Widawsky 28250e046b6SChris Wilson /** 28350e046b6SChris Wilson * List of vma that have been unbound. 28450e046b6SChris Wilson * 28550e046b6SChris Wilson * A reference is not held on the buffer while on this list. 28650e046b6SChris Wilson */ 28750e046b6SChris Wilson struct list_head unbound_list; 28850e046b6SChris Wilson 2890260c420SBen Widawsky /* FIXME: Need a more generic return type */ 29007749ef3SMichel Thierry gen6_pte_t (*pte_encode)(dma_addr_t addr, 2910260c420SBen Widawsky enum i915_cache_level level, 2924fb84d99SMichał Winiarski u32 flags); /* Create a valid PTE */ 293f329f5f6SDaniel Vetter /* flags for pte_encode */ 294f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 295678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 296678d96fbSBen Widawsky uint64_t start, 297678d96fbSBen Widawsky uint64_t length); 2980260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 2990260c420SBen Widawsky uint64_t start, 3004fb84d99SMichał Winiarski uint64_t length); 301d6473f56SChris Wilson void (*insert_page)(struct i915_address_space *vm, 302d6473f56SChris Wilson dma_addr_t addr, 303d6473f56SChris Wilson uint64_t offset, 304d6473f56SChris Wilson enum i915_cache_level cache_level, 305d6473f56SChris Wilson u32 flags); 3060260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 3070260c420SBen Widawsky struct sg_table *st, 3080260c420SBen Widawsky uint64_t start, 30924f3a8cfSAkash Goel enum i915_cache_level cache_level, u32 flags); 3100260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 311777dc5bbSDaniel Vetter /** Unmap an object from an address space. This usually consists of 312777dc5bbSDaniel Vetter * setting the valid PTE entries to a reserved scratch page. */ 313777dc5bbSDaniel Vetter void (*unbind_vma)(struct i915_vma *vma); 314777dc5bbSDaniel Vetter /* Map an object into an address space with the given cache flags. */ 31570b9f6f8SDaniel Vetter int (*bind_vma)(struct i915_vma *vma, 316777dc5bbSDaniel Vetter enum i915_cache_level cache_level, 317777dc5bbSDaniel Vetter u32 flags); 3180260c420SBen Widawsky }; 3190260c420SBen Widawsky 3202bfa996eSChris Wilson #define i915_is_ggtt(V) (!(V)->file) 321596c5923SChris Wilson 3220260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3230260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3240260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3250260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3260260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3270260c420SBen Widawsky * the spec. 3280260c420SBen Widawsky */ 32962106b4fSJoonas Lahtinen struct i915_ggtt { 3300260c420SBen Widawsky struct i915_address_space base; 331f7bbe788SChris Wilson struct io_mapping mappable; /* Mapping to our CPU mappable region */ 3320260c420SBen Widawsky 333edd1f2feSChris Wilson phys_addr_t mappable_base; /* PA of our GMADR */ 334edd1f2feSChris Wilson u64 mappable_end; /* End offset that we can CPU map */ 335edd1f2feSChris Wilson 3363c6b29b2SPaulo Zanoni /* Stolen memory is segmented in hardware with different portions 3373c6b29b2SPaulo Zanoni * offlimits to certain functions. 3383c6b29b2SPaulo Zanoni * 3393c6b29b2SPaulo Zanoni * The drm_mm is initialised to the total accessible range, as found 3403c6b29b2SPaulo Zanoni * from the PCI config. On Broadwell+, this is further restricted to 3413c6b29b2SPaulo Zanoni * avoid the first page! The upper end of stolen memory is reserved for 3423c6b29b2SPaulo Zanoni * hardware functions and similarly removed from the accessible range. 3433c6b29b2SPaulo Zanoni */ 344edd1f2feSChris Wilson u32 stolen_size; /* Total size of stolen memory */ 345edd1f2feSChris Wilson u32 stolen_usable_size; /* Total size minus reserved ranges */ 346edd1f2feSChris Wilson u32 stolen_reserved_base; 347edd1f2feSChris Wilson u32 stolen_reserved_size; 3480260c420SBen Widawsky 3490260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3500260c420SBen Widawsky void __iomem *gsm; 3517c3f86b6SChris Wilson void (*invalidate)(struct drm_i915_private *dev_priv); 3520260c420SBen Widawsky 3530260c420SBen Widawsky bool do_idle_maps; 3540260c420SBen Widawsky 3550260c420SBen Widawsky int mtrr; 35695374d75SChris Wilson 35795374d75SChris Wilson struct drm_mm_node error_capture; 3580260c420SBen Widawsky }; 3590260c420SBen Widawsky 3600260c420SBen Widawsky struct i915_hw_ppgtt { 3610260c420SBen Widawsky struct i915_address_space base; 3620260c420SBen Widawsky struct kref ref; 3630260c420SBen Widawsky struct drm_mm_node node; 364563222a7SBen Widawsky unsigned long pd_dirty_rings; 3650260c420SBen Widawsky union { 36681ba8aefSMichel Thierry struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 36781ba8aefSMichel Thierry struct i915_page_directory_pointer pdp; /* GEN8+ */ 36881ba8aefSMichel Thierry struct i915_page_directory pd; /* GEN6-7 */ 369d7b3de91SBen Widawsky }; 3700260c420SBen Widawsky 371678d96fbSBen Widawsky gen6_pte_t __iomem *pd_addr; 372678d96fbSBen Widawsky 3730260c420SBen Widawsky int (*enable)(struct i915_hw_ppgtt *ppgtt); 3740260c420SBen Widawsky int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 375e85b26dcSJohn Harrison struct drm_i915_gem_request *req); 3760260c420SBen Widawsky void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 3770260c420SBen Widawsky }; 3780260c420SBen Widawsky 379731f74c5SDave Gordon /* 380731f74c5SDave Gordon * gen6_for_each_pde() iterates over every pde from start until start+length. 381731f74c5SDave Gordon * If start and start+length are not perfectly divisible, the macro will round 382731f74c5SDave Gordon * down and up as needed. Start=0 and length=2G effectively iterates over 383731f74c5SDave Gordon * every PDE in the system. The macro modifies ALL its parameters except 'pd', 384731f74c5SDave Gordon * so each of the other parameters should preferably be a simple variable, or 385731f74c5SDave Gordon * at most an lvalue with no side-effects! 386678d96fbSBen Widawsky */ 387731f74c5SDave Gordon #define gen6_for_each_pde(pt, pd, start, length, iter) \ 388fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 389731f74c5SDave Gordon length > 0 && iter < I915_PDES && \ 390731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 391731f74c5SDave Gordon ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 392731f74c5SDave Gordon temp = min(temp - start, length); \ 393731f74c5SDave Gordon start += temp, length -= temp; }), ++iter) 394678d96fbSBen Widawsky 395731f74c5SDave Gordon #define gen6_for_all_pdes(pt, pd, iter) \ 39609942c65SMichel Thierry for (iter = 0; \ 397731f74c5SDave Gordon iter < I915_PDES && \ 398731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 399731f74c5SDave Gordon ++iter) 40009942c65SMichel Thierry 401678d96fbSBen Widawsky static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 402678d96fbSBen Widawsky { 403678d96fbSBen Widawsky const uint32_t mask = NUM_PTE(pde_shift) - 1; 404678d96fbSBen Widawsky 405678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 406678d96fbSBen Widawsky } 407678d96fbSBen Widawsky 408678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 409678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 410678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 411678d96fbSBen Widawsky */ 412678d96fbSBen Widawsky static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 413678d96fbSBen Widawsky uint32_t pde_shift) 414678d96fbSBen Widawsky { 41569603dbbSAlan const uint64_t mask = ~((1ULL << pde_shift) - 1); 416678d96fbSBen Widawsky uint64_t end; 417678d96fbSBen Widawsky 418678d96fbSBen Widawsky WARN_ON(length == 0); 419678d96fbSBen Widawsky WARN_ON(offset_in_page(addr|length)); 420678d96fbSBen Widawsky 421678d96fbSBen Widawsky end = addr + length; 422678d96fbSBen Widawsky 423678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 424678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 425678d96fbSBen Widawsky 426678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 427678d96fbSBen Widawsky } 428678d96fbSBen Widawsky 429678d96fbSBen Widawsky static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 430678d96fbSBen Widawsky { 431678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 432678d96fbSBen Widawsky } 433678d96fbSBen Widawsky 434678d96fbSBen Widawsky static inline uint32_t gen6_pte_index(uint32_t addr) 435678d96fbSBen Widawsky { 436678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 437678d96fbSBen Widawsky } 438678d96fbSBen Widawsky 439678d96fbSBen Widawsky static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 440678d96fbSBen Widawsky { 441678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 442678d96fbSBen Widawsky } 443678d96fbSBen Widawsky 444678d96fbSBen Widawsky static inline uint32_t gen6_pde_index(uint32_t addr) 445678d96fbSBen Widawsky { 446678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 447678d96fbSBen Widawsky } 448678d96fbSBen Widawsky 4499271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4509271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4519271d959SMichel Thierry * over every page directory entry in a page directory. 4529271d959SMichel Thierry */ 453e8ebd8e2SDave Gordon #define gen8_for_each_pde(pt, pd, start, length, iter) \ 4549271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 455e8ebd8e2SDave Gordon length > 0 && iter < I915_PDES && \ 456e8ebd8e2SDave Gordon (pt = (pd)->page_table[iter], true); \ 457e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 458e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 459e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4609271d959SMichel Thierry 461e8ebd8e2SDave Gordon #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 4629271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 463e8ebd8e2SDave Gordon length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 464e8ebd8e2SDave Gordon (pd = (pdp)->page_directory[iter], true); \ 465e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 466e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 467e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4689271d959SMichel Thierry 469e8ebd8e2SDave Gordon #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 470762d9936SMichel Thierry for (iter = gen8_pml4e_index(start); \ 471e8ebd8e2SDave Gordon length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 472e8ebd8e2SDave Gordon (pdp = (pml4)->pdps[iter], true); \ 473e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 474e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 475e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 476762d9936SMichel Thierry 4779271d959SMichel Thierry static inline uint32_t gen8_pte_index(uint64_t address) 4789271d959SMichel Thierry { 4799271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 4809271d959SMichel Thierry } 4819271d959SMichel Thierry 4829271d959SMichel Thierry static inline uint32_t gen8_pde_index(uint64_t address) 4839271d959SMichel Thierry { 4849271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 4859271d959SMichel Thierry } 4869271d959SMichel Thierry 4879271d959SMichel Thierry static inline uint32_t gen8_pdpe_index(uint64_t address) 4889271d959SMichel Thierry { 4899271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 4909271d959SMichel Thierry } 4919271d959SMichel Thierry 4929271d959SMichel Thierry static inline uint32_t gen8_pml4e_index(uint64_t address) 4939271d959SMichel Thierry { 494762d9936SMichel Thierry return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 4959271d959SMichel Thierry } 4969271d959SMichel Thierry 49733c8819fSMichel Thierry static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 49833c8819fSMichel Thierry { 49933c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 50033c8819fSMichel Thierry } 50133c8819fSMichel Thierry 502d852c7bfSMika Kuoppala static inline dma_addr_t 503d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 504d852c7bfSMika Kuoppala { 505d852c7bfSMika Kuoppala return test_bit(n, ppgtt->pdp.used_pdpes) ? 506567047beSMika Kuoppala px_dma(ppgtt->pdp.page_directory[n]) : 50779ab9370SMika Kuoppala px_dma(ppgtt->base.scratch_pd); 508d852c7bfSMika Kuoppala } 509d852c7bfSMika Kuoppala 510b42fe9caSJoonas Lahtinen static inline struct i915_ggtt * 511b42fe9caSJoonas Lahtinen i915_vm_to_ggtt(struct i915_address_space *vm) 512b42fe9caSJoonas Lahtinen { 513b42fe9caSJoonas Lahtinen GEM_BUG_ON(!i915_is_ggtt(vm)); 514b42fe9caSJoonas Lahtinen return container_of(vm, struct i915_ggtt, base); 515b42fe9caSJoonas Lahtinen } 516b42fe9caSJoonas Lahtinen 51797d6d7abSChris Wilson int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 51897d6d7abSChris Wilson int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 51997d6d7abSChris Wilson int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 5207c3f86b6SChris Wilson void i915_ggtt_enable_guc(struct drm_i915_private *i915); 5217c3f86b6SChris Wilson void i915_ggtt_disable_guc(struct drm_i915_private *i915); 522f6b9d5caSChris Wilson int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 52397d6d7abSChris Wilson void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 524ee960be7SDaniel Vetter 525c6be607aSTvrtko Ursulin int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 526ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 5272bfa996eSChris Wilson struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 52880b204bcSChris Wilson struct drm_i915_file_private *fpriv, 52980b204bcSChris Wilson const char *name); 5300c7eeda1SChris Wilson void i915_ppgtt_close(struct i915_address_space *vm); 531ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 532ee960be7SDaniel Vetter { 533ee960be7SDaniel Vetter if (ppgtt) 534ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 535ee960be7SDaniel Vetter } 536ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 537ee960be7SDaniel Vetter { 538ee960be7SDaniel Vetter if (ppgtt) 539ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 540ee960be7SDaniel Vetter } 5410260c420SBen Widawsky 542dc97997aSChris Wilson void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 543275a991cSTvrtko Ursulin void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 544275a991cSTvrtko Ursulin void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 5450260c420SBen Widawsky 54603ac84f1SChris Wilson int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 54703ac84f1SChris Wilson struct sg_table *pages); 54803ac84f1SChris Wilson void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 54903ac84f1SChris Wilson struct sg_table *pages); 5500260c420SBen Widawsky 551625d988aSChris Wilson int i915_gem_gtt_reserve(struct i915_address_space *vm, 552625d988aSChris Wilson struct drm_mm_node *node, 553625d988aSChris Wilson u64 size, u64 offset, unsigned long color, 554625d988aSChris Wilson unsigned int flags); 555625d988aSChris Wilson 556e007b19dSChris Wilson int i915_gem_gtt_insert(struct i915_address_space *vm, 557e007b19dSChris Wilson struct drm_mm_node *node, 558e007b19dSChris Wilson u64 size, u64 alignment, unsigned long color, 559e007b19dSChris Wilson u64 start, u64 end, unsigned int flags); 560e007b19dSChris Wilson 56159bfa124SChris Wilson /* Flags used by pin/bind&friends. */ 562305bc234SChris Wilson #define PIN_NONBLOCK BIT(0) 563305bc234SChris Wilson #define PIN_MAPPABLE BIT(1) 564305bc234SChris Wilson #define PIN_ZONE_4G BIT(2) 56582118877SChris Wilson #define PIN_NONFAULT BIT(3) 566305bc234SChris Wilson 567305bc234SChris Wilson #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 568305bc234SChris Wilson #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 569305bc234SChris Wilson #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 570305bc234SChris Wilson #define PIN_UPDATE BIT(8) 571305bc234SChris Wilson 572305bc234SChris Wilson #define PIN_HIGH BIT(9) 573305bc234SChris Wilson #define PIN_OFFSET_BIAS BIT(10) 574305bc234SChris Wilson #define PIN_OFFSET_FIXED BIT(11) 575f51455d4SChris Wilson #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 57659bfa124SChris Wilson 5770260c420SBen Widawsky #endif 578