10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 378ef8561fSChris Wilson #include <linux/io-mapping.h> 38b42fe9caSJoonas Lahtinen #include <linux/mm.h> 398ef8561fSChris Wilson 40b42fe9caSJoonas Lahtinen #include "i915_gem_timeline.h" 41b0decaf7SChris Wilson #include "i915_gem_request.h" 42b0decaf7SChris Wilson 43f51455d4SChris Wilson #define I915_GTT_PAGE_SIZE 4096UL 44f51455d4SChris Wilson #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 45f51455d4SChris Wilson 4649ef5294SChris Wilson #define I915_FENCE_REG_NONE -1 4749ef5294SChris Wilson #define I915_MAX_NUM_FENCES 32 4849ef5294SChris Wilson /* 32 fences + sign bit for FENCE_REG_NONE */ 4949ef5294SChris Wilson #define I915_MAX_NUM_FENCE_BITS 6 5049ef5294SChris Wilson 514d884705SDaniel Vetter struct drm_i915_file_private; 5249ef5294SChris Wilson struct drm_i915_fence_reg; 534d884705SDaniel Vetter 5407749ef3SMichel Thierry typedef uint32_t gen6_pte_t; 5507749ef3SMichel Thierry typedef uint64_t gen8_pte_t; 5607749ef3SMichel Thierry typedef uint64_t gen8_pde_t; 57762d9936SMichel Thierry typedef uint64_t gen8_ppgtt_pdpe_t; 58762d9936SMichel Thierry typedef uint64_t gen8_ppgtt_pml4e_t; 590260c420SBen Widawsky 6072e96d64SJoonas Lahtinen #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 610260c420SBen Widawsky 620260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 630260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 640260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 650260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 660260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 670260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 680260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 690260c420SBen Widawsky 7007749ef3SMichel Thierry #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 7107749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 7207749ef3SMichel Thierry #define I915_PDES 512 7307749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 74678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 7507749ef3SMichel Thierry 7607749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 7707749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 780260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 79678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 800260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 810260c420SBen Widawsky 820260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 830260c420SBen Widawsky 840260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 850260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 860260c420SBen Widawsky 870260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 880260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 890260c420SBen Widawsky */ 900260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 910260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 920260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 930260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 940260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 950260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 960260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 970260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 980260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 990260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1000260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1010260c420SBen Widawsky 1020260c420SBen Widawsky /* GEN8 legacy style address is defined as a 3 level page table: 1030260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 1040260c420SBen Widawsky * PDPE | PDE | PTE | offset 1050260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 1060260c420SBen Widawsky * programmed via register. 10781ba8aefSMichel Thierry * 10881ba8aefSMichel Thierry * GEN8 48b legacy style address is defined as a 4 level page table: 10981ba8aefSMichel Thierry * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 11081ba8aefSMichel Thierry * PML4E | PDPE | PDE | PTE | offset 1110260c420SBen Widawsky */ 11281ba8aefSMichel Thierry #define GEN8_PML4ES_PER_PML4 512 11381ba8aefSMichel Thierry #define GEN8_PML4E_SHIFT 39 114762d9936SMichel Thierry #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 1150260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 11681ba8aefSMichel Thierry /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 11781ba8aefSMichel Thierry * tables */ 11881ba8aefSMichel Thierry #define GEN8_PDPE_MASK 0x1ff 1190260c420SBen Widawsky #define GEN8_PDE_SHIFT 21 1200260c420SBen Widawsky #define GEN8_PDE_MASK 0x1ff 1210260c420SBen Widawsky #define GEN8_PTE_SHIFT 12 1220260c420SBen Widawsky #define GEN8_PTE_MASK 0x1ff 12376643600SBen Widawsky #define GEN8_LEGACY_PDPES 4 12407749ef3SMichel Thierry #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 1250260c420SBen Widawsky 126275a991cSTvrtko Ursulin #define I915_PDPES_PER_PDP(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\ 12781ba8aefSMichel Thierry GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 1286ac18502SMichel Thierry 1290260c420SBen Widawsky #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 1300260c420SBen Widawsky #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 1310260c420SBen Widawsky #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 1320260c420SBen Widawsky #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 1330260c420SBen Widawsky 134ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1350260c420SBen Widawsky #define GEN8_PPAT_AGE(x) (x<<4) 1360260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1370260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1380260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1390260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1400260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1410260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1420260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1430260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1440260c420SBen Widawsky #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 1450260c420SBen Widawsky 146b42fe9caSJoonas Lahtinen struct sg_table; 147b42fe9caSJoonas Lahtinen 148fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type { 149fe14d5f4STvrtko Ursulin I915_GGTT_VIEW_NORMAL = 0, 1508bd7ef16SJoonas Lahtinen I915_GGTT_VIEW_ROTATED, 1518bd7ef16SJoonas Lahtinen I915_GGTT_VIEW_PARTIAL, 15250470bb0STvrtko Ursulin }; 15350470bb0STvrtko Ursulin 15450470bb0STvrtko Ursulin struct intel_rotation_info { 1557ff19c56SChris Wilson struct intel_rotation_plane_info { 1561663b9d6SVille Syrjälä /* tiles */ 1576687c906SVille Syrjälä unsigned int width, height, stride, offset; 1581663b9d6SVille Syrjälä } plane[2]; 159fe14d5f4STvrtko Ursulin }; 160fe14d5f4STvrtko Ursulin 1617ff19c56SChris Wilson struct intel_partial_info { 1627ff19c56SChris Wilson u64 offset; 1637ff19c56SChris Wilson unsigned int size; 1647ff19c56SChris Wilson }; 1657ff19c56SChris Wilson 166fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 167fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 168fe14d5f4STvrtko Ursulin 1698bd7ef16SJoonas Lahtinen union { 1707ff19c56SChris Wilson struct intel_partial_info partial; 1717723f47dSVille Syrjälä struct intel_rotation_info rotated; 1728bd7ef16SJoonas Lahtinen } params; 173fe14d5f4STvrtko Ursulin }; 174fe14d5f4STvrtko Ursulin 175fe14d5f4STvrtko Ursulin extern const struct i915_ggtt_view i915_ggtt_view_normal; 1769abc4648SJoonas Lahtinen extern const struct i915_ggtt_view i915_ggtt_view_rotated; 177fe14d5f4STvrtko Ursulin 1780260c420SBen Widawsky enum i915_cache_level; 179fe14d5f4STvrtko Ursulin 180b42fe9caSJoonas Lahtinen struct i915_vma; 181bde13ebdSChris Wilson 18244159ddbSMika Kuoppala struct i915_page_dma { 183d7b3de91SBen Widawsky struct page *page; 18444159ddbSMika Kuoppala union { 1857324cc04SBen Widawsky dma_addr_t daddr; 186678d96fbSBen Widawsky 18744159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 18844159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 18944159ddbSMika Kuoppala */ 19044159ddbSMika Kuoppala uint32_t ggtt_offset; 19144159ddbSMika Kuoppala }; 19244159ddbSMika Kuoppala }; 19344159ddbSMika Kuoppala 194567047beSMika Kuoppala #define px_base(px) (&(px)->base) 195567047beSMika Kuoppala #define px_page(px) (px_base(px)->page) 196567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 197567047beSMika Kuoppala 19844159ddbSMika Kuoppala struct i915_page_table { 19944159ddbSMika Kuoppala struct i915_page_dma base; 20044159ddbSMika Kuoppala 201678d96fbSBen Widawsky unsigned long *used_ptes; 202d7b3de91SBen Widawsky }; 203d7b3de91SBen Widawsky 204ec565b3cSMichel Thierry struct i915_page_directory { 20544159ddbSMika Kuoppala struct i915_page_dma base; 2067324cc04SBen Widawsky 20733c8819fSMichel Thierry unsigned long *used_pdes; 208ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 209d7b3de91SBen Widawsky }; 210d7b3de91SBen Widawsky 211ec565b3cSMichel Thierry struct i915_page_directory_pointer { 2126ac18502SMichel Thierry struct i915_page_dma base; 2136ac18502SMichel Thierry 2146ac18502SMichel Thierry unsigned long *used_pdpes; 2156ac18502SMichel Thierry struct i915_page_directory **page_directory; 216d7b3de91SBen Widawsky }; 217d7b3de91SBen Widawsky 21881ba8aefSMichel Thierry struct i915_pml4 { 21981ba8aefSMichel Thierry struct i915_page_dma base; 22081ba8aefSMichel Thierry 22181ba8aefSMichel Thierry DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 22281ba8aefSMichel Thierry struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 22381ba8aefSMichel Thierry }; 22481ba8aefSMichel Thierry 2250260c420SBen Widawsky struct i915_address_space { 2260260c420SBen Widawsky struct drm_mm mm; 22780b204bcSChris Wilson struct i915_gem_timeline timeline; 22849d73912SChris Wilson struct drm_i915_private *i915; 2292bfa996eSChris Wilson /* Every address space belongs to a struct file - except for the global 2302bfa996eSChris Wilson * GTT that is owned by the driver (and so @file is set to NULL). In 2312bfa996eSChris Wilson * principle, no information should leak from one context to another 2322bfa996eSChris Wilson * (or between files/processes etc) unless explicitly shared by the 2332bfa996eSChris Wilson * owner. Tracking the owner is important in order to free up per-file 2342bfa996eSChris Wilson * objects along with the file, to aide resource tracking, and to 2352bfa996eSChris Wilson * assign blame. 2362bfa996eSChris Wilson */ 2372bfa996eSChris Wilson struct drm_i915_file_private *file; 2380260c420SBen Widawsky struct list_head global_link; 239c44ef60eSMika Kuoppala u64 start; /* Start offset always 0 for dri2 */ 240c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 2410260c420SBen Widawsky 24250e046b6SChris Wilson bool closed; 24350e046b6SChris Wilson 2448bcdd0f7SChris Wilson struct i915_page_dma scratch_page; 24579ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 24679ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 24769ab76fdSMichel Thierry struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 2480260c420SBen Widawsky 2490260c420SBen Widawsky /** 2500260c420SBen Widawsky * List of objects currently involved in rendering. 2510260c420SBen Widawsky * 2520260c420SBen Widawsky * Includes buffers having the contents of their GPU caches 25397b2a6a1SJohn Harrison * flushed, not necessarily primitives. last_read_req 2540260c420SBen Widawsky * represents when the rendering involved will be completed. 2550260c420SBen Widawsky * 2560260c420SBen Widawsky * A reference is held on the buffer while on this list. 2570260c420SBen Widawsky */ 2580260c420SBen Widawsky struct list_head active_list; 2590260c420SBen Widawsky 2600260c420SBen Widawsky /** 2610260c420SBen Widawsky * LRU list of objects which are not in the ringbuffer and 2620260c420SBen Widawsky * are ready to unbind, but are still in the GTT. 2630260c420SBen Widawsky * 26497b2a6a1SJohn Harrison * last_read_req is NULL while an object is in this list. 2650260c420SBen Widawsky * 2660260c420SBen Widawsky * A reference is not held on the buffer while on this list, 2670260c420SBen Widawsky * as merely being GTT-bound shouldn't prevent its being 2680260c420SBen Widawsky * freed, and we'll pull it off the list in the free path. 2690260c420SBen Widawsky */ 2700260c420SBen Widawsky struct list_head inactive_list; 2710260c420SBen Widawsky 27250e046b6SChris Wilson /** 27350e046b6SChris Wilson * List of vma that have been unbound. 27450e046b6SChris Wilson * 27550e046b6SChris Wilson * A reference is not held on the buffer while on this list. 27650e046b6SChris Wilson */ 27750e046b6SChris Wilson struct list_head unbound_list; 27850e046b6SChris Wilson 2790260c420SBen Widawsky /* FIXME: Need a more generic return type */ 28007749ef3SMichel Thierry gen6_pte_t (*pte_encode)(dma_addr_t addr, 2810260c420SBen Widawsky enum i915_cache_level level, 2824fb84d99SMichał Winiarski u32 flags); /* Create a valid PTE */ 283f329f5f6SDaniel Vetter /* flags for pte_encode */ 284f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 285678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 286678d96fbSBen Widawsky uint64_t start, 287678d96fbSBen Widawsky uint64_t length); 2880260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 2890260c420SBen Widawsky uint64_t start, 2904fb84d99SMichał Winiarski uint64_t length); 291d6473f56SChris Wilson void (*insert_page)(struct i915_address_space *vm, 292d6473f56SChris Wilson dma_addr_t addr, 293d6473f56SChris Wilson uint64_t offset, 294d6473f56SChris Wilson enum i915_cache_level cache_level, 295d6473f56SChris Wilson u32 flags); 2960260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 2970260c420SBen Widawsky struct sg_table *st, 2980260c420SBen Widawsky uint64_t start, 29924f3a8cfSAkash Goel enum i915_cache_level cache_level, u32 flags); 3000260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 301777dc5bbSDaniel Vetter /** Unmap an object from an address space. This usually consists of 302777dc5bbSDaniel Vetter * setting the valid PTE entries to a reserved scratch page. */ 303777dc5bbSDaniel Vetter void (*unbind_vma)(struct i915_vma *vma); 304777dc5bbSDaniel Vetter /* Map an object into an address space with the given cache flags. */ 30570b9f6f8SDaniel Vetter int (*bind_vma)(struct i915_vma *vma, 306777dc5bbSDaniel Vetter enum i915_cache_level cache_level, 307777dc5bbSDaniel Vetter u32 flags); 3080260c420SBen Widawsky }; 3090260c420SBen Widawsky 3102bfa996eSChris Wilson #define i915_is_ggtt(V) (!(V)->file) 311596c5923SChris Wilson 3120260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3130260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3140260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3150260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3160260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3170260c420SBen Widawsky * the spec. 3180260c420SBen Widawsky */ 31962106b4fSJoonas Lahtinen struct i915_ggtt { 3200260c420SBen Widawsky struct i915_address_space base; 321f7bbe788SChris Wilson struct io_mapping mappable; /* Mapping to our CPU mappable region */ 3220260c420SBen Widawsky 323edd1f2feSChris Wilson phys_addr_t mappable_base; /* PA of our GMADR */ 324edd1f2feSChris Wilson u64 mappable_end; /* End offset that we can CPU map */ 325edd1f2feSChris Wilson 3263c6b29b2SPaulo Zanoni /* Stolen memory is segmented in hardware with different portions 3273c6b29b2SPaulo Zanoni * offlimits to certain functions. 3283c6b29b2SPaulo Zanoni * 3293c6b29b2SPaulo Zanoni * The drm_mm is initialised to the total accessible range, as found 3303c6b29b2SPaulo Zanoni * from the PCI config. On Broadwell+, this is further restricted to 3313c6b29b2SPaulo Zanoni * avoid the first page! The upper end of stolen memory is reserved for 3323c6b29b2SPaulo Zanoni * hardware functions and similarly removed from the accessible range. 3333c6b29b2SPaulo Zanoni */ 334edd1f2feSChris Wilson u32 stolen_size; /* Total size of stolen memory */ 335edd1f2feSChris Wilson u32 stolen_usable_size; /* Total size minus reserved ranges */ 336edd1f2feSChris Wilson u32 stolen_reserved_base; 337edd1f2feSChris Wilson u32 stolen_reserved_size; 3380260c420SBen Widawsky 3390260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3400260c420SBen Widawsky void __iomem *gsm; 3417c3f86b6SChris Wilson void (*invalidate)(struct drm_i915_private *dev_priv); 3420260c420SBen Widawsky 3430260c420SBen Widawsky bool do_idle_maps; 3440260c420SBen Widawsky 3450260c420SBen Widawsky int mtrr; 34695374d75SChris Wilson 34795374d75SChris Wilson struct drm_mm_node error_capture; 3480260c420SBen Widawsky }; 3490260c420SBen Widawsky 3500260c420SBen Widawsky struct i915_hw_ppgtt { 3510260c420SBen Widawsky struct i915_address_space base; 3520260c420SBen Widawsky struct kref ref; 3530260c420SBen Widawsky struct drm_mm_node node; 354563222a7SBen Widawsky unsigned long pd_dirty_rings; 3550260c420SBen Widawsky union { 35681ba8aefSMichel Thierry struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 35781ba8aefSMichel Thierry struct i915_page_directory_pointer pdp; /* GEN8+ */ 35881ba8aefSMichel Thierry struct i915_page_directory pd; /* GEN6-7 */ 359d7b3de91SBen Widawsky }; 3600260c420SBen Widawsky 361678d96fbSBen Widawsky gen6_pte_t __iomem *pd_addr; 362678d96fbSBen Widawsky 3630260c420SBen Widawsky int (*enable)(struct i915_hw_ppgtt *ppgtt); 3640260c420SBen Widawsky int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 365e85b26dcSJohn Harrison struct drm_i915_gem_request *req); 3660260c420SBen Widawsky void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 3670260c420SBen Widawsky }; 3680260c420SBen Widawsky 369731f74c5SDave Gordon /* 370731f74c5SDave Gordon * gen6_for_each_pde() iterates over every pde from start until start+length. 371731f74c5SDave Gordon * If start and start+length are not perfectly divisible, the macro will round 372731f74c5SDave Gordon * down and up as needed. Start=0 and length=2G effectively iterates over 373731f74c5SDave Gordon * every PDE in the system. The macro modifies ALL its parameters except 'pd', 374731f74c5SDave Gordon * so each of the other parameters should preferably be a simple variable, or 375731f74c5SDave Gordon * at most an lvalue with no side-effects! 376678d96fbSBen Widawsky */ 377731f74c5SDave Gordon #define gen6_for_each_pde(pt, pd, start, length, iter) \ 378fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 379731f74c5SDave Gordon length > 0 && iter < I915_PDES && \ 380731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 381731f74c5SDave Gordon ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 382731f74c5SDave Gordon temp = min(temp - start, length); \ 383731f74c5SDave Gordon start += temp, length -= temp; }), ++iter) 384678d96fbSBen Widawsky 385731f74c5SDave Gordon #define gen6_for_all_pdes(pt, pd, iter) \ 38609942c65SMichel Thierry for (iter = 0; \ 387731f74c5SDave Gordon iter < I915_PDES && \ 388731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 389731f74c5SDave Gordon ++iter) 39009942c65SMichel Thierry 391678d96fbSBen Widawsky static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 392678d96fbSBen Widawsky { 393678d96fbSBen Widawsky const uint32_t mask = NUM_PTE(pde_shift) - 1; 394678d96fbSBen Widawsky 395678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 396678d96fbSBen Widawsky } 397678d96fbSBen Widawsky 398678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 399678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 400678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 401678d96fbSBen Widawsky */ 402678d96fbSBen Widawsky static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 403678d96fbSBen Widawsky uint32_t pde_shift) 404678d96fbSBen Widawsky { 40569603dbbSAlan const uint64_t mask = ~((1ULL << pde_shift) - 1); 406678d96fbSBen Widawsky uint64_t end; 407678d96fbSBen Widawsky 408678d96fbSBen Widawsky WARN_ON(length == 0); 409678d96fbSBen Widawsky WARN_ON(offset_in_page(addr|length)); 410678d96fbSBen Widawsky 411678d96fbSBen Widawsky end = addr + length; 412678d96fbSBen Widawsky 413678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 414678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 415678d96fbSBen Widawsky 416678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 417678d96fbSBen Widawsky } 418678d96fbSBen Widawsky 419678d96fbSBen Widawsky static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 420678d96fbSBen Widawsky { 421678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 422678d96fbSBen Widawsky } 423678d96fbSBen Widawsky 424678d96fbSBen Widawsky static inline uint32_t gen6_pte_index(uint32_t addr) 425678d96fbSBen Widawsky { 426678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 427678d96fbSBen Widawsky } 428678d96fbSBen Widawsky 429678d96fbSBen Widawsky static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 430678d96fbSBen Widawsky { 431678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 432678d96fbSBen Widawsky } 433678d96fbSBen Widawsky 434678d96fbSBen Widawsky static inline uint32_t gen6_pde_index(uint32_t addr) 435678d96fbSBen Widawsky { 436678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 437678d96fbSBen Widawsky } 438678d96fbSBen Widawsky 4399271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4409271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4419271d959SMichel Thierry * over every page directory entry in a page directory. 4429271d959SMichel Thierry */ 443e8ebd8e2SDave Gordon #define gen8_for_each_pde(pt, pd, start, length, iter) \ 4449271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 445e8ebd8e2SDave Gordon length > 0 && iter < I915_PDES && \ 446e8ebd8e2SDave Gordon (pt = (pd)->page_table[iter], true); \ 447e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 448e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 449e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4509271d959SMichel Thierry 451e8ebd8e2SDave Gordon #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 4529271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 453e8ebd8e2SDave Gordon length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 454e8ebd8e2SDave Gordon (pd = (pdp)->page_directory[iter], true); \ 455e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 456e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 457e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4589271d959SMichel Thierry 459e8ebd8e2SDave Gordon #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 460762d9936SMichel Thierry for (iter = gen8_pml4e_index(start); \ 461e8ebd8e2SDave Gordon length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 462e8ebd8e2SDave Gordon (pdp = (pml4)->pdps[iter], true); \ 463e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 464e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 465e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 466762d9936SMichel Thierry 4679271d959SMichel Thierry static inline uint32_t gen8_pte_index(uint64_t address) 4689271d959SMichel Thierry { 4699271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 4709271d959SMichel Thierry } 4719271d959SMichel Thierry 4729271d959SMichel Thierry static inline uint32_t gen8_pde_index(uint64_t address) 4739271d959SMichel Thierry { 4749271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 4759271d959SMichel Thierry } 4769271d959SMichel Thierry 4779271d959SMichel Thierry static inline uint32_t gen8_pdpe_index(uint64_t address) 4789271d959SMichel Thierry { 4799271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 4809271d959SMichel Thierry } 4819271d959SMichel Thierry 4829271d959SMichel Thierry static inline uint32_t gen8_pml4e_index(uint64_t address) 4839271d959SMichel Thierry { 484762d9936SMichel Thierry return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 4859271d959SMichel Thierry } 4869271d959SMichel Thierry 48733c8819fSMichel Thierry static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 48833c8819fSMichel Thierry { 48933c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 49033c8819fSMichel Thierry } 49133c8819fSMichel Thierry 492d852c7bfSMika Kuoppala static inline dma_addr_t 493d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 494d852c7bfSMika Kuoppala { 495d852c7bfSMika Kuoppala return test_bit(n, ppgtt->pdp.used_pdpes) ? 496567047beSMika Kuoppala px_dma(ppgtt->pdp.page_directory[n]) : 49779ab9370SMika Kuoppala px_dma(ppgtt->base.scratch_pd); 498d852c7bfSMika Kuoppala } 499d852c7bfSMika Kuoppala 500b42fe9caSJoonas Lahtinen static inline struct i915_ggtt * 501b42fe9caSJoonas Lahtinen i915_vm_to_ggtt(struct i915_address_space *vm) 502b42fe9caSJoonas Lahtinen { 503b42fe9caSJoonas Lahtinen GEM_BUG_ON(!i915_is_ggtt(vm)); 504b42fe9caSJoonas Lahtinen return container_of(vm, struct i915_ggtt, base); 505b42fe9caSJoonas Lahtinen } 506b42fe9caSJoonas Lahtinen 50797d6d7abSChris Wilson int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 50897d6d7abSChris Wilson int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 50997d6d7abSChris Wilson int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 5107c3f86b6SChris Wilson void i915_ggtt_enable_guc(struct drm_i915_private *i915); 5117c3f86b6SChris Wilson void i915_ggtt_disable_guc(struct drm_i915_private *i915); 512f6b9d5caSChris Wilson int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 51397d6d7abSChris Wilson void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 514ee960be7SDaniel Vetter 515c6be607aSTvrtko Ursulin int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 516ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 5172bfa996eSChris Wilson struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 51880b204bcSChris Wilson struct drm_i915_file_private *fpriv, 51980b204bcSChris Wilson const char *name); 5200c7eeda1SChris Wilson void i915_ppgtt_close(struct i915_address_space *vm); 521ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 522ee960be7SDaniel Vetter { 523ee960be7SDaniel Vetter if (ppgtt) 524ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 525ee960be7SDaniel Vetter } 526ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 527ee960be7SDaniel Vetter { 528ee960be7SDaniel Vetter if (ppgtt) 529ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 530ee960be7SDaniel Vetter } 5310260c420SBen Widawsky 532dc97997aSChris Wilson void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 533275a991cSTvrtko Ursulin void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 534275a991cSTvrtko Ursulin void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 5350260c420SBen Widawsky 53603ac84f1SChris Wilson int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 53703ac84f1SChris Wilson struct sg_table *pages); 53803ac84f1SChris Wilson void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 53903ac84f1SChris Wilson struct sg_table *pages); 5400260c420SBen Widawsky 541625d988aSChris Wilson int i915_gem_gtt_reserve(struct i915_address_space *vm, 542625d988aSChris Wilson struct drm_mm_node *node, 543625d988aSChris Wilson u64 size, u64 offset, unsigned long color, 544625d988aSChris Wilson unsigned int flags); 545625d988aSChris Wilson 546e007b19dSChris Wilson int i915_gem_gtt_insert(struct i915_address_space *vm, 547e007b19dSChris Wilson struct drm_mm_node *node, 548e007b19dSChris Wilson u64 size, u64 alignment, unsigned long color, 549e007b19dSChris Wilson u64 start, u64 end, unsigned int flags); 550e007b19dSChris Wilson 55159bfa124SChris Wilson /* Flags used by pin/bind&friends. */ 552305bc234SChris Wilson #define PIN_NONBLOCK BIT(0) 553305bc234SChris Wilson #define PIN_MAPPABLE BIT(1) 554305bc234SChris Wilson #define PIN_ZONE_4G BIT(2) 55582118877SChris Wilson #define PIN_NONFAULT BIT(3) 556305bc234SChris Wilson 557305bc234SChris Wilson #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 558305bc234SChris Wilson #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 559305bc234SChris Wilson #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 560305bc234SChris Wilson #define PIN_UPDATE BIT(8) 561305bc234SChris Wilson 562305bc234SChris Wilson #define PIN_HIGH BIT(9) 563305bc234SChris Wilson #define PIN_OFFSET_BIAS BIT(10) 564305bc234SChris Wilson #define PIN_OFFSET_FIXED BIT(11) 565f51455d4SChris Wilson #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 56659bfa124SChris Wilson 5670260c420SBen Widawsky #endif 568