10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 374d884705SDaniel Vetter struct drm_i915_file_private; 384d884705SDaniel Vetter 3907749ef3SMichel Thierry typedef uint32_t gen6_pte_t; 4007749ef3SMichel Thierry typedef uint64_t gen8_pte_t; 4107749ef3SMichel Thierry typedef uint64_t gen8_pde_t; 420260c420SBen Widawsky 430260c420SBen Widawsky #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 440260c420SBen Widawsky 4507749ef3SMichel Thierry 460260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 470260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 480260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 490260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 500260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 510260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 520260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 530260c420SBen Widawsky 5407749ef3SMichel Thierry #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 5507749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 5607749ef3SMichel Thierry #define I915_PDES 512 5707749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 58678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 5907749ef3SMichel Thierry 6007749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 6107749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 620260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 63678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 640260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 650260c420SBen Widawsky 660260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 670260c420SBen Widawsky 680260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 690260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 700260c420SBen Widawsky 710260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 720260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 730260c420SBen Widawsky */ 740260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 750260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 760260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 770260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 780260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 790260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 800260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 810260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 820260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 830260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 840260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 850260c420SBen Widawsky 860260c420SBen Widawsky /* GEN8 legacy style address is defined as a 3 level page table: 870260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 880260c420SBen Widawsky * PDPE | PDE | PTE | offset 890260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 900260c420SBen Widawsky * programmed via register. 910260c420SBen Widawsky */ 920260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 930260c420SBen Widawsky #define GEN8_PDPE_MASK 0x3 940260c420SBen Widawsky #define GEN8_PDE_SHIFT 21 950260c420SBen Widawsky #define GEN8_PDE_MASK 0x1ff 960260c420SBen Widawsky #define GEN8_PTE_SHIFT 12 970260c420SBen Widawsky #define GEN8_PTE_MASK 0x1ff 9876643600SBen Widawsky #define GEN8_LEGACY_PDPES 4 9907749ef3SMichel Thierry #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 1000260c420SBen Widawsky 1010260c420SBen Widawsky #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 1020260c420SBen Widawsky #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 1030260c420SBen Widawsky #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 1040260c420SBen Widawsky #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 1050260c420SBen Widawsky 106ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1070260c420SBen Widawsky #define GEN8_PPAT_AGE(x) (x<<4) 1080260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1090260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1100260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1110260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1120260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1130260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1140260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1150260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1160260c420SBen Widawsky #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 1170260c420SBen Widawsky 118fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type { 119fe14d5f4STvrtko Ursulin I915_GGTT_VIEW_NORMAL = 0, 1208bd7ef16SJoonas Lahtinen I915_GGTT_VIEW_ROTATED, 1218bd7ef16SJoonas Lahtinen I915_GGTT_VIEW_PARTIAL, 12250470bb0STvrtko Ursulin }; 12350470bb0STvrtko Ursulin 12450470bb0STvrtko Ursulin struct intel_rotation_info { 12550470bb0STvrtko Ursulin unsigned int height; 12650470bb0STvrtko Ursulin unsigned int pitch; 12750470bb0STvrtko Ursulin uint32_t pixel_format; 12850470bb0STvrtko Ursulin uint64_t fb_modifier; 12984fe03f7STvrtko Ursulin unsigned int width_pages, height_pages; 13084fe03f7STvrtko Ursulin uint64_t size; 131fe14d5f4STvrtko Ursulin }; 132fe14d5f4STvrtko Ursulin 133fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 134fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 135fe14d5f4STvrtko Ursulin 1368bd7ef16SJoonas Lahtinen union { 1378bd7ef16SJoonas Lahtinen struct { 1388bd7ef16SJoonas Lahtinen unsigned long offset; 1398bd7ef16SJoonas Lahtinen unsigned int size; 1408bd7ef16SJoonas Lahtinen } partial; 1418bd7ef16SJoonas Lahtinen } params; 1428bd7ef16SJoonas Lahtinen 143fe14d5f4STvrtko Ursulin struct sg_table *pages; 14450470bb0STvrtko Ursulin 14550470bb0STvrtko Ursulin union { 14650470bb0STvrtko Ursulin struct intel_rotation_info rotation_info; 14750470bb0STvrtko Ursulin }; 148fe14d5f4STvrtko Ursulin }; 149fe14d5f4STvrtko Ursulin 150fe14d5f4STvrtko Ursulin extern const struct i915_ggtt_view i915_ggtt_view_normal; 1519abc4648SJoonas Lahtinen extern const struct i915_ggtt_view i915_ggtt_view_rotated; 152fe14d5f4STvrtko Ursulin 1530260c420SBen Widawsky enum i915_cache_level; 154fe14d5f4STvrtko Ursulin 1550260c420SBen Widawsky /** 1560260c420SBen Widawsky * A VMA represents a GEM BO that is bound into an address space. Therefore, a 1570260c420SBen Widawsky * VMA's presence cannot be guaranteed before binding, or after unbinding the 1580260c420SBen Widawsky * object into/from the address space. 1590260c420SBen Widawsky * 1600260c420SBen Widawsky * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 1610260c420SBen Widawsky * will always be <= an objects lifetime. So object refcounting should cover us. 1620260c420SBen Widawsky */ 1630260c420SBen Widawsky struct i915_vma { 1640260c420SBen Widawsky struct drm_mm_node node; 1650260c420SBen Widawsky struct drm_i915_gem_object *obj; 1660260c420SBen Widawsky struct i915_address_space *vm; 1670260c420SBen Widawsky 168aff43766STvrtko Ursulin /** Flags and address space this VMA is bound to */ 169aff43766STvrtko Ursulin #define GLOBAL_BIND (1<<0) 170aff43766STvrtko Ursulin #define LOCAL_BIND (1<<1) 171aff43766STvrtko Ursulin unsigned int bound : 4; 172aff43766STvrtko Ursulin 173fe14d5f4STvrtko Ursulin /** 174fe14d5f4STvrtko Ursulin * Support different GGTT views into the same object. 175fe14d5f4STvrtko Ursulin * This means there can be multiple VMA mappings per object and per VM. 176fe14d5f4STvrtko Ursulin * i915_ggtt_view_type is used to distinguish between those entries. 177fe14d5f4STvrtko Ursulin * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 178fe14d5f4STvrtko Ursulin * assumed in GEM functions which take no ggtt view parameter. 179fe14d5f4STvrtko Ursulin */ 180fe14d5f4STvrtko Ursulin struct i915_ggtt_view ggtt_view; 181fe14d5f4STvrtko Ursulin 1820260c420SBen Widawsky /** This object's place on the active/inactive lists */ 1830260c420SBen Widawsky struct list_head mm_list; 1840260c420SBen Widawsky 1850260c420SBen Widawsky struct list_head vma_link; /* Link in the object's VMA list */ 1860260c420SBen Widawsky 1870260c420SBen Widawsky /** This vma's place in the batchbuffer or on the eviction list */ 1880260c420SBen Widawsky struct list_head exec_list; 1890260c420SBen Widawsky 1900260c420SBen Widawsky /** 1910260c420SBen Widawsky * Used for performing relocations during execbuffer insertion. 1920260c420SBen Widawsky */ 1930260c420SBen Widawsky struct hlist_node exec_node; 1940260c420SBen Widawsky unsigned long exec_handle; 1950260c420SBen Widawsky struct drm_i915_gem_exec_object2 *exec_entry; 1960260c420SBen Widawsky 1970260c420SBen Widawsky /** 1980260c420SBen Widawsky * How many users have pinned this object in GTT space. The following 1994feb7659SDaniel Vetter * users can each hold at most one reference: pwrite/pread, execbuffer 2004feb7659SDaniel Vetter * (objects are not allowed multiple times for the same batchbuffer), 2014feb7659SDaniel Vetter * and the framebuffer code. When switching/pageflipping, the 2024feb7659SDaniel Vetter * framebuffer code has at most two buffers pinned per crtc. 2030260c420SBen Widawsky * 2040260c420SBen Widawsky * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 2050260c420SBen Widawsky * bits with absolutely no headroom. So use 4 bits. */ 2060260c420SBen Widawsky unsigned int pin_count:4; 2070260c420SBen Widawsky #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 2080260c420SBen Widawsky }; 2090260c420SBen Widawsky 21044159ddbSMika Kuoppala struct i915_page_dma { 211d7b3de91SBen Widawsky struct page *page; 21244159ddbSMika Kuoppala union { 2137324cc04SBen Widawsky dma_addr_t daddr; 214678d96fbSBen Widawsky 21544159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 21644159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 21744159ddbSMika Kuoppala */ 21844159ddbSMika Kuoppala uint32_t ggtt_offset; 21944159ddbSMika Kuoppala }; 22044159ddbSMika Kuoppala }; 22144159ddbSMika Kuoppala 222567047beSMika Kuoppala #define px_base(px) (&(px)->base) 223567047beSMika Kuoppala #define px_page(px) (px_base(px)->page) 224567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 225567047beSMika Kuoppala 226c114f76aSMika Kuoppala struct i915_page_scratch { 227c114f76aSMika Kuoppala struct i915_page_dma base; 228c114f76aSMika Kuoppala }; 229c114f76aSMika Kuoppala 23044159ddbSMika Kuoppala struct i915_page_table { 23144159ddbSMika Kuoppala struct i915_page_dma base; 23244159ddbSMika Kuoppala 233678d96fbSBen Widawsky unsigned long *used_ptes; 234d7b3de91SBen Widawsky }; 235d7b3de91SBen Widawsky 236ec565b3cSMichel Thierry struct i915_page_directory { 23744159ddbSMika Kuoppala struct i915_page_dma base; 2387324cc04SBen Widawsky 23933c8819fSMichel Thierry unsigned long *used_pdes; 240ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 241d7b3de91SBen Widawsky }; 242d7b3de91SBen Widawsky 243ec565b3cSMichel Thierry struct i915_page_directory_pointer { 244d7b3de91SBen Widawsky /* struct page *page; */ 24533c8819fSMichel Thierry DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES); 246ec565b3cSMichel Thierry struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES]; 247d7b3de91SBen Widawsky }; 248d7b3de91SBen Widawsky 2490260c420SBen Widawsky struct i915_address_space { 2500260c420SBen Widawsky struct drm_mm mm; 2510260c420SBen Widawsky struct drm_device *dev; 2520260c420SBen Widawsky struct list_head global_link; 253c44ef60eSMika Kuoppala u64 start; /* Start offset always 0 for dri2 */ 254c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 2550260c420SBen Widawsky 256c114f76aSMika Kuoppala struct i915_page_scratch *scratch_page; 25779ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 25879ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 2590260c420SBen Widawsky 2600260c420SBen Widawsky /** 2610260c420SBen Widawsky * List of objects currently involved in rendering. 2620260c420SBen Widawsky * 2630260c420SBen Widawsky * Includes buffers having the contents of their GPU caches 26497b2a6a1SJohn Harrison * flushed, not necessarily primitives. last_read_req 2650260c420SBen Widawsky * represents when the rendering involved will be completed. 2660260c420SBen Widawsky * 2670260c420SBen Widawsky * A reference is held on the buffer while on this list. 2680260c420SBen Widawsky */ 2690260c420SBen Widawsky struct list_head active_list; 2700260c420SBen Widawsky 2710260c420SBen Widawsky /** 2720260c420SBen Widawsky * LRU list of objects which are not in the ringbuffer and 2730260c420SBen Widawsky * are ready to unbind, but are still in the GTT. 2740260c420SBen Widawsky * 27597b2a6a1SJohn Harrison * last_read_req is NULL while an object is in this list. 2760260c420SBen Widawsky * 2770260c420SBen Widawsky * A reference is not held on the buffer while on this list, 2780260c420SBen Widawsky * as merely being GTT-bound shouldn't prevent its being 2790260c420SBen Widawsky * freed, and we'll pull it off the list in the free path. 2800260c420SBen Widawsky */ 2810260c420SBen Widawsky struct list_head inactive_list; 2820260c420SBen Widawsky 2830260c420SBen Widawsky /* FIXME: Need a more generic return type */ 28407749ef3SMichel Thierry gen6_pte_t (*pte_encode)(dma_addr_t addr, 2850260c420SBen Widawsky enum i915_cache_level level, 28624f3a8cfSAkash Goel bool valid, u32 flags); /* Create a valid PTE */ 287f329f5f6SDaniel Vetter /* flags for pte_encode */ 288f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 289678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 290678d96fbSBen Widawsky uint64_t start, 291678d96fbSBen Widawsky uint64_t length); 2920260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 2930260c420SBen Widawsky uint64_t start, 2940260c420SBen Widawsky uint64_t length, 2950260c420SBen Widawsky bool use_scratch); 2960260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 2970260c420SBen Widawsky struct sg_table *st, 2980260c420SBen Widawsky uint64_t start, 29924f3a8cfSAkash Goel enum i915_cache_level cache_level, u32 flags); 3000260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 301777dc5bbSDaniel Vetter /** Unmap an object from an address space. This usually consists of 302777dc5bbSDaniel Vetter * setting the valid PTE entries to a reserved scratch page. */ 303777dc5bbSDaniel Vetter void (*unbind_vma)(struct i915_vma *vma); 304777dc5bbSDaniel Vetter /* Map an object into an address space with the given cache flags. */ 30570b9f6f8SDaniel Vetter int (*bind_vma)(struct i915_vma *vma, 306777dc5bbSDaniel Vetter enum i915_cache_level cache_level, 307777dc5bbSDaniel Vetter u32 flags); 3080260c420SBen Widawsky }; 3090260c420SBen Widawsky 3100260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3110260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3120260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3130260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3140260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3150260c420SBen Widawsky * the spec. 3160260c420SBen Widawsky */ 3170260c420SBen Widawsky struct i915_gtt { 3180260c420SBen Widawsky struct i915_address_space base; 3190260c420SBen Widawsky 320c44ef60eSMika Kuoppala size_t stolen_size; /* Total size of stolen memory */ 321c44ef60eSMika Kuoppala u64 mappable_end; /* End offset that we can CPU map */ 3220260c420SBen Widawsky struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 3230260c420SBen Widawsky phys_addr_t mappable_base; /* PA of our GMADR */ 3240260c420SBen Widawsky 3250260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3260260c420SBen Widawsky void __iomem *gsm; 3270260c420SBen Widawsky 3280260c420SBen Widawsky bool do_idle_maps; 3290260c420SBen Widawsky 3300260c420SBen Widawsky int mtrr; 3310260c420SBen Widawsky 3320260c420SBen Widawsky /* global gtt ops */ 333c44ef60eSMika Kuoppala int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total, 3340260c420SBen Widawsky size_t *stolen, phys_addr_t *mappable_base, 335c44ef60eSMika Kuoppala u64 *mappable_end); 3360260c420SBen Widawsky }; 3370260c420SBen Widawsky 3380260c420SBen Widawsky struct i915_hw_ppgtt { 3390260c420SBen Widawsky struct i915_address_space base; 3400260c420SBen Widawsky struct kref ref; 3410260c420SBen Widawsky struct drm_mm_node node; 342563222a7SBen Widawsky unsigned long pd_dirty_rings; 3430260c420SBen Widawsky union { 344ec565b3cSMichel Thierry struct i915_page_directory_pointer pdp; 345ec565b3cSMichel Thierry struct i915_page_directory pd; 346d7b3de91SBen Widawsky }; 3470260c420SBen Widawsky 3484d884705SDaniel Vetter struct drm_i915_file_private *file_priv; 3490260c420SBen Widawsky 350678d96fbSBen Widawsky gen6_pte_t __iomem *pd_addr; 351678d96fbSBen Widawsky 3520260c420SBen Widawsky int (*enable)(struct i915_hw_ppgtt *ppgtt); 3530260c420SBen Widawsky int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 354e85b26dcSJohn Harrison struct drm_i915_gem_request *req); 3550260c420SBen Widawsky void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 3560260c420SBen Widawsky }; 3570260c420SBen Widawsky 358678d96fbSBen Widawsky /* For each pde iterates over every pde between from start until start + length. 359678d96fbSBen Widawsky * If start, and start+length are not perfectly divisible, the macro will round 360678d96fbSBen Widawsky * down, and up as needed. The macro modifies pde, start, and length. Dev is 361678d96fbSBen Widawsky * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, 362678d96fbSBen Widawsky * and length = 2G effectively iterates over every PDE in the system. 363678d96fbSBen Widawsky * 364678d96fbSBen Widawsky * XXX: temp is not actually needed, but it saves doing the ALIGN operation. 365678d96fbSBen Widawsky */ 366678d96fbSBen Widawsky #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ 367fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 368fdc454c1SMichel Thierry pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 369fdc454c1SMichel Thierry iter++, \ 370678d96fbSBen Widawsky temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ 371678d96fbSBen Widawsky temp = min_t(unsigned, temp, length), \ 372678d96fbSBen Widawsky start += temp, length -= temp) 373678d96fbSBen Widawsky 37409942c65SMichel Thierry #define gen6_for_all_pdes(pt, ppgtt, iter) \ 37509942c65SMichel Thierry for (iter = 0; \ 37609942c65SMichel Thierry pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ 37709942c65SMichel Thierry iter++) 37809942c65SMichel Thierry 379678d96fbSBen Widawsky static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 380678d96fbSBen Widawsky { 381678d96fbSBen Widawsky const uint32_t mask = NUM_PTE(pde_shift) - 1; 382678d96fbSBen Widawsky 383678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 384678d96fbSBen Widawsky } 385678d96fbSBen Widawsky 386678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 387678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 388678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 389678d96fbSBen Widawsky */ 390678d96fbSBen Widawsky static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 391678d96fbSBen Widawsky uint32_t pde_shift) 392678d96fbSBen Widawsky { 393678d96fbSBen Widawsky const uint64_t mask = ~((1 << pde_shift) - 1); 394678d96fbSBen Widawsky uint64_t end; 395678d96fbSBen Widawsky 396678d96fbSBen Widawsky WARN_ON(length == 0); 397678d96fbSBen Widawsky WARN_ON(offset_in_page(addr|length)); 398678d96fbSBen Widawsky 399678d96fbSBen Widawsky end = addr + length; 400678d96fbSBen Widawsky 401678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 402678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 403678d96fbSBen Widawsky 404678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 405678d96fbSBen Widawsky } 406678d96fbSBen Widawsky 407678d96fbSBen Widawsky static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 408678d96fbSBen Widawsky { 409678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 410678d96fbSBen Widawsky } 411678d96fbSBen Widawsky 412678d96fbSBen Widawsky static inline uint32_t gen6_pte_index(uint32_t addr) 413678d96fbSBen Widawsky { 414678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 415678d96fbSBen Widawsky } 416678d96fbSBen Widawsky 417678d96fbSBen Widawsky static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 418678d96fbSBen Widawsky { 419678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 420678d96fbSBen Widawsky } 421678d96fbSBen Widawsky 422678d96fbSBen Widawsky static inline uint32_t gen6_pde_index(uint32_t addr) 423678d96fbSBen Widawsky { 424678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 425678d96fbSBen Widawsky } 426678d96fbSBen Widawsky 4279271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4289271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4299271d959SMichel Thierry * over every page directory entry in a page directory. 4309271d959SMichel Thierry */ 4319271d959SMichel Thierry #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ 4329271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 4339271d959SMichel Thierry pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 4349271d959SMichel Thierry iter++, \ 4359271d959SMichel Thierry temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ 4369271d959SMichel Thierry temp = min(temp, length), \ 4379271d959SMichel Thierry start += temp, length -= temp) 4389271d959SMichel Thierry 4399271d959SMichel Thierry #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ 4409271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 4419271d959SMichel Thierry pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \ 4429271d959SMichel Thierry iter++, \ 4439271d959SMichel Thierry temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ 4449271d959SMichel Thierry temp = min(temp, length), \ 4459271d959SMichel Thierry start += temp, length -= temp) 4469271d959SMichel Thierry 4479271d959SMichel Thierry /* Clamp length to the next page_directory boundary */ 4489271d959SMichel Thierry static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) 4499271d959SMichel Thierry { 4509271d959SMichel Thierry uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); 4519271d959SMichel Thierry 4529271d959SMichel Thierry if (next_pd > (start + length)) 4539271d959SMichel Thierry return length; 4549271d959SMichel Thierry 4559271d959SMichel Thierry return next_pd - start; 4569271d959SMichel Thierry } 4579271d959SMichel Thierry 4589271d959SMichel Thierry static inline uint32_t gen8_pte_index(uint64_t address) 4599271d959SMichel Thierry { 4609271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 4619271d959SMichel Thierry } 4629271d959SMichel Thierry 4639271d959SMichel Thierry static inline uint32_t gen8_pde_index(uint64_t address) 4649271d959SMichel Thierry { 4659271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 4669271d959SMichel Thierry } 4679271d959SMichel Thierry 4689271d959SMichel Thierry static inline uint32_t gen8_pdpe_index(uint64_t address) 4699271d959SMichel Thierry { 4709271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 4719271d959SMichel Thierry } 4729271d959SMichel Thierry 4739271d959SMichel Thierry static inline uint32_t gen8_pml4e_index(uint64_t address) 4749271d959SMichel Thierry { 4759271d959SMichel Thierry WARN_ON(1); /* For 64B */ 4769271d959SMichel Thierry return 0; 4779271d959SMichel Thierry } 4789271d959SMichel Thierry 47933c8819fSMichel Thierry static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 48033c8819fSMichel Thierry { 48133c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 48233c8819fSMichel Thierry } 48333c8819fSMichel Thierry 484d852c7bfSMika Kuoppala static inline dma_addr_t 485d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 486d852c7bfSMika Kuoppala { 487d852c7bfSMika Kuoppala return test_bit(n, ppgtt->pdp.used_pdpes) ? 488567047beSMika Kuoppala px_dma(ppgtt->pdp.page_directory[n]) : 48979ab9370SMika Kuoppala px_dma(ppgtt->base.scratch_pd); 490d852c7bfSMika Kuoppala } 491d852c7bfSMika Kuoppala 4920260c420SBen Widawsky int i915_gem_gtt_init(struct drm_device *dev); 4930260c420SBen Widawsky void i915_gem_init_global_gtt(struct drm_device *dev); 49490d0a0e8SDaniel Vetter void i915_global_gtt_cleanup(struct drm_device *dev); 4950260c420SBen Widawsky 496ee960be7SDaniel Vetter 497ee960be7SDaniel Vetter int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 49882460d97SDaniel Vetter int i915_ppgtt_init_hw(struct drm_device *dev); 499b3dd6b96SJohn Harrison int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); 500ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 5014d884705SDaniel Vetter struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 5024d884705SDaniel Vetter struct drm_i915_file_private *fpriv); 503ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 504ee960be7SDaniel Vetter { 505ee960be7SDaniel Vetter if (ppgtt) 506ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 507ee960be7SDaniel Vetter } 508ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 509ee960be7SDaniel Vetter { 510ee960be7SDaniel Vetter if (ppgtt) 511ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 512ee960be7SDaniel Vetter } 5130260c420SBen Widawsky 5140260c420SBen Widawsky void i915_check_and_clear_faults(struct drm_device *dev); 5150260c420SBen Widawsky void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 5160260c420SBen Widawsky void i915_gem_restore_gtt_mappings(struct drm_device *dev); 5170260c420SBen Widawsky 5180260c420SBen Widawsky int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 5190260c420SBen Widawsky void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 5200260c420SBen Widawsky 5219abc4648SJoonas Lahtinen static inline bool 5229abc4648SJoonas Lahtinen i915_ggtt_view_equal(const struct i915_ggtt_view *a, 5239abc4648SJoonas Lahtinen const struct i915_ggtt_view *b) 5249abc4648SJoonas Lahtinen { 5259abc4648SJoonas Lahtinen if (WARN_ON(!a || !b)) 5269abc4648SJoonas Lahtinen return false; 5279abc4648SJoonas Lahtinen 5288bd7ef16SJoonas Lahtinen if (a->type != b->type) 5298bd7ef16SJoonas Lahtinen return false; 5308bd7ef16SJoonas Lahtinen if (a->type == I915_GGTT_VIEW_PARTIAL) 5318bd7ef16SJoonas Lahtinen return !memcmp(&a->params, &b->params, sizeof(a->params)); 5328bd7ef16SJoonas Lahtinen return true; 5339abc4648SJoonas Lahtinen } 5349abc4648SJoonas Lahtinen 53591e6711eSJoonas Lahtinen size_t 53691e6711eSJoonas Lahtinen i915_ggtt_view_size(struct drm_i915_gem_object *obj, 53791e6711eSJoonas Lahtinen const struct i915_ggtt_view *view); 53891e6711eSJoonas Lahtinen 5390260c420SBen Widawsky #endif 540