10260c420SBen Widawsky /* 20260c420SBen Widawsky * Copyright © 2014 Intel Corporation 30260c420SBen Widawsky * 40260c420SBen Widawsky * Permission is hereby granted, free of charge, to any person obtaining a 50260c420SBen Widawsky * copy of this software and associated documentation files (the "Software"), 60260c420SBen Widawsky * to deal in the Software without restriction, including without limitation 70260c420SBen Widawsky * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80260c420SBen Widawsky * and/or sell copies of the Software, and to permit persons to whom the 90260c420SBen Widawsky * Software is furnished to do so, subject to the following conditions: 100260c420SBen Widawsky * 110260c420SBen Widawsky * The above copyright notice and this permission notice (including the next 120260c420SBen Widawsky * paragraph) shall be included in all copies or substantial portions of the 130260c420SBen Widawsky * Software. 140260c420SBen Widawsky * 150260c420SBen Widawsky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 160260c420SBen Widawsky * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 170260c420SBen Widawsky * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 180260c420SBen Widawsky * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 190260c420SBen Widawsky * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 200260c420SBen Widawsky * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 210260c420SBen Widawsky * IN THE SOFTWARE. 220260c420SBen Widawsky * 230260c420SBen Widawsky * Please try to maintain the following order within this file unless it makes 240260c420SBen Widawsky * sense to do otherwise. From top to bottom: 250260c420SBen Widawsky * 1. typedefs 260260c420SBen Widawsky * 2. #defines, and macros 270260c420SBen Widawsky * 3. structure definitions 280260c420SBen Widawsky * 4. function prototypes 290260c420SBen Widawsky * 300260c420SBen Widawsky * Within each section, please try to order by generation in ascending order, 310260c420SBen Widawsky * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 320260c420SBen Widawsky */ 330260c420SBen Widawsky 340260c420SBen Widawsky #ifndef __I915_GEM_GTT_H__ 350260c420SBen Widawsky #define __I915_GEM_GTT_H__ 360260c420SBen Widawsky 378ef8561fSChris Wilson #include <linux/io-mapping.h> 38b42fe9caSJoonas Lahtinen #include <linux/mm.h> 398448661dSChris Wilson #include <linux/pagevec.h> 408ef8561fSChris Wilson 41b42fe9caSJoonas Lahtinen #include "i915_gem_timeline.h" 42b0decaf7SChris Wilson #include "i915_gem_request.h" 438448661dSChris Wilson #include "i915_selftest.h" 44b0decaf7SChris Wilson 45f51455d4SChris Wilson #define I915_GTT_PAGE_SIZE 4096UL 46f51455d4SChris Wilson #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 47f51455d4SChris Wilson 4849ef5294SChris Wilson #define I915_FENCE_REG_NONE -1 4949ef5294SChris Wilson #define I915_MAX_NUM_FENCES 32 5049ef5294SChris Wilson /* 32 fences + sign bit for FENCE_REG_NONE */ 5149ef5294SChris Wilson #define I915_MAX_NUM_FENCE_BITS 6 5249ef5294SChris Wilson 534d884705SDaniel Vetter struct drm_i915_file_private; 5449ef5294SChris Wilson struct drm_i915_fence_reg; 554d884705SDaniel Vetter 5675c7b0b8SChris Wilson typedef u32 gen6_pte_t; 5775c7b0b8SChris Wilson typedef u64 gen8_pte_t; 5875c7b0b8SChris Wilson typedef u64 gen8_pde_t; 5975c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pdpe_t; 6075c7b0b8SChris Wilson typedef u64 gen8_ppgtt_pml4e_t; 610260c420SBen Widawsky 6272e96d64SJoonas Lahtinen #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 630260c420SBen Widawsky 640260c420SBen Widawsky /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 650260c420SBen Widawsky #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 660260c420SBen Widawsky #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 670260c420SBen Widawsky #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 680260c420SBen Widawsky #define GEN6_PTE_CACHE_LLC (2 << 1) 690260c420SBen Widawsky #define GEN6_PTE_UNCACHED (1 << 1) 700260c420SBen Widawsky #define GEN6_PTE_VALID (1 << 0) 710260c420SBen Widawsky 72dd19674bSChris Wilson #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 7307749ef3SMichel Thierry #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 7407749ef3SMichel Thierry #define I915_PDES 512 7507749ef3SMichel Thierry #define I915_PDE_MASK (I915_PDES - 1) 76678d96fbSBen Widawsky #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 7707749ef3SMichel Thierry 7807749ef3SMichel Thierry #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 7907749ef3SMichel Thierry #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 800260c420SBen Widawsky #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 81678d96fbSBen Widawsky #define GEN6_PDE_SHIFT 22 820260c420SBen Widawsky #define GEN6_PDE_VALID (1 << 0) 830260c420SBen Widawsky 840260c420SBen Widawsky #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 850260c420SBen Widawsky 860260c420SBen Widawsky #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 870260c420SBen Widawsky #define BYT_PTE_WRITEABLE (1 << 1) 880260c420SBen Widawsky 890260c420SBen Widawsky /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 900260c420SBen Widawsky * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 910260c420SBen Widawsky */ 920260c420SBen Widawsky #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 930260c420SBen Widawsky (((bits) & 0x8) << (11 - 3))) 940260c420SBen Widawsky #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 950260c420SBen Widawsky #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 960260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 970260c420SBen Widawsky #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 980260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 990260c420SBen Widawsky #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1000260c420SBen Widawsky #define HSW_PTE_UNCACHED (0) 1010260c420SBen Widawsky #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1020260c420SBen Widawsky #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1030260c420SBen Widawsky 104e7167769SMika Kuoppala /* GEN8 32b style address is defined as a 3 level page table: 1050260c420SBen Widawsky * 31:30 | 29:21 | 20:12 | 11:0 1060260c420SBen Widawsky * PDPE | PDE | PTE | offset 1070260c420SBen Widawsky * The difference as compared to normal x86 3 level page table is the PDPEs are 1080260c420SBen Widawsky * programmed via register. 109e7167769SMika Kuoppala */ 110e7167769SMika Kuoppala #define GEN8_3LVL_PDPES 4 111e7167769SMika Kuoppala #define GEN8_PDE_SHIFT 21 112e7167769SMika Kuoppala #define GEN8_PDE_MASK 0x1ff 113e7167769SMika Kuoppala #define GEN8_PTE_SHIFT 12 114e7167769SMika Kuoppala #define GEN8_PTE_MASK 0x1ff 115e7167769SMika Kuoppala #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 116e7167769SMika Kuoppala 117e7167769SMika Kuoppala /* GEN8 48b style address is defined as a 4 level page table: 11881ba8aefSMichel Thierry * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 11981ba8aefSMichel Thierry * PML4E | PDPE | PDE | PTE | offset 1200260c420SBen Widawsky */ 12181ba8aefSMichel Thierry #define GEN8_PML4ES_PER_PML4 512 12281ba8aefSMichel Thierry #define GEN8_PML4E_SHIFT 39 123762d9936SMichel Thierry #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 1240260c420SBen Widawsky #define GEN8_PDPE_SHIFT 30 12581ba8aefSMichel Thierry /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 12681ba8aefSMichel Thierry * tables */ 12781ba8aefSMichel Thierry #define GEN8_PDPE_MASK 0x1ff 1280260c420SBen Widawsky 1290260c420SBen Widawsky #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 1300260c420SBen Widawsky #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 1310260c420SBen Widawsky #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 1320260c420SBen Widawsky #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 1330260c420SBen Widawsky 134ee0ce478SVille Syrjälä #define CHV_PPAT_SNOOP (1<<6) 1351790625bSMichal Wajdeczko #define GEN8_PPAT_AGE(x) ((x)<<4) 1360260c420SBen Widawsky #define GEN8_PPAT_LLCeLLC (3<<2) 1370260c420SBen Widawsky #define GEN8_PPAT_LLCELLC (2<<2) 1380260c420SBen Widawsky #define GEN8_PPAT_LLC (1<<2) 1390260c420SBen Widawsky #define GEN8_PPAT_WB (3<<0) 1400260c420SBen Widawsky #define GEN8_PPAT_WT (2<<0) 1410260c420SBen Widawsky #define GEN8_PPAT_WC (1<<0) 1420260c420SBen Widawsky #define GEN8_PPAT_UC (0<<0) 1430260c420SBen Widawsky #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 14475c7b0b8SChris Wilson #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1450260c420SBen Widawsky 1464395890aSZhi Wang #define GEN8_PPAT_GET_CA(x) ((x) & 3) 1474395890aSZhi Wang #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2)) 1484395890aSZhi Wang #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4)) 1494395890aSZhi Wang #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6)) 1504395890aSZhi Wang 151b42fe9caSJoonas Lahtinen struct sg_table; 152b42fe9caSJoonas Lahtinen 15350470bb0STvrtko Ursulin struct intel_rotation_info { 1547ff19c56SChris Wilson struct intel_rotation_plane_info { 1551663b9d6SVille Syrjälä /* tiles */ 1566687c906SVille Syrjälä unsigned int width, height, stride, offset; 1571663b9d6SVille Syrjälä } plane[2]; 1588d9046adSChris Wilson } __packed; 1598d9046adSChris Wilson 1608d9046adSChris Wilson static inline void assert_intel_rotation_info_is_packed(void) 1618d9046adSChris Wilson { 1628d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int)); 1638d9046adSChris Wilson } 164fe14d5f4STvrtko Ursulin 1657ff19c56SChris Wilson struct intel_partial_info { 1667ff19c56SChris Wilson u64 offset; 1677ff19c56SChris Wilson unsigned int size; 1688d9046adSChris Wilson } __packed; 1698d9046adSChris Wilson 1708d9046adSChris Wilson static inline void assert_intel_partial_info_is_packed(void) 1718d9046adSChris Wilson { 1728d9046adSChris Wilson BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int)); 1738d9046adSChris Wilson } 1747ff19c56SChris Wilson 175992e418dSChris Wilson enum i915_ggtt_view_type { 176992e418dSChris Wilson I915_GGTT_VIEW_NORMAL = 0, 177992e418dSChris Wilson I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), 178992e418dSChris Wilson I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), 179992e418dSChris Wilson }; 180992e418dSChris Wilson 181992e418dSChris Wilson static inline void assert_i915_ggtt_view_type_is_unique(void) 182992e418dSChris Wilson { 183992e418dSChris Wilson /* As we encode the size of each branch inside the union into its type, 184992e418dSChris Wilson * we have to be careful that each branch has a unique size. 185992e418dSChris Wilson */ 186992e418dSChris Wilson switch ((enum i915_ggtt_view_type)0) { 187992e418dSChris Wilson case I915_GGTT_VIEW_NORMAL: 188992e418dSChris Wilson case I915_GGTT_VIEW_PARTIAL: 189992e418dSChris Wilson case I915_GGTT_VIEW_ROTATED: 190992e418dSChris Wilson /* gcc complains if these are identical cases */ 191992e418dSChris Wilson break; 192992e418dSChris Wilson } 193992e418dSChris Wilson } 194992e418dSChris Wilson 195fe14d5f4STvrtko Ursulin struct i915_ggtt_view { 196fe14d5f4STvrtko Ursulin enum i915_ggtt_view_type type; 1978bd7ef16SJoonas Lahtinen union { 198992e418dSChris Wilson /* Members need to contain no holes/padding */ 1997ff19c56SChris Wilson struct intel_partial_info partial; 2007723f47dSVille Syrjälä struct intel_rotation_info rotated; 2018bab1193SChris Wilson }; 202fe14d5f4STvrtko Ursulin }; 203fe14d5f4STvrtko Ursulin 2040260c420SBen Widawsky enum i915_cache_level; 205fe14d5f4STvrtko Ursulin 206b42fe9caSJoonas Lahtinen struct i915_vma; 207bde13ebdSChris Wilson 20844159ddbSMika Kuoppala struct i915_page_dma { 209d7b3de91SBen Widawsky struct page *page; 21044159ddbSMika Kuoppala union { 2117324cc04SBen Widawsky dma_addr_t daddr; 212678d96fbSBen Widawsky 21344159ddbSMika Kuoppala /* For gen6/gen7 only. This is the offset in the GGTT 21444159ddbSMika Kuoppala * where the page directory entries for PPGTT begin 21544159ddbSMika Kuoppala */ 21675c7b0b8SChris Wilson u32 ggtt_offset; 21744159ddbSMika Kuoppala }; 21844159ddbSMika Kuoppala }; 21944159ddbSMika Kuoppala 220567047beSMika Kuoppala #define px_base(px) (&(px)->base) 221567047beSMika Kuoppala #define px_page(px) (px_base(px)->page) 222567047beSMika Kuoppala #define px_dma(px) (px_base(px)->daddr) 223567047beSMika Kuoppala 22444159ddbSMika Kuoppala struct i915_page_table { 22544159ddbSMika Kuoppala struct i915_page_dma base; 226dd19674bSChris Wilson unsigned int used_ptes; 227d7b3de91SBen Widawsky }; 228d7b3de91SBen Widawsky 229ec565b3cSMichel Thierry struct i915_page_directory { 23044159ddbSMika Kuoppala struct i915_page_dma base; 2317324cc04SBen Widawsky 232ec565b3cSMichel Thierry struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 233fe52e37fSChris Wilson unsigned int used_pdes; 234d7b3de91SBen Widawsky }; 235d7b3de91SBen Widawsky 236ec565b3cSMichel Thierry struct i915_page_directory_pointer { 2376ac18502SMichel Thierry struct i915_page_dma base; 2386ac18502SMichel Thierry struct i915_page_directory **page_directory; 239e2b763caSChris Wilson unsigned int used_pdpes; 240d7b3de91SBen Widawsky }; 241d7b3de91SBen Widawsky 24281ba8aefSMichel Thierry struct i915_pml4 { 24381ba8aefSMichel Thierry struct i915_page_dma base; 24481ba8aefSMichel Thierry struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 24581ba8aefSMichel Thierry }; 24681ba8aefSMichel Thierry 2470260c420SBen Widawsky struct i915_address_space { 2480260c420SBen Widawsky struct drm_mm mm; 24980b204bcSChris Wilson struct i915_gem_timeline timeline; 25049d73912SChris Wilson struct drm_i915_private *i915; 2518448661dSChris Wilson struct device *dma; 2522bfa996eSChris Wilson /* Every address space belongs to a struct file - except for the global 2532bfa996eSChris Wilson * GTT that is owned by the driver (and so @file is set to NULL). In 2542bfa996eSChris Wilson * principle, no information should leak from one context to another 2552bfa996eSChris Wilson * (or between files/processes etc) unless explicitly shared by the 2562bfa996eSChris Wilson * owner. Tracking the owner is important in order to free up per-file 2572bfa996eSChris Wilson * objects along with the file, to aide resource tracking, and to 2582bfa996eSChris Wilson * assign blame. 2592bfa996eSChris Wilson */ 2602bfa996eSChris Wilson struct drm_i915_file_private *file; 2610260c420SBen Widawsky struct list_head global_link; 262c44ef60eSMika Kuoppala u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 263ff8f7975SWeinan Li u64 reserved; /* size addr space reserved */ 2640260c420SBen Widawsky 26550e046b6SChris Wilson bool closed; 26650e046b6SChris Wilson 2678bcdd0f7SChris Wilson struct i915_page_dma scratch_page; 26879ab9370SMika Kuoppala struct i915_page_table *scratch_pt; 26979ab9370SMika Kuoppala struct i915_page_directory *scratch_pd; 27069ab76fdSMichel Thierry struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 2710260c420SBen Widawsky 2720260c420SBen Widawsky /** 2730260c420SBen Widawsky * List of objects currently involved in rendering. 2740260c420SBen Widawsky * 2750260c420SBen Widawsky * Includes buffers having the contents of their GPU caches 27697b2a6a1SJohn Harrison * flushed, not necessarily primitives. last_read_req 2770260c420SBen Widawsky * represents when the rendering involved will be completed. 2780260c420SBen Widawsky * 2790260c420SBen Widawsky * A reference is held on the buffer while on this list. 2800260c420SBen Widawsky */ 2810260c420SBen Widawsky struct list_head active_list; 2820260c420SBen Widawsky 2830260c420SBen Widawsky /** 2840260c420SBen Widawsky * LRU list of objects which are not in the ringbuffer and 2850260c420SBen Widawsky * are ready to unbind, but are still in the GTT. 2860260c420SBen Widawsky * 28797b2a6a1SJohn Harrison * last_read_req is NULL while an object is in this list. 2880260c420SBen Widawsky * 2890260c420SBen Widawsky * A reference is not held on the buffer while on this list, 2900260c420SBen Widawsky * as merely being GTT-bound shouldn't prevent its being 2910260c420SBen Widawsky * freed, and we'll pull it off the list in the free path. 2920260c420SBen Widawsky */ 2930260c420SBen Widawsky struct list_head inactive_list; 2940260c420SBen Widawsky 29550e046b6SChris Wilson /** 29650e046b6SChris Wilson * List of vma that have been unbound. 29750e046b6SChris Wilson * 29850e046b6SChris Wilson * A reference is not held on the buffer while on this list. 29950e046b6SChris Wilson */ 30050e046b6SChris Wilson struct list_head unbound_list; 30150e046b6SChris Wilson 3028448661dSChris Wilson struct pagevec free_pages; 3038448661dSChris Wilson bool pt_kmap_wc; 3048448661dSChris Wilson 3050260c420SBen Widawsky /* FIXME: Need a more generic return type */ 30607749ef3SMichel Thierry gen6_pte_t (*pte_encode)(dma_addr_t addr, 3070260c420SBen Widawsky enum i915_cache_level level, 3084fb84d99SMichał Winiarski u32 flags); /* Create a valid PTE */ 309f329f5f6SDaniel Vetter /* flags for pte_encode */ 310f329f5f6SDaniel Vetter #define PTE_READ_ONLY (1<<0) 311678d96fbSBen Widawsky int (*allocate_va_range)(struct i915_address_space *vm, 31275c7b0b8SChris Wilson u64 start, u64 length); 3130260c420SBen Widawsky void (*clear_range)(struct i915_address_space *vm, 31475c7b0b8SChris Wilson u64 start, u64 length); 315d6473f56SChris Wilson void (*insert_page)(struct i915_address_space *vm, 316d6473f56SChris Wilson dma_addr_t addr, 31775c7b0b8SChris Wilson u64 offset, 318d6473f56SChris Wilson enum i915_cache_level cache_level, 319d6473f56SChris Wilson u32 flags); 3200260c420SBen Widawsky void (*insert_entries)(struct i915_address_space *vm, 3214a234c5fSMatthew Auld struct i915_vma *vma, 32275c7b0b8SChris Wilson enum i915_cache_level cache_level, 32375c7b0b8SChris Wilson u32 flags); 3240260c420SBen Widawsky void (*cleanup)(struct i915_address_space *vm); 325777dc5bbSDaniel Vetter /** Unmap an object from an address space. This usually consists of 326777dc5bbSDaniel Vetter * setting the valid PTE entries to a reserved scratch page. */ 327777dc5bbSDaniel Vetter void (*unbind_vma)(struct i915_vma *vma); 328777dc5bbSDaniel Vetter /* Map an object into an address space with the given cache flags. */ 32970b9f6f8SDaniel Vetter int (*bind_vma)(struct i915_vma *vma, 330777dc5bbSDaniel Vetter enum i915_cache_level cache_level, 331777dc5bbSDaniel Vetter u32 flags); 3328448661dSChris Wilson 3338448661dSChris Wilson I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 3340260c420SBen Widawsky }; 3350260c420SBen Widawsky 3362bfa996eSChris Wilson #define i915_is_ggtt(V) (!(V)->file) 337596c5923SChris Wilson 3383e490042SMika Kuoppala static inline bool 3393e490042SMika Kuoppala i915_vm_is_48bit(const struct i915_address_space *vm) 3403e490042SMika Kuoppala { 3413e490042SMika Kuoppala return (vm->total - 1) >> 32; 3423e490042SMika Kuoppala } 3433e490042SMika Kuoppala 3440260c420SBen Widawsky /* The Graphics Translation Table is the way in which GEN hardware translates a 3450260c420SBen Widawsky * Graphics Virtual Address into a Physical Address. In addition to the normal 3460260c420SBen Widawsky * collateral associated with any va->pa translations GEN hardware also has a 3470260c420SBen Widawsky * portion of the GTT which can be mapped by the CPU and remain both coherent 3480260c420SBen Widawsky * and correct (in cases like swizzling). That region is referred to as GMADR in 3490260c420SBen Widawsky * the spec. 3500260c420SBen Widawsky */ 35162106b4fSJoonas Lahtinen struct i915_ggtt { 3520260c420SBen Widawsky struct i915_address_space base; 353f7bbe788SChris Wilson struct io_mapping mappable; /* Mapping to our CPU mappable region */ 3540260c420SBen Widawsky 355edd1f2feSChris Wilson phys_addr_t mappable_base; /* PA of our GMADR */ 356edd1f2feSChris Wilson u64 mappable_end; /* End offset that we can CPU map */ 357edd1f2feSChris Wilson 3583c6b29b2SPaulo Zanoni /* Stolen memory is segmented in hardware with different portions 3593c6b29b2SPaulo Zanoni * offlimits to certain functions. 3603c6b29b2SPaulo Zanoni * 3613c6b29b2SPaulo Zanoni * The drm_mm is initialised to the total accessible range, as found 3623c6b29b2SPaulo Zanoni * from the PCI config. On Broadwell+, this is further restricted to 3633c6b29b2SPaulo Zanoni * avoid the first page! The upper end of stolen memory is reserved for 3643c6b29b2SPaulo Zanoni * hardware functions and similarly removed from the accessible range. 3653c6b29b2SPaulo Zanoni */ 366edd1f2feSChris Wilson u32 stolen_size; /* Total size of stolen memory */ 367edd1f2feSChris Wilson u32 stolen_usable_size; /* Total size minus reserved ranges */ 368edd1f2feSChris Wilson u32 stolen_reserved_base; 369edd1f2feSChris Wilson u32 stolen_reserved_size; 3700260c420SBen Widawsky 3710260c420SBen Widawsky /** "Graphics Stolen Memory" holds the global PTEs */ 3720260c420SBen Widawsky void __iomem *gsm; 3737c3f86b6SChris Wilson void (*invalidate)(struct drm_i915_private *dev_priv); 3740260c420SBen Widawsky 3750260c420SBen Widawsky bool do_idle_maps; 3760260c420SBen Widawsky 3770260c420SBen Widawsky int mtrr; 37895374d75SChris Wilson 37995374d75SChris Wilson struct drm_mm_node error_capture; 3800260c420SBen Widawsky }; 3810260c420SBen Widawsky 3820260c420SBen Widawsky struct i915_hw_ppgtt { 3830260c420SBen Widawsky struct i915_address_space base; 3840260c420SBen Widawsky struct kref ref; 3850260c420SBen Widawsky struct drm_mm_node node; 386563222a7SBen Widawsky unsigned long pd_dirty_rings; 3870260c420SBen Widawsky union { 38881ba8aefSMichel Thierry struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 38981ba8aefSMichel Thierry struct i915_page_directory_pointer pdp; /* GEN8+ */ 39081ba8aefSMichel Thierry struct i915_page_directory pd; /* GEN6-7 */ 391d7b3de91SBen Widawsky }; 3920260c420SBen Widawsky 393678d96fbSBen Widawsky gen6_pte_t __iomem *pd_addr; 394678d96fbSBen Widawsky 3950260c420SBen Widawsky int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 396e85b26dcSJohn Harrison struct drm_i915_gem_request *req); 3970260c420SBen Widawsky void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 3980260c420SBen Widawsky }; 3990260c420SBen Widawsky 400731f74c5SDave Gordon /* 401731f74c5SDave Gordon * gen6_for_each_pde() iterates over every pde from start until start+length. 402731f74c5SDave Gordon * If start and start+length are not perfectly divisible, the macro will round 403731f74c5SDave Gordon * down and up as needed. Start=0 and length=2G effectively iterates over 404731f74c5SDave Gordon * every PDE in the system. The macro modifies ALL its parameters except 'pd', 405731f74c5SDave Gordon * so each of the other parameters should preferably be a simple variable, or 406731f74c5SDave Gordon * at most an lvalue with no side-effects! 407678d96fbSBen Widawsky */ 408731f74c5SDave Gordon #define gen6_for_each_pde(pt, pd, start, length, iter) \ 409fdc454c1SMichel Thierry for (iter = gen6_pde_index(start); \ 410731f74c5SDave Gordon length > 0 && iter < I915_PDES && \ 411731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 412731f74c5SDave Gordon ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 413731f74c5SDave Gordon temp = min(temp - start, length); \ 414731f74c5SDave Gordon start += temp, length -= temp; }), ++iter) 415678d96fbSBen Widawsky 416731f74c5SDave Gordon #define gen6_for_all_pdes(pt, pd, iter) \ 41709942c65SMichel Thierry for (iter = 0; \ 418731f74c5SDave Gordon iter < I915_PDES && \ 419731f74c5SDave Gordon (pt = (pd)->page_table[iter], true); \ 420731f74c5SDave Gordon ++iter) 42109942c65SMichel Thierry 42275c7b0b8SChris Wilson static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 423678d96fbSBen Widawsky { 42475c7b0b8SChris Wilson const u32 mask = NUM_PTE(pde_shift) - 1; 425678d96fbSBen Widawsky 426678d96fbSBen Widawsky return (address >> PAGE_SHIFT) & mask; 427678d96fbSBen Widawsky } 428678d96fbSBen Widawsky 429678d96fbSBen Widawsky /* Helper to counts the number of PTEs within the given length. This count 430678d96fbSBen Widawsky * does not cross a page table boundary, so the max value would be 431678d96fbSBen Widawsky * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 432678d96fbSBen Widawsky */ 43375c7b0b8SChris Wilson static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 434678d96fbSBen Widawsky { 43575c7b0b8SChris Wilson const u64 mask = ~((1ULL << pde_shift) - 1); 43675c7b0b8SChris Wilson u64 end; 437678d96fbSBen Widawsky 438678d96fbSBen Widawsky WARN_ON(length == 0); 439678d96fbSBen Widawsky WARN_ON(offset_in_page(addr|length)); 440678d96fbSBen Widawsky 441678d96fbSBen Widawsky end = addr + length; 442678d96fbSBen Widawsky 443678d96fbSBen Widawsky if ((addr & mask) != (end & mask)) 444678d96fbSBen Widawsky return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 445678d96fbSBen Widawsky 446678d96fbSBen Widawsky return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 447678d96fbSBen Widawsky } 448678d96fbSBen Widawsky 44975c7b0b8SChris Wilson static inline u32 i915_pde_index(u64 addr, u32 shift) 450678d96fbSBen Widawsky { 451678d96fbSBen Widawsky return (addr >> shift) & I915_PDE_MASK; 452678d96fbSBen Widawsky } 453678d96fbSBen Widawsky 45475c7b0b8SChris Wilson static inline u32 gen6_pte_index(u32 addr) 455678d96fbSBen Widawsky { 456678d96fbSBen Widawsky return i915_pte_index(addr, GEN6_PDE_SHIFT); 457678d96fbSBen Widawsky } 458678d96fbSBen Widawsky 45975c7b0b8SChris Wilson static inline u32 gen6_pte_count(u32 addr, u32 length) 460678d96fbSBen Widawsky { 461678d96fbSBen Widawsky return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 462678d96fbSBen Widawsky } 463678d96fbSBen Widawsky 46475c7b0b8SChris Wilson static inline u32 gen6_pde_index(u32 addr) 465678d96fbSBen Widawsky { 466678d96fbSBen Widawsky return i915_pde_index(addr, GEN6_PDE_SHIFT); 467678d96fbSBen Widawsky } 468678d96fbSBen Widawsky 4693e490042SMika Kuoppala static inline unsigned int 4703e490042SMika Kuoppala i915_pdpes_per_pdp(const struct i915_address_space *vm) 4713e490042SMika Kuoppala { 4723e490042SMika Kuoppala if (i915_vm_is_48bit(vm)) 4733e490042SMika Kuoppala return GEN8_PML4ES_PER_PML4; 4743e490042SMika Kuoppala 475e7167769SMika Kuoppala return GEN8_3LVL_PDPES; 4763e490042SMika Kuoppala } 4773e490042SMika Kuoppala 4789271d959SMichel Thierry /* Equivalent to the gen6 version, For each pde iterates over every pde 4799271d959SMichel Thierry * between from start until start + length. On gen8+ it simply iterates 4809271d959SMichel Thierry * over every page directory entry in a page directory. 4819271d959SMichel Thierry */ 482e8ebd8e2SDave Gordon #define gen8_for_each_pde(pt, pd, start, length, iter) \ 4839271d959SMichel Thierry for (iter = gen8_pde_index(start); \ 484e8ebd8e2SDave Gordon length > 0 && iter < I915_PDES && \ 485e8ebd8e2SDave Gordon (pt = (pd)->page_table[iter], true); \ 486e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 487e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 488e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4899271d959SMichel Thierry 490e8ebd8e2SDave Gordon #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 4919271d959SMichel Thierry for (iter = gen8_pdpe_index(start); \ 4923e490042SMika Kuoppala length > 0 && iter < i915_pdpes_per_pdp(vm) && \ 493e8ebd8e2SDave Gordon (pd = (pdp)->page_directory[iter], true); \ 494e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 495e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 496e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 4979271d959SMichel Thierry 498e8ebd8e2SDave Gordon #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 499762d9936SMichel Thierry for (iter = gen8_pml4e_index(start); \ 500e8ebd8e2SDave Gordon length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 501e8ebd8e2SDave Gordon (pdp = (pml4)->pdps[iter], true); \ 502e8ebd8e2SDave Gordon ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 503e8ebd8e2SDave Gordon temp = min(temp - start, length); \ 504e8ebd8e2SDave Gordon start += temp, length -= temp; }), ++iter) 505762d9936SMichel Thierry 50675c7b0b8SChris Wilson static inline u32 gen8_pte_index(u64 address) 5079271d959SMichel Thierry { 5089271d959SMichel Thierry return i915_pte_index(address, GEN8_PDE_SHIFT); 5099271d959SMichel Thierry } 5109271d959SMichel Thierry 51175c7b0b8SChris Wilson static inline u32 gen8_pde_index(u64 address) 5129271d959SMichel Thierry { 5139271d959SMichel Thierry return i915_pde_index(address, GEN8_PDE_SHIFT); 5149271d959SMichel Thierry } 5159271d959SMichel Thierry 51675c7b0b8SChris Wilson static inline u32 gen8_pdpe_index(u64 address) 5179271d959SMichel Thierry { 5189271d959SMichel Thierry return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 5199271d959SMichel Thierry } 5209271d959SMichel Thierry 52175c7b0b8SChris Wilson static inline u32 gen8_pml4e_index(u64 address) 5229271d959SMichel Thierry { 523762d9936SMichel Thierry return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 5249271d959SMichel Thierry } 5259271d959SMichel Thierry 52675c7b0b8SChris Wilson static inline u64 gen8_pte_count(u64 address, u64 length) 52733c8819fSMichel Thierry { 52833c8819fSMichel Thierry return i915_pte_count(address, length, GEN8_PDE_SHIFT); 52933c8819fSMichel Thierry } 53033c8819fSMichel Thierry 531d852c7bfSMika Kuoppala static inline dma_addr_t 532d852c7bfSMika Kuoppala i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 533d852c7bfSMika Kuoppala { 534fe52e37fSChris Wilson return px_dma(ppgtt->pdp.page_directory[n]); 535d852c7bfSMika Kuoppala } 536d852c7bfSMika Kuoppala 537b42fe9caSJoonas Lahtinen static inline struct i915_ggtt * 538b42fe9caSJoonas Lahtinen i915_vm_to_ggtt(struct i915_address_space *vm) 539b42fe9caSJoonas Lahtinen { 540b42fe9caSJoonas Lahtinen GEM_BUG_ON(!i915_is_ggtt(vm)); 541b42fe9caSJoonas Lahtinen return container_of(vm, struct i915_ggtt, base); 542b42fe9caSJoonas Lahtinen } 543b42fe9caSJoonas Lahtinen 5444395890aSZhi Wang #define INTEL_MAX_PPAT_ENTRIES 8 5454395890aSZhi Wang #define INTEL_PPAT_PERFECT_MATCH (~0U) 5464395890aSZhi Wang 5474395890aSZhi Wang struct intel_ppat; 5484395890aSZhi Wang 5494395890aSZhi Wang struct intel_ppat_entry { 5504395890aSZhi Wang struct intel_ppat *ppat; 5514395890aSZhi Wang struct kref ref; 5524395890aSZhi Wang u8 value; 5534395890aSZhi Wang }; 5544395890aSZhi Wang 5554395890aSZhi Wang struct intel_ppat { 5564395890aSZhi Wang struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES]; 5574395890aSZhi Wang DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES); 5584395890aSZhi Wang DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES); 5594395890aSZhi Wang unsigned int max_entries; 5604395890aSZhi Wang u8 clear_value; 5614395890aSZhi Wang /* 5624395890aSZhi Wang * Return a score to show how two PPAT values match, 5634395890aSZhi Wang * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match 5644395890aSZhi Wang */ 5654395890aSZhi Wang unsigned int (*match)(u8 src, u8 dst); 5664395890aSZhi Wang void (*update_hw)(struct drm_i915_private *i915); 5674395890aSZhi Wang 5684395890aSZhi Wang struct drm_i915_private *i915; 5694395890aSZhi Wang }; 5704395890aSZhi Wang 5714395890aSZhi Wang const struct intel_ppat_entry * 5724395890aSZhi Wang intel_ppat_get(struct drm_i915_private *i915, u8 value); 5734395890aSZhi Wang void intel_ppat_put(const struct intel_ppat_entry *entry); 5744395890aSZhi Wang 5756cde9a02SChris Wilson int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915); 5766cde9a02SChris Wilson void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915); 5776cde9a02SChris Wilson 57897d6d7abSChris Wilson int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 57997d6d7abSChris Wilson int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 58097d6d7abSChris Wilson int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 5817c3f86b6SChris Wilson void i915_ggtt_enable_guc(struct drm_i915_private *i915); 5827c3f86b6SChris Wilson void i915_ggtt_disable_guc(struct drm_i915_private *i915); 583f6b9d5caSChris Wilson int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 58497d6d7abSChris Wilson void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 585ee960be7SDaniel Vetter 586c6be607aSTvrtko Ursulin int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 587ee960be7SDaniel Vetter void i915_ppgtt_release(struct kref *kref); 5882bfa996eSChris Wilson struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 58980b204bcSChris Wilson struct drm_i915_file_private *fpriv, 59080b204bcSChris Wilson const char *name); 5910c7eeda1SChris Wilson void i915_ppgtt_close(struct i915_address_space *vm); 592ee960be7SDaniel Vetter static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 593ee960be7SDaniel Vetter { 594ee960be7SDaniel Vetter if (ppgtt) 595ee960be7SDaniel Vetter kref_get(&ppgtt->ref); 596ee960be7SDaniel Vetter } 597ee960be7SDaniel Vetter static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 598ee960be7SDaniel Vetter { 599ee960be7SDaniel Vetter if (ppgtt) 600ee960be7SDaniel Vetter kref_put(&ppgtt->ref, i915_ppgtt_release); 601ee960be7SDaniel Vetter } 6020260c420SBen Widawsky 603dc97997aSChris Wilson void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 604275a991cSTvrtko Ursulin void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 605275a991cSTvrtko Ursulin void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 6060260c420SBen Widawsky 60703ac84f1SChris Wilson int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 60803ac84f1SChris Wilson struct sg_table *pages); 60903ac84f1SChris Wilson void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 61003ac84f1SChris Wilson struct sg_table *pages); 6110260c420SBen Widawsky 612625d988aSChris Wilson int i915_gem_gtt_reserve(struct i915_address_space *vm, 613625d988aSChris Wilson struct drm_mm_node *node, 614625d988aSChris Wilson u64 size, u64 offset, unsigned long color, 615625d988aSChris Wilson unsigned int flags); 616625d988aSChris Wilson 617e007b19dSChris Wilson int i915_gem_gtt_insert(struct i915_address_space *vm, 618e007b19dSChris Wilson struct drm_mm_node *node, 619e007b19dSChris Wilson u64 size, u64 alignment, unsigned long color, 620e007b19dSChris Wilson u64 start, u64 end, unsigned int flags); 621e007b19dSChris Wilson 62259bfa124SChris Wilson /* Flags used by pin/bind&friends. */ 623305bc234SChris Wilson #define PIN_NONBLOCK BIT(0) 624305bc234SChris Wilson #define PIN_MAPPABLE BIT(1) 625305bc234SChris Wilson #define PIN_ZONE_4G BIT(2) 62682118877SChris Wilson #define PIN_NONFAULT BIT(3) 627616d9ceeSChris Wilson #define PIN_NOEVICT BIT(4) 628305bc234SChris Wilson 629305bc234SChris Wilson #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 630305bc234SChris Wilson #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 631305bc234SChris Wilson #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 632305bc234SChris Wilson #define PIN_UPDATE BIT(8) 633305bc234SChris Wilson 634305bc234SChris Wilson #define PIN_HIGH BIT(9) 635305bc234SChris Wilson #define PIN_OFFSET_BIAS BIT(10) 636305bc234SChris Wilson #define PIN_OFFSET_FIXED BIT(11) 637f51455d4SChris Wilson #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 63859bfa124SChris Wilson 6390260c420SBen Widawsky #endif 640