1 /* 2 * Copyright © 2010 Daniel Vetter 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/i915_drm.h> 27 #include "i915_drv.h" 28 #include "i915_trace.h" 29 #include "intel_drv.h" 30 31 #define GEN6_PPGTT_PD_ENTRIES 512 32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) 33 typedef uint64_t gen8_gtt_pte_t; 34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; 35 36 /* PPGTT stuff */ 37 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 38 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 39 40 #define GEN6_PDE_VALID (1 << 0) 41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */ 42 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 43 44 #define GEN6_PTE_VALID (1 << 0) 45 #define GEN6_PTE_UNCACHED (1 << 1) 46 #define HSW_PTE_UNCACHED (0) 47 #define GEN6_PTE_CACHE_LLC (2 << 1) 48 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 49 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 50 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 51 52 /* Cacheability Control is a 4-bit value. The low three bits are stored in * 53 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 54 */ 55 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 56 (((bits) & 0x8) << (11 - 3))) 57 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 58 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 59 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 60 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 61 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 62 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 63 64 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) 65 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) 66 #define GEN8_LEGACY_PDPS 4 67 68 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 69 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 70 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 71 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 72 73 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, 74 enum i915_cache_level level, 75 bool valid) 76 { 77 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; 78 pte |= addr; 79 if (level != I915_CACHE_NONE) 80 pte |= PPAT_CACHED_INDEX; 81 else 82 pte |= PPAT_UNCACHED_INDEX; 83 return pte; 84 } 85 86 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, 87 dma_addr_t addr, 88 enum i915_cache_level level) 89 { 90 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; 91 pde |= addr; 92 if (level != I915_CACHE_NONE) 93 pde |= PPAT_CACHED_PDE_INDEX; 94 else 95 pde |= PPAT_UNCACHED_INDEX; 96 return pde; 97 } 98 99 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, 100 enum i915_cache_level level, 101 bool valid) 102 { 103 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 104 pte |= GEN6_PTE_ADDR_ENCODE(addr); 105 106 switch (level) { 107 case I915_CACHE_L3_LLC: 108 case I915_CACHE_LLC: 109 pte |= GEN6_PTE_CACHE_LLC; 110 break; 111 case I915_CACHE_NONE: 112 pte |= GEN6_PTE_UNCACHED; 113 break; 114 default: 115 WARN_ON(1); 116 } 117 118 return pte; 119 } 120 121 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, 122 enum i915_cache_level level, 123 bool valid) 124 { 125 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 126 pte |= GEN6_PTE_ADDR_ENCODE(addr); 127 128 switch (level) { 129 case I915_CACHE_L3_LLC: 130 pte |= GEN7_PTE_CACHE_L3_LLC; 131 break; 132 case I915_CACHE_LLC: 133 pte |= GEN6_PTE_CACHE_LLC; 134 break; 135 case I915_CACHE_NONE: 136 pte |= GEN6_PTE_UNCACHED; 137 break; 138 default: 139 WARN_ON(1); 140 } 141 142 return pte; 143 } 144 145 #define BYT_PTE_WRITEABLE (1 << 1) 146 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 147 148 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, 149 enum i915_cache_level level, 150 bool valid) 151 { 152 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 153 pte |= GEN6_PTE_ADDR_ENCODE(addr); 154 155 /* Mark the page as writeable. Other platforms don't have a 156 * setting for read-only/writable, so this matches that behavior. 157 */ 158 pte |= BYT_PTE_WRITEABLE; 159 160 if (level != I915_CACHE_NONE) 161 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; 162 163 return pte; 164 } 165 166 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, 167 enum i915_cache_level level, 168 bool valid) 169 { 170 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 171 pte |= HSW_PTE_ADDR_ENCODE(addr); 172 173 if (level != I915_CACHE_NONE) 174 pte |= HSW_WB_LLC_AGE3; 175 176 return pte; 177 } 178 179 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, 180 enum i915_cache_level level, 181 bool valid) 182 { 183 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; 184 pte |= HSW_PTE_ADDR_ENCODE(addr); 185 186 switch (level) { 187 case I915_CACHE_NONE: 188 break; 189 case I915_CACHE_WT: 190 pte |= HSW_WT_ELLC_LLC_AGE3; 191 break; 192 default: 193 pte |= HSW_WB_ELLC_LLC_AGE3; 194 break; 195 } 196 197 return pte; 198 } 199 200 /* Broadwell Page Directory Pointer Descriptors */ 201 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, 202 uint64_t val) 203 { 204 int ret; 205 206 BUG_ON(entry >= 4); 207 208 ret = intel_ring_begin(ring, 6); 209 if (ret) 210 return ret; 211 212 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 213 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); 214 intel_ring_emit(ring, (u32)(val >> 32)); 215 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 216 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); 217 intel_ring_emit(ring, (u32)(val)); 218 intel_ring_advance(ring); 219 220 return 0; 221 } 222 223 static int gen8_ppgtt_enable(struct drm_device *dev) 224 { 225 struct drm_i915_private *dev_priv = dev->dev_private; 226 struct intel_ring_buffer *ring; 227 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 228 int i, j, ret; 229 230 /* bit of a hack to find the actual last used pd */ 231 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; 232 233 for_each_ring(ring, dev_priv, j) { 234 I915_WRITE(RING_MODE_GEN7(ring), 235 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 236 } 237 238 for (i = used_pd - 1; i >= 0; i--) { 239 dma_addr_t addr = ppgtt->pd_dma_addr[i]; 240 for_each_ring(ring, dev_priv, j) { 241 ret = gen8_write_pdp(ring, i, addr); 242 if (ret) 243 goto err_out; 244 } 245 } 246 return 0; 247 248 err_out: 249 for_each_ring(ring, dev_priv, j) 250 I915_WRITE(RING_MODE_GEN7(ring), 251 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); 252 return ret; 253 } 254 255 static void gen8_ppgtt_clear_range(struct i915_address_space *vm, 256 unsigned first_entry, 257 unsigned num_entries, 258 bool use_scratch) 259 { 260 struct i915_hw_ppgtt *ppgtt = 261 container_of(vm, struct i915_hw_ppgtt, base); 262 gen8_gtt_pte_t *pt_vaddr, scratch_pte; 263 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; 264 unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; 265 unsigned last_pte, i; 266 267 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, 268 I915_CACHE_LLC, use_scratch); 269 270 while (num_entries) { 271 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; 272 273 last_pte = first_pte + num_entries; 274 if (last_pte > GEN8_PTES_PER_PAGE) 275 last_pte = GEN8_PTES_PER_PAGE; 276 277 pt_vaddr = kmap_atomic(page_table); 278 279 for (i = first_pte; i < last_pte; i++) 280 pt_vaddr[i] = scratch_pte; 281 282 kunmap_atomic(pt_vaddr); 283 284 num_entries -= last_pte - first_pte; 285 first_pte = 0; 286 act_pt++; 287 } 288 } 289 290 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, 291 struct sg_table *pages, 292 unsigned first_entry, 293 enum i915_cache_level cache_level) 294 { 295 struct i915_hw_ppgtt *ppgtt = 296 container_of(vm, struct i915_hw_ppgtt, base); 297 gen8_gtt_pte_t *pt_vaddr; 298 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; 299 unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; 300 struct sg_page_iter sg_iter; 301 302 pt_vaddr = NULL; 303 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { 304 if (pt_vaddr == NULL) 305 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); 306 307 pt_vaddr[act_pte] = 308 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), 309 cache_level, true); 310 if (++act_pte == GEN8_PTES_PER_PAGE) { 311 kunmap_atomic(pt_vaddr); 312 pt_vaddr = NULL; 313 act_pt++; 314 act_pte = 0; 315 } 316 } 317 if (pt_vaddr) 318 kunmap_atomic(pt_vaddr); 319 } 320 321 static void gen8_ppgtt_cleanup(struct i915_address_space *vm) 322 { 323 struct i915_hw_ppgtt *ppgtt = 324 container_of(vm, struct i915_hw_ppgtt, base); 325 int i, j; 326 327 drm_mm_takedown(&vm->mm); 328 329 for (i = 0; i < ppgtt->num_pd_pages ; i++) { 330 if (ppgtt->pd_dma_addr[i]) { 331 pci_unmap_page(ppgtt->base.dev->pdev, 332 ppgtt->pd_dma_addr[i], 333 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 334 335 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { 336 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; 337 if (addr) 338 pci_unmap_page(ppgtt->base.dev->pdev, 339 addr, 340 PAGE_SIZE, 341 PCI_DMA_BIDIRECTIONAL); 342 343 } 344 } 345 kfree(ppgtt->gen8_pt_dma_addr[i]); 346 } 347 348 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); 349 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); 350 } 351 352 /** 353 * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a 354 * net effect resembling a 2-level page table in normal x86 terms. Each PDP 355 * represents 1GB of memory 356 * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. 357 * 358 * TODO: Do something with the size parameter 359 **/ 360 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) 361 { 362 struct page *pt_pages; 363 int i, j, ret = -ENOMEM; 364 const int max_pdp = DIV_ROUND_UP(size, 1 << 30); 365 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; 366 367 if (size % (1<<30)) 368 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); 369 370 /* FIXME: split allocation into smaller pieces. For now we only ever do 371 * this once, but with full PPGTT, the multiple contiguous allocations 372 * will be bad. 373 */ 374 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); 375 if (!ppgtt->pd_pages) 376 return -ENOMEM; 377 378 pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); 379 if (!pt_pages) { 380 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); 381 return -ENOMEM; 382 } 383 384 ppgtt->gen8_pt_pages = pt_pages; 385 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); 386 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); 387 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; 388 ppgtt->enable = gen8_ppgtt_enable; 389 ppgtt->base.clear_range = gen8_ppgtt_clear_range; 390 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; 391 ppgtt->base.cleanup = gen8_ppgtt_cleanup; 392 ppgtt->base.start = 0; 393 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; 394 395 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); 396 397 /* 398 * - Create a mapping for the page directories. 399 * - For each page directory: 400 * allocate space for page table mappings. 401 * map each page table 402 */ 403 for (i = 0; i < max_pdp; i++) { 404 dma_addr_t temp; 405 temp = pci_map_page(ppgtt->base.dev->pdev, 406 &ppgtt->pd_pages[i], 0, 407 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 408 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) 409 goto err_out; 410 411 ppgtt->pd_dma_addr[i] = temp; 412 413 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); 414 if (!ppgtt->gen8_pt_dma_addr[i]) 415 goto err_out; 416 417 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { 418 struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; 419 temp = pci_map_page(ppgtt->base.dev->pdev, 420 p, 0, PAGE_SIZE, 421 PCI_DMA_BIDIRECTIONAL); 422 423 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) 424 goto err_out; 425 426 ppgtt->gen8_pt_dma_addr[i][j] = temp; 427 } 428 } 429 430 /* For now, the PPGTT helper functions all require that the PDEs are 431 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we 432 * will never need to touch the PDEs again */ 433 for (i = 0; i < max_pdp; i++) { 434 gen8_ppgtt_pde_t *pd_vaddr; 435 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); 436 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { 437 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; 438 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, 439 I915_CACHE_LLC); 440 } 441 kunmap_atomic(pd_vaddr); 442 } 443 444 ppgtt->base.clear_range(&ppgtt->base, 0, 445 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, 446 true); 447 448 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", 449 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); 450 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", 451 ppgtt->num_pt_pages, 452 (ppgtt->num_pt_pages - num_pt_pages) + 453 size % (1<<30)); 454 return 0; 455 456 err_out: 457 ppgtt->base.cleanup(&ppgtt->base); 458 return ret; 459 } 460 461 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) 462 { 463 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; 464 gen6_gtt_pte_t __iomem *pd_addr; 465 uint32_t pd_entry; 466 int i; 467 468 WARN_ON(ppgtt->pd_offset & 0x3f); 469 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + 470 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); 471 for (i = 0; i < ppgtt->num_pd_entries; i++) { 472 dma_addr_t pt_addr; 473 474 pt_addr = ppgtt->pt_dma_addr[i]; 475 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); 476 pd_entry |= GEN6_PDE_VALID; 477 478 writel(pd_entry, pd_addr + i); 479 } 480 readl(pd_addr); 481 } 482 483 static int gen6_ppgtt_enable(struct drm_device *dev) 484 { 485 drm_i915_private_t *dev_priv = dev->dev_private; 486 uint32_t pd_offset; 487 struct intel_ring_buffer *ring; 488 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 489 int i; 490 491 BUG_ON(ppgtt->pd_offset & 0x3f); 492 493 gen6_write_pdes(ppgtt); 494 495 pd_offset = ppgtt->pd_offset; 496 pd_offset /= 64; /* in cachelines, */ 497 pd_offset <<= 16; 498 499 if (INTEL_INFO(dev)->gen == 6) { 500 uint32_t ecochk, gab_ctl, ecobits; 501 502 ecobits = I915_READ(GAC_ECO_BITS); 503 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | 504 ECOBITS_PPGTT_CACHE64B); 505 506 gab_ctl = I915_READ(GAB_CTL); 507 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); 508 509 ecochk = I915_READ(GAM_ECOCHK); 510 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | 511 ECOCHK_PPGTT_CACHE64B); 512 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 513 } else if (INTEL_INFO(dev)->gen >= 7) { 514 uint32_t ecochk, ecobits; 515 516 ecobits = I915_READ(GAC_ECO_BITS); 517 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); 518 519 ecochk = I915_READ(GAM_ECOCHK); 520 if (IS_HASWELL(dev)) { 521 ecochk |= ECOCHK_PPGTT_WB_HSW; 522 } else { 523 ecochk |= ECOCHK_PPGTT_LLC_IVB; 524 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; 525 } 526 I915_WRITE(GAM_ECOCHK, ecochk); 527 /* GFX_MODE is per-ring on gen7+ */ 528 } 529 530 for_each_ring(ring, dev_priv, i) { 531 if (INTEL_INFO(dev)->gen >= 7) 532 I915_WRITE(RING_MODE_GEN7(ring), 533 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 534 535 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 536 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); 537 } 538 return 0; 539 } 540 541 /* PPGTT support for Sandybdrige/Gen6 and later */ 542 static void gen6_ppgtt_clear_range(struct i915_address_space *vm, 543 unsigned first_entry, 544 unsigned num_entries, 545 bool use_scratch) 546 { 547 struct i915_hw_ppgtt *ppgtt = 548 container_of(vm, struct i915_hw_ppgtt, base); 549 gen6_gtt_pte_t *pt_vaddr, scratch_pte; 550 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; 551 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; 552 unsigned last_pte, i; 553 554 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); 555 556 while (num_entries) { 557 last_pte = first_pte + num_entries; 558 if (last_pte > I915_PPGTT_PT_ENTRIES) 559 last_pte = I915_PPGTT_PT_ENTRIES; 560 561 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); 562 563 for (i = first_pte; i < last_pte; i++) 564 pt_vaddr[i] = scratch_pte; 565 566 kunmap_atomic(pt_vaddr); 567 568 num_entries -= last_pte - first_pte; 569 first_pte = 0; 570 act_pt++; 571 } 572 } 573 574 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, 575 struct sg_table *pages, 576 unsigned first_entry, 577 enum i915_cache_level cache_level) 578 { 579 struct i915_hw_ppgtt *ppgtt = 580 container_of(vm, struct i915_hw_ppgtt, base); 581 gen6_gtt_pte_t *pt_vaddr; 582 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; 583 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; 584 struct sg_page_iter sg_iter; 585 586 pt_vaddr = NULL; 587 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { 588 if (pt_vaddr == NULL) 589 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); 590 591 pt_vaddr[act_pte] = 592 vm->pte_encode(sg_page_iter_dma_address(&sg_iter), 593 cache_level, true); 594 if (++act_pte == I915_PPGTT_PT_ENTRIES) { 595 kunmap_atomic(pt_vaddr); 596 pt_vaddr = NULL; 597 act_pt++; 598 act_pte = 0; 599 } 600 } 601 if (pt_vaddr) 602 kunmap_atomic(pt_vaddr); 603 } 604 605 static void gen6_ppgtt_cleanup(struct i915_address_space *vm) 606 { 607 struct i915_hw_ppgtt *ppgtt = 608 container_of(vm, struct i915_hw_ppgtt, base); 609 int i; 610 611 drm_mm_takedown(&ppgtt->base.mm); 612 613 if (ppgtt->pt_dma_addr) { 614 for (i = 0; i < ppgtt->num_pd_entries; i++) 615 pci_unmap_page(ppgtt->base.dev->pdev, 616 ppgtt->pt_dma_addr[i], 617 4096, PCI_DMA_BIDIRECTIONAL); 618 } 619 620 kfree(ppgtt->pt_dma_addr); 621 for (i = 0; i < ppgtt->num_pd_entries; i++) 622 __free_page(ppgtt->pt_pages[i]); 623 kfree(ppgtt->pt_pages); 624 kfree(ppgtt); 625 } 626 627 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 628 { 629 struct drm_device *dev = ppgtt->base.dev; 630 struct drm_i915_private *dev_priv = dev->dev_private; 631 unsigned first_pd_entry_in_global_pt; 632 int i; 633 int ret = -ENOMEM; 634 635 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 636 * entries. For aliasing ppgtt support we just steal them at the end for 637 * now. */ 638 first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); 639 640 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; 641 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; 642 ppgtt->enable = gen6_ppgtt_enable; 643 ppgtt->base.clear_range = gen6_ppgtt_clear_range; 644 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; 645 ppgtt->base.cleanup = gen6_ppgtt_cleanup; 646 ppgtt->base.scratch = dev_priv->gtt.base.scratch; 647 ppgtt->base.start = 0; 648 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; 649 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), 650 GFP_KERNEL); 651 if (!ppgtt->pt_pages) 652 return -ENOMEM; 653 654 for (i = 0; i < ppgtt->num_pd_entries; i++) { 655 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); 656 if (!ppgtt->pt_pages[i]) 657 goto err_pt_alloc; 658 } 659 660 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), 661 GFP_KERNEL); 662 if (!ppgtt->pt_dma_addr) 663 goto err_pt_alloc; 664 665 for (i = 0; i < ppgtt->num_pd_entries; i++) { 666 dma_addr_t pt_addr; 667 668 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, 669 PCI_DMA_BIDIRECTIONAL); 670 671 if (pci_dma_mapping_error(dev->pdev, pt_addr)) { 672 ret = -EIO; 673 goto err_pd_pin; 674 675 } 676 ppgtt->pt_dma_addr[i] = pt_addr; 677 } 678 679 ppgtt->base.clear_range(&ppgtt->base, 0, 680 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); 681 682 ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); 683 684 return 0; 685 686 err_pd_pin: 687 if (ppgtt->pt_dma_addr) { 688 for (i--; i >= 0; i--) 689 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], 690 4096, PCI_DMA_BIDIRECTIONAL); 691 } 692 err_pt_alloc: 693 kfree(ppgtt->pt_dma_addr); 694 for (i = 0; i < ppgtt->num_pd_entries; i++) { 695 if (ppgtt->pt_pages[i]) 696 __free_page(ppgtt->pt_pages[i]); 697 } 698 kfree(ppgtt->pt_pages); 699 700 return ret; 701 } 702 703 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) 704 { 705 struct drm_i915_private *dev_priv = dev->dev_private; 706 struct i915_hw_ppgtt *ppgtt; 707 int ret; 708 709 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); 710 if (!ppgtt) 711 return -ENOMEM; 712 713 ppgtt->base.dev = dev; 714 715 if (INTEL_INFO(dev)->gen < 8) 716 ret = gen6_ppgtt_init(ppgtt); 717 else if (IS_GEN8(dev)) 718 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); 719 else 720 BUG(); 721 722 if (ret) 723 kfree(ppgtt); 724 else { 725 dev_priv->mm.aliasing_ppgtt = ppgtt; 726 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, 727 ppgtt->base.total); 728 } 729 730 return ret; 731 } 732 733 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) 734 { 735 struct drm_i915_private *dev_priv = dev->dev_private; 736 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 737 738 if (!ppgtt) 739 return; 740 741 ppgtt->base.cleanup(&ppgtt->base); 742 dev_priv->mm.aliasing_ppgtt = NULL; 743 } 744 745 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 746 struct drm_i915_gem_object *obj, 747 enum i915_cache_level cache_level) 748 { 749 ppgtt->base.insert_entries(&ppgtt->base, obj->pages, 750 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, 751 cache_level); 752 } 753 754 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 755 struct drm_i915_gem_object *obj) 756 { 757 ppgtt->base.clear_range(&ppgtt->base, 758 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, 759 obj->base.size >> PAGE_SHIFT, 760 true); 761 } 762 763 extern int intel_iommu_gfx_mapped; 764 /* Certain Gen5 chipsets require require idling the GPU before 765 * unmapping anything from the GTT when VT-d is enabled. 766 */ 767 static inline bool needs_idle_maps(struct drm_device *dev) 768 { 769 #ifdef CONFIG_INTEL_IOMMU 770 /* Query intel_iommu to see if we need the workaround. Presumably that 771 * was loaded first. 772 */ 773 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) 774 return true; 775 #endif 776 return false; 777 } 778 779 static bool do_idling(struct drm_i915_private *dev_priv) 780 { 781 bool ret = dev_priv->mm.interruptible; 782 783 if (unlikely(dev_priv->gtt.do_idle_maps)) { 784 dev_priv->mm.interruptible = false; 785 if (i915_gpu_idle(dev_priv->dev)) { 786 DRM_ERROR("Couldn't idle GPU\n"); 787 /* Wait a bit, in hopes it avoids the hang */ 788 udelay(10); 789 } 790 } 791 792 return ret; 793 } 794 795 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) 796 { 797 if (unlikely(dev_priv->gtt.do_idle_maps)) 798 dev_priv->mm.interruptible = interruptible; 799 } 800 801 void i915_check_and_clear_faults(struct drm_device *dev) 802 { 803 struct drm_i915_private *dev_priv = dev->dev_private; 804 struct intel_ring_buffer *ring; 805 int i; 806 807 if (INTEL_INFO(dev)->gen < 6) 808 return; 809 810 for_each_ring(ring, dev_priv, i) { 811 u32 fault_reg; 812 fault_reg = I915_READ(RING_FAULT_REG(ring)); 813 if (fault_reg & RING_FAULT_VALID) { 814 DRM_DEBUG_DRIVER("Unexpected fault\n" 815 "\tAddr: 0x%08lx\\n" 816 "\tAddress space: %s\n" 817 "\tSource ID: %d\n" 818 "\tType: %d\n", 819 fault_reg & PAGE_MASK, 820 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", 821 RING_FAULT_SRCID(fault_reg), 822 RING_FAULT_FAULT_TYPE(fault_reg)); 823 I915_WRITE(RING_FAULT_REG(ring), 824 fault_reg & ~RING_FAULT_VALID); 825 } 826 } 827 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); 828 } 829 830 void i915_gem_suspend_gtt_mappings(struct drm_device *dev) 831 { 832 struct drm_i915_private *dev_priv = dev->dev_private; 833 834 /* Don't bother messing with faults pre GEN6 as we have little 835 * documentation supporting that it's a good idea. 836 */ 837 if (INTEL_INFO(dev)->gen < 6) 838 return; 839 840 i915_check_and_clear_faults(dev); 841 842 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 843 dev_priv->gtt.base.start / PAGE_SIZE, 844 dev_priv->gtt.base.total / PAGE_SIZE, 845 false); 846 } 847 848 void i915_gem_restore_gtt_mappings(struct drm_device *dev) 849 { 850 struct drm_i915_private *dev_priv = dev->dev_private; 851 struct drm_i915_gem_object *obj; 852 853 i915_check_and_clear_faults(dev); 854 855 /* First fill our portion of the GTT with scratch pages */ 856 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 857 dev_priv->gtt.base.start / PAGE_SIZE, 858 dev_priv->gtt.base.total / PAGE_SIZE, 859 true); 860 861 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 862 i915_gem_clflush_object(obj, obj->pin_display); 863 i915_gem_gtt_bind_object(obj, obj->cache_level); 864 } 865 866 i915_gem_chipset_flush(dev); 867 } 868 869 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) 870 { 871 if (obj->has_dma_mapping) 872 return 0; 873 874 if (!dma_map_sg(&obj->base.dev->pdev->dev, 875 obj->pages->sgl, obj->pages->nents, 876 PCI_DMA_BIDIRECTIONAL)) 877 return -ENOSPC; 878 879 return 0; 880 } 881 882 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) 883 { 884 #ifdef writeq 885 writeq(pte, addr); 886 #else 887 iowrite32((u32)pte, addr); 888 iowrite32(pte >> 32, addr + 4); 889 #endif 890 } 891 892 static void gen8_ggtt_insert_entries(struct i915_address_space *vm, 893 struct sg_table *st, 894 unsigned int first_entry, 895 enum i915_cache_level level) 896 { 897 struct drm_i915_private *dev_priv = vm->dev->dev_private; 898 gen8_gtt_pte_t __iomem *gtt_entries = 899 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; 900 int i = 0; 901 struct sg_page_iter sg_iter; 902 dma_addr_t addr; 903 904 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 905 addr = sg_dma_address(sg_iter.sg) + 906 (sg_iter.sg_pgoffset << PAGE_SHIFT); 907 gen8_set_pte(>t_entries[i], 908 gen8_pte_encode(addr, level, true)); 909 i++; 910 } 911 912 /* 913 * XXX: This serves as a posting read to make sure that the PTE has 914 * actually been updated. There is some concern that even though 915 * registers and PTEs are within the same BAR that they are potentially 916 * of NUMA access patterns. Therefore, even with the way we assume 917 * hardware should work, we must keep this posting read for paranoia. 918 */ 919 if (i != 0) 920 WARN_ON(readq(>t_entries[i-1]) 921 != gen8_pte_encode(addr, level, true)); 922 923 /* This next bit makes the above posting read even more important. We 924 * want to flush the TLBs only after we're certain all the PTE updates 925 * have finished. 926 */ 927 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 928 POSTING_READ(GFX_FLSH_CNTL_GEN6); 929 } 930 931 /* 932 * Binds an object into the global gtt with the specified cache level. The object 933 * will be accessible to the GPU via commands whose operands reference offsets 934 * within the global GTT as well as accessible by the GPU through the GMADR 935 * mapped BAR (dev_priv->mm.gtt->gtt). 936 */ 937 static void gen6_ggtt_insert_entries(struct i915_address_space *vm, 938 struct sg_table *st, 939 unsigned int first_entry, 940 enum i915_cache_level level) 941 { 942 struct drm_i915_private *dev_priv = vm->dev->dev_private; 943 gen6_gtt_pte_t __iomem *gtt_entries = 944 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; 945 int i = 0; 946 struct sg_page_iter sg_iter; 947 dma_addr_t addr; 948 949 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 950 addr = sg_page_iter_dma_address(&sg_iter); 951 iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); 952 i++; 953 } 954 955 /* XXX: This serves as a posting read to make sure that the PTE has 956 * actually been updated. There is some concern that even though 957 * registers and PTEs are within the same BAR that they are potentially 958 * of NUMA access patterns. Therefore, even with the way we assume 959 * hardware should work, we must keep this posting read for paranoia. 960 */ 961 if (i != 0) 962 WARN_ON(readl(>t_entries[i-1]) != 963 vm->pte_encode(addr, level, true)); 964 965 /* This next bit makes the above posting read even more important. We 966 * want to flush the TLBs only after we're certain all the PTE updates 967 * have finished. 968 */ 969 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 970 POSTING_READ(GFX_FLSH_CNTL_GEN6); 971 } 972 973 static void gen8_ggtt_clear_range(struct i915_address_space *vm, 974 unsigned int first_entry, 975 unsigned int num_entries, 976 bool use_scratch) 977 { 978 struct drm_i915_private *dev_priv = vm->dev->dev_private; 979 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = 980 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; 981 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; 982 int i; 983 984 if (WARN(num_entries > max_entries, 985 "First entry = %d; Num entries = %d (max=%d)\n", 986 first_entry, num_entries, max_entries)) 987 num_entries = max_entries; 988 989 scratch_pte = gen8_pte_encode(vm->scratch.addr, 990 I915_CACHE_LLC, 991 use_scratch); 992 for (i = 0; i < num_entries; i++) 993 gen8_set_pte(>t_base[i], scratch_pte); 994 readl(gtt_base); 995 } 996 997 static void gen6_ggtt_clear_range(struct i915_address_space *vm, 998 unsigned int first_entry, 999 unsigned int num_entries, 1000 bool use_scratch) 1001 { 1002 struct drm_i915_private *dev_priv = vm->dev->dev_private; 1003 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = 1004 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; 1005 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; 1006 int i; 1007 1008 if (WARN(num_entries > max_entries, 1009 "First entry = %d; Num entries = %d (max=%d)\n", 1010 first_entry, num_entries, max_entries)) 1011 num_entries = max_entries; 1012 1013 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); 1014 1015 for (i = 0; i < num_entries; i++) 1016 iowrite32(scratch_pte, >t_base[i]); 1017 readl(gtt_base); 1018 } 1019 1020 static void i915_ggtt_insert_entries(struct i915_address_space *vm, 1021 struct sg_table *st, 1022 unsigned int pg_start, 1023 enum i915_cache_level cache_level) 1024 { 1025 unsigned int flags = (cache_level == I915_CACHE_NONE) ? 1026 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; 1027 1028 intel_gtt_insert_sg_entries(st, pg_start, flags); 1029 1030 } 1031 1032 static void i915_ggtt_clear_range(struct i915_address_space *vm, 1033 unsigned int first_entry, 1034 unsigned int num_entries, 1035 bool unused) 1036 { 1037 intel_gtt_clear_range(first_entry, num_entries); 1038 } 1039 1040 1041 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1042 enum i915_cache_level cache_level) 1043 { 1044 struct drm_device *dev = obj->base.dev; 1045 struct drm_i915_private *dev_priv = dev->dev_private; 1046 const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; 1047 1048 dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, 1049 entry, 1050 cache_level); 1051 1052 obj->has_global_gtt_mapping = 1; 1053 } 1054 1055 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) 1056 { 1057 struct drm_device *dev = obj->base.dev; 1058 struct drm_i915_private *dev_priv = dev->dev_private; 1059 const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; 1060 1061 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 1062 entry, 1063 obj->base.size >> PAGE_SHIFT, 1064 true); 1065 1066 obj->has_global_gtt_mapping = 0; 1067 } 1068 1069 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) 1070 { 1071 struct drm_device *dev = obj->base.dev; 1072 struct drm_i915_private *dev_priv = dev->dev_private; 1073 bool interruptible; 1074 1075 interruptible = do_idling(dev_priv); 1076 1077 if (!obj->has_dma_mapping) 1078 dma_unmap_sg(&dev->pdev->dev, 1079 obj->pages->sgl, obj->pages->nents, 1080 PCI_DMA_BIDIRECTIONAL); 1081 1082 undo_idling(dev_priv, interruptible); 1083 } 1084 1085 static void i915_gtt_color_adjust(struct drm_mm_node *node, 1086 unsigned long color, 1087 unsigned long *start, 1088 unsigned long *end) 1089 { 1090 if (node->color != color) 1091 *start += 4096; 1092 1093 if (!list_empty(&node->node_list)) { 1094 node = list_entry(node->node_list.next, 1095 struct drm_mm_node, 1096 node_list); 1097 if (node->allocated && node->color != color) 1098 *end -= 4096; 1099 } 1100 } 1101 1102 void i915_gem_setup_global_gtt(struct drm_device *dev, 1103 unsigned long start, 1104 unsigned long mappable_end, 1105 unsigned long end) 1106 { 1107 /* Let GEM Manage all of the aperture. 1108 * 1109 * However, leave one page at the end still bound to the scratch page. 1110 * There are a number of places where the hardware apparently prefetches 1111 * past the end of the object, and we've seen multiple hangs with the 1112 * GPU head pointer stuck in a batchbuffer bound at the last page of the 1113 * aperture. One page should be enough to keep any prefetching inside 1114 * of the aperture. 1115 */ 1116 struct drm_i915_private *dev_priv = dev->dev_private; 1117 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; 1118 struct drm_mm_node *entry; 1119 struct drm_i915_gem_object *obj; 1120 unsigned long hole_start, hole_end; 1121 1122 BUG_ON(mappable_end > end); 1123 1124 /* Subtract the guard page ... */ 1125 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); 1126 if (!HAS_LLC(dev)) 1127 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; 1128 1129 /* Mark any preallocated objects as occupied */ 1130 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1131 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); 1132 int ret; 1133 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", 1134 i915_gem_obj_ggtt_offset(obj), obj->base.size); 1135 1136 WARN_ON(i915_gem_obj_ggtt_bound(obj)); 1137 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); 1138 if (ret) 1139 DRM_DEBUG_KMS("Reservation failed\n"); 1140 obj->has_global_gtt_mapping = 1; 1141 } 1142 1143 dev_priv->gtt.base.start = start; 1144 dev_priv->gtt.base.total = end - start; 1145 1146 /* Clear any non-preallocated blocks */ 1147 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { 1148 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; 1149 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", 1150 hole_start, hole_end); 1151 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); 1152 } 1153 1154 /* And finally clear the reserved guard page */ 1155 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); 1156 } 1157 1158 static bool 1159 intel_enable_ppgtt(struct drm_device *dev) 1160 { 1161 if (i915_enable_ppgtt >= 0) 1162 return i915_enable_ppgtt; 1163 1164 #ifdef CONFIG_INTEL_IOMMU 1165 /* Disable ppgtt on SNB if VT-d is on. */ 1166 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 1167 return false; 1168 #endif 1169 1170 return true; 1171 } 1172 1173 void i915_gem_init_global_gtt(struct drm_device *dev) 1174 { 1175 struct drm_i915_private *dev_priv = dev->dev_private; 1176 unsigned long gtt_size, mappable_size; 1177 1178 gtt_size = dev_priv->gtt.base.total; 1179 mappable_size = dev_priv->gtt.mappable_end; 1180 1181 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { 1182 int ret; 1183 1184 if (INTEL_INFO(dev)->gen <= 7) { 1185 /* PPGTT pdes are stolen from global gtt ptes, so shrink the 1186 * aperture accordingly when using aliasing ppgtt. */ 1187 gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; 1188 } 1189 1190 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); 1191 1192 ret = i915_gem_init_aliasing_ppgtt(dev); 1193 if (!ret) 1194 return; 1195 1196 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); 1197 drm_mm_takedown(&dev_priv->gtt.base.mm); 1198 if (INTEL_INFO(dev)->gen < 8) 1199 gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE; 1200 } 1201 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); 1202 } 1203 1204 static int setup_scratch_page(struct drm_device *dev) 1205 { 1206 struct drm_i915_private *dev_priv = dev->dev_private; 1207 struct page *page; 1208 dma_addr_t dma_addr; 1209 1210 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 1211 if (page == NULL) 1212 return -ENOMEM; 1213 get_page(page); 1214 set_pages_uc(page, 1); 1215 1216 #ifdef CONFIG_INTEL_IOMMU 1217 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, 1218 PCI_DMA_BIDIRECTIONAL); 1219 if (pci_dma_mapping_error(dev->pdev, dma_addr)) 1220 return -EINVAL; 1221 #else 1222 dma_addr = page_to_phys(page); 1223 #endif 1224 dev_priv->gtt.base.scratch.page = page; 1225 dev_priv->gtt.base.scratch.addr = dma_addr; 1226 1227 return 0; 1228 } 1229 1230 static void teardown_scratch_page(struct drm_device *dev) 1231 { 1232 struct drm_i915_private *dev_priv = dev->dev_private; 1233 struct page *page = dev_priv->gtt.base.scratch.page; 1234 1235 set_pages_wb(page, 1); 1236 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, 1237 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 1238 put_page(page); 1239 __free_page(page); 1240 } 1241 1242 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) 1243 { 1244 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; 1245 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; 1246 return snb_gmch_ctl << 20; 1247 } 1248 1249 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) 1250 { 1251 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; 1252 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; 1253 if (bdw_gmch_ctl) 1254 bdw_gmch_ctl = 1 << bdw_gmch_ctl; 1255 if (bdw_gmch_ctl > 4) { 1256 WARN_ON(!i915_preliminary_hw_support); 1257 return 4<<20; 1258 } 1259 1260 return bdw_gmch_ctl << 20; 1261 } 1262 1263 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) 1264 { 1265 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; 1266 snb_gmch_ctl &= SNB_GMCH_GMS_MASK; 1267 return snb_gmch_ctl << 25; /* 32 MB units */ 1268 } 1269 1270 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) 1271 { 1272 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; 1273 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; 1274 return bdw_gmch_ctl << 25; /* 32 MB units */ 1275 } 1276 1277 static int ggtt_probe_common(struct drm_device *dev, 1278 size_t gtt_size) 1279 { 1280 struct drm_i915_private *dev_priv = dev->dev_private; 1281 phys_addr_t gtt_phys_addr; 1282 int ret; 1283 1284 /* For Modern GENs the PTEs and register space are split in the BAR */ 1285 gtt_phys_addr = pci_resource_start(dev->pdev, 0) + 1286 (pci_resource_len(dev->pdev, 0) / 2); 1287 1288 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); 1289 if (!dev_priv->gtt.gsm) { 1290 DRM_ERROR("Failed to map the gtt page table\n"); 1291 return -ENOMEM; 1292 } 1293 1294 ret = setup_scratch_page(dev); 1295 if (ret) { 1296 DRM_ERROR("Scratch setup failed\n"); 1297 /* iounmap will also get called at remove, but meh */ 1298 iounmap(dev_priv->gtt.gsm); 1299 } 1300 1301 return ret; 1302 } 1303 1304 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 1305 * bits. When using advanced contexts each context stores its own PAT, but 1306 * writing this data shouldn't be harmful even in those cases. */ 1307 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) 1308 { 1309 #define GEN8_PPAT_UC (0<<0) 1310 #define GEN8_PPAT_WC (1<<0) 1311 #define GEN8_PPAT_WT (2<<0) 1312 #define GEN8_PPAT_WB (3<<0) 1313 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1314 /* FIXME(BDW): Bspec is completely confused about cache control bits. */ 1315 #define GEN8_PPAT_LLC (1<<2) 1316 #define GEN8_PPAT_LLCELLC (2<<2) 1317 #define GEN8_PPAT_LLCeLLC (3<<2) 1318 #define GEN8_PPAT_AGE(x) (x<<4) 1319 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 1320 uint64_t pat; 1321 1322 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 1323 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 1324 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ 1325 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 1326 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 1327 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 1328 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 1329 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 1330 1331 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b 1332 * write would work. */ 1333 I915_WRITE(GEN8_PRIVATE_PAT, pat); 1334 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); 1335 } 1336 1337 static int gen8_gmch_probe(struct drm_device *dev, 1338 size_t *gtt_total, 1339 size_t *stolen, 1340 phys_addr_t *mappable_base, 1341 unsigned long *mappable_end) 1342 { 1343 struct drm_i915_private *dev_priv = dev->dev_private; 1344 unsigned int gtt_size; 1345 u16 snb_gmch_ctl; 1346 int ret; 1347 1348 /* TODO: We're not aware of mappable constraints on gen8 yet */ 1349 *mappable_base = pci_resource_start(dev->pdev, 2); 1350 *mappable_end = pci_resource_len(dev->pdev, 2); 1351 1352 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) 1353 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); 1354 1355 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); 1356 1357 *stolen = gen8_get_stolen_size(snb_gmch_ctl); 1358 1359 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); 1360 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; 1361 1362 gen8_setup_private_ppat(dev_priv); 1363 1364 ret = ggtt_probe_common(dev, gtt_size); 1365 1366 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; 1367 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; 1368 1369 return ret; 1370 } 1371 1372 static int gen6_gmch_probe(struct drm_device *dev, 1373 size_t *gtt_total, 1374 size_t *stolen, 1375 phys_addr_t *mappable_base, 1376 unsigned long *mappable_end) 1377 { 1378 struct drm_i915_private *dev_priv = dev->dev_private; 1379 unsigned int gtt_size; 1380 u16 snb_gmch_ctl; 1381 int ret; 1382 1383 *mappable_base = pci_resource_start(dev->pdev, 2); 1384 *mappable_end = pci_resource_len(dev->pdev, 2); 1385 1386 /* 64/512MB is the current min/max we actually know of, but this is just 1387 * a coarse sanity check. 1388 */ 1389 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { 1390 DRM_ERROR("Unknown GMADR size (%lx)\n", 1391 dev_priv->gtt.mappable_end); 1392 return -ENXIO; 1393 } 1394 1395 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) 1396 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); 1397 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); 1398 1399 *stolen = gen6_get_stolen_size(snb_gmch_ctl); 1400 1401 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); 1402 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; 1403 1404 ret = ggtt_probe_common(dev, gtt_size); 1405 1406 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; 1407 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; 1408 1409 return ret; 1410 } 1411 1412 static void gen6_gmch_remove(struct i915_address_space *vm) 1413 { 1414 1415 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); 1416 1417 drm_mm_takedown(&vm->mm); 1418 iounmap(gtt->gsm); 1419 teardown_scratch_page(vm->dev); 1420 } 1421 1422 static int i915_gmch_probe(struct drm_device *dev, 1423 size_t *gtt_total, 1424 size_t *stolen, 1425 phys_addr_t *mappable_base, 1426 unsigned long *mappable_end) 1427 { 1428 struct drm_i915_private *dev_priv = dev->dev_private; 1429 int ret; 1430 1431 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); 1432 if (!ret) { 1433 DRM_ERROR("failed to set up gmch\n"); 1434 return -EIO; 1435 } 1436 1437 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); 1438 1439 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); 1440 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; 1441 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; 1442 1443 if (unlikely(dev_priv->gtt.do_idle_maps)) 1444 DRM_INFO("applying Ironlake quirks for intel_iommu\n"); 1445 1446 return 0; 1447 } 1448 1449 static void i915_gmch_remove(struct i915_address_space *vm) 1450 { 1451 intel_gmch_remove(); 1452 } 1453 1454 int i915_gem_gtt_init(struct drm_device *dev) 1455 { 1456 struct drm_i915_private *dev_priv = dev->dev_private; 1457 struct i915_gtt *gtt = &dev_priv->gtt; 1458 int ret; 1459 1460 if (INTEL_INFO(dev)->gen <= 5) { 1461 gtt->gtt_probe = i915_gmch_probe; 1462 gtt->base.cleanup = i915_gmch_remove; 1463 } else if (INTEL_INFO(dev)->gen < 8) { 1464 gtt->gtt_probe = gen6_gmch_probe; 1465 gtt->base.cleanup = gen6_gmch_remove; 1466 if (IS_HASWELL(dev) && dev_priv->ellc_size) 1467 gtt->base.pte_encode = iris_pte_encode; 1468 else if (IS_HASWELL(dev)) 1469 gtt->base.pte_encode = hsw_pte_encode; 1470 else if (IS_VALLEYVIEW(dev)) 1471 gtt->base.pte_encode = byt_pte_encode; 1472 else if (INTEL_INFO(dev)->gen >= 7) 1473 gtt->base.pte_encode = ivb_pte_encode; 1474 else 1475 gtt->base.pte_encode = snb_pte_encode; 1476 } else { 1477 dev_priv->gtt.gtt_probe = gen8_gmch_probe; 1478 dev_priv->gtt.base.cleanup = gen6_gmch_remove; 1479 } 1480 1481 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, 1482 >t->mappable_base, >t->mappable_end); 1483 if (ret) 1484 return ret; 1485 1486 gtt->base.dev = dev; 1487 1488 /* GMADR is the PCI mmio aperture into the global GTT. */ 1489 DRM_INFO("Memory usable by graphics device = %zdM\n", 1490 gtt->base.total >> 20); 1491 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); 1492 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); 1493 1494 return 0; 1495 } 1496