1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <drm/intel-gtt.h> 40 #include <linux/backlight.h> 41 42 /* General customization: 43 */ 44 45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47 #define DRIVER_NAME "i915" 48 #define DRIVER_DESC "Intel Graphics" 49 #define DRIVER_DATE "20080730" 50 51 enum pipe { 52 PIPE_A = 0, 53 PIPE_B, 54 PIPE_C, 55 I915_MAX_PIPES 56 }; 57 #define pipe_name(p) ((p) + 'A') 58 59 enum plane { 60 PLANE_A = 0, 61 PLANE_B, 62 PLANE_C, 63 }; 64 #define plane_name(p) ((p) + 'A') 65 66 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 67 68 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 69 70 /* Interface history: 71 * 72 * 1.1: Original. 73 * 1.2: Add Power Management 74 * 1.3: Add vblank support 75 * 1.4: Fix cmdbuffer path, add heap destroy 76 * 1.5: Add vblank pipe configuration 77 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 78 * - Support vertical blank on secondary display pipe 79 */ 80 #define DRIVER_MAJOR 1 81 #define DRIVER_MINOR 6 82 #define DRIVER_PATCHLEVEL 0 83 84 #define WATCH_COHERENCY 0 85 #define WATCH_LISTS 0 86 87 #define I915_GEM_PHYS_CURSOR_0 1 88 #define I915_GEM_PHYS_CURSOR_1 2 89 #define I915_GEM_PHYS_OVERLAY_REGS 3 90 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 91 92 struct drm_i915_gem_phys_object { 93 int id; 94 struct page **page_list; 95 drm_dma_handle_t *handle; 96 struct drm_i915_gem_object *cur_obj; 97 }; 98 99 struct mem_block { 100 struct mem_block *next; 101 struct mem_block *prev; 102 int start; 103 int size; 104 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 105 }; 106 107 struct opregion_header; 108 struct opregion_acpi; 109 struct opregion_swsci; 110 struct opregion_asle; 111 struct drm_i915_private; 112 113 struct intel_opregion { 114 struct opregion_header *header; 115 struct opregion_acpi *acpi; 116 struct opregion_swsci *swsci; 117 struct opregion_asle *asle; 118 void *vbt; 119 u32 __iomem *lid_state; 120 }; 121 #define OPREGION_SIZE (8*1024) 122 123 struct intel_overlay; 124 struct intel_overlay_error_state; 125 126 struct drm_i915_master_private { 127 drm_local_map_t *sarea; 128 struct _drm_i915_sarea *sarea_priv; 129 }; 130 #define I915_FENCE_REG_NONE -1 131 #define I915_MAX_NUM_FENCES 16 132 /* 16 fences + sign bit for FENCE_REG_NONE */ 133 #define I915_MAX_NUM_FENCE_BITS 5 134 135 struct drm_i915_fence_reg { 136 struct list_head lru_list; 137 struct drm_i915_gem_object *obj; 138 uint32_t setup_seqno; 139 int pin_count; 140 }; 141 142 struct sdvo_device_mapping { 143 u8 initialized; 144 u8 dvo_port; 145 u8 slave_addr; 146 u8 dvo_wiring; 147 u8 i2c_pin; 148 u8 ddc_pin; 149 }; 150 151 struct intel_display_error_state; 152 153 struct drm_i915_error_state { 154 u32 eir; 155 u32 pgtbl_er; 156 u32 pipestat[I915_MAX_PIPES]; 157 u32 tail[I915_NUM_RINGS]; 158 u32 head[I915_NUM_RINGS]; 159 u32 ipeir[I915_NUM_RINGS]; 160 u32 ipehr[I915_NUM_RINGS]; 161 u32 instdone[I915_NUM_RINGS]; 162 u32 acthd[I915_NUM_RINGS]; 163 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 164 /* our own tracking of ring head and tail */ 165 u32 cpu_ring_head[I915_NUM_RINGS]; 166 u32 cpu_ring_tail[I915_NUM_RINGS]; 167 u32 error; /* gen6+ */ 168 u32 instpm[I915_NUM_RINGS]; 169 u32 instps[I915_NUM_RINGS]; 170 u32 instdone1; 171 u32 seqno[I915_NUM_RINGS]; 172 u64 bbaddr; 173 u32 fault_reg[I915_NUM_RINGS]; 174 u32 done_reg; 175 u32 faddr[I915_NUM_RINGS]; 176 u64 fence[I915_MAX_NUM_FENCES]; 177 struct timeval time; 178 struct drm_i915_error_ring { 179 struct drm_i915_error_object { 180 int page_count; 181 u32 gtt_offset; 182 u32 *pages[0]; 183 } *ringbuffer, *batchbuffer; 184 struct drm_i915_error_request { 185 long jiffies; 186 u32 seqno; 187 u32 tail; 188 } *requests; 189 int num_requests; 190 } ring[I915_NUM_RINGS]; 191 struct drm_i915_error_buffer { 192 u32 size; 193 u32 name; 194 u32 seqno; 195 u32 gtt_offset; 196 u32 read_domains; 197 u32 write_domain; 198 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 199 s32 pinned:2; 200 u32 tiling:2; 201 u32 dirty:1; 202 u32 purgeable:1; 203 s32 ring:4; 204 u32 cache_level:2; 205 } *active_bo, *pinned_bo; 206 u32 active_bo_count, pinned_bo_count; 207 struct intel_overlay_error_state *overlay; 208 struct intel_display_error_state *display; 209 }; 210 211 struct drm_i915_display_funcs { 212 void (*dpms)(struct drm_crtc *crtc, int mode); 213 bool (*fbc_enabled)(struct drm_device *dev); 214 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 215 void (*disable_fbc)(struct drm_device *dev); 216 int (*get_display_clock_speed)(struct drm_device *dev); 217 int (*get_fifo_size)(struct drm_device *dev, int plane); 218 void (*update_wm)(struct drm_device *dev); 219 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 220 uint32_t sprite_width, int pixel_size); 221 int (*crtc_mode_set)(struct drm_crtc *crtc, 222 struct drm_display_mode *mode, 223 struct drm_display_mode *adjusted_mode, 224 int x, int y, 225 struct drm_framebuffer *old_fb); 226 void (*write_eld)(struct drm_connector *connector, 227 struct drm_crtc *crtc); 228 void (*fdi_link_train)(struct drm_crtc *crtc); 229 void (*init_clock_gating)(struct drm_device *dev); 230 void (*init_pch_clock_gating)(struct drm_device *dev); 231 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 232 struct drm_framebuffer *fb, 233 struct drm_i915_gem_object *obj); 234 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 235 int x, int y); 236 void (*force_wake_get)(struct drm_i915_private *dev_priv); 237 void (*force_wake_put)(struct drm_i915_private *dev_priv); 238 /* clock updates for mode set */ 239 /* cursor updates */ 240 /* render clock increase/decrease */ 241 /* display clock increase/decrease */ 242 /* pll clock increase/decrease */ 243 }; 244 245 struct intel_device_info { 246 u8 gen; 247 u8 is_mobile:1; 248 u8 is_i85x:1; 249 u8 is_i915g:1; 250 u8 is_i945gm:1; 251 u8 is_g33:1; 252 u8 need_gfx_hws:1; 253 u8 is_g4x:1; 254 u8 is_pineview:1; 255 u8 is_broadwater:1; 256 u8 is_crestline:1; 257 u8 is_ivybridge:1; 258 u8 has_fbc:1; 259 u8 has_pipe_cxsr:1; 260 u8 has_hotplug:1; 261 u8 cursor_needs_physical:1; 262 u8 has_overlay:1; 263 u8 overlay_needs_physical:1; 264 u8 supports_tv:1; 265 u8 has_bsd_ring:1; 266 u8 has_blt_ring:1; 267 u8 has_llc:1; 268 }; 269 270 #define I915_PPGTT_PD_ENTRIES 512 271 #define I915_PPGTT_PT_ENTRIES 1024 272 struct i915_hw_ppgtt { 273 unsigned num_pd_entries; 274 struct page **pt_pages; 275 uint32_t pd_offset; 276 dma_addr_t *pt_dma_addr; 277 dma_addr_t scratch_page_dma_addr; 278 }; 279 280 enum no_fbc_reason { 281 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 282 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 283 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 284 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 285 FBC_BAD_PLANE, /* fbc not supported on plane */ 286 FBC_NOT_TILED, /* buffer not tiled */ 287 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 288 FBC_MODULE_PARAM, 289 }; 290 291 enum intel_pch { 292 PCH_IBX, /* Ibexpeak PCH */ 293 PCH_CPT, /* Cougarpoint PCH */ 294 }; 295 296 #define QUIRK_PIPEA_FORCE (1<<0) 297 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 298 299 struct intel_fbdev; 300 struct intel_fbc_work; 301 302 struct intel_gmbus { 303 struct i2c_adapter adapter; 304 bool force_bit; 305 bool has_gpio; 306 u32 reg0; 307 u32 gpio_reg; 308 struct i2c_algo_bit_data bit_algo; 309 struct drm_i915_private *dev_priv; 310 }; 311 312 typedef struct drm_i915_private { 313 struct drm_device *dev; 314 315 const struct intel_device_info *info; 316 317 int has_gem; 318 int relative_constants_mode; 319 320 void __iomem *regs; 321 /** gt_fifo_count and the subsequent register write are synchronized 322 * with dev->struct_mutex. */ 323 unsigned gt_fifo_count; 324 /** forcewake_count is protected by gt_lock */ 325 unsigned forcewake_count; 326 /** gt_lock is also taken in irq contexts. */ 327 struct spinlock gt_lock; 328 329 struct intel_gmbus *gmbus; 330 331 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 332 * controller on different i2c buses. */ 333 struct mutex gmbus_mutex; 334 335 struct pci_dev *bridge_dev; 336 struct intel_ring_buffer ring[I915_NUM_RINGS]; 337 uint32_t next_seqno; 338 339 drm_dma_handle_t *status_page_dmah; 340 uint32_t counter; 341 drm_local_map_t hws_map; 342 struct drm_i915_gem_object *pwrctx; 343 struct drm_i915_gem_object *renderctx; 344 345 struct resource mch_res; 346 347 unsigned int cpp; 348 int back_offset; 349 int front_offset; 350 int current_page; 351 int page_flipping; 352 353 atomic_t irq_received; 354 355 /* protects the irq masks */ 356 spinlock_t irq_lock; 357 /** Cached value of IMR to avoid reads in updating the bitfield */ 358 u32 pipestat[2]; 359 u32 irq_mask; 360 u32 gt_irq_mask; 361 u32 pch_irq_mask; 362 363 u32 hotplug_supported_mask; 364 struct work_struct hotplug_work; 365 366 int tex_lru_log_granularity; 367 int allow_batchbuffer; 368 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 369 int vblank_pipe; 370 int num_pipe; 371 372 /* For hangcheck timer */ 373 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 374 struct timer_list hangcheck_timer; 375 int hangcheck_count; 376 uint32_t last_acthd; 377 uint32_t last_acthd_bsd; 378 uint32_t last_acthd_blt; 379 uint32_t last_instdone; 380 uint32_t last_instdone1; 381 382 unsigned long cfb_size; 383 unsigned int cfb_fb; 384 enum plane cfb_plane; 385 int cfb_y; 386 struct intel_fbc_work *fbc_work; 387 388 struct intel_opregion opregion; 389 390 /* overlay */ 391 struct intel_overlay *overlay; 392 bool sprite_scaling_enabled; 393 394 /* LVDS info */ 395 int backlight_level; /* restore backlight to this value */ 396 bool backlight_enabled; 397 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 398 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 399 400 /* Feature bits from the VBIOS */ 401 unsigned int int_tv_support:1; 402 unsigned int lvds_dither:1; 403 unsigned int lvds_vbt:1; 404 unsigned int int_crt_support:1; 405 unsigned int lvds_use_ssc:1; 406 unsigned int display_clock_mode:1; 407 int lvds_ssc_freq; 408 struct { 409 int rate; 410 int lanes; 411 int preemphasis; 412 int vswing; 413 414 bool initialized; 415 bool support; 416 int bpp; 417 struct edp_power_seq pps; 418 } edp; 419 bool no_aux_handshake; 420 421 struct notifier_block lid_notifier; 422 423 int crt_ddc_pin; 424 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 425 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 426 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 427 428 unsigned int fsb_freq, mem_freq, is_ddr3; 429 430 spinlock_t error_lock; 431 struct drm_i915_error_state *first_error; 432 struct work_struct error_work; 433 struct completion error_completion; 434 struct workqueue_struct *wq; 435 436 /* Display functions */ 437 struct drm_i915_display_funcs display; 438 439 /* PCH chipset type */ 440 enum intel_pch pch_type; 441 442 unsigned long quirks; 443 444 /* Register state */ 445 bool modeset_on_lid; 446 u8 saveLBB; 447 u32 saveDSPACNTR; 448 u32 saveDSPBCNTR; 449 u32 saveDSPARB; 450 u32 saveHWS; 451 u32 savePIPEACONF; 452 u32 savePIPEBCONF; 453 u32 savePIPEASRC; 454 u32 savePIPEBSRC; 455 u32 saveFPA0; 456 u32 saveFPA1; 457 u32 saveDPLL_A; 458 u32 saveDPLL_A_MD; 459 u32 saveHTOTAL_A; 460 u32 saveHBLANK_A; 461 u32 saveHSYNC_A; 462 u32 saveVTOTAL_A; 463 u32 saveVBLANK_A; 464 u32 saveVSYNC_A; 465 u32 saveBCLRPAT_A; 466 u32 saveTRANSACONF; 467 u32 saveTRANS_HTOTAL_A; 468 u32 saveTRANS_HBLANK_A; 469 u32 saveTRANS_HSYNC_A; 470 u32 saveTRANS_VTOTAL_A; 471 u32 saveTRANS_VBLANK_A; 472 u32 saveTRANS_VSYNC_A; 473 u32 savePIPEASTAT; 474 u32 saveDSPASTRIDE; 475 u32 saveDSPASIZE; 476 u32 saveDSPAPOS; 477 u32 saveDSPAADDR; 478 u32 saveDSPASURF; 479 u32 saveDSPATILEOFF; 480 u32 savePFIT_PGM_RATIOS; 481 u32 saveBLC_HIST_CTL; 482 u32 saveBLC_PWM_CTL; 483 u32 saveBLC_PWM_CTL2; 484 u32 saveBLC_CPU_PWM_CTL; 485 u32 saveBLC_CPU_PWM_CTL2; 486 u32 saveFPB0; 487 u32 saveFPB1; 488 u32 saveDPLL_B; 489 u32 saveDPLL_B_MD; 490 u32 saveHTOTAL_B; 491 u32 saveHBLANK_B; 492 u32 saveHSYNC_B; 493 u32 saveVTOTAL_B; 494 u32 saveVBLANK_B; 495 u32 saveVSYNC_B; 496 u32 saveBCLRPAT_B; 497 u32 saveTRANSBCONF; 498 u32 saveTRANS_HTOTAL_B; 499 u32 saveTRANS_HBLANK_B; 500 u32 saveTRANS_HSYNC_B; 501 u32 saveTRANS_VTOTAL_B; 502 u32 saveTRANS_VBLANK_B; 503 u32 saveTRANS_VSYNC_B; 504 u32 savePIPEBSTAT; 505 u32 saveDSPBSTRIDE; 506 u32 saveDSPBSIZE; 507 u32 saveDSPBPOS; 508 u32 saveDSPBADDR; 509 u32 saveDSPBSURF; 510 u32 saveDSPBTILEOFF; 511 u32 saveVGA0; 512 u32 saveVGA1; 513 u32 saveVGA_PD; 514 u32 saveVGACNTRL; 515 u32 saveADPA; 516 u32 saveLVDS; 517 u32 savePP_ON_DELAYS; 518 u32 savePP_OFF_DELAYS; 519 u32 saveDVOA; 520 u32 saveDVOB; 521 u32 saveDVOC; 522 u32 savePP_ON; 523 u32 savePP_OFF; 524 u32 savePP_CONTROL; 525 u32 savePP_DIVISOR; 526 u32 savePFIT_CONTROL; 527 u32 save_palette_a[256]; 528 u32 save_palette_b[256]; 529 u32 saveDPFC_CB_BASE; 530 u32 saveFBC_CFB_BASE; 531 u32 saveFBC_LL_BASE; 532 u32 saveFBC_CONTROL; 533 u32 saveFBC_CONTROL2; 534 u32 saveIER; 535 u32 saveIIR; 536 u32 saveIMR; 537 u32 saveDEIER; 538 u32 saveDEIMR; 539 u32 saveGTIER; 540 u32 saveGTIMR; 541 u32 saveFDI_RXA_IMR; 542 u32 saveFDI_RXB_IMR; 543 u32 saveCACHE_MODE_0; 544 u32 saveMI_ARB_STATE; 545 u32 saveSWF0[16]; 546 u32 saveSWF1[16]; 547 u32 saveSWF2[3]; 548 u8 saveMSR; 549 u8 saveSR[8]; 550 u8 saveGR[25]; 551 u8 saveAR_INDEX; 552 u8 saveAR[21]; 553 u8 saveDACMASK; 554 u8 saveCR[37]; 555 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 556 u32 saveCURACNTR; 557 u32 saveCURAPOS; 558 u32 saveCURABASE; 559 u32 saveCURBCNTR; 560 u32 saveCURBPOS; 561 u32 saveCURBBASE; 562 u32 saveCURSIZE; 563 u32 saveDP_B; 564 u32 saveDP_C; 565 u32 saveDP_D; 566 u32 savePIPEA_GMCH_DATA_M; 567 u32 savePIPEB_GMCH_DATA_M; 568 u32 savePIPEA_GMCH_DATA_N; 569 u32 savePIPEB_GMCH_DATA_N; 570 u32 savePIPEA_DP_LINK_M; 571 u32 savePIPEB_DP_LINK_M; 572 u32 savePIPEA_DP_LINK_N; 573 u32 savePIPEB_DP_LINK_N; 574 u32 saveFDI_RXA_CTL; 575 u32 saveFDI_TXA_CTL; 576 u32 saveFDI_RXB_CTL; 577 u32 saveFDI_TXB_CTL; 578 u32 savePFA_CTL_1; 579 u32 savePFB_CTL_1; 580 u32 savePFA_WIN_SZ; 581 u32 savePFB_WIN_SZ; 582 u32 savePFA_WIN_POS; 583 u32 savePFB_WIN_POS; 584 u32 savePCH_DREF_CONTROL; 585 u32 saveDISP_ARB_CTL; 586 u32 savePIPEA_DATA_M1; 587 u32 savePIPEA_DATA_N1; 588 u32 savePIPEA_LINK_M1; 589 u32 savePIPEA_LINK_N1; 590 u32 savePIPEB_DATA_M1; 591 u32 savePIPEB_DATA_N1; 592 u32 savePIPEB_LINK_M1; 593 u32 savePIPEB_LINK_N1; 594 u32 saveMCHBAR_RENDER_STANDBY; 595 u32 savePCH_PORT_HOTPLUG; 596 597 struct { 598 /** Bridge to intel-gtt-ko */ 599 const struct intel_gtt *gtt; 600 /** Memory allocator for GTT stolen memory */ 601 struct drm_mm stolen; 602 /** Memory allocator for GTT */ 603 struct drm_mm gtt_space; 604 /** List of all objects in gtt_space. Used to restore gtt 605 * mappings on resume */ 606 struct list_head gtt_list; 607 608 /** Usable portion of the GTT for GEM */ 609 unsigned long gtt_start; 610 unsigned long gtt_mappable_end; 611 unsigned long gtt_end; 612 613 struct io_mapping *gtt_mapping; 614 int gtt_mtrr; 615 616 /** PPGTT used for aliasing the PPGTT with the GTT */ 617 struct i915_hw_ppgtt *aliasing_ppgtt; 618 619 struct shrinker inactive_shrinker; 620 621 /** 622 * List of objects currently involved in rendering. 623 * 624 * Includes buffers having the contents of their GPU caches 625 * flushed, not necessarily primitives. last_rendering_seqno 626 * represents when the rendering involved will be completed. 627 * 628 * A reference is held on the buffer while on this list. 629 */ 630 struct list_head active_list; 631 632 /** 633 * List of objects which are not in the ringbuffer but which 634 * still have a write_domain which needs to be flushed before 635 * unbinding. 636 * 637 * last_rendering_seqno is 0 while an object is in this list. 638 * 639 * A reference is held on the buffer while on this list. 640 */ 641 struct list_head flushing_list; 642 643 /** 644 * LRU list of objects which are not in the ringbuffer and 645 * are ready to unbind, but are still in the GTT. 646 * 647 * last_rendering_seqno is 0 while an object is in this list. 648 * 649 * A reference is not held on the buffer while on this list, 650 * as merely being GTT-bound shouldn't prevent its being 651 * freed, and we'll pull it off the list in the free path. 652 */ 653 struct list_head inactive_list; 654 655 /** 656 * LRU list of objects which are not in the ringbuffer but 657 * are still pinned in the GTT. 658 */ 659 struct list_head pinned_list; 660 661 /** LRU list of objects with fence regs on them. */ 662 struct list_head fence_list; 663 664 /** 665 * List of objects currently pending being freed. 666 * 667 * These objects are no longer in use, but due to a signal 668 * we were prevented from freeing them at the appointed time. 669 */ 670 struct list_head deferred_free_list; 671 672 /** 673 * We leave the user IRQ off as much as possible, 674 * but this means that requests will finish and never 675 * be retired once the system goes idle. Set a timer to 676 * fire periodically while the ring is running. When it 677 * fires, go retire requests. 678 */ 679 struct delayed_work retire_work; 680 681 /** 682 * Are we in a non-interruptible section of code like 683 * modesetting? 684 */ 685 bool interruptible; 686 687 /** 688 * Flag if the X Server, and thus DRM, is not currently in 689 * control of the device. 690 * 691 * This is set between LeaveVT and EnterVT. It needs to be 692 * replaced with a semaphore. It also needs to be 693 * transitioned away from for kernel modesetting. 694 */ 695 int suspended; 696 697 /** 698 * Flag if the hardware appears to be wedged. 699 * 700 * This is set when attempts to idle the device timeout. 701 * It prevents command submission from occurring and makes 702 * every pending request fail 703 */ 704 atomic_t wedged; 705 706 /** Bit 6 swizzling required for X tiling */ 707 uint32_t bit_6_swizzle_x; 708 /** Bit 6 swizzling required for Y tiling */ 709 uint32_t bit_6_swizzle_y; 710 711 /* storage for physical objects */ 712 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 713 714 /* accounting, useful for userland debugging */ 715 size_t gtt_total; 716 size_t mappable_gtt_total; 717 size_t object_memory; 718 u32 object_count; 719 } mm; 720 struct sdvo_device_mapping sdvo_mappings[2]; 721 /* indicate whether the LVDS_BORDER should be enabled or not */ 722 unsigned int lvds_border_bits; 723 /* Panel fitter placement and size for Ironlake+ */ 724 u32 pch_pf_pos, pch_pf_size; 725 726 struct drm_crtc *plane_to_crtc_mapping[3]; 727 struct drm_crtc *pipe_to_crtc_mapping[3]; 728 wait_queue_head_t pending_flip_queue; 729 bool flip_pending_is_done; 730 731 /* Reclocking support */ 732 bool render_reclock_avail; 733 bool lvds_downclock_avail; 734 /* indicates the reduced downclock for LVDS*/ 735 int lvds_downclock; 736 struct work_struct idle_work; 737 struct timer_list idle_timer; 738 bool busy; 739 u16 orig_clock; 740 int child_dev_num; 741 struct child_device_config *child_dev; 742 struct drm_connector *int_lvds_connector; 743 struct drm_connector *int_edp_connector; 744 745 bool mchbar_need_disable; 746 747 struct work_struct rps_work; 748 spinlock_t rps_lock; 749 u32 pm_iir; 750 751 u8 cur_delay; 752 u8 min_delay; 753 u8 max_delay; 754 u8 fmax; 755 u8 fstart; 756 757 u64 last_count1; 758 unsigned long last_time1; 759 unsigned long chipset_power; 760 u64 last_count2; 761 struct timespec last_time2; 762 unsigned long gfx_power; 763 int c_m; 764 int r_t; 765 u8 corr; 766 spinlock_t *mchdev_lock; 767 768 enum no_fbc_reason no_fbc_reason; 769 770 struct drm_mm_node *compressed_fb; 771 struct drm_mm_node *compressed_llb; 772 773 unsigned long last_gpu_reset; 774 775 /* list of fbdev register on this device */ 776 struct intel_fbdev *fbdev; 777 778 struct backlight_device *backlight; 779 780 struct drm_property *broadcast_rgb_property; 781 struct drm_property *force_audio_property; 782 } drm_i915_private_t; 783 784 enum hdmi_force_audio { 785 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 786 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 787 HDMI_AUDIO_AUTO, /* trust EDID */ 788 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 789 }; 790 791 enum i915_cache_level { 792 I915_CACHE_NONE, 793 I915_CACHE_LLC, 794 I915_CACHE_LLC_MLC, /* gen6+ */ 795 }; 796 797 struct drm_i915_gem_object { 798 struct drm_gem_object base; 799 800 /** Current space allocated to this object in the GTT, if any. */ 801 struct drm_mm_node *gtt_space; 802 struct list_head gtt_list; 803 804 /** This object's place on the active/flushing/inactive lists */ 805 struct list_head ring_list; 806 struct list_head mm_list; 807 /** This object's place on GPU write list */ 808 struct list_head gpu_write_list; 809 /** This object's place in the batchbuffer or on the eviction list */ 810 struct list_head exec_list; 811 812 /** 813 * This is set if the object is on the active or flushing lists 814 * (has pending rendering), and is not set if it's on inactive (ready 815 * to be unbound). 816 */ 817 unsigned int active:1; 818 819 /** 820 * This is set if the object has been written to since last bound 821 * to the GTT 822 */ 823 unsigned int dirty:1; 824 825 /** 826 * This is set if the object has been written to since the last 827 * GPU flush. 828 */ 829 unsigned int pending_gpu_write:1; 830 831 /** 832 * Fence register bits (if any) for this object. Will be set 833 * as needed when mapped into the GTT. 834 * Protected by dev->struct_mutex. 835 */ 836 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 837 838 /** 839 * Advice: are the backing pages purgeable? 840 */ 841 unsigned int madv:2; 842 843 /** 844 * Current tiling mode for the object. 845 */ 846 unsigned int tiling_mode:2; 847 unsigned int tiling_changed:1; 848 849 /** How many users have pinned this object in GTT space. The following 850 * users can each hold at most one reference: pwrite/pread, pin_ioctl 851 * (via user_pin_count), execbuffer (objects are not allowed multiple 852 * times for the same batchbuffer), and the framebuffer code. When 853 * switching/pageflipping, the framebuffer code has at most two buffers 854 * pinned per crtc. 855 * 856 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 857 * bits with absolutely no headroom. So use 4 bits. */ 858 unsigned int pin_count:4; 859 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 860 861 /** 862 * Is the object at the current location in the gtt mappable and 863 * fenceable? Used to avoid costly recalculations. 864 */ 865 unsigned int map_and_fenceable:1; 866 867 /** 868 * Whether the current gtt mapping needs to be mappable (and isn't just 869 * mappable by accident). Track pin and fault separate for a more 870 * accurate mappable working set. 871 */ 872 unsigned int fault_mappable:1; 873 unsigned int pin_mappable:1; 874 875 /* 876 * Is the GPU currently using a fence to access this buffer, 877 */ 878 unsigned int pending_fenced_gpu_access:1; 879 unsigned int fenced_gpu_access:1; 880 881 unsigned int cache_level:2; 882 883 unsigned int has_aliasing_ppgtt_mapping:1; 884 885 struct page **pages; 886 887 /** 888 * DMAR support 889 */ 890 struct scatterlist *sg_list; 891 int num_sg; 892 893 /** 894 * Used for performing relocations during execbuffer insertion. 895 */ 896 struct hlist_node exec_node; 897 unsigned long exec_handle; 898 struct drm_i915_gem_exec_object2 *exec_entry; 899 900 /** 901 * Current offset of the object in GTT space. 902 * 903 * This is the same as gtt_space->start 904 */ 905 uint32_t gtt_offset; 906 907 /** Breadcrumb of last rendering to the buffer. */ 908 uint32_t last_rendering_seqno; 909 struct intel_ring_buffer *ring; 910 911 /** Breadcrumb of last fenced GPU access to the buffer. */ 912 uint32_t last_fenced_seqno; 913 struct intel_ring_buffer *last_fenced_ring; 914 915 /** Current tiling stride for the object, if it's tiled. */ 916 uint32_t stride; 917 918 /** Record of address bit 17 of each page at last unbind. */ 919 unsigned long *bit_17; 920 921 922 /** 923 * If present, while GEM_DOMAIN_CPU is in the read domain this array 924 * flags which individual pages are valid. 925 */ 926 uint8_t *page_cpu_valid; 927 928 /** User space pin count and filp owning the pin */ 929 uint32_t user_pin_count; 930 struct drm_file *pin_filp; 931 932 /** for phy allocated objects */ 933 struct drm_i915_gem_phys_object *phys_obj; 934 935 /** 936 * Number of crtcs where this object is currently the fb, but 937 * will be page flipped away on the next vblank. When it 938 * reaches 0, dev_priv->pending_flip_queue will be woken up. 939 */ 940 atomic_t pending_flip; 941 }; 942 943 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 944 945 /** 946 * Request queue structure. 947 * 948 * The request queue allows us to note sequence numbers that have been emitted 949 * and may be associated with active buffers to be retired. 950 * 951 * By keeping this list, we can avoid having to do questionable 952 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 953 * an emission time with seqnos for tracking how far ahead of the GPU we are. 954 */ 955 struct drm_i915_gem_request { 956 /** On Which ring this request was generated */ 957 struct intel_ring_buffer *ring; 958 959 /** GEM sequence number associated with this request. */ 960 uint32_t seqno; 961 962 /** Postion in the ringbuffer of the end of the request */ 963 u32 tail; 964 965 /** Time at which this request was emitted, in jiffies. */ 966 unsigned long emitted_jiffies; 967 968 /** global list entry for this request */ 969 struct list_head list; 970 971 struct drm_i915_file_private *file_priv; 972 /** file_priv list entry for this request */ 973 struct list_head client_list; 974 }; 975 976 struct drm_i915_file_private { 977 struct { 978 struct spinlock lock; 979 struct list_head request_list; 980 } mm; 981 }; 982 983 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 984 985 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 986 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 987 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 988 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 989 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 990 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 991 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 992 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 993 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 994 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 995 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 996 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 997 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 998 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 999 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1000 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1001 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1002 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1003 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1004 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1005 1006 /* 1007 * The genX designation typically refers to the render engine, so render 1008 * capability related checks should use IS_GEN, while display and other checks 1009 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1010 * chips, etc.). 1011 */ 1012 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1013 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1014 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1015 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1016 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1017 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1018 1019 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1020 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1021 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1022 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1023 1024 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1025 1026 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1027 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1028 1029 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1030 * rows, which changed the alignment requirements and fence programming. 1031 */ 1032 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1033 IS_I915GM(dev))) 1034 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1035 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1036 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1037 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1038 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1039 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1040 /* dsparb controlled by hw only */ 1041 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1042 1043 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1044 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1045 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1046 1047 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1048 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1049 1050 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1051 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1052 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1053 1054 #include "i915_trace.h" 1055 1056 /** 1057 * RC6 is a special power stage which allows the GPU to enter an very 1058 * low-voltage mode when idle, using down to 0V while at this stage. This 1059 * stage is entered automatically when the GPU is idle when RC6 support is 1060 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1061 * 1062 * There are different RC6 modes available in Intel GPU, which differentiate 1063 * among each other with the latency required to enter and leave RC6 and 1064 * voltage consumed by the GPU in different states. 1065 * 1066 * The combination of the following flags define which states GPU is allowed 1067 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1068 * RC6pp is deepest RC6. Their support by hardware varies according to the 1069 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1070 * which brings the most power savings; deeper states save more power, but 1071 * require higher latency to switch to and wake up. 1072 */ 1073 #define INTEL_RC6_ENABLE (1<<0) 1074 #define INTEL_RC6p_ENABLE (1<<1) 1075 #define INTEL_RC6pp_ENABLE (1<<2) 1076 1077 extern struct drm_ioctl_desc i915_ioctls[]; 1078 extern int i915_max_ioctl; 1079 extern unsigned int i915_fbpercrtc __always_unused; 1080 extern int i915_panel_ignore_lid __read_mostly; 1081 extern unsigned int i915_powersave __read_mostly; 1082 extern int i915_semaphores __read_mostly; 1083 extern unsigned int i915_lvds_downclock __read_mostly; 1084 extern int i915_panel_use_ssc __read_mostly; 1085 extern int i915_vbt_sdvo_panel_type __read_mostly; 1086 extern int i915_enable_rc6 __read_mostly; 1087 extern int i915_enable_fbc __read_mostly; 1088 extern bool i915_enable_hangcheck __read_mostly; 1089 extern int i915_enable_ppgtt __read_mostly; 1090 1091 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1092 extern int i915_resume(struct drm_device *dev); 1093 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1094 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1095 1096 /* i915_dma.c */ 1097 extern void i915_kernel_lost_context(struct drm_device * dev); 1098 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1099 extern int i915_driver_unload(struct drm_device *); 1100 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1101 extern void i915_driver_lastclose(struct drm_device * dev); 1102 extern void i915_driver_preclose(struct drm_device *dev, 1103 struct drm_file *file_priv); 1104 extern void i915_driver_postclose(struct drm_device *dev, 1105 struct drm_file *file_priv); 1106 extern int i915_driver_device_is_agp(struct drm_device * dev); 1107 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1108 unsigned long arg); 1109 extern int i915_emit_box(struct drm_device *dev, 1110 struct drm_clip_rect *box, 1111 int DR1, int DR4); 1112 extern int i915_reset(struct drm_device *dev, u8 flags); 1113 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1114 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1115 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1116 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1117 1118 1119 /* i915_irq.c */ 1120 void i915_hangcheck_elapsed(unsigned long data); 1121 void i915_handle_error(struct drm_device *dev, bool wedged); 1122 extern int i915_irq_emit(struct drm_device *dev, void *data, 1123 struct drm_file *file_priv); 1124 extern int i915_irq_wait(struct drm_device *dev, void *data, 1125 struct drm_file *file_priv); 1126 1127 extern void intel_irq_init(struct drm_device *dev); 1128 1129 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1130 struct drm_file *file_priv); 1131 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1132 struct drm_file *file_priv); 1133 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1134 struct drm_file *file_priv); 1135 1136 void 1137 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1138 1139 void 1140 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1141 1142 void intel_enable_asle(struct drm_device *dev); 1143 1144 #ifdef CONFIG_DEBUG_FS 1145 extern void i915_destroy_error_state(struct drm_device *dev); 1146 #else 1147 #define i915_destroy_error_state(x) 1148 #endif 1149 1150 1151 /* i915_gem.c */ 1152 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1153 struct drm_file *file_priv); 1154 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1155 struct drm_file *file_priv); 1156 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1157 struct drm_file *file_priv); 1158 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1159 struct drm_file *file_priv); 1160 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1161 struct drm_file *file_priv); 1162 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1163 struct drm_file *file_priv); 1164 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1165 struct drm_file *file_priv); 1166 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1167 struct drm_file *file_priv); 1168 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1169 struct drm_file *file_priv); 1170 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1171 struct drm_file *file_priv); 1172 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1173 struct drm_file *file_priv); 1174 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1175 struct drm_file *file_priv); 1176 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1177 struct drm_file *file_priv); 1178 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1179 struct drm_file *file_priv); 1180 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1181 struct drm_file *file_priv); 1182 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1183 struct drm_file *file_priv); 1184 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1185 struct drm_file *file_priv); 1186 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1187 struct drm_file *file_priv); 1188 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1189 struct drm_file *file_priv); 1190 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1191 struct drm_file *file_priv); 1192 void i915_gem_load(struct drm_device *dev); 1193 int i915_gem_init_object(struct drm_gem_object *obj); 1194 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, 1195 uint32_t invalidate_domains, 1196 uint32_t flush_domains); 1197 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1198 size_t size); 1199 void i915_gem_free_object(struct drm_gem_object *obj); 1200 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1201 uint32_t alignment, 1202 bool map_and_fenceable); 1203 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1204 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1205 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1206 void i915_gem_lastclose(struct drm_device *dev); 1207 1208 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1209 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1210 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1211 struct intel_ring_buffer *ring, 1212 u32 seqno); 1213 1214 int i915_gem_dumb_create(struct drm_file *file_priv, 1215 struct drm_device *dev, 1216 struct drm_mode_create_dumb *args); 1217 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1218 uint32_t handle, uint64_t *offset); 1219 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1220 uint32_t handle); 1221 /** 1222 * Returns true if seq1 is later than seq2. 1223 */ 1224 static inline bool 1225 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1226 { 1227 return (int32_t)(seq1 - seq2) >= 0; 1228 } 1229 1230 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1231 1232 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1233 struct intel_ring_buffer *pipelined); 1234 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1235 1236 static inline void 1237 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1238 { 1239 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1241 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1242 } 1243 } 1244 1245 static inline void 1246 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1247 { 1248 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1249 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1250 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1251 } 1252 } 1253 1254 void i915_gem_retire_requests(struct drm_device *dev); 1255 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1256 1257 void i915_gem_reset(struct drm_device *dev); 1258 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1259 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1260 uint32_t read_domains, 1261 uint32_t write_domain); 1262 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1263 int __must_check i915_gem_init_hw(struct drm_device *dev); 1264 void i915_gem_init_swizzling(struct drm_device *dev); 1265 void i915_gem_init_ppgtt(struct drm_device *dev); 1266 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1267 void i915_gem_do_init(struct drm_device *dev, 1268 unsigned long start, 1269 unsigned long mappable_end, 1270 unsigned long end); 1271 int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire); 1272 int __must_check i915_gem_idle(struct drm_device *dev); 1273 int __must_check i915_add_request(struct intel_ring_buffer *ring, 1274 struct drm_file *file, 1275 struct drm_i915_gem_request *request); 1276 int __must_check i915_wait_request(struct intel_ring_buffer *ring, 1277 uint32_t seqno, 1278 bool do_retire); 1279 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1280 int __must_check 1281 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1282 bool write); 1283 int __must_check 1284 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1285 u32 alignment, 1286 struct intel_ring_buffer *pipelined); 1287 int i915_gem_attach_phys_object(struct drm_device *dev, 1288 struct drm_i915_gem_object *obj, 1289 int id, 1290 int align); 1291 void i915_gem_detach_phys_object(struct drm_device *dev, 1292 struct drm_i915_gem_object *obj); 1293 void i915_gem_free_all_phys_object(struct drm_device *dev); 1294 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1295 1296 uint32_t 1297 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1298 uint32_t size, 1299 int tiling_mode); 1300 1301 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1302 enum i915_cache_level cache_level); 1303 1304 /* i915_gem_gtt.c */ 1305 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1306 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1307 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1308 struct drm_i915_gem_object *obj, 1309 enum i915_cache_level cache_level); 1310 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1311 struct drm_i915_gem_object *obj); 1312 1313 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1314 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1315 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1316 enum i915_cache_level cache_level); 1317 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1318 1319 /* i915_gem_evict.c */ 1320 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1321 unsigned alignment, bool mappable); 1322 int __must_check i915_gem_evict_everything(struct drm_device *dev, 1323 bool purgeable_only); 1324 int __must_check i915_gem_evict_inactive(struct drm_device *dev, 1325 bool purgeable_only); 1326 1327 /* i915_gem_tiling.c */ 1328 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1329 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1330 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1331 1332 /* i915_gem_debug.c */ 1333 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1334 const char *where, uint32_t mark); 1335 #if WATCH_LISTS 1336 int i915_verify_lists(struct drm_device *dev); 1337 #else 1338 #define i915_verify_lists(dev) 0 1339 #endif 1340 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1341 int handle); 1342 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1343 const char *where, uint32_t mark); 1344 1345 /* i915_debugfs.c */ 1346 int i915_debugfs_init(struct drm_minor *minor); 1347 void i915_debugfs_cleanup(struct drm_minor *minor); 1348 1349 /* i915_suspend.c */ 1350 extern int i915_save_state(struct drm_device *dev); 1351 extern int i915_restore_state(struct drm_device *dev); 1352 1353 /* i915_suspend.c */ 1354 extern int i915_save_state(struct drm_device *dev); 1355 extern int i915_restore_state(struct drm_device *dev); 1356 1357 /* intel_i2c.c */ 1358 extern int intel_setup_gmbus(struct drm_device *dev); 1359 extern void intel_teardown_gmbus(struct drm_device *dev); 1360 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1361 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1362 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1363 { 1364 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1365 } 1366 extern void intel_i2c_reset(struct drm_device *dev); 1367 1368 /* intel_opregion.c */ 1369 extern int intel_opregion_setup(struct drm_device *dev); 1370 #ifdef CONFIG_ACPI 1371 extern void intel_opregion_init(struct drm_device *dev); 1372 extern void intel_opregion_fini(struct drm_device *dev); 1373 extern void intel_opregion_asle_intr(struct drm_device *dev); 1374 extern void intel_opregion_gse_intr(struct drm_device *dev); 1375 extern void intel_opregion_enable_asle(struct drm_device *dev); 1376 #else 1377 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1378 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1379 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1380 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1381 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1382 #endif 1383 1384 /* intel_acpi.c */ 1385 #ifdef CONFIG_ACPI 1386 extern void intel_register_dsm_handler(void); 1387 extern void intel_unregister_dsm_handler(void); 1388 #else 1389 static inline void intel_register_dsm_handler(void) { return; } 1390 static inline void intel_unregister_dsm_handler(void) { return; } 1391 #endif /* CONFIG_ACPI */ 1392 1393 /* modesetting */ 1394 extern void intel_modeset_init(struct drm_device *dev); 1395 extern void intel_modeset_gem_init(struct drm_device *dev); 1396 extern void intel_modeset_cleanup(struct drm_device *dev); 1397 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1398 extern bool intel_fbc_enabled(struct drm_device *dev); 1399 extern void intel_disable_fbc(struct drm_device *dev); 1400 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1401 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1402 extern void ironlake_enable_rc6(struct drm_device *dev); 1403 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1404 extern void intel_detect_pch(struct drm_device *dev); 1405 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1406 1407 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1408 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1409 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1410 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1411 1412 /* overlay */ 1413 #ifdef CONFIG_DEBUG_FS 1414 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1415 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1416 1417 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1418 extern void intel_display_print_error_state(struct seq_file *m, 1419 struct drm_device *dev, 1420 struct intel_display_error_state *error); 1421 #endif 1422 1423 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1424 1425 #define BEGIN_LP_RING(n) \ 1426 intel_ring_begin(LP_RING(dev_priv), (n)) 1427 1428 #define OUT_RING(x) \ 1429 intel_ring_emit(LP_RING(dev_priv), x) 1430 1431 #define ADVANCE_LP_RING() \ 1432 intel_ring_advance(LP_RING(dev_priv)) 1433 1434 /** 1435 * Lock test for when it's just for synchronization of ring access. 1436 * 1437 * In that case, we don't need to do it when GEM is initialized as nobody else 1438 * has access to the ring. 1439 */ 1440 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1441 if (LP_RING(dev->dev_private)->obj == NULL) \ 1442 LOCK_TEST_WITH_RETURN(dev, file); \ 1443 } while (0) 1444 1445 /* On SNB platform, before reading ring registers forcewake bit 1446 * must be set to prevent GT core from power down and stale values being 1447 * returned. 1448 */ 1449 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1450 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1451 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1452 1453 /* We give fast paths for the really cool registers */ 1454 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1455 (((dev_priv)->info->gen >= 6) && \ 1456 ((reg) < 0x40000) && \ 1457 ((reg) != FORCEWAKE)) 1458 1459 #define __i915_read(x, y) \ 1460 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1461 1462 __i915_read(8, b) 1463 __i915_read(16, w) 1464 __i915_read(32, l) 1465 __i915_read(64, q) 1466 #undef __i915_read 1467 1468 #define __i915_write(x, y) \ 1469 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1470 1471 __i915_write(8, b) 1472 __i915_write(16, w) 1473 __i915_write(32, l) 1474 __i915_write(64, q) 1475 #undef __i915_write 1476 1477 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1478 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1479 1480 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1481 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1482 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1483 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1484 1485 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1486 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1487 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1488 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1489 1490 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1491 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1492 1493 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1494 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1495 1496 1497 #endif 1498