1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 /* General customization: 34 */ 35 36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 37 38 #define DRIVER_NAME "i915" 39 #define DRIVER_DESC "Intel Graphics" 40 #define DRIVER_DATE "20060119" 41 42 /* Interface history: 43 * 44 * 1.1: Original. 45 * 1.2: Add Power Management 46 * 1.3: Add vblank support 47 * 1.4: Fix cmdbuffer path, add heap destroy 48 * 1.5: Add vblank pipe configuration 49 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 50 * - Support vertical blank on secondary display pipe 51 */ 52 #define DRIVER_MAJOR 1 53 #define DRIVER_MINOR 6 54 #define DRIVER_PATCHLEVEL 0 55 56 typedef struct _drm_i915_ring_buffer { 57 int tail_mask; 58 unsigned long Start; 59 unsigned long End; 60 unsigned long Size; 61 u8 *virtual_start; 62 int head; 63 int tail; 64 int space; 65 drm_local_map_t map; 66 } drm_i915_ring_buffer_t; 67 68 struct mem_block { 69 struct mem_block *next; 70 struct mem_block *prev; 71 int start; 72 int size; 73 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 74 }; 75 76 typedef struct _drm_i915_vbl_swap { 77 struct list_head head; 78 drm_drawable_t drw_id; 79 unsigned int pipe; 80 unsigned int sequence; 81 } drm_i915_vbl_swap_t; 82 83 typedef struct drm_i915_private { 84 drm_local_map_t *sarea; 85 drm_local_map_t *mmio_map; 86 87 drm_i915_sarea_t *sarea_priv; 88 drm_i915_ring_buffer_t ring; 89 90 drm_dma_handle_t *status_page_dmah; 91 void *hw_status_page; 92 dma_addr_t dma_status_page; 93 unsigned long counter; 94 unsigned int status_gfx_addr; 95 drm_local_map_t hws_map; 96 97 unsigned int cpp; 98 int back_offset; 99 int front_offset; 100 int current_page; 101 int page_flipping; 102 int use_mi_batchbuffer_start; 103 104 wait_queue_head_t irq_queue; 105 atomic_t irq_received; 106 atomic_t irq_emitted; 107 108 int tex_lru_log_granularity; 109 int allow_batchbuffer; 110 struct mem_block *agp_heap; 111 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 112 int vblank_pipe; 113 114 spinlock_t swaps_lock; 115 drm_i915_vbl_swap_t vbl_swaps; 116 unsigned int swaps_pending; 117 118 /* Register state */ 119 u8 saveLBB; 120 u32 saveDSPACNTR; 121 u32 saveDSPBCNTR; 122 u32 saveDSPARB; 123 u32 savePIPEACONF; 124 u32 savePIPEBCONF; 125 u32 savePIPEASRC; 126 u32 savePIPEBSRC; 127 u32 saveFPA0; 128 u32 saveFPA1; 129 u32 saveDPLL_A; 130 u32 saveDPLL_A_MD; 131 u32 saveHTOTAL_A; 132 u32 saveHBLANK_A; 133 u32 saveHSYNC_A; 134 u32 saveVTOTAL_A; 135 u32 saveVBLANK_A; 136 u32 saveVSYNC_A; 137 u32 saveBCLRPAT_A; 138 u32 savePIPEASTAT; 139 u32 saveDSPASTRIDE; 140 u32 saveDSPASIZE; 141 u32 saveDSPAPOS; 142 u32 saveDSPABASE; 143 u32 saveDSPASURF; 144 u32 saveDSPATILEOFF; 145 u32 savePFIT_PGM_RATIOS; 146 u32 saveBLC_PWM_CTL; 147 u32 saveBLC_PWM_CTL2; 148 u32 saveFPB0; 149 u32 saveFPB1; 150 u32 saveDPLL_B; 151 u32 saveDPLL_B_MD; 152 u32 saveHTOTAL_B; 153 u32 saveHBLANK_B; 154 u32 saveHSYNC_B; 155 u32 saveVTOTAL_B; 156 u32 saveVBLANK_B; 157 u32 saveVSYNC_B; 158 u32 saveBCLRPAT_B; 159 u32 savePIPEBSTAT; 160 u32 saveDSPBSTRIDE; 161 u32 saveDSPBSIZE; 162 u32 saveDSPBPOS; 163 u32 saveDSPBBASE; 164 u32 saveDSPBSURF; 165 u32 saveDSPBTILEOFF; 166 u32 saveVCLK_DIVISOR_VGA0; 167 u32 saveVCLK_DIVISOR_VGA1; 168 u32 saveVCLK_POST_DIV; 169 u32 saveVGACNTRL; 170 u32 saveADPA; 171 u32 saveLVDS; 172 u32 saveLVDSPP_ON; 173 u32 saveLVDSPP_OFF; 174 u32 saveDVOA; 175 u32 saveDVOB; 176 u32 saveDVOC; 177 u32 savePP_ON; 178 u32 savePP_OFF; 179 u32 savePP_CONTROL; 180 u32 savePP_CYCLE; 181 u32 savePFIT_CONTROL; 182 u32 save_palette_a[256]; 183 u32 save_palette_b[256]; 184 u32 saveFBC_CFB_BASE; 185 u32 saveFBC_LL_BASE; 186 u32 saveFBC_CONTROL; 187 u32 saveFBC_CONTROL2; 188 u32 saveIER; 189 u32 saveIIR; 190 u32 saveIMR; 191 u32 saveCACHE_MODE_0; 192 u32 saveD_STATE; 193 u32 saveDSPCLK_GATE_D; 194 u32 saveMI_ARB_STATE; 195 u32 saveSWF0[16]; 196 u32 saveSWF1[16]; 197 u32 saveSWF2[3]; 198 u8 saveMSR; 199 u8 saveSR[8]; 200 u8 saveGR[25]; 201 u8 saveAR_INDEX; 202 u8 saveAR[21]; 203 u8 saveDACMASK; 204 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 205 u8 saveCR[37]; 206 } drm_i915_private_t; 207 208 extern struct drm_ioctl_desc i915_ioctls[]; 209 extern int i915_max_ioctl; 210 211 /* i915_dma.c */ 212 extern void i915_kernel_lost_context(struct drm_device * dev); 213 extern int i915_driver_load(struct drm_device *, unsigned long flags); 214 extern int i915_driver_unload(struct drm_device *); 215 extern void i915_driver_lastclose(struct drm_device * dev); 216 extern void i915_driver_preclose(struct drm_device *dev, 217 struct drm_file *file_priv); 218 extern int i915_driver_device_is_agp(struct drm_device * dev); 219 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 220 unsigned long arg); 221 222 /* i915_irq.c */ 223 extern int i915_irq_emit(struct drm_device *dev, void *data, 224 struct drm_file *file_priv); 225 extern int i915_irq_wait(struct drm_device *dev, void *data, 226 struct drm_file *file_priv); 227 228 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); 229 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); 230 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 231 extern void i915_driver_irq_preinstall(struct drm_device * dev); 232 extern void i915_driver_irq_postinstall(struct drm_device * dev); 233 extern void i915_driver_irq_uninstall(struct drm_device * dev); 234 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 235 struct drm_file *file_priv); 236 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 237 struct drm_file *file_priv); 238 extern int i915_vblank_swap(struct drm_device *dev, void *data, 239 struct drm_file *file_priv); 240 241 /* i915_mem.c */ 242 extern int i915_mem_alloc(struct drm_device *dev, void *data, 243 struct drm_file *file_priv); 244 extern int i915_mem_free(struct drm_device *dev, void *data, 245 struct drm_file *file_priv); 246 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 247 struct drm_file *file_priv); 248 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 249 struct drm_file *file_priv); 250 extern void i915_mem_takedown(struct mem_block **heap); 251 extern void i915_mem_release(struct drm_device * dev, 252 struct drm_file *file_priv, struct mem_block *heap); 253 254 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 255 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 256 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 257 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 258 259 #define I915_VERBOSE 0 260 261 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 262 volatile char *virt; 263 264 #define BEGIN_LP_RING(n) do { \ 265 if (I915_VERBOSE) \ 266 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 267 if (dev_priv->ring.space < (n)*4) \ 268 i915_wait_ring(dev, (n)*4, __func__); \ 269 outcount = 0; \ 270 outring = dev_priv->ring.tail; \ 271 ringmask = dev_priv->ring.tail_mask; \ 272 virt = dev_priv->ring.virtual_start; \ 273 } while (0) 274 275 #define OUT_RING(n) do { \ 276 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 277 *(volatile unsigned int *)(virt + outring) = (n); \ 278 outcount++; \ 279 outring += 4; \ 280 outring &= ringmask; \ 281 } while (0) 282 283 #define ADVANCE_LP_RING() do { \ 284 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 285 dev_priv->ring.tail = outring; \ 286 dev_priv->ring.space -= outcount * 4; \ 287 I915_WRITE(LP_RING + RING_TAIL, outring); \ 288 } while(0) 289 290 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 291 292 /* Extended config space */ 293 #define LBB 0xf4 294 295 /* VGA stuff */ 296 297 #define VGA_ST01_MDA 0x3ba 298 #define VGA_ST01_CGA 0x3da 299 300 #define VGA_MSR_WRITE 0x3c2 301 #define VGA_MSR_READ 0x3cc 302 #define VGA_MSR_MEM_EN (1<<1) 303 #define VGA_MSR_CGA_MODE (1<<0) 304 305 #define VGA_SR_INDEX 0x3c4 306 #define VGA_SR_DATA 0x3c5 307 308 #define VGA_AR_INDEX 0x3c0 309 #define VGA_AR_VID_EN (1<<5) 310 #define VGA_AR_DATA_WRITE 0x3c0 311 #define VGA_AR_DATA_READ 0x3c1 312 313 #define VGA_GR_INDEX 0x3ce 314 #define VGA_GR_DATA 0x3cf 315 /* GR05 */ 316 #define VGA_GR_MEM_READ_MODE_SHIFT 3 317 #define VGA_GR_MEM_READ_MODE_PLANE 1 318 /* GR06 */ 319 #define VGA_GR_MEM_MODE_MASK 0xc 320 #define VGA_GR_MEM_MODE_SHIFT 2 321 #define VGA_GR_MEM_A0000_AFFFF 0 322 #define VGA_GR_MEM_A0000_BFFFF 1 323 #define VGA_GR_MEM_B0000_B7FFF 2 324 #define VGA_GR_MEM_B0000_BFFFF 3 325 326 #define VGA_DACMASK 0x3c6 327 #define VGA_DACRX 0x3c7 328 #define VGA_DACWX 0x3c8 329 #define VGA_DACDATA 0x3c9 330 331 #define VGA_CR_INDEX_MDA 0x3b4 332 #define VGA_CR_DATA_MDA 0x3b5 333 #define VGA_CR_INDEX_CGA 0x3d4 334 #define VGA_CR_DATA_CGA 0x3d5 335 336 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 337 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 338 #define CMD_REPORT_HEAD (7<<23) 339 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 340 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 341 342 #define INST_PARSER_CLIENT 0x00000000 343 #define INST_OP_FLUSH 0x02000000 344 #define INST_FLUSH_MAP_CACHE 0x00000001 345 346 #define BB1_START_ADDR_MASK (~0x7) 347 #define BB1_PROTECTED (1<<0) 348 #define BB1_UNPROTECTED (0<<0) 349 #define BB2_END_ADDR_MASK (~0x7) 350 351 /* Framebuffer compression */ 352 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 353 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 354 #define FBC_CONTROL 0x03208 355 #define FBC_CTL_EN (1<<31) 356 #define FBC_CTL_PERIODIC (1<<30) 357 #define FBC_CTL_INTERVAL_SHIFT (16) 358 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 359 #define FBC_CTL_STRIDE_SHIFT (5) 360 #define FBC_CTL_FENCENO (1<<0) 361 #define FBC_COMMAND 0x0320c 362 #define FBC_CMD_COMPRESS (1<<0) 363 #define FBC_STATUS 0x03210 364 #define FBC_STAT_COMPRESSING (1<<31) 365 #define FBC_STAT_COMPRESSED (1<<30) 366 #define FBC_STAT_MODIFIED (1<<29) 367 #define FBC_STAT_CURRENT_LINE (1<<0) 368 #define FBC_CONTROL2 0x03214 369 #define FBC_CTL_FENCE_DBL (0<<4) 370 #define FBC_CTL_IDLE_IMM (0<<2) 371 #define FBC_CTL_IDLE_FULL (1<<2) 372 #define FBC_CTL_IDLE_LINE (2<<2) 373 #define FBC_CTL_IDLE_DEBUG (3<<2) 374 #define FBC_CTL_CPU_FENCE (1<<1) 375 #define FBC_CTL_PLANEA (0<<0) 376 #define FBC_CTL_PLANEB (1<<0) 377 #define FBC_FENCE_OFF 0x0321b 378 379 #define FBC_LL_SIZE (1536) 380 #define FBC_LL_PAD (32) 381 382 /* Interrupt bits: 383 */ 384 #define USER_INT_FLAG (1<<1) 385 #define VSYNC_PIPEB_FLAG (1<<5) 386 #define VSYNC_PIPEA_FLAG (1<<7) 387 #define HWB_OOM_FLAG (1<<13) /* binner out of memory */ 388 389 #define I915REG_HWSTAM 0x02098 390 #define I915REG_INT_IDENTITY_R 0x020a4 391 #define I915REG_INT_MASK_R 0x020a8 392 #define I915REG_INT_ENABLE_R 0x020a0 393 394 #define I915REG_PIPEASTAT 0x70024 395 #define I915REG_PIPEBSTAT 0x71024 396 397 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 398 #define I915_VBLANK_CLEAR (1UL<<1) 399 400 #define SRX_INDEX 0x3c4 401 #define SRX_DATA 0x3c5 402 #define SR01 1 403 #define SR01_SCREEN_OFF (1<<5) 404 405 #define PPCR 0x61204 406 #define PPCR_ON (1<<0) 407 408 #define DVOB 0x61140 409 #define DVOB_ON (1<<31) 410 #define DVOC 0x61160 411 #define DVOC_ON (1<<31) 412 #define LVDS 0x61180 413 #define LVDS_ON (1<<31) 414 415 #define ADPA 0x61100 416 #define ADPA_DPMS_MASK (~(3<<10)) 417 #define ADPA_DPMS_ON (0<<10) 418 #define ADPA_DPMS_SUSPEND (1<<10) 419 #define ADPA_DPMS_STANDBY (2<<10) 420 #define ADPA_DPMS_OFF (3<<10) 421 422 #define NOPID 0x2094 423 #define LP_RING 0x2030 424 #define HP_RING 0x2040 425 /* The binner has its own ring buffer: 426 */ 427 #define HWB_RING 0x2400 428 429 #define RING_TAIL 0x00 430 #define TAIL_ADDR 0x001FFFF8 431 #define RING_HEAD 0x04 432 #define HEAD_WRAP_COUNT 0xFFE00000 433 #define HEAD_WRAP_ONE 0x00200000 434 #define HEAD_ADDR 0x001FFFFC 435 #define RING_START 0x08 436 #define START_ADDR 0x0xFFFFF000 437 #define RING_LEN 0x0C 438 #define RING_NR_PAGES 0x001FF000 439 #define RING_REPORT_MASK 0x00000006 440 #define RING_REPORT_64K 0x00000002 441 #define RING_REPORT_128K 0x00000004 442 #define RING_NO_REPORT 0x00000000 443 #define RING_VALID_MASK 0x00000001 444 #define RING_VALID 0x00000001 445 #define RING_INVALID 0x00000000 446 447 /* Instruction parser error reg: 448 */ 449 #define IPEIR 0x2088 450 451 /* Scratch pad debug 0 reg: 452 */ 453 #define SCPD0 0x209c 454 455 /* Error status reg: 456 */ 457 #define ESR 0x20b8 458 459 /* Secondary DMA fetch address debug reg: 460 */ 461 #define DMA_FADD_S 0x20d4 462 463 /* Memory Interface Arbitration State 464 */ 465 #define MI_ARB_STATE 0x20e4 466 467 /* Cache mode 0 reg. 468 * - Manipulating render cache behaviour is central 469 * to the concept of zone rendering, tuning this reg can help avoid 470 * unnecessary render cache reads and even writes (for z/stencil) 471 * at beginning and end of scene. 472 * 473 * - To change a bit, write to this reg with a mask bit set and the 474 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. 475 */ 476 #define Cache_Mode_0 0x2120 477 #define CACHE_MODE_0 0x2120 478 #define CM0_MASK_SHIFT 16 479 #define CM0_IZ_OPT_DISABLE (1<<6) 480 #define CM0_ZR_OPT_DISABLE (1<<5) 481 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 482 #define CM0_COLOR_EVICT_DISABLE (1<<3) 483 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 484 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 485 486 487 /* Graphics flush control. A CPU write flushes the GWB of all writes. 488 * The data is discarded. 489 */ 490 #define GFX_FLSH_CNTL 0x2170 491 492 /* Binner control. Defines the location of the bin pointer list: 493 */ 494 #define BINCTL 0x2420 495 #define BC_MASK (1 << 9) 496 497 /* Binned scene info. 498 */ 499 #define BINSCENE 0x2428 500 #define BS_OP_LOAD (1 << 8) 501 #define BS_MASK (1 << 22) 502 503 /* Bin command parser debug reg: 504 */ 505 #define BCPD 0x2480 506 507 /* Bin memory control debug reg: 508 */ 509 #define BMCD 0x2484 510 511 /* Bin data cache debug reg: 512 */ 513 #define BDCD 0x2488 514 515 /* Binner pointer cache debug reg: 516 */ 517 #define BPCD 0x248c 518 519 /* Binner scratch pad debug reg: 520 */ 521 #define BINSKPD 0x24f0 522 523 /* HWB scratch pad debug reg: 524 */ 525 #define HWBSKPD 0x24f4 526 527 /* Binner memory pool reg: 528 */ 529 #define BMP_BUFFER 0x2430 530 #define BMP_PAGE_SIZE_4K (0 << 10) 531 #define BMP_BUFFER_SIZE_SHIFT 1 532 #define BMP_ENABLE (1 << 0) 533 534 /* Get/put memory from the binner memory pool: 535 */ 536 #define BMP_GET 0x2438 537 #define BMP_PUT 0x2440 538 #define BMP_OFFSET_SHIFT 5 539 540 /* 3D state packets: 541 */ 542 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 543 544 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 545 #define SC_UPDATE_SCISSOR (0x1<<1) 546 #define SC_ENABLE_MASK (0x1<<0) 547 #define SC_ENABLE (0x1<<0) 548 549 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 550 551 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 552 #define SCI_YMIN_MASK (0xffff<<16) 553 #define SCI_XMIN_MASK (0xffff<<0) 554 #define SCI_YMAX_MASK (0xffff<<16) 555 #define SCI_XMAX_MASK (0xffff<<0) 556 557 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 558 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 559 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 560 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 561 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 562 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 563 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 564 565 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 566 567 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 568 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 569 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 570 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 571 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) 572 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) 573 574 #define MI_BATCH_BUFFER ((0x30<<23)|1) 575 #define MI_BATCH_BUFFER_START (0x31<<23) 576 #define MI_BATCH_BUFFER_END (0xA<<23) 577 #define MI_BATCH_NON_SECURE (1) 578 #define MI_BATCH_NON_SECURE_I965 (1<<8) 579 580 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 581 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 582 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 583 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 584 585 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 586 587 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 588 #define ASYNC_FLIP (1<<22) 589 #define DISPLAY_PLANE_A (0<<20) 590 #define DISPLAY_PLANE_B (1<<20) 591 592 /* Display regs */ 593 #define DSPACNTR 0x70180 594 #define DSPBCNTR 0x71180 595 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 596 597 /* Define the region of interest for the binner: 598 */ 599 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4) 600 601 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 602 603 #define CMD_MI_FLUSH (0x04 << 23) 604 #define MI_NO_WRITE_FLUSH (1 << 2) 605 #define MI_READ_FLUSH (1 << 0) 606 #define MI_EXE_FLUSH (1 << 1) 607 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 608 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 609 610 #define BREADCRUMB_BITS 31 611 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) 612 613 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) 614 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 615 616 #define BLC_PWM_CTL 0x61254 617 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 618 619 #define BLC_PWM_CTL2 0x61250 620 /** 621 * This is the most significant 15 bits of the number of backlight cycles in a 622 * complete cycle of the modulated backlight control. 623 * 624 * The actual value is this field multiplied by two. 625 */ 626 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 627 #define BLM_LEGACY_MODE (1 << 16) 628 /** 629 * This is the number of cycles out of the backlight modulation cycle for which 630 * the backlight is on. 631 * 632 * This field must be no greater than the number of cycles in the complete 633 * backlight modulation cycle. 634 */ 635 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 636 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 637 638 #define I915_GCFGC 0xf0 639 #define I915_LOW_FREQUENCY_ENABLE (1 << 7) 640 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 641 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 642 #define I915_DISPLAY_CLOCK_MASK (7 << 4) 643 644 #define I855_HPLLCC 0xc0 645 #define I855_CLOCK_CONTROL_MASK (3 << 0) 646 #define I855_CLOCK_133_200 (0 << 0) 647 #define I855_CLOCK_100_200 (1 << 0) 648 #define I855_CLOCK_100_133 (2 << 0) 649 #define I855_CLOCK_166_250 (3 << 0) 650 651 /* p317, 319 652 */ 653 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ 654 #define VCLK2_VCO_N 0x600a 655 #define VCLK2_VCO_DIV_SEL 0x6012 656 657 #define VCLK_DIVISOR_VGA0 0x6000 658 #define VCLK_DIVISOR_VGA1 0x6004 659 #define VCLK_POST_DIV 0x6010 660 /** Selects a post divisor of 4 instead of 2. */ 661 # define VGA1_PD_P2_DIV_4 (1 << 15) 662 /** Overrides the p2 post divisor field */ 663 # define VGA1_PD_P1_DIV_2 (1 << 13) 664 # define VGA1_PD_P1_SHIFT 8 665 /** P1 value is 2 greater than this field */ 666 # define VGA1_PD_P1_MASK (0x1f << 8) 667 /** Selects a post divisor of 4 instead of 2. */ 668 # define VGA0_PD_P2_DIV_4 (1 << 7) 669 /** Overrides the p2 post divisor field */ 670 # define VGA0_PD_P1_DIV_2 (1 << 5) 671 # define VGA0_PD_P1_SHIFT 0 672 /** P1 value is 2 greater than this field */ 673 # define VGA0_PD_P1_MASK (0x1f << 0) 674 675 /* PCI D state control register */ 676 #define D_STATE 0x6104 677 #define DSPCLK_GATE_D 0x6200 678 679 /* I830 CRTC registers */ 680 #define HTOTAL_A 0x60000 681 #define HBLANK_A 0x60004 682 #define HSYNC_A 0x60008 683 #define VTOTAL_A 0x6000c 684 #define VBLANK_A 0x60010 685 #define VSYNC_A 0x60014 686 #define PIPEASRC 0x6001c 687 #define BCLRPAT_A 0x60020 688 #define VSYNCSHIFT_A 0x60028 689 690 #define HTOTAL_B 0x61000 691 #define HBLANK_B 0x61004 692 #define HSYNC_B 0x61008 693 #define VTOTAL_B 0x6100c 694 #define VBLANK_B 0x61010 695 #define VSYNC_B 0x61014 696 #define PIPEBSRC 0x6101c 697 #define BCLRPAT_B 0x61020 698 #define VSYNCSHIFT_B 0x61028 699 700 #define PP_STATUS 0x61200 701 # define PP_ON (1 << 31) 702 /** 703 * Indicates that all dependencies of the panel are on: 704 * 705 * - PLL enabled 706 * - pipe enabled 707 * - LVDS/DVOB/DVOC on 708 */ 709 # define PP_READY (1 << 30) 710 # define PP_SEQUENCE_NONE (0 << 28) 711 # define PP_SEQUENCE_ON (1 << 28) 712 # define PP_SEQUENCE_OFF (2 << 28) 713 # define PP_SEQUENCE_MASK 0x30000000 714 #define PP_CONTROL 0x61204 715 # define POWER_TARGET_ON (1 << 0) 716 717 #define LVDSPP_ON 0x61208 718 #define LVDSPP_OFF 0x6120c 719 #define PP_CYCLE 0x61210 720 721 #define PFIT_CONTROL 0x61230 722 # define PFIT_ENABLE (1 << 31) 723 # define PFIT_PIPE_MASK (3 << 29) 724 # define PFIT_PIPE_SHIFT 29 725 # define VERT_INTERP_DISABLE (0 << 10) 726 # define VERT_INTERP_BILINEAR (1 << 10) 727 # define VERT_INTERP_MASK (3 << 10) 728 # define VERT_AUTO_SCALE (1 << 9) 729 # define HORIZ_INTERP_DISABLE (0 << 6) 730 # define HORIZ_INTERP_BILINEAR (1 << 6) 731 # define HORIZ_INTERP_MASK (3 << 6) 732 # define HORIZ_AUTO_SCALE (1 << 5) 733 # define PANEL_8TO6_DITHER_ENABLE (1 << 3) 734 735 #define PFIT_PGM_RATIOS 0x61234 736 # define PFIT_VERT_SCALE_MASK 0xfff00000 737 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0 738 739 #define PFIT_AUTO_RATIOS 0x61238 740 741 742 #define DPLL_A 0x06014 743 #define DPLL_B 0x06018 744 # define DPLL_VCO_ENABLE (1 << 31) 745 # define DPLL_DVO_HIGH_SPEED (1 << 30) 746 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 747 # define DPLL_VGA_MODE_DIS (1 << 28) 748 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 749 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 750 # define DPLL_MODE_MASK (3 << 26) 751 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 752 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 753 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 754 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 755 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 756 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 757 /** 758 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 759 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 760 */ 761 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 762 /** 763 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 764 * this field (only one bit may be set). 765 */ 766 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 767 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 768 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 769 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 770 # define PLL_REF_INPUT_DREFCLK (0 << 13) 771 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 772 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 773 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 774 # define PLL_REF_INPUT_MASK (3 << 13) 775 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 776 /* 777 * Parallel to Serial Load Pulse phase selection. 778 * Selects the phase for the 10X DPLL clock for the PCIe 779 * digital display port. The range is 4 to 13; 10 or more 780 * is just a flip delay. The default is 6 781 */ 782 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 783 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 784 785 /** 786 * SDVO multiplier for 945G/GM. Not used on 965. 787 * 788 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 789 */ 790 # define SDVO_MULTIPLIER_MASK 0x000000ff 791 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 792 # define SDVO_MULTIPLIER_SHIFT_VGA 0 793 794 /** @defgroup DPLL_MD 795 * @{ 796 */ 797 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 798 #define DPLL_A_MD 0x0601c 799 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 800 #define DPLL_B_MD 0x06020 801 /** 802 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 803 * 804 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 805 */ 806 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 807 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 808 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 809 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 810 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 811 /** 812 * SDVO/UDI pixel multiplier. 813 * 814 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 815 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 816 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 817 * dummy bytes in the datastream at an increased clock rate, with both sides of 818 * the link knowing how many bytes are fill. 819 * 820 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 821 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 822 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 823 * through an SDVO command. 824 * 825 * This register field has values of multiplication factor minus 1, with 826 * a maximum multiplier of 5 for SDVO. 827 */ 828 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 829 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 830 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 831 * This best be set to the default value (3) or the CRT won't work. No, 832 * I don't entirely understand what this does... 833 */ 834 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 835 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 836 /** @} */ 837 838 #define DPLL_TEST 0x606c 839 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 840 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 841 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 842 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 843 # define DPLLB_TEST_N_BYPASS (1 << 19) 844 # define DPLLB_TEST_M_BYPASS (1 << 18) 845 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 846 # define DPLLA_TEST_N_BYPASS (1 << 3) 847 # define DPLLA_TEST_M_BYPASS (1 << 2) 848 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 849 850 #define ADPA 0x61100 851 #define ADPA_DAC_ENABLE (1<<31) 852 #define ADPA_DAC_DISABLE 0 853 #define ADPA_PIPE_SELECT_MASK (1<<30) 854 #define ADPA_PIPE_A_SELECT 0 855 #define ADPA_PIPE_B_SELECT (1<<30) 856 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 857 #define ADPA_SETS_HVPOLARITY 0 858 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 859 #define ADPA_VSYNC_CNTL_ENABLE 0 860 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 861 #define ADPA_HSYNC_CNTL_ENABLE 0 862 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 863 #define ADPA_VSYNC_ACTIVE_LOW 0 864 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 865 #define ADPA_HSYNC_ACTIVE_LOW 0 866 867 #define FPA0 0x06040 868 #define FPA1 0x06044 869 #define FPB0 0x06048 870 #define FPB1 0x0604c 871 # define FP_N_DIV_MASK 0x003f0000 872 # define FP_N_DIV_SHIFT 16 873 # define FP_M1_DIV_MASK 0x00003f00 874 # define FP_M1_DIV_SHIFT 8 875 # define FP_M2_DIV_MASK 0x0000003f 876 # define FP_M2_DIV_SHIFT 0 877 878 879 #define PORT_HOTPLUG_EN 0x61110 880 # define SDVOB_HOTPLUG_INT_EN (1 << 26) 881 # define SDVOC_HOTPLUG_INT_EN (1 << 25) 882 # define TV_HOTPLUG_INT_EN (1 << 18) 883 # define CRT_HOTPLUG_INT_EN (1 << 9) 884 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 885 886 #define PORT_HOTPLUG_STAT 0x61114 887 # define CRT_HOTPLUG_INT_STATUS (1 << 11) 888 # define TV_HOTPLUG_INT_STATUS (1 << 10) 889 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 890 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 891 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 892 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 893 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 894 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 895 896 #define SDVOB 0x61140 897 #define SDVOC 0x61160 898 #define SDVO_ENABLE (1 << 31) 899 #define SDVO_PIPE_B_SELECT (1 << 30) 900 #define SDVO_STALL_SELECT (1 << 29) 901 #define SDVO_INTERRUPT_ENABLE (1 << 26) 902 /** 903 * 915G/GM SDVO pixel multiplier. 904 * 905 * Programmed value is multiplier - 1, up to 5x. 906 * 907 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 908 */ 909 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 910 #define SDVO_PORT_MULTIPLY_SHIFT 23 911 #define SDVO_PHASE_SELECT_MASK (15 << 19) 912 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 913 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 914 #define SDVOC_GANG_MODE (1 << 16) 915 #define SDVO_BORDER_ENABLE (1 << 7) 916 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 917 #define SDVO_DETECTED (1 << 2) 918 /* Bits to be preserved when writing */ 919 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) 920 #define SDVOC_PRESERVE_MASK (1 << 17) 921 922 /** @defgroup LVDS 923 * @{ 924 */ 925 /** 926 * This register controls the LVDS output enable, pipe selection, and data 927 * format selection. 928 * 929 * All of the clock/data pairs are force powered down by power sequencing. 930 */ 931 #define LVDS 0x61180 932 /** 933 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 934 * the DPLL semantics change when the LVDS is assigned to that pipe. 935 */ 936 # define LVDS_PORT_EN (1 << 31) 937 /** Selects pipe B for LVDS data. Must be set on pre-965. */ 938 # define LVDS_PIPEB_SELECT (1 << 30) 939 940 /** 941 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 942 * pixel. 943 */ 944 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 945 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 946 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 947 /** 948 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 949 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 950 * on. 951 */ 952 # define LVDS_A3_POWER_MASK (3 << 6) 953 # define LVDS_A3_POWER_DOWN (0 << 6) 954 # define LVDS_A3_POWER_UP (3 << 6) 955 /** 956 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 957 * is set. 958 */ 959 # define LVDS_CLKB_POWER_MASK (3 << 4) 960 # define LVDS_CLKB_POWER_DOWN (0 << 4) 961 # define LVDS_CLKB_POWER_UP (3 << 4) 962 963 /** 964 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 965 * setting for whether we are in dual-channel mode. The B3 pair will 966 * additionally only be powered up when LVDS_A3_POWER_UP is set. 967 */ 968 # define LVDS_B0B3_POWER_MASK (3 << 2) 969 # define LVDS_B0B3_POWER_DOWN (0 << 2) 970 # define LVDS_B0B3_POWER_UP (3 << 2) 971 972 #define PIPEACONF 0x70008 973 #define PIPEACONF_ENABLE (1<<31) 974 #define PIPEACONF_DISABLE 0 975 #define PIPEACONF_DOUBLE_WIDE (1<<30) 976 #define I965_PIPECONF_ACTIVE (1<<30) 977 #define PIPEACONF_SINGLE_WIDE 0 978 #define PIPEACONF_PIPE_UNLOCKED 0 979 #define PIPEACONF_PIPE_LOCKED (1<<25) 980 #define PIPEACONF_PALETTE 0 981 #define PIPEACONF_GAMMA (1<<24) 982 #define PIPECONF_FORCE_BORDER (1<<25) 983 #define PIPECONF_PROGRESSIVE (0 << 21) 984 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 985 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 986 987 #define DSPARB 0x70030 988 #define DSPARB_CSTART_MASK (0x7f << 7) 989 #define DSPARB_CSTART_SHIFT 7 990 #define DSPARB_BSTART_MASK (0x7f) 991 #define DSPARB_BSTART_SHIFT 0 992 993 #define PIPEBCONF 0x71008 994 #define PIPEBCONF_ENABLE (1<<31) 995 #define PIPEBCONF_DISABLE 0 996 #define PIPEBCONF_DOUBLE_WIDE (1<<30) 997 #define PIPEBCONF_DISABLE 0 998 #define PIPEBCONF_GAMMA (1<<24) 999 #define PIPEBCONF_PALETTE 0 1000 1001 #define PIPEBGCMAXRED 0x71010 1002 #define PIPEBGCMAXGREEN 0x71014 1003 #define PIPEBGCMAXBLUE 0x71018 1004 #define PIPEBSTAT 0x71024 1005 #define PIPEBFRAMEHIGH 0x71040 1006 #define PIPEBFRAMEPIXEL 0x71044 1007 1008 #define DSPACNTR 0x70180 1009 #define DSPBCNTR 0x71180 1010 #define DISPLAY_PLANE_ENABLE (1<<31) 1011 #define DISPLAY_PLANE_DISABLE 0 1012 #define DISPPLANE_GAMMA_ENABLE (1<<30) 1013 #define DISPPLANE_GAMMA_DISABLE 0 1014 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1015 #define DISPPLANE_8BPP (0x2<<26) 1016 #define DISPPLANE_15_16BPP (0x4<<26) 1017 #define DISPPLANE_16BPP (0x5<<26) 1018 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1019 #define DISPPLANE_32BPP (0x7<<26) 1020 #define DISPPLANE_STEREO_ENABLE (1<<25) 1021 #define DISPPLANE_STEREO_DISABLE 0 1022 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 1023 #define DISPPLANE_SEL_PIPE_A 0 1024 #define DISPPLANE_SEL_PIPE_B (1<<24) 1025 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1026 #define DISPPLANE_SRC_KEY_DISABLE 0 1027 #define DISPPLANE_LINE_DOUBLE (1<<20) 1028 #define DISPPLANE_NO_LINE_DOUBLE 0 1029 #define DISPPLANE_STEREO_POLARITY_FIRST 0 1030 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1031 /* plane B only */ 1032 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1033 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 1034 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 1035 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1036 1037 #define DSPABASE 0x70184 1038 #define DSPASTRIDE 0x70188 1039 1040 #define DSPBBASE 0x71184 1041 #define DSPBADDR DSPBBASE 1042 #define DSPBSTRIDE 0x71188 1043 1044 #define DSPAKEYVAL 0x70194 1045 #define DSPAKEYMASK 0x70198 1046 1047 #define DSPAPOS 0x7018C /* reserved */ 1048 #define DSPASIZE 0x70190 1049 #define DSPBPOS 0x7118C 1050 #define DSPBSIZE 0x71190 1051 1052 #define DSPASURF 0x7019C 1053 #define DSPATILEOFF 0x701A4 1054 1055 #define DSPBSURF 0x7119C 1056 #define DSPBTILEOFF 0x711A4 1057 1058 #define VGACNTRL 0x71400 1059 # define VGA_DISP_DISABLE (1 << 31) 1060 # define VGA_2X_MODE (1 << 30) 1061 # define VGA_PIPE_B_SELECT (1 << 29) 1062 1063 /* 1064 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 1065 * of video memory available to the BIOS in SWF1. 1066 */ 1067 1068 #define SWF0 0x71410 1069 1070 /* 1071 * 855 scratch registers. 1072 */ 1073 #define SWF10 0x70410 1074 1075 #define SWF30 0x72414 1076 1077 /* 1078 * Overlay registers. These are overlay registers accessed via MMIO. 1079 * Those loaded via the overlay register page are defined in i830_video.c. 1080 */ 1081 #define OVADD 0x30000 1082 1083 #define DOVSTA 0x30008 1084 #define OC_BUF (0x3<<20) 1085 1086 #define OGAMC5 0x30010 1087 #define OGAMC4 0x30014 1088 #define OGAMC3 0x30018 1089 #define OGAMC2 0x3001c 1090 #define OGAMC1 0x30020 1091 #define OGAMC0 0x30024 1092 /* 1093 * Palette registers 1094 */ 1095 #define PALETTE_A 0x0a000 1096 #define PALETTE_B 0x0a800 1097 1098 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1099 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1100 #define IS_I85X(dev) ((dev)->pci_device == 0x3582) 1101 #define IS_I855(dev) ((dev)->pci_device == 0x3582) 1102 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1103 1104 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 1105 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1106 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1107 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 1108 (dev)->pci_device == 0x27AE) 1109 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1110 (dev)->pci_device == 0x2982 || \ 1111 (dev)->pci_device == 0x2992 || \ 1112 (dev)->pci_device == 0x29A2 || \ 1113 (dev)->pci_device == 0x2A02 || \ 1114 (dev)->pci_device == 0x2A12 || \ 1115 (dev)->pci_device == 0x2A42 || \ 1116 (dev)->pci_device == 0x2E02 || \ 1117 (dev)->pci_device == 0x2E12 || \ 1118 (dev)->pci_device == 0x2E22) 1119 1120 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1121 1122 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) 1123 1124 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 1125 (dev)->pci_device == 0x2E12 || \ 1126 (dev)->pci_device == 0x2E22) 1127 1128 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 1129 (dev)->pci_device == 0x29B2 || \ 1130 (dev)->pci_device == 0x29D2) 1131 1132 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1133 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1134 1135 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1136 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) 1137 1138 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev)) 1139 1140 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1141 1142 #endif 1143