1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pm_qos.h> 36 37 #include <drm/ttm/ttm_device.h> 38 39 #include "display/intel_display.h" 40 #include "display/intel_display_core.h" 41 42 #include "gem/i915_gem_context_types.h" 43 #include "gem/i915_gem_shrinker.h" 44 #include "gem/i915_gem_stolen.h" 45 46 #include "gt/intel_engine.h" 47 #include "gt/intel_gt_types.h" 48 #include "gt/intel_region_lmem.h" 49 #include "gt/intel_workarounds.h" 50 #include "gt/uc/intel_uc.h" 51 52 #include "soc/intel_pch.h" 53 54 #include "i915_drm_client.h" 55 #include "i915_gem.h" 56 #include "i915_gpu_error.h" 57 #include "i915_params.h" 58 #include "i915_perf_types.h" 59 #include "i915_scheduler.h" 60 #include "i915_utils.h" 61 #include "intel_device_info.h" 62 #include "intel_memory_region.h" 63 #include "intel_runtime_pm.h" 64 #include "intel_step.h" 65 #include "intel_uncore.h" 66 67 struct drm_i915_clock_gating_funcs; 68 struct drm_i915_gem_object; 69 struct drm_i915_private; 70 struct intel_connector; 71 struct intel_dp; 72 struct intel_encoder; 73 struct intel_limit; 74 struct intel_overlay_error_state; 75 struct vlv_s0ix_state; 76 struct intel_pxp; 77 78 #define I915_GEM_GPU_DOMAINS \ 79 (I915_GEM_DOMAIN_RENDER | \ 80 I915_GEM_DOMAIN_SAMPLER | \ 81 I915_GEM_DOMAIN_COMMAND | \ 82 I915_GEM_DOMAIN_INSTRUCTION | \ 83 I915_GEM_DOMAIN_VERTEX) 84 85 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 86 87 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 88 89 struct i915_suspend_saved_registers { 90 u32 saveDSPARB; 91 u32 saveSWF0[16]; 92 u32 saveSWF1[16]; 93 u32 saveSWF3[3]; 94 u16 saveGCDGMBUS; 95 }; 96 97 #define MAX_L3_SLICES 2 98 struct intel_l3_parity { 99 u32 *remap_info[MAX_L3_SLICES]; 100 struct work_struct error_work; 101 int which_slice; 102 }; 103 104 struct i915_gem_mm { 105 /* 106 * Shortcut for the stolen region. This points to either 107 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 108 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 109 * support stolen. 110 */ 111 struct intel_memory_region *stolen_region; 112 /** Memory allocator for GTT stolen memory */ 113 struct drm_mm stolen; 114 /** Protects the usage of the GTT stolen memory allocator. This is 115 * always the inner lock when overlapping with struct_mutex. */ 116 struct mutex stolen_lock; 117 118 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 119 spinlock_t obj_lock; 120 121 /** 122 * List of objects which are purgeable. 123 */ 124 struct list_head purge_list; 125 126 /** 127 * List of objects which have allocated pages and are shrinkable. 128 */ 129 struct list_head shrink_list; 130 131 /** 132 * List of objects which are pending destruction. 133 */ 134 struct llist_head free_list; 135 struct work_struct free_work; 136 /** 137 * Count of objects pending destructions. Used to skip needlessly 138 * waiting on an RCU barrier if no objects are waiting to be freed. 139 */ 140 atomic_t free_count; 141 142 /** 143 * tmpfs instance used for shmem backed objects 144 */ 145 struct vfsmount *gemfs; 146 147 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 148 149 struct notifier_block oom_notifier; 150 struct notifier_block vmap_notifier; 151 struct shrinker shrinker; 152 153 #ifdef CONFIG_MMU_NOTIFIER 154 /** 155 * notifier_lock for mmu notifiers, memory may not be allocated 156 * while holding this lock. 157 */ 158 rwlock_t notifier_lock; 159 #endif 160 161 /* shrinker accounting, also useful for userland debugging */ 162 u64 shrink_memory; 163 u32 shrink_count; 164 }; 165 166 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 167 168 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 169 u64 context); 170 171 static inline unsigned long 172 i915_fence_timeout(const struct drm_i915_private *i915) 173 { 174 return i915_fence_context_timeout(i915, U64_MAX); 175 } 176 177 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 178 179 struct i915_virtual_gpu { 180 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 181 bool active; 182 u32 caps; 183 u32 *initial_mmio; 184 u8 *initial_cfg_space; 185 struct list_head entry; 186 }; 187 188 struct i915_selftest_stash { 189 atomic_t counter; 190 struct ida mock_region_instances; 191 }; 192 193 struct drm_i915_private { 194 struct drm_device drm; 195 196 struct intel_display display; 197 198 /* FIXME: Device release actions should all be moved to drmm_ */ 199 bool do_release; 200 201 /* i915 device parameters */ 202 struct i915_params params; 203 204 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 205 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 206 struct intel_driver_caps caps; 207 208 /** 209 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 210 * end of stolen which we can optionally use to create GEM objects 211 * backed by stolen memory. Note that stolen_usable_size tells us 212 * exactly how much of this we are actually allowed to use, given that 213 * some portion of it is in fact reserved for use by hardware functions. 214 */ 215 struct resource dsm; 216 /** 217 * Reseved portion of Data Stolen Memory 218 */ 219 struct resource dsm_reserved; 220 221 /* 222 * Stolen memory is segmented in hardware with different portions 223 * offlimits to certain functions. 224 * 225 * The drm_mm is initialised to the total accessible range, as found 226 * from the PCI config. On Broadwell+, this is further restricted to 227 * avoid the first page! The upper end of stolen memory is reserved for 228 * hardware functions and similarly removed from the accessible range. 229 */ 230 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 231 232 struct intel_uncore uncore; 233 struct intel_uncore_mmio_debug mmio_debug; 234 235 struct i915_virtual_gpu vgpu; 236 237 struct intel_gvt *gvt; 238 239 struct pci_dev *bridge_dev; 240 241 struct rb_root uabi_engines; 242 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 243 244 struct resource mch_res; 245 246 /* protects the irq masks */ 247 spinlock_t irq_lock; 248 249 bool display_irqs_enabled; 250 251 /* Sideband mailbox protection */ 252 struct mutex sb_lock; 253 struct pm_qos_request sb_qos; 254 255 /** Cached value of IMR to avoid reads in updating the bitfield */ 256 union { 257 u32 irq_mask; 258 u32 de_irq_mask[I915_MAX_PIPES]; 259 }; 260 u32 pipestat_irq_mask[I915_MAX_PIPES]; 261 262 bool preserve_bios_swizzle; 263 264 unsigned int fsb_freq, mem_freq, is_ddr3; 265 unsigned int skl_preferred_vco_freq; 266 267 unsigned int max_dotclk_freq; 268 unsigned int hpll_freq; 269 unsigned int czclk_freq; 270 271 /** 272 * wq - Driver workqueue for GEM. 273 * 274 * NOTE: Work items scheduled here are not allowed to grab any modeset 275 * locks, for otherwise the flushing done in the pageflip code will 276 * result in deadlocks. 277 */ 278 struct workqueue_struct *wq; 279 280 /* pm private clock gating functions */ 281 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 282 283 /* PCH chipset type */ 284 enum intel_pch pch_type; 285 unsigned short pch_id; 286 287 unsigned long gem_quirks; 288 289 struct i915_gem_mm mm; 290 291 bool mchbar_need_disable; 292 293 struct intel_l3_parity l3_parity; 294 295 /* 296 * edram size in MB. 297 * Cannot be determined by PCIID. You must always read a register. 298 */ 299 u32 edram_size_mb; 300 301 struct i915_gpu_error gpu_error; 302 303 /* 304 * Shadows for CHV DPLL_MD regs to keep the state 305 * checker somewhat working in the presence hardware 306 * crappiness (can't read out DPLL_MD for pipes B & C). 307 */ 308 u32 chv_dpll_md[I915_MAX_PIPES]; 309 u32 bxt_phy_grc; 310 311 u32 suspend_count; 312 struct i915_suspend_saved_registers regfile; 313 struct vlv_s0ix_state *vlv_s0ix_state; 314 315 struct dram_info { 316 bool wm_lv_0_adjust_needed; 317 u8 num_channels; 318 bool symmetric_memory; 319 enum intel_dram_type { 320 INTEL_DRAM_UNKNOWN, 321 INTEL_DRAM_DDR3, 322 INTEL_DRAM_DDR4, 323 INTEL_DRAM_LPDDR3, 324 INTEL_DRAM_LPDDR4, 325 INTEL_DRAM_DDR5, 326 INTEL_DRAM_LPDDR5, 327 } type; 328 u8 num_qgv_points; 329 u8 num_psf_gv_points; 330 } dram_info; 331 332 struct intel_runtime_pm runtime_pm; 333 334 struct i915_perf perf; 335 336 struct i915_hwmon *hwmon; 337 338 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 339 struct intel_gt gt0; 340 341 /* 342 * i915->gt[0] == &i915->gt0 343 */ 344 #define I915_MAX_GT 4 345 struct intel_gt *gt[I915_MAX_GT]; 346 347 struct kobject *sysfs_gt; 348 349 /* Quick lookup of media GT (current platforms only have one) */ 350 struct intel_gt *media_gt; 351 352 struct { 353 struct i915_gem_contexts { 354 spinlock_t lock; /* locks list */ 355 struct list_head list; 356 } contexts; 357 358 /* 359 * We replace the local file with a global mappings as the 360 * backing storage for the mmap is on the device and not 361 * on the struct file, and we do not want to prolong the 362 * lifetime of the local fd. To minimise the number of 363 * anonymous inodes we create, we use a global singleton to 364 * share the global mapping. 365 */ 366 struct file *mmap_singleton; 367 } gem; 368 369 struct intel_pxp *pxp; 370 371 u8 pch_ssc_use; 372 373 /* For i915gm/i945gm vblank irq workaround */ 374 u8 vblank_enabled; 375 376 bool irq_enabled; 377 378 /* 379 * DG2: Mask of PHYs that were not calibrated by the firmware 380 * and should not be used. 381 */ 382 u8 snps_phy_failed_calibration; 383 384 struct i915_pmu pmu; 385 386 struct i915_drm_clients clients; 387 388 /* The TTM device structure. */ 389 struct ttm_device bdev; 390 391 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 392 393 /* 394 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 395 * will be rejected. Instead look for a better place. 396 */ 397 }; 398 399 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 400 { 401 return container_of(dev, struct drm_i915_private, drm); 402 } 403 404 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 405 { 406 return dev_get_drvdata(kdev); 407 } 408 409 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 410 { 411 return pci_get_drvdata(pdev); 412 } 413 414 static inline struct intel_gt *to_gt(struct drm_i915_private *i915) 415 { 416 return &i915->gt0; 417 } 418 419 /* Simple iterator over all initialised engines */ 420 #define for_each_engine(engine__, dev_priv__, id__) \ 421 for ((id__) = 0; \ 422 (id__) < I915_NUM_ENGINES; \ 423 (id__)++) \ 424 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 425 426 /* Iterator over subset of engines selected by mask */ 427 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 428 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 429 (tmp__) ? \ 430 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 431 0;) 432 433 #define rb_to_uabi_engine(rb) \ 434 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 435 436 #define for_each_uabi_engine(engine__, i915__) \ 437 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 438 (engine__); \ 439 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 440 441 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 442 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 443 (engine__) && (engine__)->uabi_class == (class__); \ 444 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 445 446 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 447 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 448 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 449 450 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 451 452 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 453 454 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 455 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 456 RUNTIME_INFO(i915)->graphics.ip.rel) 457 #define IS_GRAPHICS_VER(i915, from, until) \ 458 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 459 460 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 461 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 462 RUNTIME_INFO(i915)->media.ip.rel) 463 #define IS_MEDIA_VER(i915, from, until) \ 464 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 465 466 #define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver) 467 #define IS_DISPLAY_VER(i915, from, until) \ 468 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 469 470 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) 471 472 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 473 #define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc) 474 475 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 476 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 477 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 478 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 479 480 #define IS_DISPLAY_STEP(__i915, since, until) \ 481 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 482 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 483 484 #define IS_GRAPHICS_STEP(__i915, since, until) \ 485 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 486 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 487 488 #define IS_MEDIA_STEP(__i915, since, until) \ 489 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 490 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 491 492 #define IS_BASEDIE_STEP(__i915, since, until) \ 493 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 494 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 495 496 static __always_inline unsigned int 497 __platform_mask_index(const struct intel_runtime_info *info, 498 enum intel_platform p) 499 { 500 const unsigned int pbits = 501 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 502 503 /* Expand the platform_mask array if this fails. */ 504 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 505 pbits * ARRAY_SIZE(info->platform_mask)); 506 507 return p / pbits; 508 } 509 510 static __always_inline unsigned int 511 __platform_mask_bit(const struct intel_runtime_info *info, 512 enum intel_platform p) 513 { 514 const unsigned int pbits = 515 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 516 517 return p % pbits + INTEL_SUBPLATFORM_BITS; 518 } 519 520 static inline u32 521 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 522 { 523 const unsigned int pi = __platform_mask_index(info, p); 524 525 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 526 } 527 528 static __always_inline bool 529 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 530 { 531 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 532 const unsigned int pi = __platform_mask_index(info, p); 533 const unsigned int pb = __platform_mask_bit(info, p); 534 535 BUILD_BUG_ON(!__builtin_constant_p(p)); 536 537 return info->platform_mask[pi] & BIT(pb); 538 } 539 540 static __always_inline bool 541 IS_SUBPLATFORM(const struct drm_i915_private *i915, 542 enum intel_platform p, unsigned int s) 543 { 544 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 545 const unsigned int pi = __platform_mask_index(info, p); 546 const unsigned int pb = __platform_mask_bit(info, p); 547 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 548 const u32 mask = info->platform_mask[pi]; 549 550 BUILD_BUG_ON(!__builtin_constant_p(p)); 551 BUILD_BUG_ON(!__builtin_constant_p(s)); 552 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 553 554 /* Shift and test on the MSB position so sign flag can be used. */ 555 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 556 } 557 558 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 559 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 560 561 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 562 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 563 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 564 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 565 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 566 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 567 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 568 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 569 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 570 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 571 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 572 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 573 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 574 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 575 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 576 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 577 #define IS_IRONLAKE_M(dev_priv) \ 578 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 579 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) 580 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 581 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 582 INTEL_INFO(dev_priv)->gt == 1) 583 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 584 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 585 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 586 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 587 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 588 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 589 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 590 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 591 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 592 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 593 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 594 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 595 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 596 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 597 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 598 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 599 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) 600 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) 601 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) 602 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) 603 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) 604 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE) 605 606 #define IS_METEORLAKE_M(dev_priv) \ 607 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) 608 #define IS_METEORLAKE_P(dev_priv) \ 609 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) 610 #define IS_DG2_G10(dev_priv) \ 611 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) 612 #define IS_DG2_G11(dev_priv) \ 613 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) 614 #define IS_DG2_G12(dev_priv) \ 615 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) 616 #define IS_ADLS_RPLS(dev_priv) \ 617 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 618 #define IS_ADLP_N(dev_priv) \ 619 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 620 #define IS_ADLP_RPLP(dev_priv) \ 621 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 622 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 623 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 624 #define IS_BDW_ULT(dev_priv) \ 625 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 626 #define IS_BDW_ULX(dev_priv) \ 627 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 628 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 629 INTEL_INFO(dev_priv)->gt == 3) 630 #define IS_HSW_ULT(dev_priv) \ 631 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 632 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 633 INTEL_INFO(dev_priv)->gt == 3) 634 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 635 INTEL_INFO(dev_priv)->gt == 1) 636 /* ULX machines are also considered ULT. */ 637 #define IS_HSW_ULX(dev_priv) \ 638 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 639 #define IS_SKL_ULT(dev_priv) \ 640 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 641 #define IS_SKL_ULX(dev_priv) \ 642 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 643 #define IS_KBL_ULT(dev_priv) \ 644 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 645 #define IS_KBL_ULX(dev_priv) \ 646 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 647 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 648 INTEL_INFO(dev_priv)->gt == 2) 649 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 650 INTEL_INFO(dev_priv)->gt == 3) 651 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 652 INTEL_INFO(dev_priv)->gt == 4) 653 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 654 INTEL_INFO(dev_priv)->gt == 2) 655 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 656 INTEL_INFO(dev_priv)->gt == 3) 657 #define IS_CFL_ULT(dev_priv) \ 658 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 659 #define IS_CFL_ULX(dev_priv) \ 660 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 661 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 662 INTEL_INFO(dev_priv)->gt == 2) 663 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 664 INTEL_INFO(dev_priv)->gt == 3) 665 666 #define IS_CML_ULT(dev_priv) \ 667 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 668 #define IS_CML_ULX(dev_priv) \ 669 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 670 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 671 INTEL_INFO(dev_priv)->gt == 2) 672 673 #define IS_ICL_WITH_PORT_F(dev_priv) \ 674 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 675 676 #define IS_TGL_UY(dev_priv) \ 677 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 678 679 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) 680 681 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \ 682 (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until)) 683 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ 684 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) 685 686 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \ 687 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) 688 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ 689 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until)) 690 691 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ 692 (IS_TIGERLAKE(__i915) && \ 693 IS_DISPLAY_STEP(__i915, since, until)) 694 695 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ 696 (IS_TGL_UY(__i915) && \ 697 IS_GRAPHICS_STEP(__i915, since, until)) 698 699 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ 700 (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \ 701 IS_GRAPHICS_STEP(__i915, since, until)) 702 703 #define IS_RKL_DISPLAY_STEP(p, since, until) \ 704 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) 705 706 #define IS_DG1_GRAPHICS_STEP(p, since, until) \ 707 (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until)) 708 #define IS_DG1_DISPLAY_STEP(p, since, until) \ 709 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until)) 710 711 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ 712 (IS_ALDERLAKE_S(__i915) && \ 713 IS_DISPLAY_STEP(__i915, since, until)) 714 715 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \ 716 (IS_ALDERLAKE_S(__i915) && \ 717 IS_GRAPHICS_STEP(__i915, since, until)) 718 719 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ 720 (IS_ALDERLAKE_P(__i915) && \ 721 IS_DISPLAY_STEP(__i915, since, until)) 722 723 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ 724 (IS_ALDERLAKE_P(__i915) && \ 725 IS_GRAPHICS_STEP(__i915, since, until)) 726 727 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ 728 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) 729 730 #define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \ 731 (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \ 732 IS_GRAPHICS_STEP(__i915, since, until)) 733 734 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \ 735 (IS_METEORLAKE(__i915) && \ 736 IS_DISPLAY_STEP(__i915, since, until)) 737 738 /* 739 * DG2 hardware steppings are a bit unusual. The hardware design was forked to 740 * create three variants (G10, G11, and G12) which each have distinct 741 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT 742 * stepping back to "A0" for their first iterations, even though they're more 743 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of 744 * functionality and workarounds. However the display stepping does not reset 745 * in the same manner --- a specific stepping like "B0" has a consistent 746 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. 747 * 748 * TLDR: All GT workarounds and stepping-specific logic must be applied in 749 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds 750 * and stepping-specific logic will be applied with a general DG2-wide stepping 751 * number. 752 */ 753 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \ 754 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ 755 IS_GRAPHICS_STEP(__i915, since, until)) 756 757 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \ 758 (IS_DG2(__i915) && \ 759 IS_DISPLAY_STEP(__i915, since, until)) 760 761 #define IS_PVC_BD_STEP(__i915, since, until) \ 762 (IS_PONTEVECCHIO(__i915) && \ 763 IS_BASEDIE_STEP(__i915, since, until)) 764 765 #define IS_PVC_CT_STEP(__i915, since, until) \ 766 (IS_PONTEVECCHIO(__i915) && \ 767 IS_GRAPHICS_STEP(__i915, since, until)) 768 769 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 770 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) 771 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) 772 773 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 774 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 775 776 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ 777 unsigned int first__ = (first); \ 778 unsigned int count__ = (count); \ 779 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ 780 }) 781 782 #define ENGINE_INSTANCES_MASK(gt, first, count) \ 783 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) 784 785 #define RCS_MASK(gt) \ 786 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 787 #define BCS_MASK(gt) \ 788 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 789 #define VDBOX_MASK(gt) \ 790 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 791 #define VEBOX_MASK(gt) \ 792 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 793 #define CCS_MASK(gt) \ 794 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 795 796 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode) 797 798 /* 799 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 800 * All later gens can run the final buffer from the ppgtt 801 */ 802 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) 803 804 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 805 #define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) 806 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 807 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 808 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) 809 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 810 811 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 812 813 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 814 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 815 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 816 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 817 818 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 819 820 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type) 821 #define HAS_PPGTT(dev_priv) \ 822 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 823 #define HAS_FULL_PPGTT(dev_priv) \ 824 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 825 826 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 827 GEM_BUG_ON((sizes) == 0); \ 828 ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \ 829 }) 830 831 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 832 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 833 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 834 835 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 836 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 837 838 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 839 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9) 840 841 /* WaRsDisableCoarsePowerGating:skl,cnl */ 842 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 843 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) 844 845 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4) 846 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \ 847 IS_GEMINILAKE(dev_priv) || \ 848 IS_KABYLAKE(dev_priv)) 849 850 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 851 * rows, which changed the alignment requirements and fence programming. 852 */ 853 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ 854 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) 855 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 856 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 857 858 #define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2) 859 #define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0) 860 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7) 861 862 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 863 864 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 865 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 866 867 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 868 869 #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) 870 #define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash) 871 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 872 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) 873 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 874 #define HAS_PSR_HW_TRACKING(dev_priv) \ 875 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 876 #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) 877 #define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 878 879 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 880 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 881 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 882 883 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 884 885 #define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc) 886 887 #define HAS_HECI_PXP(dev_priv) \ 888 (INTEL_INFO(dev_priv)->has_heci_pxp) 889 890 #define HAS_HECI_GSCFI(dev_priv) \ 891 (INTEL_INFO(dev_priv)->has_heci_gscfi) 892 893 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv)) 894 895 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 896 897 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 898 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 899 900 #define HAS_OA_BPC_REPORTING(dev_priv) \ 901 (INTEL_INFO(dev_priv)->has_oa_bpc_reporting) 902 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \ 903 (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits) 904 905 /* 906 * Set this flag, when platform requires 64K GTT page sizes or larger for 907 * device local memory access. 908 */ 909 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages) 910 911 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 912 913 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i)) 914 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 915 916 #define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list) 917 918 /* 919 * Platform has the dedicated compression control state for each lmem surfaces 920 * stored in lmem to support the 3D and media compression formats. 921 */ 922 #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs) 923 924 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 925 926 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu) 927 928 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 929 930 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 931 932 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 933 934 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10)) 935 936 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 937 938 /* DPF == dynamic parity feature */ 939 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 940 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 941 2 : HAS_L3_DPF(dev_priv)) 942 943 #define GT_FREQUENCY_MULTIPLIER 50 944 #define GEN9_FREQ_SCALER 3 945 946 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask)) 947 948 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0) 949 950 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 951 952 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 953 954 /* Only valid when HAS_DISPLAY() is true */ 955 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 956 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \ 957 !(dev_priv)->params.disable_display && \ 958 !intel_opregion_headless_sku(dev_priv)) 959 960 #define HAS_GUC_DEPRIVILEGE(dev_priv) \ 961 (INTEL_INFO(dev_priv)->has_guc_deprivilege) 962 963 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ 964 IS_ALDERLAKE_S(dev_priv)) 965 966 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 967 968 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 969 970 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 971 972 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 973 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 974 975 /* intel_device_info.c */ 976 static inline struct intel_device_info * 977 mkwrite_device_info(struct drm_i915_private *dev_priv) 978 { 979 return (struct intel_device_info *)INTEL_INFO(dev_priv); 980 } 981 982 #endif 983