1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/dma-resv.h> 47 #include <linux/shmem_fs.h> 48 #include <linux/stackdepot.h> 49 #include <linux/xarray.h> 50 51 #include <drm/intel-gtt.h> 52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 53 #include <drm/drm_gem.h> 54 #include <drm/drm_auth.h> 55 #include <drm/drm_cache.h> 56 #include <drm/drm_util.h> 57 #include <drm/drm_dsc.h> 58 #include <drm/drm_atomic.h> 59 #include <drm/drm_connector.h> 60 #include <drm/i915_mei_hdcp_interface.h> 61 62 #include "i915_params.h" 63 #include "i915_reg.h" 64 #include "i915_utils.h" 65 66 #include "display/intel_bios.h" 67 #include "display/intel_display.h" 68 #include "display/intel_display_power.h" 69 #include "display/intel_dpll_mgr.h" 70 #include "display/intel_dsb.h" 71 #include "display/intel_frontbuffer.h" 72 #include "display/intel_global_state.h" 73 #include "display/intel_gmbus.h" 74 #include "display/intel_opregion.h" 75 76 #include "gem/i915_gem_context_types.h" 77 #include "gem/i915_gem_shrinker.h" 78 #include "gem/i915_gem_stolen.h" 79 80 #include "gt/intel_lrc.h" 81 #include "gt/intel_engine.h" 82 #include "gt/intel_gt_types.h" 83 #include "gt/intel_workarounds.h" 84 #include "gt/uc/intel_uc.h" 85 86 #include "intel_device_info.h" 87 #include "intel_pch.h" 88 #include "intel_runtime_pm.h" 89 #include "intel_memory_region.h" 90 #include "intel_uncore.h" 91 #include "intel_wakeref.h" 92 #include "intel_wopcm.h" 93 94 #include "i915_gem.h" 95 #include "i915_gem_fence_reg.h" 96 #include "i915_gem_gtt.h" 97 #include "i915_gpu_error.h" 98 #include "i915_perf_types.h" 99 #include "i915_request.h" 100 #include "i915_scheduler.h" 101 #include "gt/intel_timeline.h" 102 #include "i915_vma.h" 103 #include "i915_irq.h" 104 105 #include "intel_region_lmem.h" 106 107 /* General customization: 108 */ 109 110 #define DRIVER_NAME "i915" 111 #define DRIVER_DESC "Intel Graphics" 112 #define DRIVER_DATE "20200313" 113 #define DRIVER_TIMESTAMP 1584144591 114 115 struct drm_i915_gem_object; 116 117 /* 118 * The code assumes that the hpd_pins below have consecutive values and 119 * starting with HPD_PORT_A, the HPD pin associated with any port can be 120 * retrieved by adding the corresponding port (or phy) enum value to 121 * HPD_PORT_A in most cases. For example: 122 * HPD_PORT_C = HPD_PORT_A + PHY_C - PHY_A 123 */ 124 enum hpd_pin { 125 HPD_NONE = 0, 126 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 127 HPD_CRT, 128 HPD_SDVO_B, 129 HPD_SDVO_C, 130 HPD_PORT_A, 131 HPD_PORT_B, 132 HPD_PORT_C, 133 HPD_PORT_D, 134 HPD_PORT_E, 135 HPD_PORT_F, 136 HPD_PORT_G, 137 HPD_PORT_H, 138 HPD_PORT_I, 139 140 HPD_NUM_PINS 141 }; 142 143 #define for_each_hpd_pin(__pin) \ 144 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 145 146 /* Threshold == 5 for long IRQs, 50 for short */ 147 #define HPD_STORM_DEFAULT_THRESHOLD 50 148 149 struct i915_hotplug { 150 struct delayed_work hotplug_work; 151 152 struct { 153 unsigned long last_jiffies; 154 int count; 155 enum { 156 HPD_ENABLED = 0, 157 HPD_DISABLED = 1, 158 HPD_MARK_DISABLED = 2 159 } state; 160 } stats[HPD_NUM_PINS]; 161 u32 event_bits; 162 u32 retry_bits; 163 struct delayed_work reenable_work; 164 165 u32 long_port_mask; 166 u32 short_port_mask; 167 struct work_struct dig_port_work; 168 169 struct work_struct poll_init_work; 170 bool poll_enabled; 171 172 unsigned int hpd_storm_threshold; 173 /* Whether or not to count short HPD IRQs in HPD storms */ 174 u8 hpd_short_storm_enabled; 175 176 /* 177 * if we get a HPD irq from DP and a HPD irq from non-DP 178 * the non-DP HPD could block the workqueue on a mode config 179 * mutex getting, that userspace may have taken. However 180 * userspace is waiting on the DP workqueue to run which is 181 * blocked behind the non-DP one. 182 */ 183 struct workqueue_struct *dp_wq; 184 }; 185 186 #define I915_GEM_GPU_DOMAINS \ 187 (I915_GEM_DOMAIN_RENDER | \ 188 I915_GEM_DOMAIN_SAMPLER | \ 189 I915_GEM_DOMAIN_COMMAND | \ 190 I915_GEM_DOMAIN_INSTRUCTION | \ 191 I915_GEM_DOMAIN_VERTEX) 192 193 struct drm_i915_private; 194 struct i915_mm_struct; 195 struct i915_mmu_object; 196 197 struct drm_i915_file_private { 198 struct drm_i915_private *dev_priv; 199 200 union { 201 struct drm_file *file; 202 struct rcu_head rcu; 203 }; 204 205 struct { 206 spinlock_t lock; 207 struct list_head request_list; 208 } mm; 209 210 struct xarray context_xa; 211 struct xarray vm_xa; 212 213 unsigned int bsd_engine; 214 215 /* 216 * Every context ban increments per client ban score. Also 217 * hangs in short succession increments ban score. If ban threshold 218 * is reached, client is considered banned and submitting more work 219 * will fail. This is a stop gap measure to limit the badly behaving 220 * clients access to gpu. Note that unbannable contexts never increment 221 * the client ban score. 222 */ 223 #define I915_CLIENT_SCORE_HANG_FAST 1 224 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 225 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 226 #define I915_CLIENT_SCORE_BANNED 9 227 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 228 atomic_t ban_score; 229 unsigned long hang_timestamp; 230 }; 231 232 /* Interface history: 233 * 234 * 1.1: Original. 235 * 1.2: Add Power Management 236 * 1.3: Add vblank support 237 * 1.4: Fix cmdbuffer path, add heap destroy 238 * 1.5: Add vblank pipe configuration 239 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 240 * - Support vertical blank on secondary display pipe 241 */ 242 #define DRIVER_MAJOR 1 243 #define DRIVER_MINOR 6 244 #define DRIVER_PATCHLEVEL 0 245 246 struct intel_overlay; 247 struct intel_overlay_error_state; 248 249 struct sdvo_device_mapping { 250 u8 initialized; 251 u8 dvo_port; 252 u8 slave_addr; 253 u8 dvo_wiring; 254 u8 i2c_pin; 255 u8 ddc_pin; 256 }; 257 258 struct intel_connector; 259 struct intel_encoder; 260 struct intel_atomic_state; 261 struct intel_cdclk_config; 262 struct intel_cdclk_state; 263 struct intel_cdclk_vals; 264 struct intel_initial_plane_config; 265 struct intel_crtc; 266 struct intel_limit; 267 struct dpll; 268 269 struct drm_i915_display_funcs { 270 void (*get_cdclk)(struct drm_i915_private *dev_priv, 271 struct intel_cdclk_config *cdclk_config); 272 void (*set_cdclk)(struct drm_i915_private *dev_priv, 273 const struct intel_cdclk_config *cdclk_config, 274 enum pipe pipe); 275 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 276 enum i9xx_plane_id i9xx_plane); 277 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 278 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 279 void (*initial_watermarks)(struct intel_atomic_state *state, 280 struct intel_crtc *crtc); 281 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 282 struct intel_crtc *crtc); 283 void (*optimize_watermarks)(struct intel_atomic_state *state, 284 struct intel_crtc *crtc); 285 int (*compute_global_watermarks)(struct intel_atomic_state *state); 286 void (*update_wm)(struct intel_crtc *crtc); 287 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 288 u8 (*calc_voltage_level)(int cdclk); 289 /* Returns the active state of the crtc, and if the crtc is active, 290 * fills out the pipe-config with the hw state. */ 291 bool (*get_pipe_config)(struct intel_crtc *, 292 struct intel_crtc_state *); 293 void (*get_initial_plane_config)(struct intel_crtc *, 294 struct intel_initial_plane_config *); 295 int (*crtc_compute_clock)(struct intel_crtc *crtc, 296 struct intel_crtc_state *crtc_state); 297 void (*crtc_enable)(struct intel_atomic_state *state, 298 struct intel_crtc *crtc); 299 void (*crtc_disable)(struct intel_atomic_state *state, 300 struct intel_crtc *crtc); 301 void (*commit_modeset_enables)(struct intel_atomic_state *state); 302 void (*commit_modeset_disables)(struct intel_atomic_state *state); 303 void (*audio_codec_enable)(struct intel_encoder *encoder, 304 const struct intel_crtc_state *crtc_state, 305 const struct drm_connector_state *conn_state); 306 void (*audio_codec_disable)(struct intel_encoder *encoder, 307 const struct intel_crtc_state *old_crtc_state, 308 const struct drm_connector_state *old_conn_state); 309 void (*fdi_link_train)(struct intel_crtc *crtc, 310 const struct intel_crtc_state *crtc_state); 311 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 312 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 313 /* clock updates for mode set */ 314 /* cursor updates */ 315 /* render clock increase/decrease */ 316 /* display clock increase/decrease */ 317 /* pll clock increase/decrease */ 318 319 int (*color_check)(struct intel_crtc_state *crtc_state); 320 /* 321 * Program double buffered color management registers during 322 * vblank evasion. The registers should then latch during the 323 * next vblank start, alongside any other double buffered registers 324 * involved with the same commit. 325 */ 326 void (*color_commit)(const struct intel_crtc_state *crtc_state); 327 /* 328 * Load LUTs (and other single buffered color management 329 * registers). Will (hopefully) be called during the vblank 330 * following the latching of any double buffered registers 331 * involved with the same commit. 332 */ 333 void (*load_luts)(const struct intel_crtc_state *crtc_state); 334 void (*read_luts)(struct intel_crtc_state *crtc_state); 335 }; 336 337 struct intel_csr { 338 struct work_struct work; 339 const char *fw_path; 340 u32 required_version; 341 u32 max_fw_size; /* bytes */ 342 u32 *dmc_payload; 343 u32 dmc_fw_size; /* dwords */ 344 u32 version; 345 u32 mmio_count; 346 i915_reg_t mmioaddr[20]; 347 u32 mmiodata[20]; 348 u32 dc_state; 349 u32 target_dc_state; 350 u32 allowed_dc_mask; 351 intel_wakeref_t wakeref; 352 }; 353 354 enum i915_cache_level { 355 I915_CACHE_NONE = 0, 356 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 357 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 358 caches, eg sampler/render caches, and the 359 large Last-Level-Cache. LLC is coherent with 360 the CPU, but L3 is only visible to the GPU. */ 361 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 362 }; 363 364 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 365 366 struct intel_fbc { 367 /* This is always the inner lock when overlapping with struct_mutex and 368 * it's the outer lock when overlapping with stolen_lock. */ 369 struct mutex lock; 370 unsigned threshold; 371 unsigned int possible_framebuffer_bits; 372 unsigned int busy_bits; 373 struct intel_crtc *crtc; 374 375 struct drm_mm_node compressed_fb; 376 struct drm_mm_node *compressed_llb; 377 378 bool false_color; 379 380 bool active; 381 bool activated; 382 bool flip_pending; 383 384 bool underrun_detected; 385 struct work_struct underrun_work; 386 387 /* 388 * Due to the atomic rules we can't access some structures without the 389 * appropriate locking, so we cache information here in order to avoid 390 * these problems. 391 */ 392 struct intel_fbc_state_cache { 393 struct { 394 unsigned int mode_flags; 395 u32 hsw_bdw_pixel_rate; 396 } crtc; 397 398 struct { 399 unsigned int rotation; 400 int src_w; 401 int src_h; 402 bool visible; 403 /* 404 * Display surface base address adjustement for 405 * pageflips. Note that on gen4+ this only adjusts up 406 * to a tile, offsets within a tile are handled in 407 * the hw itself (with the TILEOFF register). 408 */ 409 int adjusted_x; 410 int adjusted_y; 411 412 int y; 413 414 u16 pixel_blend_mode; 415 } plane; 416 417 struct { 418 const struct drm_format_info *format; 419 unsigned int stride; 420 } fb; 421 u16 gen9_wa_cfb_stride; 422 s8 fence_id; 423 } state_cache; 424 425 /* 426 * This structure contains everything that's relevant to program the 427 * hardware registers. When we want to figure out if we need to disable 428 * and re-enable FBC for a new configuration we just check if there's 429 * something different in the struct. The genx_fbc_activate functions 430 * are supposed to read from it in order to program the registers. 431 */ 432 struct intel_fbc_reg_params { 433 struct { 434 enum pipe pipe; 435 enum i9xx_plane_id i9xx_plane; 436 unsigned int fence_y_offset; 437 } crtc; 438 439 struct { 440 const struct drm_format_info *format; 441 unsigned int stride; 442 } fb; 443 444 int cfb_size; 445 u16 gen9_wa_cfb_stride; 446 s8 fence_id; 447 bool plane_visible; 448 } params; 449 450 const char *no_fbc_reason; 451 }; 452 453 /* 454 * HIGH_RR is the highest eDP panel refresh rate read from EDID 455 * LOW_RR is the lowest eDP panel refresh rate found from EDID 456 * parsing for same resolution. 457 */ 458 enum drrs_refresh_rate_type { 459 DRRS_HIGH_RR, 460 DRRS_LOW_RR, 461 DRRS_MAX_RR, /* RR count */ 462 }; 463 464 enum drrs_support_type { 465 DRRS_NOT_SUPPORTED = 0, 466 STATIC_DRRS_SUPPORT = 1, 467 SEAMLESS_DRRS_SUPPORT = 2 468 }; 469 470 struct intel_dp; 471 struct i915_drrs { 472 struct mutex mutex; 473 struct delayed_work work; 474 struct intel_dp *dp; 475 unsigned busy_frontbuffer_bits; 476 enum drrs_refresh_rate_type refresh_rate_type; 477 enum drrs_support_type type; 478 }; 479 480 struct i915_psr { 481 struct mutex lock; 482 483 #define I915_PSR_DEBUG_MODE_MASK 0x0f 484 #define I915_PSR_DEBUG_DEFAULT 0x00 485 #define I915_PSR_DEBUG_DISABLE 0x01 486 #define I915_PSR_DEBUG_ENABLE 0x02 487 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 488 #define I915_PSR_DEBUG_IRQ 0x10 489 490 u32 debug; 491 bool sink_support; 492 bool enabled; 493 struct intel_dp *dp; 494 enum pipe pipe; 495 enum transcoder transcoder; 496 bool active; 497 struct work_struct work; 498 unsigned busy_frontbuffer_bits; 499 bool sink_psr2_support; 500 bool link_standby; 501 bool colorimetry_support; 502 bool psr2_enabled; 503 u8 sink_sync_latency; 504 ktime_t last_entry_attempt; 505 ktime_t last_exit; 506 bool sink_not_reliable; 507 bool irq_aux_error; 508 u16 su_x_granularity; 509 bool dc3co_enabled; 510 u32 dc3co_exit_delay; 511 struct delayed_work dc3co_work; 512 bool force_mode_changed; 513 }; 514 515 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 516 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 517 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 518 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 519 #define QUIRK_INCREASE_T12_DELAY (1<<6) 520 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 521 522 struct intel_fbdev; 523 struct intel_fbc_work; 524 525 struct intel_gmbus { 526 struct i2c_adapter adapter; 527 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 528 u32 force_bit; 529 u32 reg0; 530 i915_reg_t gpio_reg; 531 struct i2c_algo_bit_data bit_algo; 532 struct drm_i915_private *dev_priv; 533 }; 534 535 struct i915_suspend_saved_registers { 536 u32 saveDSPARB; 537 u32 saveFBC_CONTROL; 538 u32 saveCACHE_MODE_0; 539 u32 saveMI_ARB_STATE; 540 u32 saveSWF0[16]; 541 u32 saveSWF1[16]; 542 u32 saveSWF3[3]; 543 u64 saveFENCE[I915_MAX_NUM_FENCES]; 544 u32 savePCH_PORT_HOTPLUG; 545 u16 saveGCDGMBUS; 546 }; 547 548 struct vlv_s0ix_state; 549 550 #define MAX_L3_SLICES 2 551 struct intel_l3_parity { 552 u32 *remap_info[MAX_L3_SLICES]; 553 struct work_struct error_work; 554 int which_slice; 555 }; 556 557 struct i915_gem_mm { 558 /** Memory allocator for GTT stolen memory */ 559 struct drm_mm stolen; 560 /** Protects the usage of the GTT stolen memory allocator. This is 561 * always the inner lock when overlapping with struct_mutex. */ 562 struct mutex stolen_lock; 563 564 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 565 spinlock_t obj_lock; 566 567 /** 568 * List of objects which are purgeable. 569 */ 570 struct list_head purge_list; 571 572 /** 573 * List of objects which have allocated pages and are shrinkable. 574 */ 575 struct list_head shrink_list; 576 577 /** 578 * List of objects which are pending destruction. 579 */ 580 struct llist_head free_list; 581 struct work_struct free_work; 582 /** 583 * Count of objects pending destructions. Used to skip needlessly 584 * waiting on an RCU barrier if no objects are waiting to be freed. 585 */ 586 atomic_t free_count; 587 588 /** 589 * Small stash of WC pages 590 */ 591 struct pagestash wc_stash; 592 593 /** 594 * tmpfs instance used for shmem backed objects 595 */ 596 struct vfsmount *gemfs; 597 598 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 599 600 struct notifier_block oom_notifier; 601 struct notifier_block vmap_notifier; 602 struct shrinker shrinker; 603 604 /** 605 * Workqueue to fault in userptr pages, flushed by the execbuf 606 * when required but otherwise left to userspace to try again 607 * on EAGAIN. 608 */ 609 struct workqueue_struct *userptr_wq; 610 611 /* shrinker accounting, also useful for userland debugging */ 612 u64 shrink_memory; 613 u32 shrink_count; 614 }; 615 616 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 617 618 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 619 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 620 621 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 622 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 623 624 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 625 626 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 627 #define I915_NUM_QGV_POINTS 8 628 629 struct ddi_vbt_port_info { 630 /* Non-NULL if port present. */ 631 const struct child_device_config *child; 632 633 int max_tmds_clock; 634 635 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 636 u8 hdmi_level_shift; 637 u8 hdmi_level_shift_set:1; 638 639 u8 supports_dvi:1; 640 u8 supports_hdmi:1; 641 u8 supports_dp:1; 642 u8 supports_edp:1; 643 u8 supports_typec_usb:1; 644 u8 supports_tbt:1; 645 646 u8 alternate_aux_channel; 647 u8 alternate_ddc_pin; 648 649 u8 dp_boost_level; 650 u8 hdmi_boost_level; 651 int dp_max_link_rate; /* 0 for not limited by VBT */ 652 }; 653 654 enum psr_lines_to_wait { 655 PSR_0_LINES_TO_WAIT = 0, 656 PSR_1_LINE_TO_WAIT, 657 PSR_4_LINES_TO_WAIT, 658 PSR_8_LINES_TO_WAIT 659 }; 660 661 struct intel_vbt_data { 662 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 663 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 664 665 /* Feature bits */ 666 unsigned int int_tv_support:1; 667 unsigned int lvds_dither:1; 668 unsigned int int_crt_support:1; 669 unsigned int lvds_use_ssc:1; 670 unsigned int int_lvds_support:1; 671 unsigned int display_clock_mode:1; 672 unsigned int fdi_rx_polarity_inverted:1; 673 unsigned int panel_type:4; 674 int lvds_ssc_freq; 675 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 676 enum drm_panel_orientation orientation; 677 678 enum drrs_support_type drrs_type; 679 680 struct { 681 int rate; 682 int lanes; 683 int preemphasis; 684 int vswing; 685 bool low_vswing; 686 bool initialized; 687 int bpp; 688 struct edp_power_seq pps; 689 } edp; 690 691 struct { 692 bool enable; 693 bool full_link; 694 bool require_aux_wakeup; 695 int idle_frames; 696 enum psr_lines_to_wait lines_to_wait; 697 int tp1_wakeup_time_us; 698 int tp2_tp3_wakeup_time_us; 699 int psr2_tp2_tp3_wakeup_time_us; 700 } psr; 701 702 struct { 703 u16 pwm_freq_hz; 704 bool present; 705 bool active_low_pwm; 706 u8 min_brightness; /* min_brightness/255 of max */ 707 u8 controller; /* brightness controller number */ 708 enum intel_backlight_type type; 709 } backlight; 710 711 /* MIPI DSI */ 712 struct { 713 u16 panel_id; 714 struct mipi_config *config; 715 struct mipi_pps_data *pps; 716 u16 bl_ports; 717 u16 cabc_ports; 718 u8 seq_version; 719 u32 size; 720 u8 *data; 721 const u8 *sequence[MIPI_SEQ_MAX]; 722 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 723 enum drm_panel_orientation orientation; 724 } dsi; 725 726 int crt_ddc_pin; 727 728 struct list_head display_devices; 729 730 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 731 struct sdvo_device_mapping sdvo_mappings[2]; 732 }; 733 734 enum intel_ddb_partitioning { 735 INTEL_DDB_PART_1_2, 736 INTEL_DDB_PART_5_6, /* IVB+ */ 737 }; 738 739 struct ilk_wm_values { 740 u32 wm_pipe[3]; 741 u32 wm_lp[3]; 742 u32 wm_lp_spr[3]; 743 bool enable_fbc_wm; 744 enum intel_ddb_partitioning partitioning; 745 }; 746 747 struct g4x_pipe_wm { 748 u16 plane[I915_MAX_PLANES]; 749 u16 fbc; 750 }; 751 752 struct g4x_sr_wm { 753 u16 plane; 754 u16 cursor; 755 u16 fbc; 756 }; 757 758 struct vlv_wm_ddl_values { 759 u8 plane[I915_MAX_PLANES]; 760 }; 761 762 struct vlv_wm_values { 763 struct g4x_pipe_wm pipe[3]; 764 struct g4x_sr_wm sr; 765 struct vlv_wm_ddl_values ddl[3]; 766 u8 level; 767 bool cxsr; 768 }; 769 770 struct g4x_wm_values { 771 struct g4x_pipe_wm pipe[2]; 772 struct g4x_sr_wm sr; 773 struct g4x_sr_wm hpll; 774 bool cxsr; 775 bool hpll_en; 776 bool fbc_en; 777 }; 778 779 struct skl_ddb_entry { 780 u16 start, end; /* in number of blocks, 'end' is exclusive */ 781 }; 782 783 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 784 { 785 return entry->end - entry->start; 786 } 787 788 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 789 const struct skl_ddb_entry *e2) 790 { 791 if (e1->start == e2->start && e1->end == e2->end) 792 return true; 793 794 return false; 795 } 796 797 struct i915_frontbuffer_tracking { 798 spinlock_t lock; 799 800 /* 801 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 802 * scheduled flips. 803 */ 804 unsigned busy_bits; 805 unsigned flip_bits; 806 }; 807 808 struct i915_virtual_gpu { 809 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 810 bool active; 811 u32 caps; 812 }; 813 814 struct intel_cdclk_config { 815 unsigned int cdclk, vco, ref, bypass; 816 u8 voltage_level; 817 }; 818 819 struct i915_selftest_stash { 820 atomic_t counter; 821 }; 822 823 struct drm_i915_private { 824 struct drm_device drm; 825 826 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 827 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 828 struct intel_driver_caps caps; 829 830 /** 831 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 832 * end of stolen which we can optionally use to create GEM objects 833 * backed by stolen memory. Note that stolen_usable_size tells us 834 * exactly how much of this we are actually allowed to use, given that 835 * some portion of it is in fact reserved for use by hardware functions. 836 */ 837 struct resource dsm; 838 /** 839 * Reseved portion of Data Stolen Memory 840 */ 841 struct resource dsm_reserved; 842 843 /* 844 * Stolen memory is segmented in hardware with different portions 845 * offlimits to certain functions. 846 * 847 * The drm_mm is initialised to the total accessible range, as found 848 * from the PCI config. On Broadwell+, this is further restricted to 849 * avoid the first page! The upper end of stolen memory is reserved for 850 * hardware functions and similarly removed from the accessible range. 851 */ 852 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 853 854 struct intel_uncore uncore; 855 struct intel_uncore_mmio_debug mmio_debug; 856 857 struct i915_virtual_gpu vgpu; 858 859 struct intel_gvt *gvt; 860 861 struct intel_wopcm wopcm; 862 863 struct intel_csr csr; 864 865 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 866 867 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 868 * controller on different i2c buses. */ 869 struct mutex gmbus_mutex; 870 871 /** 872 * Base address of where the gmbus and gpio blocks are located (either 873 * on PCH or on SoC for platforms without PCH). 874 */ 875 u32 gpio_mmio_base; 876 877 u32 hsw_psr_mmio_adjust; 878 879 /* MMIO base address for MIPI regs */ 880 u32 mipi_mmio_base; 881 882 u32 pps_mmio_base; 883 884 wait_queue_head_t gmbus_wait_queue; 885 886 struct pci_dev *bridge_dev; 887 888 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 889 struct rb_root uabi_engines; 890 891 struct resource mch_res; 892 893 /* protects the irq masks */ 894 spinlock_t irq_lock; 895 896 bool display_irqs_enabled; 897 898 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 899 struct pm_qos_request pm_qos; 900 901 /* Sideband mailbox protection */ 902 struct mutex sb_lock; 903 struct pm_qos_request sb_qos; 904 905 /** Cached value of IMR to avoid reads in updating the bitfield */ 906 union { 907 u32 irq_mask; 908 u32 de_irq_mask[I915_MAX_PIPES]; 909 }; 910 u32 pipestat_irq_mask[I915_MAX_PIPES]; 911 912 struct i915_hotplug hotplug; 913 struct intel_fbc fbc; 914 struct i915_drrs drrs; 915 struct intel_opregion opregion; 916 struct intel_vbt_data vbt; 917 918 bool preserve_bios_swizzle; 919 920 /* overlay */ 921 struct intel_overlay *overlay; 922 923 /* backlight registers and fields in struct intel_panel */ 924 struct mutex backlight_lock; 925 926 /* protects panel power sequencer state */ 927 struct mutex pps_mutex; 928 929 unsigned int fsb_freq, mem_freq, is_ddr3; 930 unsigned int skl_preferred_vco_freq; 931 unsigned int max_cdclk_freq; 932 933 unsigned int max_dotclk_freq; 934 unsigned int hpll_freq; 935 unsigned int fdi_pll_freq; 936 unsigned int czclk_freq; 937 938 struct { 939 /* The current hardware cdclk configuration */ 940 struct intel_cdclk_config hw; 941 942 /* cdclk, divider, and ratio table from bspec */ 943 const struct intel_cdclk_vals *table; 944 945 struct intel_global_obj obj; 946 } cdclk; 947 948 /** 949 * wq - Driver workqueue for GEM. 950 * 951 * NOTE: Work items scheduled here are not allowed to grab any modeset 952 * locks, for otherwise the flushing done in the pageflip code will 953 * result in deadlocks. 954 */ 955 struct workqueue_struct *wq; 956 957 /* ordered wq for modesets */ 958 struct workqueue_struct *modeset_wq; 959 /* unbound hipri wq for page flips/plane updates */ 960 struct workqueue_struct *flip_wq; 961 962 /* Display functions */ 963 struct drm_i915_display_funcs display; 964 965 /* PCH chipset type */ 966 enum intel_pch pch_type; 967 unsigned short pch_id; 968 969 unsigned long quirks; 970 971 struct drm_atomic_state *modeset_restore_state; 972 struct drm_modeset_acquire_ctx reset_ctx; 973 974 struct i915_ggtt ggtt; /* VM representing the global address space */ 975 976 struct i915_gem_mm mm; 977 DECLARE_HASHTABLE(mm_structs, 7); 978 struct mutex mm_lock; 979 980 /* Kernel Modesetting */ 981 982 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 983 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 984 985 /** 986 * dpll and cdclk state is protected by connection_mutex 987 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 988 * Must be global rather than per dpll, because on some platforms plls 989 * share registers. 990 */ 991 struct { 992 struct mutex lock; 993 994 int num_shared_dpll; 995 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 996 const struct intel_dpll_mgr *mgr; 997 998 struct { 999 int nssc; 1000 int ssc; 1001 } ref_clks; 1002 } dpll; 1003 1004 struct list_head global_obj_list; 1005 1006 /* 1007 * For reading active_pipes holding any crtc lock is 1008 * sufficient, for writing must hold all of them. 1009 */ 1010 u8 active_pipes; 1011 1012 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1013 1014 struct i915_wa_list gt_wa_list; 1015 1016 struct i915_frontbuffer_tracking fb_tracking; 1017 1018 struct intel_atomic_helper { 1019 struct llist_head free_list; 1020 struct work_struct free_work; 1021 } atomic_helper; 1022 1023 bool mchbar_need_disable; 1024 1025 struct intel_l3_parity l3_parity; 1026 1027 /* 1028 * edram size in MB. 1029 * Cannot be determined by PCIID. You must always read a register. 1030 */ 1031 u32 edram_size_mb; 1032 1033 struct i915_power_domains power_domains; 1034 1035 struct i915_psr psr; 1036 1037 struct i915_gpu_error gpu_error; 1038 1039 struct drm_i915_gem_object *vlv_pctx; 1040 1041 /* list of fbdev register on this device */ 1042 struct intel_fbdev *fbdev; 1043 struct work_struct fbdev_suspend_work; 1044 1045 struct drm_property *broadcast_rgb_property; 1046 struct drm_property *force_audio_property; 1047 1048 /* hda/i915 audio component */ 1049 struct i915_audio_component *audio_component; 1050 bool audio_component_registered; 1051 /** 1052 * av_mutex - mutex for audio/video sync 1053 * 1054 */ 1055 struct mutex av_mutex; 1056 int audio_power_refcount; 1057 u32 audio_freq_cntrl; 1058 1059 u32 fdi_rx_config; 1060 1061 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1062 u32 chv_phy_control; 1063 /* 1064 * Shadows for CHV DPLL_MD regs to keep the state 1065 * checker somewhat working in the presence hardware 1066 * crappiness (can't read out DPLL_MD for pipes B & C). 1067 */ 1068 u32 chv_dpll_md[I915_MAX_PIPES]; 1069 u32 bxt_phy_grc; 1070 1071 u32 suspend_count; 1072 bool power_domains_suspended; 1073 struct i915_suspend_saved_registers regfile; 1074 struct vlv_s0ix_state *vlv_s0ix_state; 1075 1076 enum { 1077 I915_SAGV_UNKNOWN = 0, 1078 I915_SAGV_DISABLED, 1079 I915_SAGV_ENABLED, 1080 I915_SAGV_NOT_CONTROLLED 1081 } sagv_status; 1082 1083 u32 sagv_block_time_us; 1084 1085 struct { 1086 /* 1087 * Raw watermark latency values: 1088 * in 0.1us units for WM0, 1089 * in 0.5us units for WM1+. 1090 */ 1091 /* primary */ 1092 u16 pri_latency[5]; 1093 /* sprite */ 1094 u16 spr_latency[5]; 1095 /* cursor */ 1096 u16 cur_latency[5]; 1097 /* 1098 * Raw watermark memory latency values 1099 * for SKL for all 8 levels 1100 * in 1us units. 1101 */ 1102 u16 skl_latency[8]; 1103 1104 /* current hardware state */ 1105 union { 1106 struct ilk_wm_values hw; 1107 struct vlv_wm_values vlv; 1108 struct g4x_wm_values g4x; 1109 }; 1110 1111 u8 max_level; 1112 1113 /* 1114 * Should be held around atomic WM register writing; also 1115 * protects * intel_crtc->wm.active and 1116 * crtc_state->wm.need_postvbl_update. 1117 */ 1118 struct mutex wm_mutex; 1119 1120 /* 1121 * Set during HW readout of watermarks/DDB. Some platforms 1122 * need to know when we're still using BIOS-provided values 1123 * (which we don't fully trust). 1124 */ 1125 bool distrust_bios_wm; 1126 } wm; 1127 1128 u8 enabled_dbuf_slices_mask; /* GEN11 has configurable 2 slices */ 1129 1130 struct dram_info { 1131 bool valid; 1132 bool is_16gb_dimm; 1133 u8 num_channels; 1134 u8 ranks; 1135 u32 bandwidth_kbps; 1136 bool symmetric_memory; 1137 enum intel_dram_type { 1138 INTEL_DRAM_UNKNOWN, 1139 INTEL_DRAM_DDR3, 1140 INTEL_DRAM_DDR4, 1141 INTEL_DRAM_LPDDR3, 1142 INTEL_DRAM_LPDDR4 1143 } type; 1144 } dram_info; 1145 1146 struct intel_bw_info { 1147 /* for each QGV point */ 1148 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1149 u8 num_qgv_points; 1150 u8 num_planes; 1151 } max_bw[6]; 1152 1153 struct intel_global_obj bw_obj; 1154 1155 struct intel_runtime_pm runtime_pm; 1156 1157 struct i915_perf perf; 1158 1159 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1160 struct intel_gt gt; 1161 1162 struct { 1163 struct i915_gem_contexts { 1164 spinlock_t lock; /* locks list */ 1165 struct list_head list; 1166 1167 struct llist_head free_list; 1168 struct work_struct free_work; 1169 } contexts; 1170 1171 /* 1172 * We replace the local file with a global mappings as the 1173 * backing storage for the mmap is on the device and not 1174 * on the struct file, and we do not want to prolong the 1175 * lifetime of the local fd. To minimise the number of 1176 * anonymous inodes we create, we use a global singleton to 1177 * share the global mapping. 1178 */ 1179 struct file *mmap_singleton; 1180 } gem; 1181 1182 u8 pch_ssc_use; 1183 1184 /* For i915gm/i945gm vblank irq workaround */ 1185 u8 vblank_enabled; 1186 1187 /* perform PHY state sanity checks? */ 1188 bool chv_phy_assert[2]; 1189 1190 bool ipc_enabled; 1191 1192 /* Used to save the pipe-to-encoder mapping for audio */ 1193 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1194 1195 /* necessary resource sharing with HDMI LPE audio driver. */ 1196 struct { 1197 struct platform_device *platdev; 1198 int irq; 1199 } lpe_audio; 1200 1201 struct i915_pmu pmu; 1202 1203 struct i915_hdcp_comp_master *hdcp_master; 1204 bool hdcp_comp_added; 1205 1206 /* Mutex to protect the above hdcp component related values. */ 1207 struct mutex hdcp_comp_mutex; 1208 1209 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1210 1211 /* 1212 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1213 * will be rejected. Instead look for a better place. 1214 */ 1215 }; 1216 1217 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1218 { 1219 return container_of(dev, struct drm_i915_private, drm); 1220 } 1221 1222 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1223 { 1224 return dev_get_drvdata(kdev); 1225 } 1226 1227 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1228 { 1229 return pci_get_drvdata(pdev); 1230 } 1231 1232 /* Simple iterator over all initialised engines */ 1233 #define for_each_engine(engine__, dev_priv__, id__) \ 1234 for ((id__) = 0; \ 1235 (id__) < I915_NUM_ENGINES; \ 1236 (id__)++) \ 1237 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1238 1239 /* Iterator over subset of engines selected by mask */ 1240 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1241 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ 1242 (tmp__) ? \ 1243 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1244 0;) 1245 1246 #define rb_to_uabi_engine(rb) \ 1247 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1248 1249 #define for_each_uabi_engine(engine__, i915__) \ 1250 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1251 (engine__); \ 1252 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1253 1254 #define I915_GTT_OFFSET_NONE ((u32)-1) 1255 1256 /* 1257 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1258 * considered to be the frontbuffer for the given plane interface-wise. This 1259 * doesn't mean that the hw necessarily already scans it out, but that any 1260 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1261 * 1262 * We have one bit per pipe and per scanout plane type. 1263 */ 1264 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1265 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1266 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1267 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1268 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1269 }) 1270 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1271 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1272 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1273 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1274 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1275 1276 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1277 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1278 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1279 1280 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1281 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1282 1283 #define REVID_FOREVER 0xff 1284 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1285 1286 #define INTEL_GEN_MASK(s, e) ( \ 1287 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1288 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1289 GENMASK((e) - 1, (s) - 1)) 1290 1291 /* Returns true if Gen is in inclusive range [Start, End] */ 1292 #define IS_GEN_RANGE(dev_priv, s, e) \ 1293 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1294 1295 #define IS_GEN(dev_priv, n) \ 1296 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1297 INTEL_INFO(dev_priv)->gen == (n)) 1298 1299 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1300 1301 /* 1302 * Return true if revision is in range [since,until] inclusive. 1303 * 1304 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1305 */ 1306 #define IS_REVID(p, since, until) \ 1307 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1308 1309 static __always_inline unsigned int 1310 __platform_mask_index(const struct intel_runtime_info *info, 1311 enum intel_platform p) 1312 { 1313 const unsigned int pbits = 1314 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1315 1316 /* Expand the platform_mask array if this fails. */ 1317 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1318 pbits * ARRAY_SIZE(info->platform_mask)); 1319 1320 return p / pbits; 1321 } 1322 1323 static __always_inline unsigned int 1324 __platform_mask_bit(const struct intel_runtime_info *info, 1325 enum intel_platform p) 1326 { 1327 const unsigned int pbits = 1328 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1329 1330 return p % pbits + INTEL_SUBPLATFORM_BITS; 1331 } 1332 1333 static inline u32 1334 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1335 { 1336 const unsigned int pi = __platform_mask_index(info, p); 1337 1338 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1339 } 1340 1341 static __always_inline bool 1342 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1343 { 1344 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1345 const unsigned int pi = __platform_mask_index(info, p); 1346 const unsigned int pb = __platform_mask_bit(info, p); 1347 1348 BUILD_BUG_ON(!__builtin_constant_p(p)); 1349 1350 return info->platform_mask[pi] & BIT(pb); 1351 } 1352 1353 static __always_inline bool 1354 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1355 enum intel_platform p, unsigned int s) 1356 { 1357 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1358 const unsigned int pi = __platform_mask_index(info, p); 1359 const unsigned int pb = __platform_mask_bit(info, p); 1360 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1361 const u32 mask = info->platform_mask[pi]; 1362 1363 BUILD_BUG_ON(!__builtin_constant_p(p)); 1364 BUILD_BUG_ON(!__builtin_constant_p(s)); 1365 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1366 1367 /* Shift and test on the MSB position so sign flag can be used. */ 1368 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1369 } 1370 1371 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1372 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1373 1374 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1375 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1376 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1377 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1378 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1379 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1380 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1381 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1382 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1383 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1384 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1385 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1386 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1387 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1388 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1389 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1390 #define IS_IRONLAKE_M(dev_priv) \ 1391 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1392 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1393 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1394 INTEL_INFO(dev_priv)->gt == 1) 1395 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1396 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1397 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1398 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1399 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1400 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1401 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1402 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1403 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1404 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1405 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1406 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1407 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1408 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1409 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1410 #define IS_BDW_ULT(dev_priv) \ 1411 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1412 #define IS_BDW_ULX(dev_priv) \ 1413 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1414 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1415 INTEL_INFO(dev_priv)->gt == 3) 1416 #define IS_HSW_ULT(dev_priv) \ 1417 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1418 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1419 INTEL_INFO(dev_priv)->gt == 3) 1420 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1421 INTEL_INFO(dev_priv)->gt == 1) 1422 /* ULX machines are also considered ULT. */ 1423 #define IS_HSW_ULX(dev_priv) \ 1424 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1425 #define IS_SKL_ULT(dev_priv) \ 1426 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1427 #define IS_SKL_ULX(dev_priv) \ 1428 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1429 #define IS_KBL_ULT(dev_priv) \ 1430 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1431 #define IS_KBL_ULX(dev_priv) \ 1432 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1433 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1434 INTEL_INFO(dev_priv)->gt == 2) 1435 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1436 INTEL_INFO(dev_priv)->gt == 3) 1437 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1438 INTEL_INFO(dev_priv)->gt == 4) 1439 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1440 INTEL_INFO(dev_priv)->gt == 2) 1441 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1442 INTEL_INFO(dev_priv)->gt == 3) 1443 #define IS_CFL_ULT(dev_priv) \ 1444 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1445 #define IS_CFL_ULX(dev_priv) \ 1446 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1447 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1448 INTEL_INFO(dev_priv)->gt == 2) 1449 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1450 INTEL_INFO(dev_priv)->gt == 3) 1451 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1452 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1453 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1454 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1455 1456 #define SKL_REVID_A0 0x0 1457 #define SKL_REVID_B0 0x1 1458 #define SKL_REVID_C0 0x2 1459 #define SKL_REVID_D0 0x3 1460 #define SKL_REVID_E0 0x4 1461 #define SKL_REVID_F0 0x5 1462 #define SKL_REVID_G0 0x6 1463 #define SKL_REVID_H0 0x7 1464 1465 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1466 1467 #define BXT_REVID_A0 0x0 1468 #define BXT_REVID_A1 0x1 1469 #define BXT_REVID_B0 0x3 1470 #define BXT_REVID_B_LAST 0x8 1471 #define BXT_REVID_C0 0x9 1472 1473 #define IS_BXT_REVID(dev_priv, since, until) \ 1474 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1475 1476 #define KBL_REVID_A0 0x0 1477 #define KBL_REVID_B0 0x1 1478 #define KBL_REVID_C0 0x2 1479 #define KBL_REVID_D0 0x3 1480 #define KBL_REVID_E0 0x4 1481 1482 #define IS_KBL_REVID(dev_priv, since, until) \ 1483 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1484 1485 #define GLK_REVID_A0 0x0 1486 #define GLK_REVID_A1 0x1 1487 #define GLK_REVID_A2 0x2 1488 #define GLK_REVID_B0 0x3 1489 1490 #define IS_GLK_REVID(dev_priv, since, until) \ 1491 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1492 1493 #define CNL_REVID_A0 0x0 1494 #define CNL_REVID_B0 0x1 1495 #define CNL_REVID_C0 0x2 1496 1497 #define IS_CNL_REVID(p, since, until) \ 1498 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1499 1500 #define ICL_REVID_A0 0x0 1501 #define ICL_REVID_A2 0x1 1502 #define ICL_REVID_B0 0x3 1503 #define ICL_REVID_B2 0x4 1504 #define ICL_REVID_C0 0x5 1505 1506 #define IS_ICL_REVID(p, since, until) \ 1507 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1508 1509 #define TGL_REVID_A0 0x0 1510 #define TGL_REVID_B0 0x1 1511 #define TGL_REVID_C0 0x2 1512 1513 #define IS_TGL_REVID(p, since, until) \ 1514 (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) 1515 1516 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1517 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1518 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1519 1520 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 1521 1522 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 1523 unsigned int first__ = (first); \ 1524 unsigned int count__ = (count); \ 1525 (INTEL_INFO(dev_priv)->engine_mask & \ 1526 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1527 }) 1528 #define VDBOX_MASK(dev_priv) \ 1529 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 1530 #define VEBOX_MASK(dev_priv) \ 1531 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 1532 1533 /* 1534 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1535 * All later gens can run the final buffer from the ppgtt 1536 */ 1537 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1538 1539 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1540 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1541 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1542 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1543 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 1544 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 1545 1546 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1547 1548 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1549 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1550 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1551 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1552 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 1553 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 1554 1555 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1556 1557 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1558 #define HAS_PPGTT(dev_priv) \ 1559 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1560 #define HAS_FULL_PPGTT(dev_priv) \ 1561 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1562 1563 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1564 GEM_BUG_ON((sizes) == 0); \ 1565 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1566 }) 1567 1568 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1569 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1570 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1571 1572 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1573 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1574 1575 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1576 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1577 1578 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1579 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1580 (IS_CANNONLAKE(dev_priv) || \ 1581 IS_SKL_GT3(dev_priv) || \ 1582 IS_SKL_GT4(dev_priv)) 1583 1584 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1585 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1586 IS_GEMINILAKE(dev_priv) || \ 1587 IS_KABYLAKE(dev_priv)) 1588 1589 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1590 * rows, which changed the alignment requirements and fence programming. 1591 */ 1592 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1593 !(IS_I915G(dev_priv) || \ 1594 IS_I915GM(dev_priv))) 1595 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1596 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1597 1598 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1599 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1600 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1601 1602 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1603 1604 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1605 1606 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1607 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1608 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1609 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) 1610 1611 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1612 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1613 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1614 1615 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1616 1617 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1618 1619 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1620 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1621 1622 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1623 1624 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1625 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1626 1627 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1628 1629 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1630 1631 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1632 1633 1634 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1635 1636 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1637 1638 /* DPF == dynamic parity feature */ 1639 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1640 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1641 2 : HAS_L3_DPF(dev_priv)) 1642 1643 #define GT_FREQUENCY_MULTIPLIER 50 1644 #define GEN9_FREQ_SCALER 3 1645 1646 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1647 1648 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1649 1650 /* Only valid when HAS_DISPLAY() is true */ 1651 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) 1652 1653 static inline bool intel_vtd_active(void) 1654 { 1655 #ifdef CONFIG_INTEL_IOMMU 1656 if (intel_iommu_gfx_mapped) 1657 return true; 1658 #endif 1659 return false; 1660 } 1661 1662 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1663 { 1664 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1665 } 1666 1667 static inline bool 1668 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1669 { 1670 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1671 } 1672 1673 /* i915_drv.c */ 1674 extern const struct dev_pm_ops i915_pm_ops; 1675 1676 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1677 void i915_driver_remove(struct drm_i915_private *i915); 1678 1679 int i915_resume_switcheroo(struct drm_i915_private *i915); 1680 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1681 1682 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1683 struct drm_file *file_priv); 1684 1685 /* i915_gem.c */ 1686 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1687 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1688 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1689 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1690 int i915_gem_freeze(struct drm_i915_private *dev_priv); 1691 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 1692 1693 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1694 1695 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1696 { 1697 /* 1698 * A single pass should suffice to release all the freed objects (along 1699 * most call paths) , but be a little more paranoid in that freeing 1700 * the objects does take a little amount of time, during which the rcu 1701 * callbacks could have added new objects into the freed list, and 1702 * armed the work again. 1703 */ 1704 while (atomic_read(&i915->mm.free_count)) { 1705 flush_work(&i915->mm.free_work); 1706 rcu_barrier(); 1707 } 1708 } 1709 1710 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1711 { 1712 /* 1713 * Similar to objects above (see i915_gem_drain_freed-objects), in 1714 * general we have workers that are armed by RCU and then rearm 1715 * themselves in their callbacks. To be paranoid, we need to 1716 * drain the workqueue a second time after waiting for the RCU 1717 * grace period so that we catch work queued via RCU from the first 1718 * pass. As neither drain_workqueue() nor flush_workqueue() report 1719 * a result, we make an assumption that we only don't require more 1720 * than 3 passes to catch all _recursive_ RCU delayed work. 1721 * 1722 */ 1723 int pass = 3; 1724 do { 1725 flush_workqueue(i915->wq); 1726 rcu_barrier(); 1727 i915_gem_drain_freed_objects(i915); 1728 } while (--pass); 1729 drain_workqueue(i915->wq); 1730 } 1731 1732 struct i915_vma * __must_check 1733 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1734 const struct i915_ggtt_view *view, 1735 u64 size, 1736 u64 alignment, 1737 u64 flags); 1738 1739 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1740 unsigned long flags); 1741 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1742 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1743 1744 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1745 1746 int i915_gem_dumb_create(struct drm_file *file_priv, 1747 struct drm_device *dev, 1748 struct drm_mode_create_dumb *args); 1749 1750 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1751 1752 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1753 { 1754 return atomic_read(&error->reset_count); 1755 } 1756 1757 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1758 const struct intel_engine_cs *engine) 1759 { 1760 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1761 } 1762 1763 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1764 void i915_gem_driver_register(struct drm_i915_private *i915); 1765 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1766 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1767 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1768 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1769 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1770 void i915_gem_resume(struct drm_i915_private *dev_priv); 1771 1772 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1773 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1774 1775 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1776 enum i915_cache_level cache_level); 1777 1778 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1779 struct dma_buf *dma_buf); 1780 1781 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1782 1783 static inline struct i915_gem_context * 1784 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1785 { 1786 return xa_load(&file_priv->context_xa, id); 1787 } 1788 1789 static inline struct i915_gem_context * 1790 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1791 { 1792 struct i915_gem_context *ctx; 1793 1794 rcu_read_lock(); 1795 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1796 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1797 ctx = NULL; 1798 rcu_read_unlock(); 1799 1800 return ctx; 1801 } 1802 1803 /* i915_gem_evict.c */ 1804 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1805 u64 min_size, u64 alignment, 1806 unsigned long color, 1807 u64 start, u64 end, 1808 unsigned flags); 1809 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1810 struct drm_mm_node *node, 1811 unsigned int flags); 1812 int i915_gem_evict_vm(struct i915_address_space *vm); 1813 1814 /* i915_gem_internal.c */ 1815 struct drm_i915_gem_object * 1816 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1817 phys_addr_t size); 1818 1819 /* i915_gem_tiling.c */ 1820 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1821 { 1822 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1823 1824 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1825 i915_gem_object_is_tiled(obj); 1826 } 1827 1828 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1829 unsigned int tiling, unsigned int stride); 1830 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1831 unsigned int tiling, unsigned int stride); 1832 1833 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1834 1835 /* i915_cmd_parser.c */ 1836 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1837 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1838 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1839 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1840 struct i915_vma *batch, 1841 u32 batch_offset, 1842 u32 batch_length, 1843 struct i915_vma *shadow, 1844 bool trampoline); 1845 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1846 1847 /* intel_device_info.c */ 1848 static inline struct intel_device_info * 1849 mkwrite_device_info(struct drm_i915_private *dev_priv) 1850 { 1851 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1852 } 1853 1854 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *file); 1856 1857 #define __I915_REG_OP(op__, dev_priv__, ...) \ 1858 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 1859 1860 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 1861 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 1862 1863 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 1864 1865 /* These are untraced mmio-accessors that are only valid to be used inside 1866 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 1867 * controlled. 1868 * 1869 * Think twice, and think again, before using these. 1870 * 1871 * As an example, these accessors can possibly be used between: 1872 * 1873 * spin_lock_irq(&dev_priv->uncore.lock); 1874 * intel_uncore_forcewake_get__locked(); 1875 * 1876 * and 1877 * 1878 * intel_uncore_forcewake_put__locked(); 1879 * spin_unlock_irq(&dev_priv->uncore.lock); 1880 * 1881 * 1882 * Note: some registers may not need forcewake held, so 1883 * intel_uncore_forcewake_{get,put} can be omitted, see 1884 * intel_uncore_forcewake_for_reg(). 1885 * 1886 * Certain architectures will die if the same cacheline is concurrently accessed 1887 * by different clients (e.g. on Ivybridge). Access to registers should 1888 * therefore generally be serialised, by either the dev_priv->uncore.lock or 1889 * a more localised lock guarding all access to that bank of registers. 1890 */ 1891 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 1892 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 1893 1894 /* i915_mm.c */ 1895 int remap_io_mapping(struct vm_area_struct *vma, 1896 unsigned long addr, unsigned long pfn, unsigned long size, 1897 struct io_mapping *iomap); 1898 int remap_io_sg(struct vm_area_struct *vma, 1899 unsigned long addr, unsigned long size, 1900 struct scatterlist *sgl, resource_size_t iobase); 1901 1902 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1903 { 1904 if (INTEL_GEN(i915) >= 10) 1905 return CNL_HWS_CSB_WRITE_INDEX; 1906 else 1907 return I915_HWS_CSB_WRITE_INDEX; 1908 } 1909 1910 static inline enum i915_map_type 1911 i915_coherent_map_type(struct drm_i915_private *i915) 1912 { 1913 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 1914 } 1915 1916 #endif 1917