1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <drm/intel-gtt.h> 39 40 /* General customization: 41 */ 42 43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 44 45 #define DRIVER_NAME "i915" 46 #define DRIVER_DESC "Intel Graphics" 47 #define DRIVER_DATE "20080730" 48 49 enum pipe { 50 PIPE_A = 0, 51 PIPE_B, 52 }; 53 54 enum plane { 55 PLANE_A = 0, 56 PLANE_B, 57 }; 58 59 #define I915_NUM_PIPE 2 60 61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 62 63 /* Interface history: 64 * 65 * 1.1: Original. 66 * 1.2: Add Power Management 67 * 1.3: Add vblank support 68 * 1.4: Fix cmdbuffer path, add heap destroy 69 * 1.5: Add vblank pipe configuration 70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 71 * - Support vertical blank on secondary display pipe 72 */ 73 #define DRIVER_MAJOR 1 74 #define DRIVER_MINOR 6 75 #define DRIVER_PATCHLEVEL 0 76 77 #define WATCH_COHERENCY 0 78 #define WATCH_EXEC 0 79 #define WATCH_RELOC 0 80 #define WATCH_LISTS 0 81 #define WATCH_PWRITE 0 82 83 #define I915_GEM_PHYS_CURSOR_0 1 84 #define I915_GEM_PHYS_CURSOR_1 2 85 #define I915_GEM_PHYS_OVERLAY_REGS 3 86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 87 88 struct drm_i915_gem_phys_object { 89 int id; 90 struct page **page_list; 91 drm_dma_handle_t *handle; 92 struct drm_gem_object *cur_obj; 93 }; 94 95 struct mem_block { 96 struct mem_block *next; 97 struct mem_block *prev; 98 int start; 99 int size; 100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 101 }; 102 103 struct opregion_header; 104 struct opregion_acpi; 105 struct opregion_swsci; 106 struct opregion_asle; 107 108 struct intel_opregion { 109 struct opregion_header *header; 110 struct opregion_acpi *acpi; 111 struct opregion_swsci *swsci; 112 struct opregion_asle *asle; 113 void *vbt; 114 }; 115 #define OPREGION_SIZE (8*1024) 116 117 struct intel_overlay; 118 struct intel_overlay_error_state; 119 120 struct drm_i915_master_private { 121 drm_local_map_t *sarea; 122 struct _drm_i915_sarea *sarea_priv; 123 }; 124 #define I915_FENCE_REG_NONE -1 125 126 struct drm_i915_fence_reg { 127 struct drm_gem_object *obj; 128 struct list_head lru_list; 129 bool gpu; 130 }; 131 132 struct sdvo_device_mapping { 133 u8 initialized; 134 u8 dvo_port; 135 u8 slave_addr; 136 u8 dvo_wiring; 137 u8 i2c_pin; 138 u8 i2c_speed; 139 u8 ddc_pin; 140 }; 141 142 struct drm_i915_error_state { 143 u32 eir; 144 u32 pgtbl_er; 145 u32 pipeastat; 146 u32 pipebstat; 147 u32 ipeir; 148 u32 ipehr; 149 u32 instdone; 150 u32 acthd; 151 u32 instpm; 152 u32 instps; 153 u32 instdone1; 154 u32 seqno; 155 u64 bbaddr; 156 struct timeval time; 157 struct drm_i915_error_object { 158 int page_count; 159 u32 gtt_offset; 160 u32 *pages[0]; 161 } *ringbuffer, *batchbuffer[2]; 162 struct drm_i915_error_buffer { 163 size_t size; 164 u32 name; 165 u32 seqno; 166 u32 gtt_offset; 167 u32 read_domains; 168 u32 write_domain; 169 u32 fence_reg; 170 s32 pinned:2; 171 u32 tiling:2; 172 u32 dirty:1; 173 u32 purgeable:1; 174 } *active_bo; 175 u32 active_bo_count; 176 struct intel_overlay_error_state *overlay; 177 }; 178 179 struct drm_i915_display_funcs { 180 void (*dpms)(struct drm_crtc *crtc, int mode); 181 bool (*fbc_enabled)(struct drm_device *dev); 182 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 183 void (*disable_fbc)(struct drm_device *dev); 184 int (*get_display_clock_speed)(struct drm_device *dev); 185 int (*get_fifo_size)(struct drm_device *dev, int plane); 186 void (*update_wm)(struct drm_device *dev, int planea_clock, 187 int planeb_clock, int sr_hdisplay, int sr_htotal, 188 int pixel_size); 189 /* clock updates for mode set */ 190 /* cursor updates */ 191 /* render clock increase/decrease */ 192 /* display clock increase/decrease */ 193 /* pll clock increase/decrease */ 194 /* clock gating init */ 195 }; 196 197 struct intel_device_info { 198 u8 gen; 199 u8 is_mobile : 1; 200 u8 is_i85x : 1; 201 u8 is_i915g : 1; 202 u8 is_i945gm : 1; 203 u8 is_g33 : 1; 204 u8 need_gfx_hws : 1; 205 u8 is_g4x : 1; 206 u8 is_pineview : 1; 207 u8 is_broadwater : 1; 208 u8 is_crestline : 1; 209 u8 has_fbc : 1; 210 u8 has_rc6 : 1; 211 u8 has_pipe_cxsr : 1; 212 u8 has_hotplug : 1; 213 u8 cursor_needs_physical : 1; 214 u8 has_overlay : 1; 215 u8 overlay_needs_physical : 1; 216 u8 supports_tv : 1; 217 u8 has_bsd_ring : 1; 218 u8 has_blt_ring : 1; 219 }; 220 221 enum no_fbc_reason { 222 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 223 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 224 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 225 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 226 FBC_BAD_PLANE, /* fbc not supported on plane */ 227 FBC_NOT_TILED, /* buffer not tiled */ 228 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 229 }; 230 231 enum intel_pch { 232 PCH_IBX, /* Ibexpeak PCH */ 233 PCH_CPT, /* Cougarpoint PCH */ 234 }; 235 236 #define QUIRK_PIPEA_FORCE (1<<0) 237 238 struct intel_fbdev; 239 240 typedef struct drm_i915_private { 241 struct drm_device *dev; 242 243 const struct intel_device_info *info; 244 245 int has_gem; 246 247 void __iomem *regs; 248 249 struct intel_gmbus { 250 struct i2c_adapter adapter; 251 struct i2c_adapter *force_bit; 252 u32 reg0; 253 } *gmbus; 254 255 struct pci_dev *bridge_dev; 256 struct intel_ring_buffer render_ring; 257 struct intel_ring_buffer bsd_ring; 258 struct intel_ring_buffer blt_ring; 259 uint32_t next_seqno; 260 261 drm_dma_handle_t *status_page_dmah; 262 void *seqno_page; 263 dma_addr_t dma_status_page; 264 uint32_t counter; 265 unsigned int seqno_gfx_addr; 266 drm_local_map_t hws_map; 267 struct drm_gem_object *seqno_obj; 268 struct drm_gem_object *pwrctx; 269 struct drm_gem_object *renderctx; 270 271 struct resource mch_res; 272 273 unsigned int cpp; 274 int back_offset; 275 int front_offset; 276 int current_page; 277 int page_flipping; 278 #define I915_DEBUG_READ (1<<0) 279 #define I915_DEBUG_WRITE (1<<1) 280 unsigned long debug_flags; 281 282 wait_queue_head_t irq_queue; 283 atomic_t irq_received; 284 /** Protects user_irq_refcount and irq_mask_reg */ 285 spinlock_t user_irq_lock; 286 u32 trace_irq_seqno; 287 /** Cached value of IMR to avoid reads in updating the bitfield */ 288 u32 irq_mask_reg; 289 u32 pipestat[2]; 290 /** splitted irq regs for graphics and display engine on Ironlake, 291 irq_mask_reg is still used for display irq. */ 292 u32 gt_irq_mask_reg; 293 u32 gt_irq_enable_reg; 294 u32 de_irq_enable_reg; 295 u32 pch_irq_mask_reg; 296 u32 pch_irq_enable_reg; 297 298 u32 hotplug_supported_mask; 299 struct work_struct hotplug_work; 300 301 int tex_lru_log_granularity; 302 int allow_batchbuffer; 303 struct mem_block *agp_heap; 304 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 305 int vblank_pipe; 306 int num_pipe; 307 308 /* For hangcheck timer */ 309 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */ 310 struct timer_list hangcheck_timer; 311 int hangcheck_count; 312 uint32_t last_acthd; 313 uint32_t last_instdone; 314 uint32_t last_instdone1; 315 316 unsigned long cfb_size; 317 unsigned long cfb_pitch; 318 unsigned long cfb_offset; 319 int cfb_fence; 320 int cfb_plane; 321 int cfb_y; 322 323 int irq_enabled; 324 325 struct intel_opregion opregion; 326 327 /* overlay */ 328 struct intel_overlay *overlay; 329 330 /* LVDS info */ 331 int backlight_level; /* restore backlight to this value */ 332 struct drm_display_mode *panel_fixed_mode; 333 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 334 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 335 336 /* Feature bits from the VBIOS */ 337 unsigned int int_tv_support:1; 338 unsigned int lvds_dither:1; 339 unsigned int lvds_vbt:1; 340 unsigned int int_crt_support:1; 341 unsigned int lvds_use_ssc:1; 342 int lvds_ssc_freq; 343 struct { 344 int rate; 345 int lanes; 346 int preemphasis; 347 int vswing; 348 349 bool initialized; 350 bool support; 351 int bpp; 352 struct edp_power_seq pps; 353 } edp; 354 bool no_aux_handshake; 355 356 struct notifier_block lid_notifier; 357 358 int crt_ddc_pin; 359 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 360 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 361 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 362 363 unsigned int fsb_freq, mem_freq, is_ddr3; 364 365 spinlock_t error_lock; 366 struct drm_i915_error_state *first_error; 367 struct work_struct error_work; 368 struct completion error_completion; 369 struct workqueue_struct *wq; 370 371 /* Display functions */ 372 struct drm_i915_display_funcs display; 373 374 /* PCH chipset type */ 375 enum intel_pch pch_type; 376 377 unsigned long quirks; 378 379 /* Register state */ 380 bool modeset_on_lid; 381 u8 saveLBB; 382 u32 saveDSPACNTR; 383 u32 saveDSPBCNTR; 384 u32 saveDSPARB; 385 u32 saveHWS; 386 u32 savePIPEACONF; 387 u32 savePIPEBCONF; 388 u32 savePIPEASRC; 389 u32 savePIPEBSRC; 390 u32 saveFPA0; 391 u32 saveFPA1; 392 u32 saveDPLL_A; 393 u32 saveDPLL_A_MD; 394 u32 saveHTOTAL_A; 395 u32 saveHBLANK_A; 396 u32 saveHSYNC_A; 397 u32 saveVTOTAL_A; 398 u32 saveVBLANK_A; 399 u32 saveVSYNC_A; 400 u32 saveBCLRPAT_A; 401 u32 saveTRANSACONF; 402 u32 saveTRANS_HTOTAL_A; 403 u32 saveTRANS_HBLANK_A; 404 u32 saveTRANS_HSYNC_A; 405 u32 saveTRANS_VTOTAL_A; 406 u32 saveTRANS_VBLANK_A; 407 u32 saveTRANS_VSYNC_A; 408 u32 savePIPEASTAT; 409 u32 saveDSPASTRIDE; 410 u32 saveDSPASIZE; 411 u32 saveDSPAPOS; 412 u32 saveDSPAADDR; 413 u32 saveDSPASURF; 414 u32 saveDSPATILEOFF; 415 u32 savePFIT_PGM_RATIOS; 416 u32 saveBLC_HIST_CTL; 417 u32 saveBLC_PWM_CTL; 418 u32 saveBLC_PWM_CTL2; 419 u32 saveBLC_CPU_PWM_CTL; 420 u32 saveBLC_CPU_PWM_CTL2; 421 u32 saveFPB0; 422 u32 saveFPB1; 423 u32 saveDPLL_B; 424 u32 saveDPLL_B_MD; 425 u32 saveHTOTAL_B; 426 u32 saveHBLANK_B; 427 u32 saveHSYNC_B; 428 u32 saveVTOTAL_B; 429 u32 saveVBLANK_B; 430 u32 saveVSYNC_B; 431 u32 saveBCLRPAT_B; 432 u32 saveTRANSBCONF; 433 u32 saveTRANS_HTOTAL_B; 434 u32 saveTRANS_HBLANK_B; 435 u32 saveTRANS_HSYNC_B; 436 u32 saveTRANS_VTOTAL_B; 437 u32 saveTRANS_VBLANK_B; 438 u32 saveTRANS_VSYNC_B; 439 u32 savePIPEBSTAT; 440 u32 saveDSPBSTRIDE; 441 u32 saveDSPBSIZE; 442 u32 saveDSPBPOS; 443 u32 saveDSPBADDR; 444 u32 saveDSPBSURF; 445 u32 saveDSPBTILEOFF; 446 u32 saveVGA0; 447 u32 saveVGA1; 448 u32 saveVGA_PD; 449 u32 saveVGACNTRL; 450 u32 saveADPA; 451 u32 saveLVDS; 452 u32 savePP_ON_DELAYS; 453 u32 savePP_OFF_DELAYS; 454 u32 saveDVOA; 455 u32 saveDVOB; 456 u32 saveDVOC; 457 u32 savePP_ON; 458 u32 savePP_OFF; 459 u32 savePP_CONTROL; 460 u32 savePP_DIVISOR; 461 u32 savePFIT_CONTROL; 462 u32 save_palette_a[256]; 463 u32 save_palette_b[256]; 464 u32 saveDPFC_CB_BASE; 465 u32 saveFBC_CFB_BASE; 466 u32 saveFBC_LL_BASE; 467 u32 saveFBC_CONTROL; 468 u32 saveFBC_CONTROL2; 469 u32 saveIER; 470 u32 saveIIR; 471 u32 saveIMR; 472 u32 saveDEIER; 473 u32 saveDEIMR; 474 u32 saveGTIER; 475 u32 saveGTIMR; 476 u32 saveFDI_RXA_IMR; 477 u32 saveFDI_RXB_IMR; 478 u32 saveCACHE_MODE_0; 479 u32 saveMI_ARB_STATE; 480 u32 saveSWF0[16]; 481 u32 saveSWF1[16]; 482 u32 saveSWF2[3]; 483 u8 saveMSR; 484 u8 saveSR[8]; 485 u8 saveGR[25]; 486 u8 saveAR_INDEX; 487 u8 saveAR[21]; 488 u8 saveDACMASK; 489 u8 saveCR[37]; 490 uint64_t saveFENCE[16]; 491 u32 saveCURACNTR; 492 u32 saveCURAPOS; 493 u32 saveCURABASE; 494 u32 saveCURBCNTR; 495 u32 saveCURBPOS; 496 u32 saveCURBBASE; 497 u32 saveCURSIZE; 498 u32 saveDP_B; 499 u32 saveDP_C; 500 u32 saveDP_D; 501 u32 savePIPEA_GMCH_DATA_M; 502 u32 savePIPEB_GMCH_DATA_M; 503 u32 savePIPEA_GMCH_DATA_N; 504 u32 savePIPEB_GMCH_DATA_N; 505 u32 savePIPEA_DP_LINK_M; 506 u32 savePIPEB_DP_LINK_M; 507 u32 savePIPEA_DP_LINK_N; 508 u32 savePIPEB_DP_LINK_N; 509 u32 saveFDI_RXA_CTL; 510 u32 saveFDI_TXA_CTL; 511 u32 saveFDI_RXB_CTL; 512 u32 saveFDI_TXB_CTL; 513 u32 savePFA_CTL_1; 514 u32 savePFB_CTL_1; 515 u32 savePFA_WIN_SZ; 516 u32 savePFB_WIN_SZ; 517 u32 savePFA_WIN_POS; 518 u32 savePFB_WIN_POS; 519 u32 savePCH_DREF_CONTROL; 520 u32 saveDISP_ARB_CTL; 521 u32 savePIPEA_DATA_M1; 522 u32 savePIPEA_DATA_N1; 523 u32 savePIPEA_LINK_M1; 524 u32 savePIPEA_LINK_N1; 525 u32 savePIPEB_DATA_M1; 526 u32 savePIPEB_DATA_N1; 527 u32 savePIPEB_LINK_M1; 528 u32 savePIPEB_LINK_N1; 529 u32 saveMCHBAR_RENDER_STANDBY; 530 531 struct { 532 /** Bridge to intel-gtt-ko */ 533 struct intel_gtt *gtt; 534 /** Memory allocator for GTT stolen memory */ 535 struct drm_mm vram; 536 /** Memory allocator for GTT */ 537 struct drm_mm gtt_space; 538 539 struct io_mapping *gtt_mapping; 540 int gtt_mtrr; 541 542 /** 543 * Membership on list of all loaded devices, used to evict 544 * inactive buffers under memory pressure. 545 * 546 * Modifications should only be done whilst holding the 547 * shrink_list_lock spinlock. 548 */ 549 struct list_head shrink_list; 550 551 /** 552 * List of objects currently involved in rendering. 553 * 554 * Includes buffers having the contents of their GPU caches 555 * flushed, not necessarily primitives. last_rendering_seqno 556 * represents when the rendering involved will be completed. 557 * 558 * A reference is held on the buffer while on this list. 559 */ 560 struct list_head active_list; 561 562 /** 563 * List of objects which are not in the ringbuffer but which 564 * still have a write_domain which needs to be flushed before 565 * unbinding. 566 * 567 * last_rendering_seqno is 0 while an object is in this list. 568 * 569 * A reference is held on the buffer while on this list. 570 */ 571 struct list_head flushing_list; 572 573 /** 574 * LRU list of objects which are not in the ringbuffer and 575 * are ready to unbind, but are still in the GTT. 576 * 577 * last_rendering_seqno is 0 while an object is in this list. 578 * 579 * A reference is not held on the buffer while on this list, 580 * as merely being GTT-bound shouldn't prevent its being 581 * freed, and we'll pull it off the list in the free path. 582 */ 583 struct list_head inactive_list; 584 585 /** 586 * LRU list of objects which are not in the ringbuffer but 587 * are still pinned in the GTT. 588 */ 589 struct list_head pinned_list; 590 591 /** LRU list of objects with fence regs on them. */ 592 struct list_head fence_list; 593 594 /** 595 * List of objects currently pending being freed. 596 * 597 * These objects are no longer in use, but due to a signal 598 * we were prevented from freeing them at the appointed time. 599 */ 600 struct list_head deferred_free_list; 601 602 /** 603 * We leave the user IRQ off as much as possible, 604 * but this means that requests will finish and never 605 * be retired once the system goes idle. Set a timer to 606 * fire periodically while the ring is running. When it 607 * fires, go retire requests. 608 */ 609 struct delayed_work retire_work; 610 611 /** 612 * Waiting sequence number, if any 613 */ 614 uint32_t waiting_gem_seqno; 615 616 /** 617 * Last seq seen at irq time 618 */ 619 uint32_t irq_gem_seqno; 620 621 /** 622 * Flag if the X Server, and thus DRM, is not currently in 623 * control of the device. 624 * 625 * This is set between LeaveVT and EnterVT. It needs to be 626 * replaced with a semaphore. It also needs to be 627 * transitioned away from for kernel modesetting. 628 */ 629 int suspended; 630 631 /** 632 * Flag if the hardware appears to be wedged. 633 * 634 * This is set when attempts to idle the device timeout. 635 * It prevents command submission from occuring and makes 636 * every pending request fail 637 */ 638 atomic_t wedged; 639 640 /** Bit 6 swizzling required for X tiling */ 641 uint32_t bit_6_swizzle_x; 642 /** Bit 6 swizzling required for Y tiling */ 643 uint32_t bit_6_swizzle_y; 644 645 /* storage for physical objects */ 646 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 647 648 uint32_t flush_rings; 649 650 /* accounting, useful for userland debugging */ 651 size_t object_memory; 652 size_t pin_memory; 653 size_t gtt_memory; 654 size_t gtt_total; 655 u32 object_count; 656 u32 pin_count; 657 u32 gtt_count; 658 } mm; 659 struct sdvo_device_mapping sdvo_mappings[2]; 660 /* indicate whether the LVDS_BORDER should be enabled or not */ 661 unsigned int lvds_border_bits; 662 /* Panel fitter placement and size for Ironlake+ */ 663 u32 pch_pf_pos, pch_pf_size; 664 665 struct drm_crtc *plane_to_crtc_mapping[2]; 666 struct drm_crtc *pipe_to_crtc_mapping[2]; 667 wait_queue_head_t pending_flip_queue; 668 bool flip_pending_is_done; 669 670 /* Reclocking support */ 671 bool render_reclock_avail; 672 bool lvds_downclock_avail; 673 /* indicates the reduced downclock for LVDS*/ 674 int lvds_downclock; 675 struct work_struct idle_work; 676 struct timer_list idle_timer; 677 bool busy; 678 u16 orig_clock; 679 int child_dev_num; 680 struct child_device_config *child_dev; 681 struct drm_connector *int_lvds_connector; 682 683 bool mchbar_need_disable; 684 685 u8 cur_delay; 686 u8 min_delay; 687 u8 max_delay; 688 u8 fmax; 689 u8 fstart; 690 691 u64 last_count1; 692 unsigned long last_time1; 693 u64 last_count2; 694 struct timespec last_time2; 695 unsigned long gfx_power; 696 int c_m; 697 int r_t; 698 u8 corr; 699 spinlock_t *mchdev_lock; 700 701 enum no_fbc_reason no_fbc_reason; 702 703 struct drm_mm_node *compressed_fb; 704 struct drm_mm_node *compressed_llb; 705 706 unsigned long last_gpu_reset; 707 708 /* list of fbdev register on this device */ 709 struct intel_fbdev *fbdev; 710 } drm_i915_private_t; 711 712 /** driver private structure attached to each drm_gem_object */ 713 struct drm_i915_gem_object { 714 struct drm_gem_object base; 715 716 /** Current space allocated to this object in the GTT, if any. */ 717 struct drm_mm_node *gtt_space; 718 719 /** This object's place on the active/flushing/inactive lists */ 720 struct list_head ring_list; 721 struct list_head mm_list; 722 /** This object's place on GPU write list */ 723 struct list_head gpu_write_list; 724 /** This object's place on eviction list */ 725 struct list_head evict_list; 726 727 /** 728 * This is set if the object is on the active or flushing lists 729 * (has pending rendering), and is not set if it's on inactive (ready 730 * to be unbound). 731 */ 732 unsigned int active : 1; 733 734 /** 735 * This is set if the object has been written to since last bound 736 * to the GTT 737 */ 738 unsigned int dirty : 1; 739 740 /** 741 * Fence register bits (if any) for this object. Will be set 742 * as needed when mapped into the GTT. 743 * Protected by dev->struct_mutex. 744 * 745 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) 746 */ 747 signed int fence_reg : 5; 748 749 /** 750 * Used for checking the object doesn't appear more than once 751 * in an execbuffer object list. 752 */ 753 unsigned int in_execbuffer : 1; 754 755 /** 756 * Advice: are the backing pages purgeable? 757 */ 758 unsigned int madv : 2; 759 760 /** 761 * Refcount for the pages array. With the current locking scheme, there 762 * are at most two concurrent users: Binding a bo to the gtt and 763 * pwrite/pread using physical addresses. So two bits for a maximum 764 * of two users are enough. 765 */ 766 unsigned int pages_refcount : 2; 767 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 768 769 /** 770 * Current tiling mode for the object. 771 */ 772 unsigned int tiling_mode : 2; 773 774 /** How many users have pinned this object in GTT space. The following 775 * users can each hold at most one reference: pwrite/pread, pin_ioctl 776 * (via user_pin_count), execbuffer (objects are not allowed multiple 777 * times for the same batchbuffer), and the framebuffer code. When 778 * switching/pageflipping, the framebuffer code has at most two buffers 779 * pinned per crtc. 780 * 781 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 782 * bits with absolutely no headroom. So use 4 bits. */ 783 unsigned int pin_count : 4; 784 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 785 786 /** AGP memory structure for our GTT binding. */ 787 DRM_AGP_MEM *agp_mem; 788 789 struct page **pages; 790 791 /** 792 * Current offset of the object in GTT space. 793 * 794 * This is the same as gtt_space->start 795 */ 796 uint32_t gtt_offset; 797 798 /* Which ring is refering to is this object */ 799 struct intel_ring_buffer *ring; 800 801 /** 802 * Fake offset for use by mmap(2) 803 */ 804 uint64_t mmap_offset; 805 806 /** Breadcrumb of last rendering to the buffer. */ 807 uint32_t last_rendering_seqno; 808 809 /** Current tiling stride for the object, if it's tiled. */ 810 uint32_t stride; 811 812 /** Record of address bit 17 of each page at last unbind. */ 813 unsigned long *bit_17; 814 815 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 816 uint32_t agp_type; 817 818 /** 819 * If present, while GEM_DOMAIN_CPU is in the read domain this array 820 * flags which individual pages are valid. 821 */ 822 uint8_t *page_cpu_valid; 823 824 /** User space pin count and filp owning the pin */ 825 uint32_t user_pin_count; 826 struct drm_file *pin_filp; 827 828 /** for phy allocated objects */ 829 struct drm_i915_gem_phys_object *phys_obj; 830 831 /** 832 * Number of crtcs where this object is currently the fb, but 833 * will be page flipped away on the next vblank. When it 834 * reaches 0, dev_priv->pending_flip_queue will be woken up. 835 */ 836 atomic_t pending_flip; 837 }; 838 839 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 840 841 /** 842 * Request queue structure. 843 * 844 * The request queue allows us to note sequence numbers that have been emitted 845 * and may be associated with active buffers to be retired. 846 * 847 * By keeping this list, we can avoid having to do questionable 848 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 849 * an emission time with seqnos for tracking how far ahead of the GPU we are. 850 */ 851 struct drm_i915_gem_request { 852 /** On Which ring this request was generated */ 853 struct intel_ring_buffer *ring; 854 855 /** GEM sequence number associated with this request. */ 856 uint32_t seqno; 857 858 /** Time at which this request was emitted, in jiffies. */ 859 unsigned long emitted_jiffies; 860 861 /** global list entry for this request */ 862 struct list_head list; 863 864 struct drm_i915_file_private *file_priv; 865 /** file_priv list entry for this request */ 866 struct list_head client_list; 867 }; 868 869 struct drm_i915_file_private { 870 struct { 871 struct spinlock lock; 872 struct list_head request_list; 873 } mm; 874 }; 875 876 enum intel_chip_family { 877 CHIP_I8XX = 0x01, 878 CHIP_I9XX = 0x02, 879 CHIP_I915 = 0x04, 880 CHIP_I965 = 0x08, 881 }; 882 883 extern struct drm_ioctl_desc i915_ioctls[]; 884 extern int i915_max_ioctl; 885 extern unsigned int i915_fbpercrtc; 886 extern unsigned int i915_powersave; 887 extern unsigned int i915_lvds_downclock; 888 889 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 890 extern int i915_resume(struct drm_device *dev); 891 extern void i915_save_display(struct drm_device *dev); 892 extern void i915_restore_display(struct drm_device *dev); 893 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 894 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 895 896 /* i915_dma.c */ 897 extern void i915_kernel_lost_context(struct drm_device * dev); 898 extern int i915_driver_load(struct drm_device *, unsigned long flags); 899 extern int i915_driver_unload(struct drm_device *); 900 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 901 extern void i915_driver_lastclose(struct drm_device * dev); 902 extern void i915_driver_preclose(struct drm_device *dev, 903 struct drm_file *file_priv); 904 extern void i915_driver_postclose(struct drm_device *dev, 905 struct drm_file *file_priv); 906 extern int i915_driver_device_is_agp(struct drm_device * dev); 907 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 908 unsigned long arg); 909 extern int i915_emit_box(struct drm_device *dev, 910 struct drm_clip_rect *boxes, 911 int i, int DR1, int DR4); 912 extern int i915_reset(struct drm_device *dev, u8 flags); 913 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 914 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 915 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 916 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 917 918 919 /* i915_irq.c */ 920 void i915_hangcheck_elapsed(unsigned long data); 921 extern int i915_irq_emit(struct drm_device *dev, void *data, 922 struct drm_file *file_priv); 923 extern int i915_irq_wait(struct drm_device *dev, void *data, 924 struct drm_file *file_priv); 925 void i915_trace_irq_get(struct drm_device *dev, u32 seqno); 926 extern void i915_enable_interrupt (struct drm_device *dev); 927 928 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 929 extern void i915_driver_irq_preinstall(struct drm_device * dev); 930 extern int i915_driver_irq_postinstall(struct drm_device *dev); 931 extern void i915_driver_irq_uninstall(struct drm_device * dev); 932 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 933 struct drm_file *file_priv); 934 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 935 struct drm_file *file_priv); 936 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 937 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 938 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 939 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 940 extern int i915_vblank_swap(struct drm_device *dev, void *data, 941 struct drm_file *file_priv); 942 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 943 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); 944 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, 945 u32 mask); 946 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, 947 u32 mask); 948 949 void 950 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 951 952 void 953 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 954 955 void intel_enable_asle (struct drm_device *dev); 956 957 #ifdef CONFIG_DEBUG_FS 958 extern void i915_destroy_error_state(struct drm_device *dev); 959 #else 960 #define i915_destroy_error_state(x) 961 #endif 962 963 964 /* i915_mem.c */ 965 extern int i915_mem_alloc(struct drm_device *dev, void *data, 966 struct drm_file *file_priv); 967 extern int i915_mem_free(struct drm_device *dev, void *data, 968 struct drm_file *file_priv); 969 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 970 struct drm_file *file_priv); 971 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 972 struct drm_file *file_priv); 973 extern void i915_mem_takedown(struct mem_block **heap); 974 extern void i915_mem_release(struct drm_device * dev, 975 struct drm_file *file_priv, struct mem_block *heap); 976 /* i915_gem.c */ 977 int i915_gem_check_is_wedged(struct drm_device *dev); 978 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 979 struct drm_file *file_priv); 980 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 981 struct drm_file *file_priv); 982 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 983 struct drm_file *file_priv); 984 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 985 struct drm_file *file_priv); 986 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 987 struct drm_file *file_priv); 988 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 989 struct drm_file *file_priv); 990 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 991 struct drm_file *file_priv); 992 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 993 struct drm_file *file_priv); 994 int i915_gem_execbuffer(struct drm_device *dev, void *data, 995 struct drm_file *file_priv); 996 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 997 struct drm_file *file_priv); 998 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 999 struct drm_file *file_priv); 1000 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1001 struct drm_file *file_priv); 1002 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1003 struct drm_file *file_priv); 1004 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1005 struct drm_file *file_priv); 1006 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1007 struct drm_file *file_priv); 1008 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1009 struct drm_file *file_priv); 1010 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1011 struct drm_file *file_priv); 1012 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1013 struct drm_file *file_priv); 1014 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1015 struct drm_file *file_priv); 1016 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1017 struct drm_file *file_priv); 1018 void i915_gem_load(struct drm_device *dev); 1019 int i915_gem_init_object(struct drm_gem_object *obj); 1020 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, 1021 size_t size); 1022 void i915_gem_free_object(struct drm_gem_object *obj); 1023 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 1024 void i915_gem_object_unpin(struct drm_gem_object *obj); 1025 int i915_gem_object_unbind(struct drm_gem_object *obj); 1026 void i915_gem_release_mmap(struct drm_gem_object *obj); 1027 void i915_gem_lastclose(struct drm_device *dev); 1028 1029 /** 1030 * Returns true if seq1 is later than seq2. 1031 */ 1032 static inline bool 1033 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1034 { 1035 return (int32_t)(seq1 - seq2) >= 0; 1036 } 1037 1038 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, 1039 bool interruptible); 1040 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj, 1041 bool interruptible); 1042 void i915_gem_retire_requests(struct drm_device *dev); 1043 void i915_gem_reset(struct drm_device *dev); 1044 void i915_gem_clflush_object(struct drm_gem_object *obj); 1045 int i915_gem_object_set_domain(struct drm_gem_object *obj, 1046 uint32_t read_domains, 1047 uint32_t write_domain); 1048 int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, 1049 bool interruptible); 1050 int i915_gem_init_ringbuffer(struct drm_device *dev); 1051 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1052 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1053 unsigned long end); 1054 int i915_gpu_idle(struct drm_device *dev); 1055 int i915_gem_idle(struct drm_device *dev); 1056 uint32_t i915_add_request(struct drm_device *dev, 1057 struct drm_file *file_priv, 1058 struct drm_i915_gem_request *request, 1059 struct intel_ring_buffer *ring); 1060 int i915_do_wait_request(struct drm_device *dev, 1061 uint32_t seqno, 1062 bool interruptible, 1063 struct intel_ring_buffer *ring); 1064 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1065 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 1066 int write); 1067 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, 1068 bool pipelined); 1069 int i915_gem_attach_phys_object(struct drm_device *dev, 1070 struct drm_gem_object *obj, 1071 int id, 1072 int align); 1073 void i915_gem_detach_phys_object(struct drm_device *dev, 1074 struct drm_gem_object *obj); 1075 void i915_gem_free_all_phys_object(struct drm_device *dev); 1076 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); 1077 1078 void i915_gem_shrinker_init(void); 1079 void i915_gem_shrinker_exit(void); 1080 1081 /* i915_gem_evict.c */ 1082 int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); 1083 int i915_gem_evict_everything(struct drm_device *dev); 1084 int i915_gem_evict_inactive(struct drm_device *dev); 1085 1086 /* i915_gem_tiling.c */ 1087 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1088 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 1089 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 1090 bool i915_tiling_ok(struct drm_device *dev, int stride, int size, 1091 int tiling_mode); 1092 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, 1093 int tiling_mode); 1094 1095 /* i915_gem_debug.c */ 1096 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 1097 const char *where, uint32_t mark); 1098 #if WATCH_LISTS 1099 int i915_verify_lists(struct drm_device *dev); 1100 #else 1101 #define i915_verify_lists(dev) 0 1102 #endif 1103 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 1104 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 1105 const char *where, uint32_t mark); 1106 1107 /* i915_debugfs.c */ 1108 int i915_debugfs_init(struct drm_minor *minor); 1109 void i915_debugfs_cleanup(struct drm_minor *minor); 1110 1111 /* i915_suspend.c */ 1112 extern int i915_save_state(struct drm_device *dev); 1113 extern int i915_restore_state(struct drm_device *dev); 1114 1115 /* i915_suspend.c */ 1116 extern int i915_save_state(struct drm_device *dev); 1117 extern int i915_restore_state(struct drm_device *dev); 1118 1119 /* intel_i2c.c */ 1120 extern int intel_setup_gmbus(struct drm_device *dev); 1121 extern void intel_teardown_gmbus(struct drm_device *dev); 1122 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1123 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1124 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1125 { 1126 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1127 } 1128 extern void intel_i2c_reset(struct drm_device *dev); 1129 1130 /* intel_opregion.c */ 1131 extern int intel_opregion_setup(struct drm_device *dev); 1132 #ifdef CONFIG_ACPI 1133 extern void intel_opregion_init(struct drm_device *dev); 1134 extern void intel_opregion_fini(struct drm_device *dev); 1135 extern void intel_opregion_asle_intr(struct drm_device *dev); 1136 extern void intel_opregion_gse_intr(struct drm_device *dev); 1137 extern void intel_opregion_enable_asle(struct drm_device *dev); 1138 #else 1139 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1140 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1141 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1142 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1143 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1144 #endif 1145 1146 /* intel_acpi.c */ 1147 #ifdef CONFIG_ACPI 1148 extern void intel_register_dsm_handler(void); 1149 extern void intel_unregister_dsm_handler(void); 1150 #else 1151 static inline void intel_register_dsm_handler(void) { return; } 1152 static inline void intel_unregister_dsm_handler(void) { return; } 1153 #endif /* CONFIG_ACPI */ 1154 1155 /* modesetting */ 1156 extern void intel_modeset_init(struct drm_device *dev); 1157 extern void intel_modeset_cleanup(struct drm_device *dev); 1158 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1159 extern void i8xx_disable_fbc(struct drm_device *dev); 1160 extern void g4x_disable_fbc(struct drm_device *dev); 1161 extern void ironlake_disable_fbc(struct drm_device *dev); 1162 extern void intel_disable_fbc(struct drm_device *dev); 1163 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 1164 extern bool intel_fbc_enabled(struct drm_device *dev); 1165 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1166 extern void intel_detect_pch (struct drm_device *dev); 1167 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 1168 1169 /* overlay */ 1170 #ifdef CONFIG_DEBUG_FS 1171 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1172 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1173 #endif 1174 1175 /** 1176 * Lock test for when it's just for synchronization of ring access. 1177 * 1178 * In that case, we don't need to do it when GEM is initialized as nobody else 1179 * has access to the ring. 1180 */ 1181 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 1182 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ 1183 == NULL) \ 1184 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 1185 } while (0) 1186 1187 static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg) 1188 { 1189 u32 val; 1190 1191 val = readl(dev_priv->regs + reg); 1192 if (dev_priv->debug_flags & I915_DEBUG_READ) 1193 printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg); 1194 return val; 1195 } 1196 1197 static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 1198 u32 val) 1199 { 1200 writel(val, dev_priv->regs + reg); 1201 if (dev_priv->debug_flags & I915_DEBUG_WRITE) 1202 printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg); 1203 } 1204 1205 #define I915_READ(reg) i915_read(dev_priv, (reg)) 1206 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val)) 1207 #define I915_READ16(reg) readw(dev_priv->regs + (reg)) 1208 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) 1209 #define I915_READ8(reg) readb(dev_priv->regs + (reg)) 1210 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) 1211 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) 1212 #define I915_READ64(reg) readq(dev_priv->regs + (reg)) 1213 #define POSTING_READ(reg) (void)I915_READ(reg) 1214 #define POSTING_READ16(reg) (void)I915_READ16(reg) 1215 1216 #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \ 1217 I915_DEBUG_WRITE) 1218 #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \ 1219 I915_DEBUG_WRITE)) 1220 1221 #define I915_VERBOSE 0 1222 1223 #define BEGIN_LP_RING(n) do { \ 1224 drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1225 if (I915_VERBOSE) \ 1226 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ 1227 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ 1228 } while (0) 1229 1230 1231 #define OUT_RING(x) do { \ 1232 drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1233 if (I915_VERBOSE) \ 1234 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ 1235 intel_ring_emit(dev, &dev_priv__->render_ring, x); \ 1236 } while (0) 1237 1238 #define ADVANCE_LP_RING() do { \ 1239 drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1240 if (I915_VERBOSE) \ 1241 DRM_DEBUG("ADVANCE_LP_RING %x\n", \ 1242 dev_priv__->render_ring.tail); \ 1243 intel_ring_advance(dev, &dev_priv__->render_ring); \ 1244 } while(0) 1245 1246 /** 1247 * Reads a dword out of the status page, which is written to from the command 1248 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1249 * MI_STORE_DATA_IMM. 1250 * 1251 * The following dwords have a reserved meaning: 1252 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1253 * 0x04: ring 0 head pointer 1254 * 0x05: ring 1 head pointer (915-class) 1255 * 0x06: ring 2 head pointer (915-class) 1256 * 0x10-0x1b: Context status DWords (GM45) 1257 * 0x1f: Last written status offset. (GM45) 1258 * 1259 * The area from dword 0x20 to 0x3ff is available for driver usage. 1260 */ 1261 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ 1262 (dev_priv->render_ring.status_page.page_addr))[reg]) 1263 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1264 #define I915_GEM_HWS_INDEX 0x20 1265 #define I915_BREADCRUMB_INDEX 0x21 1266 1267 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1268 1269 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1270 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1271 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1272 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1273 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1274 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1275 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1276 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1277 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1278 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1279 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1280 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1281 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1282 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1283 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1284 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1285 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1286 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1287 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1288 1289 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1290 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1291 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1292 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1293 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1294 1295 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1296 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1297 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1298 1299 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1300 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1301 1302 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1303 * rows, which changed the alignment requirements and fence programming. 1304 */ 1305 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1306 IS_I915GM(dev))) 1307 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1308 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1309 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1310 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1311 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1312 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1313 /* dsparb controlled by hw only */ 1314 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1315 1316 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1317 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1318 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1319 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) 1320 1321 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) 1322 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) 1323 1324 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1325 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1326 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1327 1328 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1329 1330 #endif 1331