1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/dma-resv.h> 47 #include <linux/shmem_fs.h> 48 #include <linux/stackdepot.h> 49 50 #include <drm/intel-gtt.h> 51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 52 #include <drm/drm_gem.h> 53 #include <drm/drm_auth.h> 54 #include <drm/drm_cache.h> 55 #include <drm/drm_util.h> 56 #include <drm/drm_dsc.h> 57 #include <drm/drm_atomic.h> 58 #include <drm/drm_connector.h> 59 #include <drm/i915_mei_hdcp_interface.h> 60 61 #include "i915_fixed.h" 62 #include "i915_params.h" 63 #include "i915_reg.h" 64 #include "i915_utils.h" 65 66 #include "display/intel_bios.h" 67 #include "display/intel_display.h" 68 #include "display/intel_display_power.h" 69 #include "display/intel_dpll_mgr.h" 70 #include "display/intel_frontbuffer.h" 71 #include "display/intel_gmbus.h" 72 #include "display/intel_opregion.h" 73 74 #include "gem/i915_gem_context_types.h" 75 #include "gem/i915_gem_shrinker.h" 76 #include "gem/i915_gem_stolen.h" 77 78 #include "gt/intel_lrc.h" 79 #include "gt/intel_engine.h" 80 #include "gt/intel_gt_types.h" 81 #include "gt/intel_workarounds.h" 82 #include "gt/uc/intel_uc.h" 83 84 #include "intel_device_info.h" 85 #include "intel_pch.h" 86 #include "intel_runtime_pm.h" 87 #include "intel_uncore.h" 88 #include "intel_wakeref.h" 89 #include "intel_wopcm.h" 90 91 #include "i915_gem.h" 92 #include "i915_gem_fence_reg.h" 93 #include "i915_gem_gtt.h" 94 #include "i915_gpu_error.h" 95 #include "i915_request.h" 96 #include "i915_scheduler.h" 97 #include "gt/intel_timeline.h" 98 #include "i915_vma.h" 99 #include "i915_irq.h" 100 101 #include "intel_gvt.h" 102 103 /* General customization: 104 */ 105 106 #define DRIVER_NAME "i915" 107 #define DRIVER_DESC "Intel Graphics" 108 #define DRIVER_DATE "20190822" 109 #define DRIVER_TIMESTAMP 1566477988 110 111 struct drm_i915_gem_object; 112 113 enum hpd_pin { 114 HPD_NONE = 0, 115 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 116 HPD_CRT, 117 HPD_SDVO_B, 118 HPD_SDVO_C, 119 HPD_PORT_A, 120 HPD_PORT_B, 121 HPD_PORT_C, 122 HPD_PORT_D, 123 HPD_PORT_E, 124 HPD_PORT_F, 125 HPD_PORT_G, 126 HPD_PORT_H, 127 HPD_PORT_I, 128 129 HPD_NUM_PINS 130 }; 131 132 #define for_each_hpd_pin(__pin) \ 133 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 134 135 /* Threshold == 5 for long IRQs, 50 for short */ 136 #define HPD_STORM_DEFAULT_THRESHOLD 50 137 138 struct i915_hotplug { 139 struct delayed_work hotplug_work; 140 141 struct { 142 unsigned long last_jiffies; 143 int count; 144 enum { 145 HPD_ENABLED = 0, 146 HPD_DISABLED = 1, 147 HPD_MARK_DISABLED = 2 148 } state; 149 } stats[HPD_NUM_PINS]; 150 u32 event_bits; 151 u32 retry_bits; 152 struct delayed_work reenable_work; 153 154 u32 long_port_mask; 155 u32 short_port_mask; 156 struct work_struct dig_port_work; 157 158 struct work_struct poll_init_work; 159 bool poll_enabled; 160 161 unsigned int hpd_storm_threshold; 162 /* Whether or not to count short HPD IRQs in HPD storms */ 163 u8 hpd_short_storm_enabled; 164 165 /* 166 * if we get a HPD irq from DP and a HPD irq from non-DP 167 * the non-DP HPD could block the workqueue on a mode config 168 * mutex getting, that userspace may have taken. However 169 * userspace is waiting on the DP workqueue to run which is 170 * blocked behind the non-DP one. 171 */ 172 struct workqueue_struct *dp_wq; 173 }; 174 175 #define I915_GEM_GPU_DOMAINS \ 176 (I915_GEM_DOMAIN_RENDER | \ 177 I915_GEM_DOMAIN_SAMPLER | \ 178 I915_GEM_DOMAIN_COMMAND | \ 179 I915_GEM_DOMAIN_INSTRUCTION | \ 180 I915_GEM_DOMAIN_VERTEX) 181 182 struct drm_i915_private; 183 struct i915_mm_struct; 184 struct i915_mmu_object; 185 186 struct drm_i915_file_private { 187 struct drm_i915_private *dev_priv; 188 struct drm_file *file; 189 190 struct { 191 spinlock_t lock; 192 struct list_head request_list; 193 } mm; 194 195 struct idr context_idr; 196 struct mutex context_idr_lock; /* guards context_idr */ 197 198 struct idr vm_idr; 199 struct mutex vm_idr_lock; /* guards vm_idr */ 200 201 unsigned int bsd_engine; 202 203 /* 204 * Every context ban increments per client ban score. Also 205 * hangs in short succession increments ban score. If ban threshold 206 * is reached, client is considered banned and submitting more work 207 * will fail. This is a stop gap measure to limit the badly behaving 208 * clients access to gpu. Note that unbannable contexts never increment 209 * the client ban score. 210 */ 211 #define I915_CLIENT_SCORE_HANG_FAST 1 212 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 213 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 214 #define I915_CLIENT_SCORE_BANNED 9 215 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 216 atomic_t ban_score; 217 unsigned long hang_timestamp; 218 }; 219 220 /* Interface history: 221 * 222 * 1.1: Original. 223 * 1.2: Add Power Management 224 * 1.3: Add vblank support 225 * 1.4: Fix cmdbuffer path, add heap destroy 226 * 1.5: Add vblank pipe configuration 227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 228 * - Support vertical blank on secondary display pipe 229 */ 230 #define DRIVER_MAJOR 1 231 #define DRIVER_MINOR 6 232 #define DRIVER_PATCHLEVEL 0 233 234 struct intel_overlay; 235 struct intel_overlay_error_state; 236 237 struct sdvo_device_mapping { 238 u8 initialized; 239 u8 dvo_port; 240 u8 slave_addr; 241 u8 dvo_wiring; 242 u8 i2c_pin; 243 u8 ddc_pin; 244 }; 245 246 struct intel_connector; 247 struct intel_encoder; 248 struct intel_atomic_state; 249 struct intel_crtc_state; 250 struct intel_initial_plane_config; 251 struct intel_crtc; 252 struct intel_limit; 253 struct dpll; 254 struct intel_cdclk_state; 255 256 struct drm_i915_display_funcs { 257 void (*get_cdclk)(struct drm_i915_private *dev_priv, 258 struct intel_cdclk_state *cdclk_state); 259 void (*set_cdclk)(struct drm_i915_private *dev_priv, 260 const struct intel_cdclk_state *cdclk_state, 261 enum pipe pipe); 262 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 263 enum i9xx_plane_id i9xx_plane); 264 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 265 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 266 void (*initial_watermarks)(struct intel_atomic_state *state, 267 struct intel_crtc_state *crtc_state); 268 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 269 struct intel_crtc_state *crtc_state); 270 void (*optimize_watermarks)(struct intel_atomic_state *state, 271 struct intel_crtc_state *crtc_state); 272 int (*compute_global_watermarks)(struct intel_atomic_state *state); 273 void (*update_wm)(struct intel_crtc *crtc); 274 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 275 /* Returns the active state of the crtc, and if the crtc is active, 276 * fills out the pipe-config with the hw state. */ 277 bool (*get_pipe_config)(struct intel_crtc *, 278 struct intel_crtc_state *); 279 void (*get_initial_plane_config)(struct intel_crtc *, 280 struct intel_initial_plane_config *); 281 int (*crtc_compute_clock)(struct intel_crtc *crtc, 282 struct intel_crtc_state *crtc_state); 283 void (*crtc_enable)(struct intel_crtc_state *pipe_config, 284 struct intel_atomic_state *old_state); 285 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, 286 struct intel_atomic_state *old_state); 287 void (*update_crtcs)(struct intel_atomic_state *state); 288 void (*audio_codec_enable)(struct intel_encoder *encoder, 289 const struct intel_crtc_state *crtc_state, 290 const struct drm_connector_state *conn_state); 291 void (*audio_codec_disable)(struct intel_encoder *encoder, 292 const struct intel_crtc_state *old_crtc_state, 293 const struct drm_connector_state *old_conn_state); 294 void (*fdi_link_train)(struct intel_crtc *crtc, 295 const struct intel_crtc_state *crtc_state); 296 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 297 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 298 /* clock updates for mode set */ 299 /* cursor updates */ 300 /* render clock increase/decrease */ 301 /* display clock increase/decrease */ 302 /* pll clock increase/decrease */ 303 304 int (*color_check)(struct intel_crtc_state *crtc_state); 305 /* 306 * Program double buffered color management registers during 307 * vblank evasion. The registers should then latch during the 308 * next vblank start, alongside any other double buffered registers 309 * involved with the same commit. 310 */ 311 void (*color_commit)(const struct intel_crtc_state *crtc_state); 312 /* 313 * Load LUTs (and other single buffered color management 314 * registers). Will (hopefully) be called during the vblank 315 * following the latching of any double buffered registers 316 * involved with the same commit. 317 */ 318 void (*load_luts)(const struct intel_crtc_state *crtc_state); 319 void (*read_luts)(struct intel_crtc_state *crtc_state); 320 }; 321 322 struct intel_csr { 323 struct work_struct work; 324 const char *fw_path; 325 u32 required_version; 326 u32 max_fw_size; /* bytes */ 327 u32 *dmc_payload; 328 u32 dmc_fw_size; /* dwords */ 329 u32 version; 330 u32 mmio_count; 331 i915_reg_t mmioaddr[20]; 332 u32 mmiodata[20]; 333 u32 dc_state; 334 u32 allowed_dc_mask; 335 intel_wakeref_t wakeref; 336 }; 337 338 enum i915_cache_level { 339 I915_CACHE_NONE = 0, 340 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 341 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 342 caches, eg sampler/render caches, and the 343 large Last-Level-Cache. LLC is coherent with 344 the CPU, but L3 is only visible to the GPU. */ 345 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 346 }; 347 348 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 349 350 struct intel_fbc { 351 /* This is always the inner lock when overlapping with struct_mutex and 352 * it's the outer lock when overlapping with stolen_lock. */ 353 struct mutex lock; 354 unsigned threshold; 355 unsigned int possible_framebuffer_bits; 356 unsigned int busy_bits; 357 unsigned int visible_pipes_mask; 358 struct intel_crtc *crtc; 359 360 struct drm_mm_node compressed_fb; 361 struct drm_mm_node *compressed_llb; 362 363 bool false_color; 364 365 bool enabled; 366 bool active; 367 bool flip_pending; 368 369 bool underrun_detected; 370 struct work_struct underrun_work; 371 372 /* 373 * Due to the atomic rules we can't access some structures without the 374 * appropriate locking, so we cache information here in order to avoid 375 * these problems. 376 */ 377 struct intel_fbc_state_cache { 378 struct i915_vma *vma; 379 unsigned long flags; 380 381 struct { 382 unsigned int mode_flags; 383 u32 hsw_bdw_pixel_rate; 384 } crtc; 385 386 struct { 387 unsigned int rotation; 388 int src_w; 389 int src_h; 390 bool visible; 391 /* 392 * Display surface base address adjustement for 393 * pageflips. Note that on gen4+ this only adjusts up 394 * to a tile, offsets within a tile are handled in 395 * the hw itself (with the TILEOFF register). 396 */ 397 int adjusted_x; 398 int adjusted_y; 399 400 int y; 401 402 u16 pixel_blend_mode; 403 } plane; 404 405 struct { 406 const struct drm_format_info *format; 407 unsigned int stride; 408 } fb; 409 } state_cache; 410 411 /* 412 * This structure contains everything that's relevant to program the 413 * hardware registers. When we want to figure out if we need to disable 414 * and re-enable FBC for a new configuration we just check if there's 415 * something different in the struct. The genx_fbc_activate functions 416 * are supposed to read from it in order to program the registers. 417 */ 418 struct intel_fbc_reg_params { 419 struct i915_vma *vma; 420 unsigned long flags; 421 422 struct { 423 enum pipe pipe; 424 enum i9xx_plane_id i9xx_plane; 425 unsigned int fence_y_offset; 426 } crtc; 427 428 struct { 429 const struct drm_format_info *format; 430 unsigned int stride; 431 } fb; 432 433 int cfb_size; 434 unsigned int gen9_wa_cfb_stride; 435 } params; 436 437 const char *no_fbc_reason; 438 }; 439 440 /* 441 * HIGH_RR is the highest eDP panel refresh rate read from EDID 442 * LOW_RR is the lowest eDP panel refresh rate found from EDID 443 * parsing for same resolution. 444 */ 445 enum drrs_refresh_rate_type { 446 DRRS_HIGH_RR, 447 DRRS_LOW_RR, 448 DRRS_MAX_RR, /* RR count */ 449 }; 450 451 enum drrs_support_type { 452 DRRS_NOT_SUPPORTED = 0, 453 STATIC_DRRS_SUPPORT = 1, 454 SEAMLESS_DRRS_SUPPORT = 2 455 }; 456 457 struct intel_dp; 458 struct i915_drrs { 459 struct mutex mutex; 460 struct delayed_work work; 461 struct intel_dp *dp; 462 unsigned busy_frontbuffer_bits; 463 enum drrs_refresh_rate_type refresh_rate_type; 464 enum drrs_support_type type; 465 }; 466 467 struct i915_psr { 468 struct mutex lock; 469 470 #define I915_PSR_DEBUG_MODE_MASK 0x0f 471 #define I915_PSR_DEBUG_DEFAULT 0x00 472 #define I915_PSR_DEBUG_DISABLE 0x01 473 #define I915_PSR_DEBUG_ENABLE 0x02 474 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 475 #define I915_PSR_DEBUG_IRQ 0x10 476 477 u32 debug; 478 bool sink_support; 479 bool enabled; 480 struct intel_dp *dp; 481 enum pipe pipe; 482 bool active; 483 struct work_struct work; 484 unsigned busy_frontbuffer_bits; 485 bool sink_psr2_support; 486 bool link_standby; 487 bool colorimetry_support; 488 bool psr2_enabled; 489 u8 sink_sync_latency; 490 ktime_t last_entry_attempt; 491 ktime_t last_exit; 492 bool sink_not_reliable; 493 bool irq_aux_error; 494 u16 su_x_granularity; 495 }; 496 497 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 498 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 499 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 500 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 501 #define QUIRK_INCREASE_T12_DELAY (1<<6) 502 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 503 504 struct intel_fbdev; 505 struct intel_fbc_work; 506 507 struct intel_gmbus { 508 struct i2c_adapter adapter; 509 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 510 u32 force_bit; 511 u32 reg0; 512 i915_reg_t gpio_reg; 513 struct i2c_algo_bit_data bit_algo; 514 struct drm_i915_private *dev_priv; 515 }; 516 517 struct i915_suspend_saved_registers { 518 u32 saveDSPARB; 519 u32 saveFBC_CONTROL; 520 u32 saveCACHE_MODE_0; 521 u32 saveMI_ARB_STATE; 522 u32 saveSWF0[16]; 523 u32 saveSWF1[16]; 524 u32 saveSWF3[3]; 525 u64 saveFENCE[I915_MAX_NUM_FENCES]; 526 u32 savePCH_PORT_HOTPLUG; 527 u16 saveGCDGMBUS; 528 }; 529 530 struct vlv_s0ix_state; 531 532 struct intel_rps_ei { 533 ktime_t ktime; 534 u32 render_c0; 535 u32 media_c0; 536 }; 537 538 struct intel_rps { 539 struct mutex lock; /* protects enabling and the worker */ 540 541 /* 542 * work, interrupts_enabled and pm_iir are protected by 543 * dev_priv->irq_lock 544 */ 545 struct work_struct work; 546 bool interrupts_enabled; 547 u32 pm_iir; 548 549 /* PM interrupt bits that should never be masked */ 550 u32 pm_intrmsk_mbz; 551 552 /* Frequencies are stored in potentially platform dependent multiples. 553 * In other words, *_freq needs to be multiplied by X to be interesting. 554 * Soft limits are those which are used for the dynamic reclocking done 555 * by the driver (raise frequencies under heavy loads, and lower for 556 * lighter loads). Hard limits are those imposed by the hardware. 557 * 558 * A distinction is made for overclocking, which is never enabled by 559 * default, and is considered to be above the hard limit if it's 560 * possible at all. 561 */ 562 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 563 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 564 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 565 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 566 u8 min_freq; /* AKA RPn. Minimum frequency */ 567 u8 boost_freq; /* Frequency to request when wait boosting */ 568 u8 idle_freq; /* Frequency to request when we are idle */ 569 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 570 u8 rp1_freq; /* "less than" RP0 power/freqency */ 571 u8 rp0_freq; /* Non-overclocked max frequency. */ 572 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ 573 574 int last_adj; 575 576 struct { 577 struct mutex mutex; 578 579 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode; 580 unsigned int interactive; 581 582 u8 up_threshold; /* Current %busy required to uplock */ 583 u8 down_threshold; /* Current %busy required to downclock */ 584 } power; 585 586 bool enabled; 587 atomic_t num_waiters; 588 atomic_t boosts; 589 590 /* manual wa residency calculations */ 591 struct intel_rps_ei ei; 592 }; 593 594 struct intel_rc6 { 595 bool enabled; 596 u64 prev_hw_residency[4]; 597 u64 cur_residency[4]; 598 }; 599 600 struct intel_llc_pstate { 601 bool enabled; 602 }; 603 604 struct intel_gen6_power_mgmt { 605 struct intel_rps rps; 606 struct intel_rc6 rc6; 607 struct intel_llc_pstate llc_pstate; 608 }; 609 610 /* defined intel_pm.c */ 611 extern spinlock_t mchdev_lock; 612 613 struct intel_ilk_power_mgmt { 614 u8 cur_delay; 615 u8 min_delay; 616 u8 max_delay; 617 u8 fmax; 618 u8 fstart; 619 620 u64 last_count1; 621 unsigned long last_time1; 622 unsigned long chipset_power; 623 u64 last_count2; 624 u64 last_time2; 625 unsigned long gfx_power; 626 u8 corr; 627 628 int c_m; 629 int r_t; 630 }; 631 632 #define MAX_L3_SLICES 2 633 struct intel_l3_parity { 634 u32 *remap_info[MAX_L3_SLICES]; 635 struct work_struct error_work; 636 int which_slice; 637 }; 638 639 struct i915_gem_mm { 640 /** Memory allocator for GTT stolen memory */ 641 struct drm_mm stolen; 642 /** Protects the usage of the GTT stolen memory allocator. This is 643 * always the inner lock when overlapping with struct_mutex. */ 644 struct mutex stolen_lock; 645 646 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 647 spinlock_t obj_lock; 648 649 /** 650 * List of objects which are purgeable. 651 */ 652 struct list_head purge_list; 653 654 /** 655 * List of objects which have allocated pages and are shrinkable. 656 */ 657 struct list_head shrink_list; 658 659 /** 660 * List of objects which are pending destruction. 661 */ 662 struct llist_head free_list; 663 struct work_struct free_work; 664 /** 665 * Count of objects pending destructions. Used to skip needlessly 666 * waiting on an RCU barrier if no objects are waiting to be freed. 667 */ 668 atomic_t free_count; 669 670 /** 671 * Small stash of WC pages 672 */ 673 struct pagestash wc_stash; 674 675 /** 676 * tmpfs instance used for shmem backed objects 677 */ 678 struct vfsmount *gemfs; 679 680 struct notifier_block oom_notifier; 681 struct notifier_block vmap_notifier; 682 struct shrinker shrinker; 683 684 /** 685 * Workqueue to fault in userptr pages, flushed by the execbuf 686 * when required but otherwise left to userspace to try again 687 * on EAGAIN. 688 */ 689 struct workqueue_struct *userptr_wq; 690 691 /** Bit 6 swizzling required for X tiling */ 692 u32 bit_6_swizzle_x; 693 /** Bit 6 swizzling required for Y tiling */ 694 u32 bit_6_swizzle_y; 695 696 /* shrinker accounting, also useful for userland debugging */ 697 u64 shrink_memory; 698 u32 shrink_count; 699 }; 700 701 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 702 703 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 704 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 705 706 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 707 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 708 709 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 710 711 struct ddi_vbt_port_info { 712 /* Non-NULL if port present. */ 713 const struct child_device_config *child; 714 715 int max_tmds_clock; 716 717 /* 718 * This is an index in the HDMI/DVI DDI buffer translation table. 719 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 720 * populate this field. 721 */ 722 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 723 u8 hdmi_level_shift; 724 725 u8 supports_dvi:1; 726 u8 supports_hdmi:1; 727 u8 supports_dp:1; 728 u8 supports_edp:1; 729 u8 supports_typec_usb:1; 730 u8 supports_tbt:1; 731 732 u8 alternate_aux_channel; 733 u8 alternate_ddc_pin; 734 735 u8 dp_boost_level; 736 u8 hdmi_boost_level; 737 int dp_max_link_rate; /* 0 for not limited by VBT */ 738 }; 739 740 enum psr_lines_to_wait { 741 PSR_0_LINES_TO_WAIT = 0, 742 PSR_1_LINE_TO_WAIT, 743 PSR_4_LINES_TO_WAIT, 744 PSR_8_LINES_TO_WAIT 745 }; 746 747 struct intel_vbt_data { 748 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 749 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 750 751 /* Feature bits */ 752 unsigned int int_tv_support:1; 753 unsigned int lvds_dither:1; 754 unsigned int int_crt_support:1; 755 unsigned int lvds_use_ssc:1; 756 unsigned int int_lvds_support:1; 757 unsigned int display_clock_mode:1; 758 unsigned int fdi_rx_polarity_inverted:1; 759 unsigned int panel_type:4; 760 int lvds_ssc_freq; 761 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 762 enum drm_panel_orientation orientation; 763 764 enum drrs_support_type drrs_type; 765 766 struct { 767 int rate; 768 int lanes; 769 int preemphasis; 770 int vswing; 771 bool low_vswing; 772 bool initialized; 773 int bpp; 774 struct edp_power_seq pps; 775 } edp; 776 777 struct { 778 bool enable; 779 bool full_link; 780 bool require_aux_wakeup; 781 int idle_frames; 782 enum psr_lines_to_wait lines_to_wait; 783 int tp1_wakeup_time_us; 784 int tp2_tp3_wakeup_time_us; 785 int psr2_tp2_tp3_wakeup_time_us; 786 } psr; 787 788 struct { 789 u16 pwm_freq_hz; 790 bool present; 791 bool active_low_pwm; 792 u8 min_brightness; /* min_brightness/255 of max */ 793 u8 controller; /* brightness controller number */ 794 enum intel_backlight_type type; 795 } backlight; 796 797 /* MIPI DSI */ 798 struct { 799 u16 panel_id; 800 struct mipi_config *config; 801 struct mipi_pps_data *pps; 802 u16 bl_ports; 803 u16 cabc_ports; 804 u8 seq_version; 805 u32 size; 806 u8 *data; 807 const u8 *sequence[MIPI_SEQ_MAX]; 808 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 809 enum drm_panel_orientation orientation; 810 } dsi; 811 812 int crt_ddc_pin; 813 814 int child_dev_num; 815 struct child_device_config *child_dev; 816 817 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 818 struct sdvo_device_mapping sdvo_mappings[2]; 819 }; 820 821 enum intel_ddb_partitioning { 822 INTEL_DDB_PART_1_2, 823 INTEL_DDB_PART_5_6, /* IVB+ */ 824 }; 825 826 struct intel_wm_level { 827 bool enable; 828 u32 pri_val; 829 u32 spr_val; 830 u32 cur_val; 831 u32 fbc_val; 832 }; 833 834 struct ilk_wm_values { 835 u32 wm_pipe[3]; 836 u32 wm_lp[3]; 837 u32 wm_lp_spr[3]; 838 u32 wm_linetime[3]; 839 bool enable_fbc_wm; 840 enum intel_ddb_partitioning partitioning; 841 }; 842 843 struct g4x_pipe_wm { 844 u16 plane[I915_MAX_PLANES]; 845 u16 fbc; 846 }; 847 848 struct g4x_sr_wm { 849 u16 plane; 850 u16 cursor; 851 u16 fbc; 852 }; 853 854 struct vlv_wm_ddl_values { 855 u8 plane[I915_MAX_PLANES]; 856 }; 857 858 struct vlv_wm_values { 859 struct g4x_pipe_wm pipe[3]; 860 struct g4x_sr_wm sr; 861 struct vlv_wm_ddl_values ddl[3]; 862 u8 level; 863 bool cxsr; 864 }; 865 866 struct g4x_wm_values { 867 struct g4x_pipe_wm pipe[2]; 868 struct g4x_sr_wm sr; 869 struct g4x_sr_wm hpll; 870 bool cxsr; 871 bool hpll_en; 872 bool fbc_en; 873 }; 874 875 struct skl_ddb_entry { 876 u16 start, end; /* in number of blocks, 'end' is exclusive */ 877 }; 878 879 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 880 { 881 return entry->end - entry->start; 882 } 883 884 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 885 const struct skl_ddb_entry *e2) 886 { 887 if (e1->start == e2->start && e1->end == e2->end) 888 return true; 889 890 return false; 891 } 892 893 struct skl_ddb_allocation { 894 u8 enabled_slices; /* GEN11 has configurable 2 slices */ 895 }; 896 897 struct skl_ddb_values { 898 unsigned dirty_pipes; 899 struct skl_ddb_allocation ddb; 900 }; 901 902 struct skl_wm_level { 903 u16 min_ddb_alloc; 904 u16 plane_res_b; 905 u8 plane_res_l; 906 bool plane_en; 907 bool ignore_lines; 908 }; 909 910 /* Stores plane specific WM parameters */ 911 struct skl_wm_params { 912 bool x_tiled, y_tiled; 913 bool rc_surface; 914 bool is_planar; 915 u32 width; 916 u8 cpp; 917 u32 plane_pixel_rate; 918 u32 y_min_scanlines; 919 u32 plane_bytes_per_line; 920 uint_fixed_16_16_t plane_blocks_per_line; 921 uint_fixed_16_16_t y_tile_minimum; 922 u32 linetime_us; 923 u32 dbuf_block_size; 924 }; 925 926 enum intel_pipe_crc_source { 927 INTEL_PIPE_CRC_SOURCE_NONE, 928 INTEL_PIPE_CRC_SOURCE_PLANE1, 929 INTEL_PIPE_CRC_SOURCE_PLANE2, 930 INTEL_PIPE_CRC_SOURCE_PLANE3, 931 INTEL_PIPE_CRC_SOURCE_PLANE4, 932 INTEL_PIPE_CRC_SOURCE_PLANE5, 933 INTEL_PIPE_CRC_SOURCE_PLANE6, 934 INTEL_PIPE_CRC_SOURCE_PLANE7, 935 INTEL_PIPE_CRC_SOURCE_PIPE, 936 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 937 INTEL_PIPE_CRC_SOURCE_TV, 938 INTEL_PIPE_CRC_SOURCE_DP_B, 939 INTEL_PIPE_CRC_SOURCE_DP_C, 940 INTEL_PIPE_CRC_SOURCE_DP_D, 941 INTEL_PIPE_CRC_SOURCE_AUTO, 942 INTEL_PIPE_CRC_SOURCE_MAX, 943 }; 944 945 #define INTEL_PIPE_CRC_ENTRIES_NR 128 946 struct intel_pipe_crc { 947 spinlock_t lock; 948 int skipped; 949 enum intel_pipe_crc_source source; 950 }; 951 952 struct i915_frontbuffer_tracking { 953 spinlock_t lock; 954 955 /* 956 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 957 * scheduled flips. 958 */ 959 unsigned busy_bits; 960 unsigned flip_bits; 961 }; 962 963 struct i915_virtual_gpu { 964 bool active; 965 u32 caps; 966 }; 967 968 /* used in computing the new watermarks state */ 969 struct intel_wm_config { 970 unsigned int num_pipes_active; 971 bool sprites_enabled; 972 bool sprites_scaled; 973 }; 974 975 struct i915_oa_format { 976 u32 format; 977 int size; 978 }; 979 980 struct i915_oa_reg { 981 i915_reg_t addr; 982 u32 value; 983 }; 984 985 struct i915_oa_config { 986 char uuid[UUID_STRING_LEN + 1]; 987 int id; 988 989 const struct i915_oa_reg *mux_regs; 990 u32 mux_regs_len; 991 const struct i915_oa_reg *b_counter_regs; 992 u32 b_counter_regs_len; 993 const struct i915_oa_reg *flex_regs; 994 u32 flex_regs_len; 995 996 struct attribute_group sysfs_metric; 997 struct attribute *attrs[2]; 998 struct device_attribute sysfs_metric_id; 999 1000 atomic_t ref_count; 1001 }; 1002 1003 struct i915_perf_stream; 1004 1005 /** 1006 * struct i915_perf_stream_ops - the OPs to support a specific stream type 1007 */ 1008 struct i915_perf_stream_ops { 1009 /** 1010 * @enable: Enables the collection of HW samples, either in response to 1011 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened 1012 * without `I915_PERF_FLAG_DISABLED`. 1013 */ 1014 void (*enable)(struct i915_perf_stream *stream); 1015 1016 /** 1017 * @disable: Disables the collection of HW samples, either in response 1018 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying 1019 * the stream. 1020 */ 1021 void (*disable)(struct i915_perf_stream *stream); 1022 1023 /** 1024 * @poll_wait: Call poll_wait, passing a wait queue that will be woken 1025 * once there is something ready to read() for the stream 1026 */ 1027 void (*poll_wait)(struct i915_perf_stream *stream, 1028 struct file *file, 1029 poll_table *wait); 1030 1031 /** 1032 * @wait_unlocked: For handling a blocking read, wait until there is 1033 * something to ready to read() for the stream. E.g. wait on the same 1034 * wait queue that would be passed to poll_wait(). 1035 */ 1036 int (*wait_unlocked)(struct i915_perf_stream *stream); 1037 1038 /** 1039 * @read: Copy buffered metrics as records to userspace 1040 * **buf**: the userspace, destination buffer 1041 * **count**: the number of bytes to copy, requested by userspace 1042 * **offset**: zero at the start of the read, updated as the read 1043 * proceeds, it represents how many bytes have been copied so far and 1044 * the buffer offset for copying the next record. 1045 * 1046 * Copy as many buffered i915 perf samples and records for this stream 1047 * to userspace as will fit in the given buffer. 1048 * 1049 * Only write complete records; returning -%ENOSPC if there isn't room 1050 * for a complete record. 1051 * 1052 * Return any error condition that results in a short read such as 1053 * -%ENOSPC or -%EFAULT, even though these may be squashed before 1054 * returning to userspace. 1055 */ 1056 int (*read)(struct i915_perf_stream *stream, 1057 char __user *buf, 1058 size_t count, 1059 size_t *offset); 1060 1061 /** 1062 * @destroy: Cleanup any stream specific resources. 1063 * 1064 * The stream will always be disabled before this is called. 1065 */ 1066 void (*destroy)(struct i915_perf_stream *stream); 1067 }; 1068 1069 /** 1070 * struct i915_perf_stream - state for a single open stream FD 1071 */ 1072 struct i915_perf_stream { 1073 /** 1074 * @dev_priv: i915 drm device 1075 */ 1076 struct drm_i915_private *dev_priv; 1077 1078 /** 1079 * @link: Links the stream into ``&drm_i915_private->streams`` 1080 */ 1081 struct list_head link; 1082 1083 /** 1084 * @wakeref: As we keep the device awake while the perf stream is 1085 * active, we track our runtime pm reference for later release. 1086 */ 1087 intel_wakeref_t wakeref; 1088 1089 /** 1090 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` 1091 * properties given when opening a stream, representing the contents 1092 * of a single sample as read() by userspace. 1093 */ 1094 u32 sample_flags; 1095 1096 /** 1097 * @sample_size: Considering the configured contents of a sample 1098 * combined with the required header size, this is the total size 1099 * of a single sample record. 1100 */ 1101 int sample_size; 1102 1103 /** 1104 * @ctx: %NULL if measuring system-wide across all contexts or a 1105 * specific context that is being monitored. 1106 */ 1107 struct i915_gem_context *ctx; 1108 1109 /** 1110 * @enabled: Whether the stream is currently enabled, considering 1111 * whether the stream was opened in a disabled state and based 1112 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. 1113 */ 1114 bool enabled; 1115 1116 /** 1117 * @ops: The callbacks providing the implementation of this specific 1118 * type of configured stream. 1119 */ 1120 const struct i915_perf_stream_ops *ops; 1121 1122 /** 1123 * @oa_config: The OA configuration used by the stream. 1124 */ 1125 struct i915_oa_config *oa_config; 1126 1127 /** 1128 * The OA context specific information. 1129 */ 1130 struct intel_context *pinned_ctx; 1131 u32 specific_ctx_id; 1132 u32 specific_ctx_id_mask; 1133 1134 struct hrtimer poll_check_timer; 1135 wait_queue_head_t poll_wq; 1136 bool pollin; 1137 1138 bool periodic; 1139 int period_exponent; 1140 1141 /** 1142 * State of the OA buffer. 1143 */ 1144 struct { 1145 struct i915_vma *vma; 1146 u8 *vaddr; 1147 u32 last_ctx_id; 1148 int format; 1149 int format_size; 1150 int size_exponent; 1151 1152 /** 1153 * Locks reads and writes to all head/tail state 1154 * 1155 * Consider: the head and tail pointer state needs to be read 1156 * consistently from a hrtimer callback (atomic context) and 1157 * read() fop (user context) with tail pointer updates happening 1158 * in atomic context and head updates in user context and the 1159 * (unlikely) possibility of read() errors needing to reset all 1160 * head/tail state. 1161 * 1162 * Note: Contention/performance aren't currently a significant 1163 * concern here considering the relatively low frequency of 1164 * hrtimer callbacks (5ms period) and that reads typically only 1165 * happen in response to a hrtimer event and likely complete 1166 * before the next callback. 1167 * 1168 * Note: This lock is not held *while* reading and copying data 1169 * to userspace so the value of head observed in htrimer 1170 * callbacks won't represent any partial consumption of data. 1171 */ 1172 spinlock_t ptr_lock; 1173 1174 /** 1175 * One 'aging' tail pointer and one 'aged' tail pointer ready to 1176 * used for reading. 1177 * 1178 * Initial values of 0xffffffff are invalid and imply that an 1179 * update is required (and should be ignored by an attempted 1180 * read) 1181 */ 1182 struct { 1183 u32 offset; 1184 } tails[2]; 1185 1186 /** 1187 * Index for the aged tail ready to read() data up to. 1188 */ 1189 unsigned int aged_tail_idx; 1190 1191 /** 1192 * A monotonic timestamp for when the current aging tail pointer 1193 * was read; used to determine when it is old enough to trust. 1194 */ 1195 u64 aging_timestamp; 1196 1197 /** 1198 * Although we can always read back the head pointer register, 1199 * we prefer to avoid trusting the HW state, just to avoid any 1200 * risk that some hardware condition could * somehow bump the 1201 * head pointer unpredictably and cause us to forward the wrong 1202 * OA buffer data to userspace. 1203 */ 1204 u32 head; 1205 } oa_buffer; 1206 }; 1207 1208 /** 1209 * struct i915_oa_ops - Gen specific implementation of an OA unit stream 1210 */ 1211 struct i915_oa_ops { 1212 /** 1213 * @is_valid_b_counter_reg: Validates register's address for 1214 * programming boolean counters for a particular platform. 1215 */ 1216 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, 1217 u32 addr); 1218 1219 /** 1220 * @is_valid_mux_reg: Validates register's address for programming mux 1221 * for a particular platform. 1222 */ 1223 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); 1224 1225 /** 1226 * @is_valid_flex_reg: Validates register's address for programming 1227 * flex EU filtering for a particular platform. 1228 */ 1229 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); 1230 1231 /** 1232 * @enable_metric_set: Selects and applies any MUX configuration to set 1233 * up the Boolean and Custom (B/C) counters that are part of the 1234 * counter reports being sampled. May apply system constraints such as 1235 * disabling EU clock gating as required. 1236 */ 1237 int (*enable_metric_set)(struct i915_perf_stream *stream); 1238 1239 /** 1240 * @disable_metric_set: Remove system constraints associated with using 1241 * the OA unit. 1242 */ 1243 void (*disable_metric_set)(struct i915_perf_stream *stream); 1244 1245 /** 1246 * @oa_enable: Enable periodic sampling 1247 */ 1248 void (*oa_enable)(struct i915_perf_stream *stream); 1249 1250 /** 1251 * @oa_disable: Disable periodic sampling 1252 */ 1253 void (*oa_disable)(struct i915_perf_stream *stream); 1254 1255 /** 1256 * @read: Copy data from the circular OA buffer into a given userspace 1257 * buffer. 1258 */ 1259 int (*read)(struct i915_perf_stream *stream, 1260 char __user *buf, 1261 size_t count, 1262 size_t *offset); 1263 1264 /** 1265 * @oa_hw_tail_read: read the OA tail pointer register 1266 * 1267 * In particular this enables us to share all the fiddly code for 1268 * handling the OA unit tail pointer race that affects multiple 1269 * generations. 1270 */ 1271 u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); 1272 }; 1273 1274 struct intel_cdclk_state { 1275 unsigned int cdclk, vco, ref, bypass; 1276 u8 voltage_level; 1277 }; 1278 1279 struct drm_i915_private { 1280 struct drm_device drm; 1281 1282 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 1283 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 1284 struct intel_driver_caps caps; 1285 1286 /** 1287 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 1288 * end of stolen which we can optionally use to create GEM objects 1289 * backed by stolen memory. Note that stolen_usable_size tells us 1290 * exactly how much of this we are actually allowed to use, given that 1291 * some portion of it is in fact reserved for use by hardware functions. 1292 */ 1293 struct resource dsm; 1294 /** 1295 * Reseved portion of Data Stolen Memory 1296 */ 1297 struct resource dsm_reserved; 1298 1299 /* 1300 * Stolen memory is segmented in hardware with different portions 1301 * offlimits to certain functions. 1302 * 1303 * The drm_mm is initialised to the total accessible range, as found 1304 * from the PCI config. On Broadwell+, this is further restricted to 1305 * avoid the first page! The upper end of stolen memory is reserved for 1306 * hardware functions and similarly removed from the accessible range. 1307 */ 1308 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 1309 1310 struct intel_uncore uncore; 1311 struct intel_uncore_mmio_debug mmio_debug; 1312 1313 struct i915_virtual_gpu vgpu; 1314 1315 struct intel_gvt *gvt; 1316 1317 struct intel_wopcm wopcm; 1318 1319 struct intel_csr csr; 1320 1321 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 1322 1323 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1324 * controller on different i2c buses. */ 1325 struct mutex gmbus_mutex; 1326 1327 /** 1328 * Base address of where the gmbus and gpio blocks are located (either 1329 * on PCH or on SoC for platforms without PCH). 1330 */ 1331 u32 gpio_mmio_base; 1332 1333 /* MMIO base address for MIPI regs */ 1334 u32 mipi_mmio_base; 1335 1336 u32 psr_mmio_base; 1337 1338 u32 pps_mmio_base; 1339 1340 wait_queue_head_t gmbus_wait_queue; 1341 1342 struct pci_dev *bridge_dev; 1343 1344 /* Context used internally to idle the GPU and setup initial state */ 1345 struct i915_gem_context *kernel_context; 1346 1347 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 1348 struct rb_root uabi_engines; 1349 1350 struct resource mch_res; 1351 1352 /* protects the irq masks */ 1353 spinlock_t irq_lock; 1354 1355 bool display_irqs_enabled; 1356 1357 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1358 struct pm_qos_request pm_qos; 1359 1360 /* Sideband mailbox protection */ 1361 struct mutex sb_lock; 1362 struct pm_qos_request sb_qos; 1363 1364 /** Cached value of IMR to avoid reads in updating the bitfield */ 1365 union { 1366 u32 irq_mask; 1367 u32 de_irq_mask[I915_MAX_PIPES]; 1368 }; 1369 u32 pm_rps_events; 1370 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1371 1372 struct i915_hotplug hotplug; 1373 struct intel_fbc fbc; 1374 struct i915_drrs drrs; 1375 struct intel_opregion opregion; 1376 struct intel_vbt_data vbt; 1377 1378 bool preserve_bios_swizzle; 1379 1380 /* overlay */ 1381 struct intel_overlay *overlay; 1382 1383 /* backlight registers and fields in struct intel_panel */ 1384 struct mutex backlight_lock; 1385 1386 /* protects panel power sequencer state */ 1387 struct mutex pps_mutex; 1388 1389 unsigned int fsb_freq, mem_freq, is_ddr3; 1390 unsigned int skl_preferred_vco_freq; 1391 unsigned int max_cdclk_freq; 1392 1393 unsigned int max_dotclk_freq; 1394 unsigned int rawclk_freq; 1395 unsigned int hpll_freq; 1396 unsigned int fdi_pll_freq; 1397 unsigned int czclk_freq; 1398 1399 struct { 1400 /* 1401 * The current logical cdclk state. 1402 * See intel_atomic_state.cdclk.logical 1403 * 1404 * For reading holding any crtc lock is sufficient, 1405 * for writing must hold all of them. 1406 */ 1407 struct intel_cdclk_state logical; 1408 /* 1409 * The current actual cdclk state. 1410 * See intel_atomic_state.cdclk.actual 1411 */ 1412 struct intel_cdclk_state actual; 1413 /* The current hardware cdclk state */ 1414 struct intel_cdclk_state hw; 1415 1416 int force_min_cdclk; 1417 } cdclk; 1418 1419 /** 1420 * wq - Driver workqueue for GEM. 1421 * 1422 * NOTE: Work items scheduled here are not allowed to grab any modeset 1423 * locks, for otherwise the flushing done in the pageflip code will 1424 * result in deadlocks. 1425 */ 1426 struct workqueue_struct *wq; 1427 1428 /* ordered wq for modesets */ 1429 struct workqueue_struct *modeset_wq; 1430 1431 /* Display functions */ 1432 struct drm_i915_display_funcs display; 1433 1434 /* PCH chipset type */ 1435 enum intel_pch pch_type; 1436 unsigned short pch_id; 1437 1438 unsigned long quirks; 1439 1440 struct drm_atomic_state *modeset_restore_state; 1441 struct drm_modeset_acquire_ctx reset_ctx; 1442 1443 struct i915_ggtt ggtt; /* VM representing the global address space */ 1444 1445 struct i915_gem_mm mm; 1446 DECLARE_HASHTABLE(mm_structs, 7); 1447 struct mutex mm_lock; 1448 1449 /* Kernel Modesetting */ 1450 1451 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1452 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1453 1454 #ifdef CONFIG_DEBUG_FS 1455 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1456 #endif 1457 1458 /* dpll and cdclk state is protected by connection_mutex */ 1459 int num_shared_dpll; 1460 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1461 const struct intel_dpll_mgr *dpll_mgr; 1462 1463 /* 1464 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1465 * Must be global rather than per dpll, because on some platforms 1466 * plls share registers. 1467 */ 1468 struct mutex dpll_lock; 1469 1470 unsigned int active_crtcs; 1471 /* minimum acceptable cdclk for each pipe */ 1472 int min_cdclk[I915_MAX_PIPES]; 1473 /* minimum acceptable voltage level for each pipe */ 1474 u8 min_voltage_level[I915_MAX_PIPES]; 1475 1476 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1477 1478 struct i915_wa_list gt_wa_list; 1479 1480 struct i915_frontbuffer_tracking fb_tracking; 1481 1482 struct intel_atomic_helper { 1483 struct llist_head free_list; 1484 struct work_struct free_work; 1485 } atomic_helper; 1486 1487 u16 orig_clock; 1488 1489 bool mchbar_need_disable; 1490 1491 struct intel_l3_parity l3_parity; 1492 1493 /* 1494 * edram size in MB. 1495 * Cannot be determined by PCIID. You must always read a register. 1496 */ 1497 u32 edram_size_mb; 1498 1499 /* gen6+ GT PM state */ 1500 struct intel_gen6_power_mgmt gt_pm; 1501 1502 /* ilk-only ips/rps state. Everything in here is protected by the global 1503 * mchdev_lock in intel_pm.c */ 1504 struct intel_ilk_power_mgmt ips; 1505 1506 struct i915_power_domains power_domains; 1507 1508 struct i915_psr psr; 1509 1510 struct i915_gpu_error gpu_error; 1511 1512 struct drm_i915_gem_object *vlv_pctx; 1513 1514 /* list of fbdev register on this device */ 1515 struct intel_fbdev *fbdev; 1516 struct work_struct fbdev_suspend_work; 1517 1518 struct drm_property *broadcast_rgb_property; 1519 struct drm_property *force_audio_property; 1520 1521 /* hda/i915 audio component */ 1522 struct i915_audio_component *audio_component; 1523 bool audio_component_registered; 1524 /** 1525 * av_mutex - mutex for audio/video sync 1526 * 1527 */ 1528 struct mutex av_mutex; 1529 int audio_power_refcount; 1530 1531 struct { 1532 struct mutex mutex; 1533 struct list_head list; 1534 struct llist_head free_list; 1535 struct work_struct free_work; 1536 1537 /* The hw wants to have a stable context identifier for the 1538 * lifetime of the context (for OA, PASID, faults, etc). 1539 * This is limited in execlists to 21 bits. 1540 */ 1541 struct ida hw_ida; 1542 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 1543 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 1544 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ 1545 /* in Gen12 ID 0x7FF is reserved to indicate idle */ 1546 #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 1547 struct list_head hw_id_list; 1548 } contexts; 1549 1550 u32 fdi_rx_config; 1551 1552 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1553 u32 chv_phy_control; 1554 /* 1555 * Shadows for CHV DPLL_MD regs to keep the state 1556 * checker somewhat working in the presence hardware 1557 * crappiness (can't read out DPLL_MD for pipes B & C). 1558 */ 1559 u32 chv_dpll_md[I915_MAX_PIPES]; 1560 u32 bxt_phy_grc; 1561 1562 u32 suspend_count; 1563 bool power_domains_suspended; 1564 struct i915_suspend_saved_registers regfile; 1565 struct vlv_s0ix_state *vlv_s0ix_state; 1566 1567 enum { 1568 I915_SAGV_UNKNOWN = 0, 1569 I915_SAGV_DISABLED, 1570 I915_SAGV_ENABLED, 1571 I915_SAGV_NOT_CONTROLLED 1572 } sagv_status; 1573 1574 struct { 1575 /* 1576 * Raw watermark latency values: 1577 * in 0.1us units for WM0, 1578 * in 0.5us units for WM1+. 1579 */ 1580 /* primary */ 1581 u16 pri_latency[5]; 1582 /* sprite */ 1583 u16 spr_latency[5]; 1584 /* cursor */ 1585 u16 cur_latency[5]; 1586 /* 1587 * Raw watermark memory latency values 1588 * for SKL for all 8 levels 1589 * in 1us units. 1590 */ 1591 u16 skl_latency[8]; 1592 1593 /* current hardware state */ 1594 union { 1595 struct ilk_wm_values hw; 1596 struct skl_ddb_values skl_hw; 1597 struct vlv_wm_values vlv; 1598 struct g4x_wm_values g4x; 1599 }; 1600 1601 u8 max_level; 1602 1603 /* 1604 * Should be held around atomic WM register writing; also 1605 * protects * intel_crtc->wm.active and 1606 * crtc_state->wm.need_postvbl_update. 1607 */ 1608 struct mutex wm_mutex; 1609 1610 /* 1611 * Set during HW readout of watermarks/DDB. Some platforms 1612 * need to know when we're still using BIOS-provided values 1613 * (which we don't fully trust). 1614 */ 1615 bool distrust_bios_wm; 1616 } wm; 1617 1618 struct dram_info { 1619 bool valid; 1620 bool is_16gb_dimm; 1621 u8 num_channels; 1622 u8 ranks; 1623 u32 bandwidth_kbps; 1624 bool symmetric_memory; 1625 enum intel_dram_type { 1626 INTEL_DRAM_UNKNOWN, 1627 INTEL_DRAM_DDR3, 1628 INTEL_DRAM_DDR4, 1629 INTEL_DRAM_LPDDR3, 1630 INTEL_DRAM_LPDDR4 1631 } type; 1632 } dram_info; 1633 1634 struct intel_bw_info { 1635 unsigned int deratedbw[3]; /* for each QGV point */ 1636 u8 num_qgv_points; 1637 u8 num_planes; 1638 } max_bw[6]; 1639 1640 struct drm_private_obj bw_obj; 1641 1642 struct intel_runtime_pm runtime_pm; 1643 1644 struct { 1645 bool initialized; 1646 1647 struct kobject *metrics_kobj; 1648 struct ctl_table_header *sysctl_header; 1649 1650 /* 1651 * Lock associated with adding/modifying/removing OA configs 1652 * in dev_priv->perf.metrics_idr. 1653 */ 1654 struct mutex metrics_lock; 1655 1656 /* 1657 * List of dynamic configurations, you need to hold 1658 * dev_priv->perf.metrics_lock to access it. 1659 */ 1660 struct idr metrics_idr; 1661 1662 /* 1663 * Lock associated with anything below within this structure 1664 * except exclusive_stream. 1665 */ 1666 struct mutex lock; 1667 struct list_head streams; 1668 1669 /* 1670 * The stream currently using the OA unit. If accessed 1671 * outside a syscall associated to its file 1672 * descriptor, you need to hold 1673 * dev_priv->drm.struct_mutex. 1674 */ 1675 struct i915_perf_stream *exclusive_stream; 1676 1677 /** 1678 * For rate limiting any notifications of spurious 1679 * invalid OA reports 1680 */ 1681 struct ratelimit_state spurious_report_rs; 1682 1683 struct i915_oa_config test_config; 1684 1685 u32 gen7_latched_oastatus1; 1686 u32 ctx_oactxctrl_offset; 1687 u32 ctx_flexeu0_offset; 1688 1689 /** 1690 * The RPT_ID/reason field for Gen8+ includes a bit 1691 * to determine if the CTX ID in the report is valid 1692 * but the specific bit differs between Gen 8 and 9 1693 */ 1694 u32 gen8_valid_ctx_bit; 1695 1696 struct i915_oa_ops ops; 1697 const struct i915_oa_format *oa_formats; 1698 } perf; 1699 1700 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1701 struct intel_gt gt; 1702 1703 struct { 1704 struct notifier_block pm_notifier; 1705 1706 /** 1707 * We leave the user IRQ off as much as possible, 1708 * but this means that requests will finish and never 1709 * be retired once the system goes idle. Set a timer to 1710 * fire periodically while the ring is running. When it 1711 * fires, go retire requests. 1712 */ 1713 struct delayed_work retire_work; 1714 1715 /** 1716 * When we detect an idle GPU, we want to turn on 1717 * powersaving features. So once we see that there 1718 * are no more requests outstanding and no more 1719 * arrive within a small period of time, we fire 1720 * off the idle_work. 1721 */ 1722 struct work_struct idle_work; 1723 } gem; 1724 1725 /* For i945gm vblank irq vs. C3 workaround */ 1726 struct { 1727 struct work_struct work; 1728 struct pm_qos_request pm_qos; 1729 u8 c3_disable_latency; 1730 u8 enabled; 1731 } i945gm_vblank; 1732 1733 /* perform PHY state sanity checks? */ 1734 bool chv_phy_assert[2]; 1735 1736 bool ipc_enabled; 1737 1738 /* Used to save the pipe-to-encoder mapping for audio */ 1739 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1740 1741 /* necessary resource sharing with HDMI LPE audio driver. */ 1742 struct { 1743 struct platform_device *platdev; 1744 int irq; 1745 } lpe_audio; 1746 1747 struct i915_pmu pmu; 1748 1749 struct i915_hdcp_comp_master *hdcp_master; 1750 bool hdcp_comp_added; 1751 1752 /* Mutex to protect the above hdcp component related values. */ 1753 struct mutex hdcp_comp_mutex; 1754 1755 /* 1756 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1757 * will be rejected. Instead look for a better place. 1758 */ 1759 }; 1760 1761 struct dram_dimm_info { 1762 u8 size, width, ranks; 1763 }; 1764 1765 struct dram_channel_info { 1766 struct dram_dimm_info dimm_l, dimm_s; 1767 u8 ranks; 1768 bool is_16gb_dimm; 1769 }; 1770 1771 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1772 { 1773 return container_of(dev, struct drm_i915_private, drm); 1774 } 1775 1776 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1777 { 1778 return dev_get_drvdata(kdev); 1779 } 1780 1781 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1782 { 1783 return pci_get_drvdata(pdev); 1784 } 1785 1786 /* Simple iterator over all initialised engines */ 1787 #define for_each_engine(engine__, dev_priv__, id__) \ 1788 for ((id__) = 0; \ 1789 (id__) < I915_NUM_ENGINES; \ 1790 (id__)++) \ 1791 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1792 1793 /* Iterator over subset of engines selected by mask */ 1794 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ 1795 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \ 1796 (tmp__) ? \ 1797 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1798 0;) 1799 1800 #define rb_to_uabi_engine(rb) \ 1801 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1802 1803 #define for_each_uabi_engine(engine__, i915__) \ 1804 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1805 (engine__); \ 1806 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1807 1808 #define I915_GTT_OFFSET_NONE ((u32)-1) 1809 1810 /* 1811 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1812 * considered to be the frontbuffer for the given plane interface-wise. This 1813 * doesn't mean that the hw necessarily already scans it out, but that any 1814 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1815 * 1816 * We have one bit per pipe and per scanout plane type. 1817 */ 1818 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1819 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1820 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1821 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1822 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1823 }) 1824 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1825 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1826 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1827 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1828 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1829 1830 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1831 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1832 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1833 1834 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1835 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1836 1837 #define REVID_FOREVER 0xff 1838 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1839 1840 #define INTEL_GEN_MASK(s, e) ( \ 1841 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1842 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1843 GENMASK((e) - 1, (s) - 1)) 1844 1845 /* Returns true if Gen is in inclusive range [Start, End] */ 1846 #define IS_GEN_RANGE(dev_priv, s, e) \ 1847 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1848 1849 #define IS_GEN(dev_priv, n) \ 1850 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1851 INTEL_INFO(dev_priv)->gen == (n)) 1852 1853 /* 1854 * Return true if revision is in range [since,until] inclusive. 1855 * 1856 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1857 */ 1858 #define IS_REVID(p, since, until) \ 1859 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1860 1861 static __always_inline unsigned int 1862 __platform_mask_index(const struct intel_runtime_info *info, 1863 enum intel_platform p) 1864 { 1865 const unsigned int pbits = 1866 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1867 1868 /* Expand the platform_mask array if this fails. */ 1869 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1870 pbits * ARRAY_SIZE(info->platform_mask)); 1871 1872 return p / pbits; 1873 } 1874 1875 static __always_inline unsigned int 1876 __platform_mask_bit(const struct intel_runtime_info *info, 1877 enum intel_platform p) 1878 { 1879 const unsigned int pbits = 1880 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1881 1882 return p % pbits + INTEL_SUBPLATFORM_BITS; 1883 } 1884 1885 static inline u32 1886 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1887 { 1888 const unsigned int pi = __platform_mask_index(info, p); 1889 1890 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1891 } 1892 1893 static __always_inline bool 1894 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1895 { 1896 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1897 const unsigned int pi = __platform_mask_index(info, p); 1898 const unsigned int pb = __platform_mask_bit(info, p); 1899 1900 BUILD_BUG_ON(!__builtin_constant_p(p)); 1901 1902 return info->platform_mask[pi] & BIT(pb); 1903 } 1904 1905 static __always_inline bool 1906 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1907 enum intel_platform p, unsigned int s) 1908 { 1909 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1910 const unsigned int pi = __platform_mask_index(info, p); 1911 const unsigned int pb = __platform_mask_bit(info, p); 1912 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1913 const u32 mask = info->platform_mask[pi]; 1914 1915 BUILD_BUG_ON(!__builtin_constant_p(p)); 1916 BUILD_BUG_ON(!__builtin_constant_p(s)); 1917 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1918 1919 /* Shift and test on the MSB position so sign flag can be used. */ 1920 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1921 } 1922 1923 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1924 1925 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1926 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1927 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1928 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1929 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1930 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1931 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1932 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1933 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1934 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1935 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1936 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1937 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1938 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1939 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1940 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1941 #define IS_IRONLAKE_M(dev_priv) \ 1942 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1943 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1944 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1945 INTEL_INFO(dev_priv)->gt == 1) 1946 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1947 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1948 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1949 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1950 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1951 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1952 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1953 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1954 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1955 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1956 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1957 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1958 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1959 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1960 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1961 #define IS_BDW_ULT(dev_priv) \ 1962 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1963 #define IS_BDW_ULX(dev_priv) \ 1964 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1965 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1966 INTEL_INFO(dev_priv)->gt == 3) 1967 #define IS_HSW_ULT(dev_priv) \ 1968 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1969 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1970 INTEL_INFO(dev_priv)->gt == 3) 1971 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1972 INTEL_INFO(dev_priv)->gt == 1) 1973 /* ULX machines are also considered ULT. */ 1974 #define IS_HSW_ULX(dev_priv) \ 1975 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1976 #define IS_SKL_ULT(dev_priv) \ 1977 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1978 #define IS_SKL_ULX(dev_priv) \ 1979 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1980 #define IS_KBL_ULT(dev_priv) \ 1981 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1982 #define IS_KBL_ULX(dev_priv) \ 1983 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1984 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1985 INTEL_INFO(dev_priv)->gt == 2) 1986 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1987 INTEL_INFO(dev_priv)->gt == 3) 1988 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1989 INTEL_INFO(dev_priv)->gt == 4) 1990 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1991 INTEL_INFO(dev_priv)->gt == 2) 1992 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1993 INTEL_INFO(dev_priv)->gt == 3) 1994 #define IS_CFL_ULT(dev_priv) \ 1995 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1996 #define IS_CFL_ULX(dev_priv) \ 1997 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1998 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1999 INTEL_INFO(dev_priv)->gt == 2) 2000 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2001 INTEL_INFO(dev_priv)->gt == 3) 2002 #define IS_CNL_WITH_PORT_F(dev_priv) \ 2003 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 2004 #define IS_ICL_WITH_PORT_F(dev_priv) \ 2005 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 2006 2007 #define SKL_REVID_A0 0x0 2008 #define SKL_REVID_B0 0x1 2009 #define SKL_REVID_C0 0x2 2010 #define SKL_REVID_D0 0x3 2011 #define SKL_REVID_E0 0x4 2012 #define SKL_REVID_F0 0x5 2013 #define SKL_REVID_G0 0x6 2014 #define SKL_REVID_H0 0x7 2015 2016 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 2017 2018 #define BXT_REVID_A0 0x0 2019 #define BXT_REVID_A1 0x1 2020 #define BXT_REVID_B0 0x3 2021 #define BXT_REVID_B_LAST 0x8 2022 #define BXT_REVID_C0 0x9 2023 2024 #define IS_BXT_REVID(dev_priv, since, until) \ 2025 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 2026 2027 #define KBL_REVID_A0 0x0 2028 #define KBL_REVID_B0 0x1 2029 #define KBL_REVID_C0 0x2 2030 #define KBL_REVID_D0 0x3 2031 #define KBL_REVID_E0 0x4 2032 2033 #define IS_KBL_REVID(dev_priv, since, until) \ 2034 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 2035 2036 #define GLK_REVID_A0 0x0 2037 #define GLK_REVID_A1 0x1 2038 2039 #define IS_GLK_REVID(dev_priv, since, until) \ 2040 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 2041 2042 #define CNL_REVID_A0 0x0 2043 #define CNL_REVID_B0 0x1 2044 #define CNL_REVID_C0 0x2 2045 2046 #define IS_CNL_REVID(p, since, until) \ 2047 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 2048 2049 #define ICL_REVID_A0 0x0 2050 #define ICL_REVID_A2 0x1 2051 #define ICL_REVID_B0 0x3 2052 #define ICL_REVID_B2 0x4 2053 #define ICL_REVID_C0 0x5 2054 2055 #define IS_ICL_REVID(p, since, until) \ 2056 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 2057 2058 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 2059 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 2060 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 2061 2062 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 2063 2064 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 2065 unsigned int first__ = (first); \ 2066 unsigned int count__ = (count); \ 2067 (INTEL_INFO(dev_priv)->engine_mask & \ 2068 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 2069 }) 2070 #define VDBOX_MASK(dev_priv) \ 2071 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 2072 #define VEBOX_MASK(dev_priv) \ 2073 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 2074 2075 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 2076 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 2077 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 2078 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 2079 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 2080 2081 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 2082 2083 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 2084 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 2085 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 2086 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 2087 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 2088 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 2089 2090 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 2091 2092 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 2093 #define HAS_PPGTT(dev_priv) \ 2094 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 2095 #define HAS_FULL_PPGTT(dev_priv) \ 2096 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 2097 2098 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 2099 GEM_BUG_ON((sizes) == 0); \ 2100 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 2101 }) 2102 2103 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 2104 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 2105 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 2106 2107 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2108 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 2109 2110 /* WaRsDisableCoarsePowerGating:skl,cnl */ 2111 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 2112 (IS_CANNONLAKE(dev_priv) || \ 2113 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) 2114 2115 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 2116 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 2117 IS_GEMINILAKE(dev_priv) || \ 2118 IS_KABYLAKE(dev_priv)) 2119 2120 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2121 * rows, which changed the alignment requirements and fence programming. 2122 */ 2123 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 2124 !(IS_I915G(dev_priv) || \ 2125 IS_I915GM(dev_priv))) 2126 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 2127 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 2128 2129 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 2130 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 2131 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 2132 2133 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 2134 2135 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 2136 2137 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 2138 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 2139 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 2140 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) 2141 2142 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 2143 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 2144 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 2145 2146 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 2147 2148 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 2149 2150 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 2151 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 2152 2153 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 2154 2155 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 2156 2157 /* Having GuC is not the same as using GuC */ 2158 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) 2159 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) 2160 2161 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 2162 2163 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 2164 2165 2166 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 2167 2168 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 2169 2170 /* DPF == dynamic parity feature */ 2171 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 2172 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 2173 2 : HAS_L3_DPF(dev_priv)) 2174 2175 #define GT_FREQUENCY_MULTIPLIER 50 2176 #define GEN9_FREQ_SCALER 3 2177 2178 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0) 2179 2180 static inline bool intel_vtd_active(void) 2181 { 2182 #ifdef CONFIG_INTEL_IOMMU 2183 if (intel_iommu_gfx_mapped) 2184 return true; 2185 #endif 2186 return false; 2187 } 2188 2189 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 2190 { 2191 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 2192 } 2193 2194 static inline bool 2195 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 2196 { 2197 return IS_BROXTON(dev_priv) && intel_vtd_active(); 2198 } 2199 2200 /* i915_drv.c */ 2201 #ifdef CONFIG_COMPAT 2202 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 2203 #else 2204 #define i915_compat_ioctl NULL 2205 #endif 2206 extern const struct dev_pm_ops i915_pm_ops; 2207 2208 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 2209 void i915_driver_remove(struct drm_i915_private *i915); 2210 2211 void intel_engine_init_hangcheck(struct intel_engine_cs *engine); 2212 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2213 2214 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 2215 { 2216 return dev_priv->gvt; 2217 } 2218 2219 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 2220 { 2221 return dev_priv->vgpu.active; 2222 } 2223 2224 int i915_getparam_ioctl(struct drm_device *dev, void *data, 2225 struct drm_file *file_priv); 2226 2227 /* i915_gem.c */ 2228 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 2229 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 2230 void i915_gem_sanitize(struct drm_i915_private *i915); 2231 int i915_gem_init_early(struct drm_i915_private *dev_priv); 2232 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 2233 int i915_gem_freeze(struct drm_i915_private *dev_priv); 2234 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 2235 2236 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 2237 { 2238 /* 2239 * A single pass should suffice to release all the freed objects (along 2240 * most call paths) , but be a little more paranoid in that freeing 2241 * the objects does take a little amount of time, during which the rcu 2242 * callbacks could have added new objects into the freed list, and 2243 * armed the work again. 2244 */ 2245 while (atomic_read(&i915->mm.free_count)) { 2246 flush_work(&i915->mm.free_work); 2247 rcu_barrier(); 2248 } 2249 } 2250 2251 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 2252 { 2253 /* 2254 * Similar to objects above (see i915_gem_drain_freed-objects), in 2255 * general we have workers that are armed by RCU and then rearm 2256 * themselves in their callbacks. To be paranoid, we need to 2257 * drain the workqueue a second time after waiting for the RCU 2258 * grace period so that we catch work queued via RCU from the first 2259 * pass. As neither drain_workqueue() nor flush_workqueue() report 2260 * a result, we make an assumption that we only don't require more 2261 * than 3 passes to catch all _recursive_ RCU delayed work. 2262 * 2263 */ 2264 int pass = 3; 2265 do { 2266 flush_workqueue(i915->wq); 2267 rcu_barrier(); 2268 i915_gem_drain_freed_objects(i915); 2269 } while (--pass); 2270 drain_workqueue(i915->wq); 2271 } 2272 2273 struct i915_vma * __must_check 2274 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 2275 const struct i915_ggtt_view *view, 2276 u64 size, 2277 u64 alignment, 2278 u64 flags); 2279 2280 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 2281 unsigned long flags); 2282 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 2283 2284 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 2285 2286 static inline int __must_check 2287 i915_mutex_lock_interruptible(struct drm_device *dev) 2288 { 2289 return mutex_lock_interruptible(&dev->struct_mutex); 2290 } 2291 2292 int i915_gem_dumb_create(struct drm_file *file_priv, 2293 struct drm_device *dev, 2294 struct drm_mode_create_dumb *args); 2295 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2296 u32 handle, u64 *offset); 2297 int i915_gem_mmap_gtt_version(void); 2298 2299 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 2300 2301 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2302 { 2303 return atomic_read(&error->reset_count); 2304 } 2305 2306 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 2307 struct intel_engine_cs *engine) 2308 { 2309 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 2310 } 2311 2312 void i915_gem_init_mmio(struct drm_i915_private *i915); 2313 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 2314 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); 2315 void i915_gem_driver_register(struct drm_i915_private *i915); 2316 void i915_gem_driver_unregister(struct drm_i915_private *i915); 2317 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 2318 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 2319 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, 2320 unsigned int flags, long timeout); 2321 void i915_gem_suspend(struct drm_i915_private *dev_priv); 2322 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 2323 void i915_gem_resume(struct drm_i915_private *dev_priv); 2324 vm_fault_t i915_gem_fault(struct vm_fault *vmf); 2325 2326 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 2327 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2328 2329 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2330 enum i915_cache_level cache_level); 2331 2332 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2333 struct dma_buf *dma_buf); 2334 2335 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 2336 2337 static inline struct i915_gem_context * 2338 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 2339 { 2340 return idr_find(&file_priv->context_idr, id); 2341 } 2342 2343 static inline struct i915_gem_context * 2344 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 2345 { 2346 struct i915_gem_context *ctx; 2347 2348 rcu_read_lock(); 2349 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 2350 if (ctx && !kref_get_unless_zero(&ctx->ref)) 2351 ctx = NULL; 2352 rcu_read_unlock(); 2353 2354 return ctx; 2355 } 2356 2357 /* i915_gem_evict.c */ 2358 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 2359 u64 min_size, u64 alignment, 2360 unsigned cache_level, 2361 u64 start, u64 end, 2362 unsigned flags); 2363 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 2364 struct drm_mm_node *node, 2365 unsigned int flags); 2366 int i915_gem_evict_vm(struct i915_address_space *vm); 2367 2368 /* i915_gem_internal.c */ 2369 struct drm_i915_gem_object * 2370 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 2371 phys_addr_t size); 2372 2373 /* i915_gem_tiling.c */ 2374 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2375 { 2376 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 2377 2378 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2379 i915_gem_object_is_tiled(obj); 2380 } 2381 2382 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 2383 unsigned int tiling, unsigned int stride); 2384 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 2385 unsigned int tiling, unsigned int stride); 2386 2387 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 2388 2389 /* i915_cmd_parser.c */ 2390 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 2391 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 2392 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 2393 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 2394 struct drm_i915_gem_object *batch_obj, 2395 struct drm_i915_gem_object *shadow_batch_obj, 2396 u32 batch_start_offset, 2397 u32 batch_len, 2398 bool is_master); 2399 2400 /* intel_device_info.c */ 2401 static inline struct intel_device_info * 2402 mkwrite_device_info(struct drm_i915_private *dev_priv) 2403 { 2404 return (struct intel_device_info *)INTEL_INFO(dev_priv); 2405 } 2406 2407 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2408 struct drm_file *file); 2409 2410 #define __I915_REG_OP(op__, dev_priv__, ...) \ 2411 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 2412 2413 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 2414 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 2415 2416 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 2417 2418 /* These are untraced mmio-accessors that are only valid to be used inside 2419 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 2420 * controlled. 2421 * 2422 * Think twice, and think again, before using these. 2423 * 2424 * As an example, these accessors can possibly be used between: 2425 * 2426 * spin_lock_irq(&dev_priv->uncore.lock); 2427 * intel_uncore_forcewake_get__locked(); 2428 * 2429 * and 2430 * 2431 * intel_uncore_forcewake_put__locked(); 2432 * spin_unlock_irq(&dev_priv->uncore.lock); 2433 * 2434 * 2435 * Note: some registers may not need forcewake held, so 2436 * intel_uncore_forcewake_{get,put} can be omitted, see 2437 * intel_uncore_forcewake_for_reg(). 2438 * 2439 * Certain architectures will die if the same cacheline is concurrently accessed 2440 * by different clients (e.g. on Ivybridge). Access to registers should 2441 * therefore generally be serialised, by either the dev_priv->uncore.lock or 2442 * a more localised lock guarding all access to that bank of registers. 2443 */ 2444 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 2445 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 2446 2447 /* register wait wrappers for display regs */ 2448 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \ 2449 intel_wait_for_register(&(dev_priv_)->uncore, \ 2450 (reg_), (mask_), (value_), (timeout_)) 2451 2452 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \ 2453 u32 mask__ = (mask_); \ 2454 intel_de_wait_for_register((dev_priv_), (reg_), \ 2455 mask__, mask__, (timeout_)); \ 2456 }) 2457 2458 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ 2459 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_)) 2460 2461 /* i915_mm.c */ 2462 int remap_io_mapping(struct vm_area_struct *vma, 2463 unsigned long addr, unsigned long pfn, unsigned long size, 2464 struct io_mapping *iomap); 2465 2466 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 2467 { 2468 if (INTEL_GEN(i915) >= 10) 2469 return CNL_HWS_CSB_WRITE_INDEX; 2470 else 2471 return I915_HWS_CSB_WRITE_INDEX; 2472 } 2473 2474 static inline enum i915_map_type 2475 i915_coherent_map_type(struct drm_i915_private *i915) 2476 { 2477 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 2478 } 2479 2480 #endif 2481