1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include <linux/io-mapping.h> 36 37 /* General customization: 38 */ 39 40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 41 42 #define DRIVER_NAME "i915" 43 #define DRIVER_DESC "Intel Graphics" 44 #define DRIVER_DATE "20080730" 45 46 enum pipe { 47 PIPE_A = 0, 48 PIPE_B, 49 }; 50 51 enum plane { 52 PLANE_A = 0, 53 PLANE_B, 54 }; 55 56 #define I915_NUM_PIPE 2 57 58 /* Interface history: 59 * 60 * 1.1: Original. 61 * 1.2: Add Power Management 62 * 1.3: Add vblank support 63 * 1.4: Fix cmdbuffer path, add heap destroy 64 * 1.5: Add vblank pipe configuration 65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 66 * - Support vertical blank on secondary display pipe 67 */ 68 #define DRIVER_MAJOR 1 69 #define DRIVER_MINOR 6 70 #define DRIVER_PATCHLEVEL 0 71 72 #define WATCH_COHERENCY 0 73 #define WATCH_BUF 0 74 #define WATCH_EXEC 0 75 #define WATCH_LRU 0 76 #define WATCH_RELOC 0 77 #define WATCH_INACTIVE 0 78 #define WATCH_PWRITE 0 79 80 #define I915_GEM_PHYS_CURSOR_0 1 81 #define I915_GEM_PHYS_CURSOR_1 2 82 #define I915_GEM_PHYS_OVERLAY_REGS 3 83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 84 85 struct drm_i915_gem_phys_object { 86 int id; 87 struct page **page_list; 88 drm_dma_handle_t *handle; 89 struct drm_gem_object *cur_obj; 90 }; 91 92 typedef struct _drm_i915_ring_buffer { 93 unsigned long Size; 94 u8 *virtual_start; 95 int head; 96 int tail; 97 int space; 98 drm_local_map_t map; 99 struct drm_gem_object *ring_obj; 100 } drm_i915_ring_buffer_t; 101 102 struct mem_block { 103 struct mem_block *next; 104 struct mem_block *prev; 105 int start; 106 int size; 107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 108 }; 109 110 struct opregion_header; 111 struct opregion_acpi; 112 struct opregion_swsci; 113 struct opregion_asle; 114 115 struct intel_opregion { 116 struct opregion_header *header; 117 struct opregion_acpi *acpi; 118 struct opregion_swsci *swsci; 119 struct opregion_asle *asle; 120 int enabled; 121 }; 122 123 struct drm_i915_master_private { 124 drm_local_map_t *sarea; 125 struct _drm_i915_sarea *sarea_priv; 126 }; 127 #define I915_FENCE_REG_NONE -1 128 129 struct drm_i915_fence_reg { 130 struct drm_gem_object *obj; 131 }; 132 133 struct sdvo_device_mapping { 134 u8 dvo_port; 135 u8 slave_addr; 136 u8 dvo_wiring; 137 u8 initialized; 138 }; 139 140 struct drm_i915_error_state { 141 u32 eir; 142 u32 pgtbl_er; 143 u32 pipeastat; 144 u32 pipebstat; 145 u32 ipeir; 146 u32 ipehr; 147 u32 instdone; 148 u32 acthd; 149 u32 instpm; 150 u32 instps; 151 u32 instdone1; 152 u32 seqno; 153 struct timeval time; 154 }; 155 156 struct drm_i915_display_funcs { 157 void (*dpms)(struct drm_crtc *crtc, int mode); 158 bool (*fbc_enabled)(struct drm_crtc *crtc); 159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 160 void (*disable_fbc)(struct drm_device *dev); 161 int (*get_display_clock_speed)(struct drm_device *dev); 162 int (*get_fifo_size)(struct drm_device *dev, int plane); 163 void (*update_wm)(struct drm_device *dev, int planea_clock, 164 int planeb_clock, int sr_hdisplay, int pixel_size); 165 /* clock updates for mode set */ 166 /* cursor updates */ 167 /* render clock increase/decrease */ 168 /* display clock increase/decrease */ 169 /* pll clock increase/decrease */ 170 /* clock gating init */ 171 }; 172 173 struct intel_overlay; 174 175 struct intel_device_info { 176 u8 is_mobile : 1; 177 u8 is_i8xx : 1; 178 u8 is_i915g : 1; 179 u8 is_i9xx : 1; 180 u8 is_i945gm : 1; 181 u8 is_i965g : 1; 182 u8 is_i965gm : 1; 183 u8 is_g33 : 1; 184 u8 need_gfx_hws : 1; 185 u8 is_g4x : 1; 186 u8 is_pineview : 1; 187 u8 is_ironlake : 1; 188 u8 has_fbc : 1; 189 u8 has_rc6 : 1; 190 u8 has_pipe_cxsr : 1; 191 u8 has_hotplug : 1; 192 u8 cursor_needs_physical : 1; 193 }; 194 195 typedef struct drm_i915_private { 196 struct drm_device *dev; 197 198 const struct intel_device_info *info; 199 200 int has_gem; 201 202 void __iomem *regs; 203 204 struct pci_dev *bridge_dev; 205 drm_i915_ring_buffer_t ring; 206 207 drm_dma_handle_t *status_page_dmah; 208 void *hw_status_page; 209 dma_addr_t dma_status_page; 210 uint32_t counter; 211 unsigned int status_gfx_addr; 212 drm_local_map_t hws_map; 213 struct drm_gem_object *hws_obj; 214 struct drm_gem_object *pwrctx; 215 216 struct resource mch_res; 217 218 unsigned int cpp; 219 int back_offset; 220 int front_offset; 221 int current_page; 222 int page_flipping; 223 224 wait_queue_head_t irq_queue; 225 atomic_t irq_received; 226 /** Protects user_irq_refcount and irq_mask_reg */ 227 spinlock_t user_irq_lock; 228 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 229 int user_irq_refcount; 230 u32 trace_irq_seqno; 231 /** Cached value of IMR to avoid reads in updating the bitfield */ 232 u32 irq_mask_reg; 233 u32 pipestat[2]; 234 /** splitted irq regs for graphics and display engine on Ironlake, 235 irq_mask_reg is still used for display irq. */ 236 u32 gt_irq_mask_reg; 237 u32 gt_irq_enable_reg; 238 u32 de_irq_enable_reg; 239 u32 pch_irq_mask_reg; 240 u32 pch_irq_enable_reg; 241 242 u32 hotplug_supported_mask; 243 struct work_struct hotplug_work; 244 245 int tex_lru_log_granularity; 246 int allow_batchbuffer; 247 struct mem_block *agp_heap; 248 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 249 int vblank_pipe; 250 251 /* For hangcheck timer */ 252 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ 253 struct timer_list hangcheck_timer; 254 int hangcheck_count; 255 uint32_t last_acthd; 256 257 struct drm_mm vram; 258 259 unsigned long cfb_size; 260 unsigned long cfb_pitch; 261 int cfb_fence; 262 int cfb_plane; 263 264 int irq_enabled; 265 266 struct intel_opregion opregion; 267 268 /* overlay */ 269 struct intel_overlay *overlay; 270 271 /* LVDS info */ 272 int backlight_duty_cycle; /* restore backlight to this value */ 273 bool panel_wants_dither; 274 struct drm_display_mode *panel_fixed_mode; 275 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 276 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 277 278 /* Feature bits from the VBIOS */ 279 unsigned int int_tv_support:1; 280 unsigned int lvds_dither:1; 281 unsigned int lvds_vbt:1; 282 unsigned int int_crt_support:1; 283 unsigned int lvds_use_ssc:1; 284 unsigned int edp_support:1; 285 int lvds_ssc_freq; 286 int edp_bpp; 287 288 struct notifier_block lid_notifier; 289 290 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ 291 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 292 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 293 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 294 295 unsigned int fsb_freq, mem_freq; 296 297 spinlock_t error_lock; 298 struct drm_i915_error_state *first_error; 299 struct work_struct error_work; 300 struct workqueue_struct *wq; 301 302 /* Display functions */ 303 struct drm_i915_display_funcs display; 304 305 /* Register state */ 306 bool modeset_on_lid; 307 u8 saveLBB; 308 u32 saveDSPACNTR; 309 u32 saveDSPBCNTR; 310 u32 saveDSPARB; 311 u32 saveHWS; 312 u32 savePIPEACONF; 313 u32 savePIPEBCONF; 314 u32 savePIPEASRC; 315 u32 savePIPEBSRC; 316 u32 saveFPA0; 317 u32 saveFPA1; 318 u32 saveDPLL_A; 319 u32 saveDPLL_A_MD; 320 u32 saveHTOTAL_A; 321 u32 saveHBLANK_A; 322 u32 saveHSYNC_A; 323 u32 saveVTOTAL_A; 324 u32 saveVBLANK_A; 325 u32 saveVSYNC_A; 326 u32 saveBCLRPAT_A; 327 u32 saveTRANSACONF; 328 u32 saveTRANS_HTOTAL_A; 329 u32 saveTRANS_HBLANK_A; 330 u32 saveTRANS_HSYNC_A; 331 u32 saveTRANS_VTOTAL_A; 332 u32 saveTRANS_VBLANK_A; 333 u32 saveTRANS_VSYNC_A; 334 u32 savePIPEASTAT; 335 u32 saveDSPASTRIDE; 336 u32 saveDSPASIZE; 337 u32 saveDSPAPOS; 338 u32 saveDSPAADDR; 339 u32 saveDSPASURF; 340 u32 saveDSPATILEOFF; 341 u32 savePFIT_PGM_RATIOS; 342 u32 saveBLC_HIST_CTL; 343 u32 saveBLC_PWM_CTL; 344 u32 saveBLC_PWM_CTL2; 345 u32 saveBLC_CPU_PWM_CTL; 346 u32 saveBLC_CPU_PWM_CTL2; 347 u32 saveFPB0; 348 u32 saveFPB1; 349 u32 saveDPLL_B; 350 u32 saveDPLL_B_MD; 351 u32 saveHTOTAL_B; 352 u32 saveHBLANK_B; 353 u32 saveHSYNC_B; 354 u32 saveVTOTAL_B; 355 u32 saveVBLANK_B; 356 u32 saveVSYNC_B; 357 u32 saveBCLRPAT_B; 358 u32 saveTRANSBCONF; 359 u32 saveTRANS_HTOTAL_B; 360 u32 saveTRANS_HBLANK_B; 361 u32 saveTRANS_HSYNC_B; 362 u32 saveTRANS_VTOTAL_B; 363 u32 saveTRANS_VBLANK_B; 364 u32 saveTRANS_VSYNC_B; 365 u32 savePIPEBSTAT; 366 u32 saveDSPBSTRIDE; 367 u32 saveDSPBSIZE; 368 u32 saveDSPBPOS; 369 u32 saveDSPBADDR; 370 u32 saveDSPBSURF; 371 u32 saveDSPBTILEOFF; 372 u32 saveVGA0; 373 u32 saveVGA1; 374 u32 saveVGA_PD; 375 u32 saveVGACNTRL; 376 u32 saveADPA; 377 u32 saveLVDS; 378 u32 savePP_ON_DELAYS; 379 u32 savePP_OFF_DELAYS; 380 u32 saveDVOA; 381 u32 saveDVOB; 382 u32 saveDVOC; 383 u32 savePP_ON; 384 u32 savePP_OFF; 385 u32 savePP_CONTROL; 386 u32 savePP_DIVISOR; 387 u32 savePFIT_CONTROL; 388 u32 save_palette_a[256]; 389 u32 save_palette_b[256]; 390 u32 saveDPFC_CB_BASE; 391 u32 saveFBC_CFB_BASE; 392 u32 saveFBC_LL_BASE; 393 u32 saveFBC_CONTROL; 394 u32 saveFBC_CONTROL2; 395 u32 saveIER; 396 u32 saveIIR; 397 u32 saveIMR; 398 u32 saveDEIER; 399 u32 saveDEIMR; 400 u32 saveGTIER; 401 u32 saveGTIMR; 402 u32 saveFDI_RXA_IMR; 403 u32 saveFDI_RXB_IMR; 404 u32 saveCACHE_MODE_0; 405 u32 saveMI_ARB_STATE; 406 u32 saveSWF0[16]; 407 u32 saveSWF1[16]; 408 u32 saveSWF2[3]; 409 u8 saveMSR; 410 u8 saveSR[8]; 411 u8 saveGR[25]; 412 u8 saveAR_INDEX; 413 u8 saveAR[21]; 414 u8 saveDACMASK; 415 u8 saveCR[37]; 416 uint64_t saveFENCE[16]; 417 u32 saveCURACNTR; 418 u32 saveCURAPOS; 419 u32 saveCURABASE; 420 u32 saveCURBCNTR; 421 u32 saveCURBPOS; 422 u32 saveCURBBASE; 423 u32 saveCURSIZE; 424 u32 saveDP_B; 425 u32 saveDP_C; 426 u32 saveDP_D; 427 u32 savePIPEA_GMCH_DATA_M; 428 u32 savePIPEB_GMCH_DATA_M; 429 u32 savePIPEA_GMCH_DATA_N; 430 u32 savePIPEB_GMCH_DATA_N; 431 u32 savePIPEA_DP_LINK_M; 432 u32 savePIPEB_DP_LINK_M; 433 u32 savePIPEA_DP_LINK_N; 434 u32 savePIPEB_DP_LINK_N; 435 u32 saveFDI_RXA_CTL; 436 u32 saveFDI_TXA_CTL; 437 u32 saveFDI_RXB_CTL; 438 u32 saveFDI_TXB_CTL; 439 u32 savePFA_CTL_1; 440 u32 savePFB_CTL_1; 441 u32 savePFA_WIN_SZ; 442 u32 savePFB_WIN_SZ; 443 u32 savePFA_WIN_POS; 444 u32 savePFB_WIN_POS; 445 u32 savePCH_DREF_CONTROL; 446 u32 saveDISP_ARB_CTL; 447 u32 savePIPEA_DATA_M1; 448 u32 savePIPEA_DATA_N1; 449 u32 savePIPEA_LINK_M1; 450 u32 savePIPEA_LINK_N1; 451 u32 savePIPEB_DATA_M1; 452 u32 savePIPEB_DATA_N1; 453 u32 savePIPEB_LINK_M1; 454 u32 savePIPEB_LINK_N1; 455 456 struct { 457 struct drm_mm gtt_space; 458 459 struct io_mapping *gtt_mapping; 460 int gtt_mtrr; 461 462 /** 463 * Membership on list of all loaded devices, used to evict 464 * inactive buffers under memory pressure. 465 * 466 * Modifications should only be done whilst holding the 467 * shrink_list_lock spinlock. 468 */ 469 struct list_head shrink_list; 470 471 /** 472 * List of objects currently involved in rendering from the 473 * ringbuffer. 474 * 475 * Includes buffers having the contents of their GPU caches 476 * flushed, not necessarily primitives. last_rendering_seqno 477 * represents when the rendering involved will be completed. 478 * 479 * A reference is held on the buffer while on this list. 480 */ 481 spinlock_t active_list_lock; 482 struct list_head active_list; 483 484 /** 485 * List of objects which are not in the ringbuffer but which 486 * still have a write_domain which needs to be flushed before 487 * unbinding. 488 * 489 * last_rendering_seqno is 0 while an object is in this list. 490 * 491 * A reference is held on the buffer while on this list. 492 */ 493 struct list_head flushing_list; 494 495 /** 496 * List of objects currently pending a GPU write flush. 497 * 498 * All elements on this list will belong to either the 499 * active_list or flushing_list, last_rendering_seqno can 500 * be used to differentiate between the two elements. 501 */ 502 struct list_head gpu_write_list; 503 504 /** 505 * LRU list of objects which are not in the ringbuffer and 506 * are ready to unbind, but are still in the GTT. 507 * 508 * last_rendering_seqno is 0 while an object is in this list. 509 * 510 * A reference is not held on the buffer while on this list, 511 * as merely being GTT-bound shouldn't prevent its being 512 * freed, and we'll pull it off the list in the free path. 513 */ 514 struct list_head inactive_list; 515 516 /** LRU list of objects with fence regs on them. */ 517 struct list_head fence_list; 518 519 /** 520 * List of breadcrumbs associated with GPU requests currently 521 * outstanding. 522 */ 523 struct list_head request_list; 524 525 /** 526 * We leave the user IRQ off as much as possible, 527 * but this means that requests will finish and never 528 * be retired once the system goes idle. Set a timer to 529 * fire periodically while the ring is running. When it 530 * fires, go retire requests. 531 */ 532 struct delayed_work retire_work; 533 534 uint32_t next_gem_seqno; 535 536 /** 537 * Waiting sequence number, if any 538 */ 539 uint32_t waiting_gem_seqno; 540 541 /** 542 * Last seq seen at irq time 543 */ 544 uint32_t irq_gem_seqno; 545 546 /** 547 * Flag if the X Server, and thus DRM, is not currently in 548 * control of the device. 549 * 550 * This is set between LeaveVT and EnterVT. It needs to be 551 * replaced with a semaphore. It also needs to be 552 * transitioned away from for kernel modesetting. 553 */ 554 int suspended; 555 556 /** 557 * Flag if the hardware appears to be wedged. 558 * 559 * This is set when attempts to idle the device timeout. 560 * It prevents command submission from occuring and makes 561 * every pending request fail 562 */ 563 atomic_t wedged; 564 565 /** Bit 6 swizzling required for X tiling */ 566 uint32_t bit_6_swizzle_x; 567 /** Bit 6 swizzling required for Y tiling */ 568 uint32_t bit_6_swizzle_y; 569 570 /* storage for physical objects */ 571 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 572 } mm; 573 struct sdvo_device_mapping sdvo_mappings[2]; 574 /* indicate whether the LVDS_BORDER should be enabled or not */ 575 unsigned int lvds_border_bits; 576 577 struct drm_crtc *plane_to_crtc_mapping[2]; 578 struct drm_crtc *pipe_to_crtc_mapping[2]; 579 wait_queue_head_t pending_flip_queue; 580 581 /* Reclocking support */ 582 bool render_reclock_avail; 583 bool lvds_downclock_avail; 584 /* indicates the reduced downclock for LVDS*/ 585 int lvds_downclock; 586 struct work_struct idle_work; 587 struct timer_list idle_timer; 588 bool busy; 589 u16 orig_clock; 590 int child_dev_num; 591 struct child_device_config *child_dev; 592 struct drm_connector *int_lvds_connector; 593 } drm_i915_private_t; 594 595 /** driver private structure attached to each drm_gem_object */ 596 struct drm_i915_gem_object { 597 struct drm_gem_object *obj; 598 599 /** Current space allocated to this object in the GTT, if any. */ 600 struct drm_mm_node *gtt_space; 601 602 /** This object's place on the active/flushing/inactive lists */ 603 struct list_head list; 604 /** This object's place on GPU write list */ 605 struct list_head gpu_write_list; 606 607 /** This object's place on the fenced object LRU */ 608 struct list_head fence_list; 609 610 /** 611 * This is set if the object is on the active or flushing lists 612 * (has pending rendering), and is not set if it's on inactive (ready 613 * to be unbound). 614 */ 615 int active; 616 617 /** 618 * This is set if the object has been written to since last bound 619 * to the GTT 620 */ 621 int dirty; 622 623 /** AGP memory structure for our GTT binding. */ 624 DRM_AGP_MEM *agp_mem; 625 626 struct page **pages; 627 int pages_refcount; 628 629 /** 630 * Current offset of the object in GTT space. 631 * 632 * This is the same as gtt_space->start 633 */ 634 uint32_t gtt_offset; 635 636 /** 637 * Fake offset for use by mmap(2) 638 */ 639 uint64_t mmap_offset; 640 641 /** 642 * Fence register bits (if any) for this object. Will be set 643 * as needed when mapped into the GTT. 644 * Protected by dev->struct_mutex. 645 */ 646 int fence_reg; 647 648 /** How many users have pinned this object in GTT space */ 649 int pin_count; 650 651 /** Breadcrumb of last rendering to the buffer. */ 652 uint32_t last_rendering_seqno; 653 654 /** Current tiling mode for the object. */ 655 uint32_t tiling_mode; 656 uint32_t stride; 657 658 /** Record of address bit 17 of each page at last unbind. */ 659 long *bit_17; 660 661 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 662 uint32_t agp_type; 663 664 /** 665 * If present, while GEM_DOMAIN_CPU is in the read domain this array 666 * flags which individual pages are valid. 667 */ 668 uint8_t *page_cpu_valid; 669 670 /** User space pin count and filp owning the pin */ 671 uint32_t user_pin_count; 672 struct drm_file *pin_filp; 673 674 /** for phy allocated objects */ 675 struct drm_i915_gem_phys_object *phys_obj; 676 677 /** 678 * Used for checking the object doesn't appear more than once 679 * in an execbuffer object list. 680 */ 681 int in_execbuffer; 682 683 /** 684 * Advice: are the backing pages purgeable? 685 */ 686 int madv; 687 688 /** 689 * Number of crtcs where this object is currently the fb, but 690 * will be page flipped away on the next vblank. When it 691 * reaches 0, dev_priv->pending_flip_queue will be woken up. 692 */ 693 atomic_t pending_flip; 694 }; 695 696 /** 697 * Request queue structure. 698 * 699 * The request queue allows us to note sequence numbers that have been emitted 700 * and may be associated with active buffers to be retired. 701 * 702 * By keeping this list, we can avoid having to do questionable 703 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 704 * an emission time with seqnos for tracking how far ahead of the GPU we are. 705 */ 706 struct drm_i915_gem_request { 707 /** GEM sequence number associated with this request. */ 708 uint32_t seqno; 709 710 /** Time at which this request was emitted, in jiffies. */ 711 unsigned long emitted_jiffies; 712 713 /** global list entry for this request */ 714 struct list_head list; 715 716 /** file_priv list entry for this request */ 717 struct list_head client_list; 718 }; 719 720 struct drm_i915_file_private { 721 struct { 722 struct list_head request_list; 723 } mm; 724 }; 725 726 enum intel_chip_family { 727 CHIP_I8XX = 0x01, 728 CHIP_I9XX = 0x02, 729 CHIP_I915 = 0x04, 730 CHIP_I965 = 0x08, 731 }; 732 733 extern struct drm_ioctl_desc i915_ioctls[]; 734 extern int i915_max_ioctl; 735 extern unsigned int i915_fbpercrtc; 736 extern unsigned int i915_powersave; 737 extern unsigned int i915_lvds_downclock; 738 739 extern void i915_save_display(struct drm_device *dev); 740 extern void i915_restore_display(struct drm_device *dev); 741 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 742 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 743 744 /* i915_dma.c */ 745 extern void i915_kernel_lost_context(struct drm_device * dev); 746 extern int i915_driver_load(struct drm_device *, unsigned long flags); 747 extern int i915_driver_unload(struct drm_device *); 748 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 749 extern void i915_driver_lastclose(struct drm_device * dev); 750 extern void i915_driver_preclose(struct drm_device *dev, 751 struct drm_file *file_priv); 752 extern void i915_driver_postclose(struct drm_device *dev, 753 struct drm_file *file_priv); 754 extern int i915_driver_device_is_agp(struct drm_device * dev); 755 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 756 unsigned long arg); 757 extern int i915_emit_box(struct drm_device *dev, 758 struct drm_clip_rect *boxes, 759 int i, int DR1, int DR4); 760 extern int i965_reset(struct drm_device *dev, u8 flags); 761 762 /* i915_irq.c */ 763 void i915_hangcheck_elapsed(unsigned long data); 764 extern int i915_irq_emit(struct drm_device *dev, void *data, 765 struct drm_file *file_priv); 766 extern int i915_irq_wait(struct drm_device *dev, void *data, 767 struct drm_file *file_priv); 768 void i915_user_irq_get(struct drm_device *dev); 769 void i915_trace_irq_get(struct drm_device *dev, u32 seqno); 770 void i915_user_irq_put(struct drm_device *dev); 771 extern void i915_enable_interrupt (struct drm_device *dev); 772 773 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 774 extern void i915_driver_irq_preinstall(struct drm_device * dev); 775 extern int i915_driver_irq_postinstall(struct drm_device *dev); 776 extern void i915_driver_irq_uninstall(struct drm_device * dev); 777 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 778 struct drm_file *file_priv); 779 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 780 struct drm_file *file_priv); 781 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 782 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 783 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 784 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 785 extern int i915_vblank_swap(struct drm_device *dev, void *data, 786 struct drm_file *file_priv); 787 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 788 789 void 790 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 791 792 void 793 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 794 795 void intel_enable_asle (struct drm_device *dev); 796 797 798 /* i915_mem.c */ 799 extern int i915_mem_alloc(struct drm_device *dev, void *data, 800 struct drm_file *file_priv); 801 extern int i915_mem_free(struct drm_device *dev, void *data, 802 struct drm_file *file_priv); 803 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 804 struct drm_file *file_priv); 805 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 806 struct drm_file *file_priv); 807 extern void i915_mem_takedown(struct mem_block **heap); 808 extern void i915_mem_release(struct drm_device * dev, 809 struct drm_file *file_priv, struct mem_block *heap); 810 /* i915_gem.c */ 811 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 812 struct drm_file *file_priv); 813 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 814 struct drm_file *file_priv); 815 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 816 struct drm_file *file_priv); 817 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 818 struct drm_file *file_priv); 819 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 820 struct drm_file *file_priv); 821 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 822 struct drm_file *file_priv); 823 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 824 struct drm_file *file_priv); 825 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 826 struct drm_file *file_priv); 827 int i915_gem_execbuffer(struct drm_device *dev, void *data, 828 struct drm_file *file_priv); 829 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 830 struct drm_file *file_priv); 831 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 832 struct drm_file *file_priv); 833 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 834 struct drm_file *file_priv); 835 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 836 struct drm_file *file_priv); 837 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 838 struct drm_file *file_priv); 839 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 840 struct drm_file *file_priv); 841 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 842 struct drm_file *file_priv); 843 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 844 struct drm_file *file_priv); 845 int i915_gem_set_tiling(struct drm_device *dev, void *data, 846 struct drm_file *file_priv); 847 int i915_gem_get_tiling(struct drm_device *dev, void *data, 848 struct drm_file *file_priv); 849 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 850 struct drm_file *file_priv); 851 void i915_gem_load(struct drm_device *dev); 852 int i915_gem_init_object(struct drm_gem_object *obj); 853 void i915_gem_free_object(struct drm_gem_object *obj); 854 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 855 void i915_gem_object_unpin(struct drm_gem_object *obj); 856 int i915_gem_object_unbind(struct drm_gem_object *obj); 857 void i915_gem_release_mmap(struct drm_gem_object *obj); 858 void i915_gem_lastclose(struct drm_device *dev); 859 uint32_t i915_get_gem_seqno(struct drm_device *dev); 860 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); 861 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); 862 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); 863 void i915_gem_retire_requests(struct drm_device *dev); 864 void i915_gem_retire_work_handler(struct work_struct *work); 865 void i915_gem_clflush_object(struct drm_gem_object *obj); 866 int i915_gem_object_set_domain(struct drm_gem_object *obj, 867 uint32_t read_domains, 868 uint32_t write_domain); 869 int i915_gem_init_ringbuffer(struct drm_device *dev); 870 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 871 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 872 unsigned long end); 873 int i915_gem_idle(struct drm_device *dev); 874 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv, 875 uint32_t flush_domains); 876 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible); 877 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 878 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 879 int write); 880 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); 881 int i915_gem_attach_phys_object(struct drm_device *dev, 882 struct drm_gem_object *obj, int id); 883 void i915_gem_detach_phys_object(struct drm_device *dev, 884 struct drm_gem_object *obj); 885 void i915_gem_free_all_phys_object(struct drm_device *dev); 886 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); 887 void i915_gem_object_put_pages(struct drm_gem_object *obj); 888 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); 889 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj); 890 891 void i915_gem_shrinker_init(void); 892 void i915_gem_shrinker_exit(void); 893 894 /* i915_gem_tiling.c */ 895 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 896 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 897 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 898 bool i915_tiling_ok(struct drm_device *dev, int stride, int size, 899 int tiling_mode); 900 bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj); 901 902 /* i915_gem_debug.c */ 903 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 904 const char *where, uint32_t mark); 905 #if WATCH_INACTIVE 906 void i915_verify_inactive(struct drm_device *dev, char *file, int line); 907 #else 908 #define i915_verify_inactive(dev, file, line) 909 #endif 910 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 911 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 912 const char *where, uint32_t mark); 913 void i915_dump_lru(struct drm_device *dev, const char *where); 914 915 /* i915_debugfs.c */ 916 int i915_debugfs_init(struct drm_minor *minor); 917 void i915_debugfs_cleanup(struct drm_minor *minor); 918 919 /* i915_suspend.c */ 920 extern int i915_save_state(struct drm_device *dev); 921 extern int i915_restore_state(struct drm_device *dev); 922 923 /* i915_suspend.c */ 924 extern int i915_save_state(struct drm_device *dev); 925 extern int i915_restore_state(struct drm_device *dev); 926 927 #ifdef CONFIG_ACPI 928 /* i915_opregion.c */ 929 extern int intel_opregion_init(struct drm_device *dev, int resume); 930 extern void intel_opregion_free(struct drm_device *dev, int suspend); 931 extern void opregion_asle_intr(struct drm_device *dev); 932 extern void ironlake_opregion_gse_intr(struct drm_device *dev); 933 extern void opregion_enable_asle(struct drm_device *dev); 934 #else 935 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } 936 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } 937 static inline void opregion_asle_intr(struct drm_device *dev) { return; } 938 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; } 939 static inline void opregion_enable_asle(struct drm_device *dev) { return; } 940 #endif 941 942 /* modesetting */ 943 extern void intel_modeset_init(struct drm_device *dev); 944 extern void intel_modeset_cleanup(struct drm_device *dev); 945 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 946 extern void i8xx_disable_fbc(struct drm_device *dev); 947 extern void g4x_disable_fbc(struct drm_device *dev); 948 949 /** 950 * Lock test for when it's just for synchronization of ring access. 951 * 952 * In that case, we don't need to do it when GEM is initialized as nobody else 953 * has access to the ring. 954 */ 955 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 956 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 957 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 958 } while (0) 959 960 #define I915_READ(reg) readl(dev_priv->regs + (reg)) 961 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) 962 #define I915_READ16(reg) readw(dev_priv->regs + (reg)) 963 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) 964 #define I915_READ8(reg) readb(dev_priv->regs + (reg)) 965 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) 966 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) 967 #define I915_READ64(reg) readq(dev_priv->regs + (reg)) 968 #define POSTING_READ(reg) (void)I915_READ(reg) 969 970 #define I915_VERBOSE 0 971 972 #define RING_LOCALS volatile unsigned int *ring_virt__; 973 974 #define BEGIN_LP_RING(n) do { \ 975 int bytes__ = 4*(n); \ 976 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 977 /* a wrap must occur between instructions so pad beforehand */ \ 978 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ 979 i915_wrap_ring(dev); \ 980 if (unlikely (dev_priv->ring.space < bytes__)) \ 981 i915_wait_ring(dev, bytes__, __func__); \ 982 ring_virt__ = (unsigned int *) \ 983 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ 984 dev_priv->ring.tail += bytes__; \ 985 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ 986 dev_priv->ring.space -= bytes__; \ 987 } while (0) 988 989 #define OUT_RING(n) do { \ 990 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 991 *ring_virt__++ = (n); \ 992 } while (0) 993 994 #define ADVANCE_LP_RING() do { \ 995 if (I915_VERBOSE) \ 996 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ 997 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ 998 } while(0) 999 1000 /** 1001 * Reads a dword out of the status page, which is written to from the command 1002 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1003 * MI_STORE_DATA_IMM. 1004 * 1005 * The following dwords have a reserved meaning: 1006 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1007 * 0x04: ring 0 head pointer 1008 * 0x05: ring 1 head pointer (915-class) 1009 * 0x06: ring 2 head pointer (915-class) 1010 * 0x10-0x1b: Context status DWords (GM45) 1011 * 0x1f: Last written status offset. (GM45) 1012 * 1013 * The area from dword 0x20 to 0x3ff is available for driver usage. 1014 */ 1015 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1016 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1017 #define I915_GEM_HWS_INDEX 0x20 1018 #define I915_BREADCRUMB_INDEX 0x21 1019 1020 extern int i915_wrap_ring(struct drm_device * dev); 1021 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 1022 1023 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1024 1025 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1026 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1027 #define IS_I85X(dev) ((dev)->pci_device == 0x3582) 1028 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1029 #define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx) 1030 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1031 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1032 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1033 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1034 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) 1035 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) 1036 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1037 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1038 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1039 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1040 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1041 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1042 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1043 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1044 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) 1045 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) 1046 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1047 1048 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1049 1050 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1051 * rows, which changed the alignment requirements and fence programming. 1052 */ 1053 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 1054 IS_I915GM(dev))) 1055 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) 1056 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1057 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1058 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1059 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ 1060 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev)) 1061 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1062 /* dsparb controlled by hw only */ 1063 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1064 1065 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) 1066 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1067 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1068 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) 1069 1070 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1071 1072 #endif 1073