1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include <linux/io-mapping.h> 36 37 /* General customization: 38 */ 39 40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 41 42 #define DRIVER_NAME "i915" 43 #define DRIVER_DESC "Intel Graphics" 44 #define DRIVER_DATE "20080730" 45 46 enum pipe { 47 PIPE_A = 0, 48 PIPE_B, 49 }; 50 51 #define I915_NUM_PIPE 2 52 53 /* Interface history: 54 * 55 * 1.1: Original. 56 * 1.2: Add Power Management 57 * 1.3: Add vblank support 58 * 1.4: Fix cmdbuffer path, add heap destroy 59 * 1.5: Add vblank pipe configuration 60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 61 * - Support vertical blank on secondary display pipe 62 */ 63 #define DRIVER_MAJOR 1 64 #define DRIVER_MINOR 6 65 #define DRIVER_PATCHLEVEL 0 66 67 #define WATCH_COHERENCY 0 68 #define WATCH_BUF 0 69 #define WATCH_EXEC 0 70 #define WATCH_LRU 0 71 #define WATCH_RELOC 0 72 #define WATCH_INACTIVE 0 73 #define WATCH_PWRITE 0 74 75 #define I915_GEM_PHYS_CURSOR_0 1 76 #define I915_GEM_PHYS_CURSOR_1 2 77 #define I915_GEM_PHYS_OVERLAY_REGS 3 78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 79 80 struct drm_i915_gem_phys_object { 81 int id; 82 struct page **page_list; 83 drm_dma_handle_t *handle; 84 struct drm_gem_object *cur_obj; 85 }; 86 87 typedef struct _drm_i915_ring_buffer { 88 int tail_mask; 89 unsigned long Size; 90 u8 *virtual_start; 91 int head; 92 int tail; 93 int space; 94 drm_local_map_t map; 95 struct drm_gem_object *ring_obj; 96 } drm_i915_ring_buffer_t; 97 98 struct mem_block { 99 struct mem_block *next; 100 struct mem_block *prev; 101 int start; 102 int size; 103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 104 }; 105 106 struct opregion_header; 107 struct opregion_acpi; 108 struct opregion_swsci; 109 struct opregion_asle; 110 111 struct intel_opregion { 112 struct opregion_header *header; 113 struct opregion_acpi *acpi; 114 struct opregion_swsci *swsci; 115 struct opregion_asle *asle; 116 int enabled; 117 }; 118 119 struct drm_i915_master_private { 120 drm_local_map_t *sarea; 121 struct _drm_i915_sarea *sarea_priv; 122 }; 123 #define I915_FENCE_REG_NONE -1 124 125 struct drm_i915_fence_reg { 126 struct drm_gem_object *obj; 127 }; 128 129 typedef struct drm_i915_private { 130 struct drm_device *dev; 131 132 int has_gem; 133 134 void __iomem *regs; 135 136 drm_i915_ring_buffer_t ring; 137 138 drm_dma_handle_t *status_page_dmah; 139 void *hw_status_page; 140 dma_addr_t dma_status_page; 141 uint32_t counter; 142 unsigned int status_gfx_addr; 143 drm_local_map_t hws_map; 144 struct drm_gem_object *hws_obj; 145 146 unsigned int cpp; 147 int back_offset; 148 int front_offset; 149 int current_page; 150 int page_flipping; 151 152 wait_queue_head_t irq_queue; 153 atomic_t irq_received; 154 /** Protects user_irq_refcount and irq_mask_reg */ 155 spinlock_t user_irq_lock; 156 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 157 int user_irq_refcount; 158 /** Cached value of IMR to avoid reads in updating the bitfield */ 159 u32 irq_mask_reg; 160 u32 pipestat[2]; 161 162 u32 hotplug_supported_mask; 163 struct work_struct hotplug_work; 164 165 int tex_lru_log_granularity; 166 int allow_batchbuffer; 167 struct mem_block *agp_heap; 168 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 169 int vblank_pipe; 170 171 bool cursor_needs_physical; 172 173 struct drm_mm vram; 174 175 int irq_enabled; 176 177 struct intel_opregion opregion; 178 179 /* LVDS info */ 180 int backlight_duty_cycle; /* restore backlight to this value */ 181 bool panel_wants_dither; 182 struct drm_display_mode *panel_fixed_mode; 183 struct drm_display_mode *vbt_mode; /* if any */ 184 185 /* Feature bits from the VBIOS */ 186 unsigned int int_tv_support:1; 187 unsigned int lvds_dither:1; 188 unsigned int lvds_vbt:1; 189 unsigned int int_crt_support:1; 190 unsigned int lvds_use_ssc:1; 191 int lvds_ssc_freq; 192 193 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 194 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 195 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 196 197 /* Register state */ 198 u8 saveLBB; 199 u32 saveDSPACNTR; 200 u32 saveDSPBCNTR; 201 u32 saveDSPARB; 202 u32 saveRENDERSTANDBY; 203 u32 saveHWS; 204 u32 savePIPEACONF; 205 u32 savePIPEBCONF; 206 u32 savePIPEASRC; 207 u32 savePIPEBSRC; 208 u32 saveFPA0; 209 u32 saveFPA1; 210 u32 saveDPLL_A; 211 u32 saveDPLL_A_MD; 212 u32 saveHTOTAL_A; 213 u32 saveHBLANK_A; 214 u32 saveHSYNC_A; 215 u32 saveVTOTAL_A; 216 u32 saveVBLANK_A; 217 u32 saveVSYNC_A; 218 u32 saveBCLRPAT_A; 219 u32 savePIPEASTAT; 220 u32 saveDSPASTRIDE; 221 u32 saveDSPASIZE; 222 u32 saveDSPAPOS; 223 u32 saveDSPAADDR; 224 u32 saveDSPASURF; 225 u32 saveDSPATILEOFF; 226 u32 savePFIT_PGM_RATIOS; 227 u32 saveBLC_PWM_CTL; 228 u32 saveBLC_PWM_CTL2; 229 u32 saveFPB0; 230 u32 saveFPB1; 231 u32 saveDPLL_B; 232 u32 saveDPLL_B_MD; 233 u32 saveHTOTAL_B; 234 u32 saveHBLANK_B; 235 u32 saveHSYNC_B; 236 u32 saveVTOTAL_B; 237 u32 saveVBLANK_B; 238 u32 saveVSYNC_B; 239 u32 saveBCLRPAT_B; 240 u32 savePIPEBSTAT; 241 u32 saveDSPBSTRIDE; 242 u32 saveDSPBSIZE; 243 u32 saveDSPBPOS; 244 u32 saveDSPBADDR; 245 u32 saveDSPBSURF; 246 u32 saveDSPBTILEOFF; 247 u32 saveVGA0; 248 u32 saveVGA1; 249 u32 saveVGA_PD; 250 u32 saveVGACNTRL; 251 u32 saveADPA; 252 u32 saveLVDS; 253 u32 savePP_ON_DELAYS; 254 u32 savePP_OFF_DELAYS; 255 u32 saveDVOA; 256 u32 saveDVOB; 257 u32 saveDVOC; 258 u32 savePP_ON; 259 u32 savePP_OFF; 260 u32 savePP_CONTROL; 261 u32 savePP_DIVISOR; 262 u32 savePFIT_CONTROL; 263 u32 save_palette_a[256]; 264 u32 save_palette_b[256]; 265 u32 saveFBC_CFB_BASE; 266 u32 saveFBC_LL_BASE; 267 u32 saveFBC_CONTROL; 268 u32 saveFBC_CONTROL2; 269 u32 saveIER; 270 u32 saveIIR; 271 u32 saveIMR; 272 u32 saveCACHE_MODE_0; 273 u32 saveD_STATE; 274 u32 saveCG_2D_DIS; 275 u32 saveMI_ARB_STATE; 276 u32 saveSWF0[16]; 277 u32 saveSWF1[16]; 278 u32 saveSWF2[3]; 279 u8 saveMSR; 280 u8 saveSR[8]; 281 u8 saveGR[25]; 282 u8 saveAR_INDEX; 283 u8 saveAR[21]; 284 u8 saveDACMASK; 285 u8 saveCR[37]; 286 287 struct { 288 struct drm_mm gtt_space; 289 290 struct io_mapping *gtt_mapping; 291 int gtt_mtrr; 292 293 /** 294 * List of objects currently involved in rendering from the 295 * ringbuffer. 296 * 297 * Includes buffers having the contents of their GPU caches 298 * flushed, not necessarily primitives. last_rendering_seqno 299 * represents when the rendering involved will be completed. 300 * 301 * A reference is held on the buffer while on this list. 302 */ 303 spinlock_t active_list_lock; 304 struct list_head active_list; 305 306 /** 307 * List of objects which are not in the ringbuffer but which 308 * still have a write_domain which needs to be flushed before 309 * unbinding. 310 * 311 * last_rendering_seqno is 0 while an object is in this list. 312 * 313 * A reference is held on the buffer while on this list. 314 */ 315 struct list_head flushing_list; 316 317 /** 318 * LRU list of objects which are not in the ringbuffer and 319 * are ready to unbind, but are still in the GTT. 320 * 321 * last_rendering_seqno is 0 while an object is in this list. 322 * 323 * A reference is not held on the buffer while on this list, 324 * as merely being GTT-bound shouldn't prevent its being 325 * freed, and we'll pull it off the list in the free path. 326 */ 327 struct list_head inactive_list; 328 329 /** 330 * List of breadcrumbs associated with GPU requests currently 331 * outstanding. 332 */ 333 struct list_head request_list; 334 335 /** 336 * We leave the user IRQ off as much as possible, 337 * but this means that requests will finish and never 338 * be retired once the system goes idle. Set a timer to 339 * fire periodically while the ring is running. When it 340 * fires, go retire requests. 341 */ 342 struct delayed_work retire_work; 343 344 uint32_t next_gem_seqno; 345 346 /** 347 * Waiting sequence number, if any 348 */ 349 uint32_t waiting_gem_seqno; 350 351 /** 352 * Last seq seen at irq time 353 */ 354 uint32_t irq_gem_seqno; 355 356 /** 357 * Flag if the X Server, and thus DRM, is not currently in 358 * control of the device. 359 * 360 * This is set between LeaveVT and EnterVT. It needs to be 361 * replaced with a semaphore. It also needs to be 362 * transitioned away from for kernel modesetting. 363 */ 364 int suspended; 365 366 /** 367 * Flag if the hardware appears to be wedged. 368 * 369 * This is set when attempts to idle the device timeout. 370 * It prevents command submission from occuring and makes 371 * every pending request fail 372 */ 373 int wedged; 374 375 /** Bit 6 swizzling required for X tiling */ 376 uint32_t bit_6_swizzle_x; 377 /** Bit 6 swizzling required for Y tiling */ 378 uint32_t bit_6_swizzle_y; 379 380 /* storage for physical objects */ 381 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 382 } mm; 383 } drm_i915_private_t; 384 385 /** driver private structure attached to each drm_gem_object */ 386 struct drm_i915_gem_object { 387 struct drm_gem_object *obj; 388 389 /** Current space allocated to this object in the GTT, if any. */ 390 struct drm_mm_node *gtt_space; 391 392 /** This object's place on the active/flushing/inactive lists */ 393 struct list_head list; 394 395 /** 396 * This is set if the object is on the active or flushing lists 397 * (has pending rendering), and is not set if it's on inactive (ready 398 * to be unbound). 399 */ 400 int active; 401 402 /** 403 * This is set if the object has been written to since last bound 404 * to the GTT 405 */ 406 int dirty; 407 408 /** AGP memory structure for our GTT binding. */ 409 DRM_AGP_MEM *agp_mem; 410 411 struct page **pages; 412 int pages_refcount; 413 414 /** 415 * Current offset of the object in GTT space. 416 * 417 * This is the same as gtt_space->start 418 */ 419 uint32_t gtt_offset; 420 /** 421 * Required alignment for the object 422 */ 423 uint32_t gtt_alignment; 424 /** 425 * Fake offset for use by mmap(2) 426 */ 427 uint64_t mmap_offset; 428 429 /** 430 * Fence register bits (if any) for this object. Will be set 431 * as needed when mapped into the GTT. 432 * Protected by dev->struct_mutex. 433 */ 434 int fence_reg; 435 436 /** Boolean whether this object has a valid gtt offset. */ 437 int gtt_bound; 438 439 /** How many users have pinned this object in GTT space */ 440 int pin_count; 441 442 /** Breadcrumb of last rendering to the buffer. */ 443 uint32_t last_rendering_seqno; 444 445 /** Current tiling mode for the object. */ 446 uint32_t tiling_mode; 447 uint32_t stride; 448 449 /** Record of address bit 17 of each page at last unbind. */ 450 long *bit_17; 451 452 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 453 uint32_t agp_type; 454 455 /** 456 * If present, while GEM_DOMAIN_CPU is in the read domain this array 457 * flags which individual pages are valid. 458 */ 459 uint8_t *page_cpu_valid; 460 461 /** User space pin count and filp owning the pin */ 462 uint32_t user_pin_count; 463 struct drm_file *pin_filp; 464 465 /** for phy allocated objects */ 466 struct drm_i915_gem_phys_object *phys_obj; 467 468 /** 469 * Used for checking the object doesn't appear more than once 470 * in an execbuffer object list. 471 */ 472 int in_execbuffer; 473 }; 474 475 /** 476 * Request queue structure. 477 * 478 * The request queue allows us to note sequence numbers that have been emitted 479 * and may be associated with active buffers to be retired. 480 * 481 * By keeping this list, we can avoid having to do questionable 482 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 483 * an emission time with seqnos for tracking how far ahead of the GPU we are. 484 */ 485 struct drm_i915_gem_request { 486 /** GEM sequence number associated with this request. */ 487 uint32_t seqno; 488 489 /** Time at which this request was emitted, in jiffies. */ 490 unsigned long emitted_jiffies; 491 492 struct list_head list; 493 }; 494 495 struct drm_i915_file_private { 496 struct { 497 uint32_t last_gem_seqno; 498 uint32_t last_gem_throttle_seqno; 499 } mm; 500 }; 501 502 enum intel_chip_family { 503 CHIP_I8XX = 0x01, 504 CHIP_I9XX = 0x02, 505 CHIP_I915 = 0x04, 506 CHIP_I965 = 0x08, 507 }; 508 509 extern struct drm_ioctl_desc i915_ioctls[]; 510 extern int i915_max_ioctl; 511 extern unsigned int i915_fbpercrtc; 512 513 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 514 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 515 516 /* i915_dma.c */ 517 extern void i915_kernel_lost_context(struct drm_device * dev); 518 extern int i915_driver_load(struct drm_device *, unsigned long flags); 519 extern int i915_driver_unload(struct drm_device *); 520 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 521 extern void i915_driver_lastclose(struct drm_device * dev); 522 extern void i915_driver_preclose(struct drm_device *dev, 523 struct drm_file *file_priv); 524 extern void i915_driver_postclose(struct drm_device *dev, 525 struct drm_file *file_priv); 526 extern int i915_driver_device_is_agp(struct drm_device * dev); 527 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 528 unsigned long arg); 529 extern int i915_emit_box(struct drm_device *dev, 530 struct drm_clip_rect *boxes, 531 int i, int DR1, int DR4); 532 533 /* i915_irq.c */ 534 extern int i915_irq_emit(struct drm_device *dev, void *data, 535 struct drm_file *file_priv); 536 extern int i915_irq_wait(struct drm_device *dev, void *data, 537 struct drm_file *file_priv); 538 void i915_user_irq_get(struct drm_device *dev); 539 void i915_user_irq_put(struct drm_device *dev); 540 extern void i915_enable_interrupt (struct drm_device *dev); 541 542 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 543 extern void i915_driver_irq_preinstall(struct drm_device * dev); 544 extern int i915_driver_irq_postinstall(struct drm_device *dev); 545 extern void i915_driver_irq_uninstall(struct drm_device * dev); 546 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 547 struct drm_file *file_priv); 548 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 549 struct drm_file *file_priv); 550 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 551 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 552 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 553 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 554 extern int i915_vblank_swap(struct drm_device *dev, void *data, 555 struct drm_file *file_priv); 556 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 557 558 void 559 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 560 561 void 562 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 563 564 565 /* i915_mem.c */ 566 extern int i915_mem_alloc(struct drm_device *dev, void *data, 567 struct drm_file *file_priv); 568 extern int i915_mem_free(struct drm_device *dev, void *data, 569 struct drm_file *file_priv); 570 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 571 struct drm_file *file_priv); 572 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 573 struct drm_file *file_priv); 574 extern void i915_mem_takedown(struct mem_block **heap); 575 extern void i915_mem_release(struct drm_device * dev, 576 struct drm_file *file_priv, struct mem_block *heap); 577 /* i915_gem.c */ 578 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 579 struct drm_file *file_priv); 580 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 581 struct drm_file *file_priv); 582 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *file_priv); 584 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 585 struct drm_file *file_priv); 586 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 587 struct drm_file *file_priv); 588 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 589 struct drm_file *file_priv); 590 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 591 struct drm_file *file_priv); 592 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 593 struct drm_file *file_priv); 594 int i915_gem_execbuffer(struct drm_device *dev, void *data, 595 struct drm_file *file_priv); 596 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 597 struct drm_file *file_priv); 598 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 599 struct drm_file *file_priv); 600 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 601 struct drm_file *file_priv); 602 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 603 struct drm_file *file_priv); 604 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 605 struct drm_file *file_priv); 606 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 607 struct drm_file *file_priv); 608 int i915_gem_set_tiling(struct drm_device *dev, void *data, 609 struct drm_file *file_priv); 610 int i915_gem_get_tiling(struct drm_device *dev, void *data, 611 struct drm_file *file_priv); 612 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 613 struct drm_file *file_priv); 614 void i915_gem_load(struct drm_device *dev); 615 int i915_gem_init_object(struct drm_gem_object *obj); 616 void i915_gem_free_object(struct drm_gem_object *obj); 617 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 618 void i915_gem_object_unpin(struct drm_gem_object *obj); 619 int i915_gem_object_unbind(struct drm_gem_object *obj); 620 void i915_gem_lastclose(struct drm_device *dev); 621 uint32_t i915_get_gem_seqno(struct drm_device *dev); 622 void i915_gem_retire_requests(struct drm_device *dev); 623 void i915_gem_retire_work_handler(struct work_struct *work); 624 void i915_gem_clflush_object(struct drm_gem_object *obj); 625 int i915_gem_object_set_domain(struct drm_gem_object *obj, 626 uint32_t read_domains, 627 uint32_t write_domain); 628 int i915_gem_init_ringbuffer(struct drm_device *dev); 629 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 630 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 631 unsigned long end); 632 int i915_gem_idle(struct drm_device *dev); 633 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 634 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 635 int write); 636 int i915_gem_attach_phys_object(struct drm_device *dev, 637 struct drm_gem_object *obj, int id); 638 void i915_gem_detach_phys_object(struct drm_device *dev, 639 struct drm_gem_object *obj); 640 void i915_gem_free_all_phys_object(struct drm_device *dev); 641 int i915_gem_object_get_pages(struct drm_gem_object *obj); 642 void i915_gem_object_put_pages(struct drm_gem_object *obj); 643 644 /* i915_gem_tiling.c */ 645 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 646 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 647 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 648 649 /* i915_gem_debug.c */ 650 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 651 const char *where, uint32_t mark); 652 #if WATCH_INACTIVE 653 void i915_verify_inactive(struct drm_device *dev, char *file, int line); 654 #else 655 #define i915_verify_inactive(dev, file, line) 656 #endif 657 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 658 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 659 const char *where, uint32_t mark); 660 void i915_dump_lru(struct drm_device *dev, const char *where); 661 662 /* i915_debugfs.c */ 663 int i915_gem_debugfs_init(struct drm_minor *minor); 664 void i915_gem_debugfs_cleanup(struct drm_minor *minor); 665 666 /* i915_suspend.c */ 667 extern int i915_save_state(struct drm_device *dev); 668 extern int i915_restore_state(struct drm_device *dev); 669 670 /* i915_suspend.c */ 671 extern int i915_save_state(struct drm_device *dev); 672 extern int i915_restore_state(struct drm_device *dev); 673 674 #ifdef CONFIG_ACPI 675 /* i915_opregion.c */ 676 extern int intel_opregion_init(struct drm_device *dev, int resume); 677 extern void intel_opregion_free(struct drm_device *dev, int suspend); 678 extern void opregion_asle_intr(struct drm_device *dev); 679 extern void opregion_enable_asle(struct drm_device *dev); 680 #else 681 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } 682 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } 683 static inline void opregion_asle_intr(struct drm_device *dev) { return; } 684 static inline void opregion_enable_asle(struct drm_device *dev) { return; } 685 #endif 686 687 /* modesetting */ 688 extern void intel_modeset_init(struct drm_device *dev); 689 extern void intel_modeset_cleanup(struct drm_device *dev); 690 691 /** 692 * Lock test for when it's just for synchronization of ring access. 693 * 694 * In that case, we don't need to do it when GEM is initialized as nobody else 695 * has access to the ring. 696 */ 697 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 698 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 699 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 700 } while (0) 701 702 #define I915_READ(reg) readl(dev_priv->regs + (reg)) 703 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) 704 #define I915_READ16(reg) readw(dev_priv->regs + (reg)) 705 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) 706 #define I915_READ8(reg) readb(dev_priv->regs + (reg)) 707 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) 708 #ifdef writeq 709 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) 710 #else 711 #define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \ 712 writel(upper_32_bits(val), dev_priv->regs + \ 713 (reg) + 4)) 714 #endif 715 #define POSTING_READ(reg) (void)I915_READ(reg) 716 717 #define I915_VERBOSE 0 718 719 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 720 volatile char *virt; 721 722 #define BEGIN_LP_RING(n) do { \ 723 if (I915_VERBOSE) \ 724 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 725 if (dev_priv->ring.space < (n)*4) \ 726 i915_wait_ring(dev, (n)*4, __func__); \ 727 outcount = 0; \ 728 outring = dev_priv->ring.tail; \ 729 ringmask = dev_priv->ring.tail_mask; \ 730 virt = dev_priv->ring.virtual_start; \ 731 } while (0) 732 733 #define OUT_RING(n) do { \ 734 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 735 *(volatile unsigned int *)(virt + outring) = (n); \ 736 outcount++; \ 737 outring += 4; \ 738 outring &= ringmask; \ 739 } while (0) 740 741 #define ADVANCE_LP_RING() do { \ 742 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 743 dev_priv->ring.tail = outring; \ 744 dev_priv->ring.space -= outcount * 4; \ 745 I915_WRITE(PRB0_TAIL, outring); \ 746 } while(0) 747 748 /** 749 * Reads a dword out of the status page, which is written to from the command 750 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 751 * MI_STORE_DATA_IMM. 752 * 753 * The following dwords have a reserved meaning: 754 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 755 * 0x04: ring 0 head pointer 756 * 0x05: ring 1 head pointer (915-class) 757 * 0x06: ring 2 head pointer (915-class) 758 * 0x10-0x1b: Context status DWords (GM45) 759 * 0x1f: Last written status offset. (GM45) 760 * 761 * The area from dword 0x20 to 0x3ff is available for driver usage. 762 */ 763 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 764 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 765 #define I915_GEM_HWS_INDEX 0x20 766 #define I915_BREADCRUMB_INDEX 0x21 767 768 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 769 770 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 771 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 772 #define IS_I85X(dev) ((dev)->pci_device == 0x3582) 773 #define IS_I855(dev) ((dev)->pci_device == 0x3582) 774 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 775 776 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 777 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 778 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 779 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 780 (dev)->pci_device == 0x27AE) 781 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 782 (dev)->pci_device == 0x2982 || \ 783 (dev)->pci_device == 0x2992 || \ 784 (dev)->pci_device == 0x29A2 || \ 785 (dev)->pci_device == 0x2A02 || \ 786 (dev)->pci_device == 0x2A12 || \ 787 (dev)->pci_device == 0x2A42 || \ 788 (dev)->pci_device == 0x2E02 || \ 789 (dev)->pci_device == 0x2E12 || \ 790 (dev)->pci_device == 0x2E22 || \ 791 (dev)->pci_device == 0x2E32) 792 793 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 794 795 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 796 797 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 798 (dev)->pci_device == 0x2E12 || \ 799 (dev)->pci_device == 0x2E22 || \ 800 (dev)->pci_device == 0x2E32 || \ 801 IS_GM45(dev)) 802 803 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 804 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 805 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 806 807 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 808 (dev)->pci_device == 0x29B2 || \ 809 (dev)->pci_device == 0x29D2 || \ 810 (IS_IGD(dev))) 811 812 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 813 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 814 815 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 816 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 817 IS_IGD(dev)) 818 819 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 820 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 821 * rows, which changed the alignment requirements and fence programming. 822 */ 823 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 824 IS_I915GM(dev))) 825 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev)) 826 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev)) 827 828 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 829 830 #endif 831