1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <asm/hypervisor.h> 37 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/backlight.h> 42 #include <linux/hash.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/mm_types.h> 46 #include <linux/perf_event.h> 47 #include <linux/pm_qos.h> 48 #include <linux/dma-resv.h> 49 #include <linux/shmem_fs.h> 50 #include <linux/stackdepot.h> 51 #include <linux/xarray.h> 52 53 #include <drm/intel-gtt.h> 54 #include <drm/drm_gem.h> 55 #include <drm/drm_auth.h> 56 #include <drm/drm_cache.h> 57 #include <drm/drm_util.h> 58 #include <drm/drm_dsc.h> 59 #include <drm/drm_atomic.h> 60 #include <drm/drm_connector.h> 61 #include <drm/i915_mei_hdcp_interface.h> 62 63 #include "i915_params.h" 64 #include "i915_reg.h" 65 #include "i915_utils.h" 66 67 #include "display/intel_bios.h" 68 #include "display/intel_display.h" 69 #include "display/intel_display_power.h" 70 #include "display/intel_dpll_mgr.h" 71 #include "display/intel_dsb.h" 72 #include "display/intel_frontbuffer.h" 73 #include "display/intel_global_state.h" 74 #include "display/intel_gmbus.h" 75 #include "display/intel_opregion.h" 76 77 #include "gem/i915_gem_context_types.h" 78 #include "gem/i915_gem_shrinker.h" 79 #include "gem/i915_gem_stolen.h" 80 #include "gem/i915_gem_lmem.h" 81 82 #include "gt/intel_engine.h" 83 #include "gt/intel_gt_types.h" 84 #include "gt/intel_region_lmem.h" 85 #include "gt/intel_workarounds.h" 86 #include "gt/uc/intel_uc.h" 87 88 #include "intel_device_info.h" 89 #include "intel_memory_region.h" 90 #include "intel_pch.h" 91 #include "intel_runtime_pm.h" 92 #include "intel_step.h" 93 #include "intel_uncore.h" 94 #include "intel_wakeref.h" 95 #include "intel_wopcm.h" 96 97 #include "i915_gem.h" 98 #include "i915_gem_gtt.h" 99 #include "i915_gpu_error.h" 100 #include "i915_perf_types.h" 101 #include "i915_request.h" 102 #include "i915_scheduler.h" 103 #include "gt/intel_timeline.h" 104 #include "i915_vma.h" 105 #include "i915_irq.h" 106 107 108 /* General customization: 109 */ 110 111 #define DRIVER_NAME "i915" 112 #define DRIVER_DESC "Intel Graphics" 113 #define DRIVER_DATE "20201103" 114 #define DRIVER_TIMESTAMP 1604406085 115 116 struct drm_i915_gem_object; 117 118 enum hpd_pin { 119 HPD_NONE = 0, 120 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 121 HPD_CRT, 122 HPD_SDVO_B, 123 HPD_SDVO_C, 124 HPD_PORT_A, 125 HPD_PORT_B, 126 HPD_PORT_C, 127 HPD_PORT_D, 128 HPD_PORT_E, 129 HPD_PORT_TC1, 130 HPD_PORT_TC2, 131 HPD_PORT_TC3, 132 HPD_PORT_TC4, 133 HPD_PORT_TC5, 134 HPD_PORT_TC6, 135 136 HPD_NUM_PINS 137 }; 138 139 #define for_each_hpd_pin(__pin) \ 140 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 141 142 /* Threshold == 5 for long IRQs, 50 for short */ 143 #define HPD_STORM_DEFAULT_THRESHOLD 50 144 145 struct i915_hotplug { 146 struct delayed_work hotplug_work; 147 148 const u32 *hpd, *pch_hpd; 149 150 struct { 151 unsigned long last_jiffies; 152 int count; 153 enum { 154 HPD_ENABLED = 0, 155 HPD_DISABLED = 1, 156 HPD_MARK_DISABLED = 2 157 } state; 158 } stats[HPD_NUM_PINS]; 159 u32 event_bits; 160 u32 retry_bits; 161 struct delayed_work reenable_work; 162 163 u32 long_port_mask; 164 u32 short_port_mask; 165 struct work_struct dig_port_work; 166 167 struct work_struct poll_init_work; 168 bool poll_enabled; 169 170 unsigned int hpd_storm_threshold; 171 /* Whether or not to count short HPD IRQs in HPD storms */ 172 u8 hpd_short_storm_enabled; 173 174 /* 175 * if we get a HPD irq from DP and a HPD irq from non-DP 176 * the non-DP HPD could block the workqueue on a mode config 177 * mutex getting, that userspace may have taken. However 178 * userspace is waiting on the DP workqueue to run which is 179 * blocked behind the non-DP one. 180 */ 181 struct workqueue_struct *dp_wq; 182 }; 183 184 #define I915_GEM_GPU_DOMAINS \ 185 (I915_GEM_DOMAIN_RENDER | \ 186 I915_GEM_DOMAIN_SAMPLER | \ 187 I915_GEM_DOMAIN_COMMAND | \ 188 I915_GEM_DOMAIN_INSTRUCTION | \ 189 I915_GEM_DOMAIN_VERTEX) 190 191 struct drm_i915_private; 192 struct i915_mm_struct; 193 struct i915_mmu_object; 194 195 struct drm_i915_file_private { 196 struct drm_i915_private *dev_priv; 197 198 union { 199 struct drm_file *file; 200 struct rcu_head rcu; 201 }; 202 203 struct xarray context_xa; 204 struct xarray vm_xa; 205 206 unsigned int bsd_engine; 207 208 /* 209 * Every context ban increments per client ban score. Also 210 * hangs in short succession increments ban score. If ban threshold 211 * is reached, client is considered banned and submitting more work 212 * will fail. This is a stop gap measure to limit the badly behaving 213 * clients access to gpu. Note that unbannable contexts never increment 214 * the client ban score. 215 */ 216 #define I915_CLIENT_SCORE_HANG_FAST 1 217 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 218 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 219 #define I915_CLIENT_SCORE_BANNED 9 220 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 221 atomic_t ban_score; 222 unsigned long hang_timestamp; 223 }; 224 225 /* Interface history: 226 * 227 * 1.1: Original. 228 * 1.2: Add Power Management 229 * 1.3: Add vblank support 230 * 1.4: Fix cmdbuffer path, add heap destroy 231 * 1.5: Add vblank pipe configuration 232 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 233 * - Support vertical blank on secondary display pipe 234 */ 235 #define DRIVER_MAJOR 1 236 #define DRIVER_MINOR 6 237 #define DRIVER_PATCHLEVEL 0 238 239 struct intel_overlay; 240 struct intel_overlay_error_state; 241 242 struct sdvo_device_mapping { 243 u8 initialized; 244 u8 dvo_port; 245 u8 slave_addr; 246 u8 dvo_wiring; 247 u8 i2c_pin; 248 u8 ddc_pin; 249 }; 250 251 struct intel_connector; 252 struct intel_encoder; 253 struct intel_atomic_state; 254 struct intel_cdclk_config; 255 struct intel_cdclk_state; 256 struct intel_cdclk_vals; 257 struct intel_initial_plane_config; 258 struct intel_crtc; 259 struct intel_limit; 260 struct dpll; 261 262 struct drm_i915_display_funcs { 263 void (*get_cdclk)(struct drm_i915_private *dev_priv, 264 struct intel_cdclk_config *cdclk_config); 265 void (*set_cdclk)(struct drm_i915_private *dev_priv, 266 const struct intel_cdclk_config *cdclk_config, 267 enum pipe pipe); 268 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); 269 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 270 enum i9xx_plane_id i9xx_plane); 271 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 272 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 273 void (*initial_watermarks)(struct intel_atomic_state *state, 274 struct intel_crtc *crtc); 275 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 276 struct intel_crtc *crtc); 277 void (*optimize_watermarks)(struct intel_atomic_state *state, 278 struct intel_crtc *crtc); 279 int (*compute_global_watermarks)(struct intel_atomic_state *state); 280 void (*update_wm)(struct intel_crtc *crtc); 281 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 282 u8 (*calc_voltage_level)(int cdclk); 283 /* Returns the active state of the crtc, and if the crtc is active, 284 * fills out the pipe-config with the hw state. */ 285 bool (*get_pipe_config)(struct intel_crtc *, 286 struct intel_crtc_state *); 287 void (*get_initial_plane_config)(struct intel_crtc *, 288 struct intel_initial_plane_config *); 289 int (*crtc_compute_clock)(struct intel_crtc *crtc, 290 struct intel_crtc_state *crtc_state); 291 void (*crtc_enable)(struct intel_atomic_state *state, 292 struct intel_crtc *crtc); 293 void (*crtc_disable)(struct intel_atomic_state *state, 294 struct intel_crtc *crtc); 295 void (*commit_modeset_enables)(struct intel_atomic_state *state); 296 void (*commit_modeset_disables)(struct intel_atomic_state *state); 297 void (*audio_codec_enable)(struct intel_encoder *encoder, 298 const struct intel_crtc_state *crtc_state, 299 const struct drm_connector_state *conn_state); 300 void (*audio_codec_disable)(struct intel_encoder *encoder, 301 const struct intel_crtc_state *old_crtc_state, 302 const struct drm_connector_state *old_conn_state); 303 void (*fdi_link_train)(struct intel_crtc *crtc, 304 const struct intel_crtc_state *crtc_state); 305 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 306 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 307 /* clock updates for mode set */ 308 /* cursor updates */ 309 /* render clock increase/decrease */ 310 /* display clock increase/decrease */ 311 /* pll clock increase/decrease */ 312 313 int (*color_check)(struct intel_crtc_state *crtc_state); 314 /* 315 * Program double buffered color management registers during 316 * vblank evasion. The registers should then latch during the 317 * next vblank start, alongside any other double buffered registers 318 * involved with the same commit. 319 */ 320 void (*color_commit)(const struct intel_crtc_state *crtc_state); 321 /* 322 * Load LUTs (and other single buffered color management 323 * registers). Will (hopefully) be called during the vblank 324 * following the latching of any double buffered registers 325 * involved with the same commit. 326 */ 327 void (*load_luts)(const struct intel_crtc_state *crtc_state); 328 void (*read_luts)(struct intel_crtc_state *crtc_state); 329 }; 330 331 struct intel_csr { 332 struct work_struct work; 333 const char *fw_path; 334 u32 required_version; 335 u32 max_fw_size; /* bytes */ 336 u32 *dmc_payload; 337 u32 dmc_fw_size; /* dwords */ 338 u32 version; 339 u32 mmio_count; 340 i915_reg_t mmioaddr[20]; 341 u32 mmiodata[20]; 342 u32 dc_state; 343 u32 target_dc_state; 344 u32 allowed_dc_mask; 345 intel_wakeref_t wakeref; 346 }; 347 348 enum i915_cache_level { 349 I915_CACHE_NONE = 0, 350 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 351 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 352 caches, eg sampler/render caches, and the 353 large Last-Level-Cache. LLC is coherent with 354 the CPU, but L3 is only visible to the GPU. */ 355 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 356 }; 357 358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 359 360 struct intel_fbc { 361 /* This is always the inner lock when overlapping with struct_mutex and 362 * it's the outer lock when overlapping with stolen_lock. */ 363 struct mutex lock; 364 unsigned threshold; 365 unsigned int possible_framebuffer_bits; 366 unsigned int busy_bits; 367 struct intel_crtc *crtc; 368 369 struct drm_mm_node compressed_fb; 370 struct drm_mm_node *compressed_llb; 371 372 bool false_color; 373 374 bool active; 375 bool activated; 376 bool flip_pending; 377 378 bool underrun_detected; 379 struct work_struct underrun_work; 380 381 /* 382 * Due to the atomic rules we can't access some structures without the 383 * appropriate locking, so we cache information here in order to avoid 384 * these problems. 385 */ 386 struct intel_fbc_state_cache { 387 struct { 388 unsigned int mode_flags; 389 u32 hsw_bdw_pixel_rate; 390 } crtc; 391 392 struct { 393 unsigned int rotation; 394 int src_w; 395 int src_h; 396 bool visible; 397 /* 398 * Display surface base address adjustement for 399 * pageflips. Note that on gen4+ this only adjusts up 400 * to a tile, offsets within a tile are handled in 401 * the hw itself (with the TILEOFF register). 402 */ 403 int adjusted_x; 404 int adjusted_y; 405 406 u16 pixel_blend_mode; 407 } plane; 408 409 struct { 410 const struct drm_format_info *format; 411 unsigned int stride; 412 u64 modifier; 413 } fb; 414 415 unsigned int fence_y_offset; 416 u16 gen9_wa_cfb_stride; 417 u16 interval; 418 s8 fence_id; 419 bool psr2_active; 420 } state_cache; 421 422 /* 423 * This structure contains everything that's relevant to program the 424 * hardware registers. When we want to figure out if we need to disable 425 * and re-enable FBC for a new configuration we just check if there's 426 * something different in the struct. The genx_fbc_activate functions 427 * are supposed to read from it in order to program the registers. 428 */ 429 struct intel_fbc_reg_params { 430 struct { 431 enum pipe pipe; 432 enum i9xx_plane_id i9xx_plane; 433 } crtc; 434 435 struct { 436 const struct drm_format_info *format; 437 unsigned int stride; 438 u64 modifier; 439 } fb; 440 441 int cfb_size; 442 unsigned int fence_y_offset; 443 u16 gen9_wa_cfb_stride; 444 u16 interval; 445 s8 fence_id; 446 bool plane_visible; 447 } params; 448 449 const char *no_fbc_reason; 450 }; 451 452 /* 453 * HIGH_RR is the highest eDP panel refresh rate read from EDID 454 * LOW_RR is the lowest eDP panel refresh rate found from EDID 455 * parsing for same resolution. 456 */ 457 enum drrs_refresh_rate_type { 458 DRRS_HIGH_RR, 459 DRRS_LOW_RR, 460 DRRS_MAX_RR, /* RR count */ 461 }; 462 463 enum drrs_support_type { 464 DRRS_NOT_SUPPORTED = 0, 465 STATIC_DRRS_SUPPORT = 1, 466 SEAMLESS_DRRS_SUPPORT = 2 467 }; 468 469 struct intel_dp; 470 struct i915_drrs { 471 struct mutex mutex; 472 struct delayed_work work; 473 struct intel_dp *dp; 474 unsigned busy_frontbuffer_bits; 475 enum drrs_refresh_rate_type refresh_rate_type; 476 enum drrs_support_type type; 477 }; 478 479 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 480 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 481 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 482 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 483 #define QUIRK_INCREASE_T12_DELAY (1<<6) 484 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 485 486 struct intel_fbdev; 487 struct intel_fbc_work; 488 489 struct intel_gmbus { 490 struct i2c_adapter adapter; 491 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 492 u32 force_bit; 493 u32 reg0; 494 i915_reg_t gpio_reg; 495 struct i2c_algo_bit_data bit_algo; 496 struct drm_i915_private *dev_priv; 497 }; 498 499 struct i915_suspend_saved_registers { 500 u32 saveDSPARB; 501 u32 saveSWF0[16]; 502 u32 saveSWF1[16]; 503 u32 saveSWF3[3]; 504 u16 saveGCDGMBUS; 505 }; 506 507 struct vlv_s0ix_state; 508 509 #define MAX_L3_SLICES 2 510 struct intel_l3_parity { 511 u32 *remap_info[MAX_L3_SLICES]; 512 struct work_struct error_work; 513 int which_slice; 514 }; 515 516 struct i915_gem_mm { 517 /* 518 * Shortcut for the stolen region. This points to either 519 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 520 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 521 * support stolen. 522 */ 523 struct intel_memory_region *stolen_region; 524 /** Memory allocator for GTT stolen memory */ 525 struct drm_mm stolen; 526 /** Protects the usage of the GTT stolen memory allocator. This is 527 * always the inner lock when overlapping with struct_mutex. */ 528 struct mutex stolen_lock; 529 530 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 531 spinlock_t obj_lock; 532 533 /** 534 * List of objects which are purgeable. 535 */ 536 struct list_head purge_list; 537 538 /** 539 * List of objects which have allocated pages and are shrinkable. 540 */ 541 struct list_head shrink_list; 542 543 /** 544 * List of objects which are pending destruction. 545 */ 546 struct llist_head free_list; 547 struct work_struct free_work; 548 /** 549 * Count of objects pending destructions. Used to skip needlessly 550 * waiting on an RCU barrier if no objects are waiting to be freed. 551 */ 552 atomic_t free_count; 553 554 /** 555 * tmpfs instance used for shmem backed objects 556 */ 557 struct vfsmount *gemfs; 558 559 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 560 561 struct notifier_block oom_notifier; 562 struct notifier_block vmap_notifier; 563 struct shrinker shrinker; 564 565 #ifdef CONFIG_MMU_NOTIFIER 566 /** 567 * notifier_lock for mmu notifiers, memory may not be allocated 568 * while holding this lock. 569 */ 570 spinlock_t notifier_lock; 571 #endif 572 573 /* shrinker accounting, also useful for userland debugging */ 574 u64 shrink_memory; 575 u32 shrink_count; 576 }; 577 578 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 579 580 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 581 u64 context); 582 583 static inline unsigned long 584 i915_fence_timeout(const struct drm_i915_private *i915) 585 { 586 return i915_fence_context_timeout(i915, U64_MAX); 587 } 588 589 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 590 #define I915_NUM_QGV_POINTS 8 591 592 struct ddi_vbt_port_info { 593 /* Non-NULL if port present. */ 594 struct intel_bios_encoder_data *devdata; 595 596 int max_tmds_clock; 597 598 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 599 u8 hdmi_level_shift; 600 u8 hdmi_level_shift_set:1; 601 602 u8 alternate_aux_channel; 603 u8 alternate_ddc_pin; 604 605 int dp_max_link_rate; /* 0 for not limited by VBT */ 606 }; 607 608 enum psr_lines_to_wait { 609 PSR_0_LINES_TO_WAIT = 0, 610 PSR_1_LINE_TO_WAIT, 611 PSR_4_LINES_TO_WAIT, 612 PSR_8_LINES_TO_WAIT 613 }; 614 615 struct intel_vbt_data { 616 /* bdb version */ 617 u16 version; 618 619 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 620 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 621 622 /* Feature bits */ 623 unsigned int int_tv_support:1; 624 unsigned int lvds_dither:1; 625 unsigned int int_crt_support:1; 626 unsigned int lvds_use_ssc:1; 627 unsigned int int_lvds_support:1; 628 unsigned int display_clock_mode:1; 629 unsigned int fdi_rx_polarity_inverted:1; 630 unsigned int panel_type:4; 631 int lvds_ssc_freq; 632 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 633 enum drm_panel_orientation orientation; 634 635 enum drrs_support_type drrs_type; 636 637 struct { 638 int rate; 639 int lanes; 640 int preemphasis; 641 int vswing; 642 bool low_vswing; 643 bool initialized; 644 int bpp; 645 struct edp_power_seq pps; 646 bool hobl; 647 } edp; 648 649 struct { 650 bool enable; 651 bool full_link; 652 bool require_aux_wakeup; 653 int idle_frames; 654 enum psr_lines_to_wait lines_to_wait; 655 int tp1_wakeup_time_us; 656 int tp2_tp3_wakeup_time_us; 657 int psr2_tp2_tp3_wakeup_time_us; 658 } psr; 659 660 struct { 661 u16 pwm_freq_hz; 662 bool present; 663 bool active_low_pwm; 664 u8 min_brightness; /* min_brightness/255 of max */ 665 u8 controller; /* brightness controller number */ 666 enum intel_backlight_type type; 667 } backlight; 668 669 /* MIPI DSI */ 670 struct { 671 u16 panel_id; 672 struct mipi_config *config; 673 struct mipi_pps_data *pps; 674 u16 bl_ports; 675 u16 cabc_ports; 676 u8 seq_version; 677 u32 size; 678 u8 *data; 679 const u8 *sequence[MIPI_SEQ_MAX]; 680 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 681 enum drm_panel_orientation orientation; 682 } dsi; 683 684 int crt_ddc_pin; 685 686 struct list_head display_devices; 687 688 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 689 struct sdvo_device_mapping sdvo_mappings[2]; 690 }; 691 692 enum intel_ddb_partitioning { 693 INTEL_DDB_PART_1_2, 694 INTEL_DDB_PART_5_6, /* IVB+ */ 695 }; 696 697 struct ilk_wm_values { 698 u32 wm_pipe[3]; 699 u32 wm_lp[3]; 700 u32 wm_lp_spr[3]; 701 bool enable_fbc_wm; 702 enum intel_ddb_partitioning partitioning; 703 }; 704 705 struct g4x_pipe_wm { 706 u16 plane[I915_MAX_PLANES]; 707 u16 fbc; 708 }; 709 710 struct g4x_sr_wm { 711 u16 plane; 712 u16 cursor; 713 u16 fbc; 714 }; 715 716 struct vlv_wm_ddl_values { 717 u8 plane[I915_MAX_PLANES]; 718 }; 719 720 struct vlv_wm_values { 721 struct g4x_pipe_wm pipe[3]; 722 struct g4x_sr_wm sr; 723 struct vlv_wm_ddl_values ddl[3]; 724 u8 level; 725 bool cxsr; 726 }; 727 728 struct g4x_wm_values { 729 struct g4x_pipe_wm pipe[2]; 730 struct g4x_sr_wm sr; 731 struct g4x_sr_wm hpll; 732 bool cxsr; 733 bool hpll_en; 734 bool fbc_en; 735 }; 736 737 struct skl_ddb_entry { 738 u16 start, end; /* in number of blocks, 'end' is exclusive */ 739 }; 740 741 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 742 { 743 return entry->end - entry->start; 744 } 745 746 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 747 const struct skl_ddb_entry *e2) 748 { 749 if (e1->start == e2->start && e1->end == e2->end) 750 return true; 751 752 return false; 753 } 754 755 struct i915_frontbuffer_tracking { 756 spinlock_t lock; 757 758 /* 759 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 760 * scheduled flips. 761 */ 762 unsigned busy_bits; 763 unsigned flip_bits; 764 }; 765 766 struct i915_virtual_gpu { 767 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 768 bool active; 769 u32 caps; 770 }; 771 772 struct intel_cdclk_config { 773 unsigned int cdclk, vco, ref, bypass; 774 u8 voltage_level; 775 }; 776 777 struct i915_selftest_stash { 778 atomic_t counter; 779 }; 780 781 struct drm_i915_private { 782 struct drm_device drm; 783 784 /* FIXME: Device release actions should all be moved to drmm_ */ 785 bool do_release; 786 787 /* i915 device parameters */ 788 struct i915_params params; 789 790 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 791 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 792 struct intel_driver_caps caps; 793 794 /** 795 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 796 * end of stolen which we can optionally use to create GEM objects 797 * backed by stolen memory. Note that stolen_usable_size tells us 798 * exactly how much of this we are actually allowed to use, given that 799 * some portion of it is in fact reserved for use by hardware functions. 800 */ 801 struct resource dsm; 802 /** 803 * Reseved portion of Data Stolen Memory 804 */ 805 struct resource dsm_reserved; 806 807 /* 808 * Stolen memory is segmented in hardware with different portions 809 * offlimits to certain functions. 810 * 811 * The drm_mm is initialised to the total accessible range, as found 812 * from the PCI config. On Broadwell+, this is further restricted to 813 * avoid the first page! The upper end of stolen memory is reserved for 814 * hardware functions and similarly removed from the accessible range. 815 */ 816 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 817 818 struct intel_uncore uncore; 819 struct intel_uncore_mmio_debug mmio_debug; 820 821 struct i915_virtual_gpu vgpu; 822 823 struct intel_gvt *gvt; 824 825 struct intel_wopcm wopcm; 826 827 struct intel_csr csr; 828 829 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 830 831 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 832 * controller on different i2c buses. */ 833 struct mutex gmbus_mutex; 834 835 /** 836 * Base address of where the gmbus and gpio blocks are located (either 837 * on PCH or on SoC for platforms without PCH). 838 */ 839 u32 gpio_mmio_base; 840 841 u32 hsw_psr_mmio_adjust; 842 843 /* MMIO base address for MIPI regs */ 844 u32 mipi_mmio_base; 845 846 u32 pps_mmio_base; 847 848 wait_queue_head_t gmbus_wait_queue; 849 850 struct pci_dev *bridge_dev; 851 852 struct rb_root uabi_engines; 853 854 struct resource mch_res; 855 856 /* protects the irq masks */ 857 spinlock_t irq_lock; 858 859 bool display_irqs_enabled; 860 861 /* Sideband mailbox protection */ 862 struct mutex sb_lock; 863 struct pm_qos_request sb_qos; 864 865 /** Cached value of IMR to avoid reads in updating the bitfield */ 866 union { 867 u32 irq_mask; 868 u32 de_irq_mask[I915_MAX_PIPES]; 869 }; 870 u32 pipestat_irq_mask[I915_MAX_PIPES]; 871 872 struct i915_hotplug hotplug; 873 struct intel_fbc fbc; 874 struct i915_drrs drrs; 875 struct intel_opregion opregion; 876 struct intel_vbt_data vbt; 877 878 bool preserve_bios_swizzle; 879 880 /* overlay */ 881 struct intel_overlay *overlay; 882 883 /* backlight registers and fields in struct intel_panel */ 884 struct mutex backlight_lock; 885 886 /* protects panel power sequencer state */ 887 struct mutex pps_mutex; 888 889 unsigned int fsb_freq, mem_freq, is_ddr3; 890 unsigned int skl_preferred_vco_freq; 891 unsigned int max_cdclk_freq; 892 893 unsigned int max_dotclk_freq; 894 unsigned int hpll_freq; 895 unsigned int fdi_pll_freq; 896 unsigned int czclk_freq; 897 898 struct { 899 /* The current hardware cdclk configuration */ 900 struct intel_cdclk_config hw; 901 902 /* cdclk, divider, and ratio table from bspec */ 903 const struct intel_cdclk_vals *table; 904 905 struct intel_global_obj obj; 906 } cdclk; 907 908 struct { 909 /* The current hardware dbuf configuration */ 910 u8 enabled_slices; 911 912 struct intel_global_obj obj; 913 } dbuf; 914 915 /** 916 * wq - Driver workqueue for GEM. 917 * 918 * NOTE: Work items scheduled here are not allowed to grab any modeset 919 * locks, for otherwise the flushing done in the pageflip code will 920 * result in deadlocks. 921 */ 922 struct workqueue_struct *wq; 923 924 /* ordered wq for modesets */ 925 struct workqueue_struct *modeset_wq; 926 /* unbound hipri wq for page flips/plane updates */ 927 struct workqueue_struct *flip_wq; 928 929 /* Display functions */ 930 struct drm_i915_display_funcs display; 931 932 /* PCH chipset type */ 933 enum intel_pch pch_type; 934 unsigned short pch_id; 935 936 unsigned long quirks; 937 938 struct drm_atomic_state *modeset_restore_state; 939 struct drm_modeset_acquire_ctx reset_ctx; 940 941 struct i915_ggtt ggtt; /* VM representing the global address space */ 942 943 struct i915_gem_mm mm; 944 945 /* Kernel Modesetting */ 946 947 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 948 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 949 950 /** 951 * dpll and cdclk state is protected by connection_mutex 952 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 953 * Must be global rather than per dpll, because on some platforms plls 954 * share registers. 955 */ 956 struct { 957 struct mutex lock; 958 959 int num_shared_dpll; 960 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 961 const struct intel_dpll_mgr *mgr; 962 963 struct { 964 int nssc; 965 int ssc; 966 } ref_clks; 967 } dpll; 968 969 struct list_head global_obj_list; 970 971 /* 972 * For reading active_pipes holding any crtc lock is 973 * sufficient, for writing must hold all of them. 974 */ 975 u8 active_pipes; 976 977 struct i915_wa_list gt_wa_list; 978 979 struct i915_frontbuffer_tracking fb_tracking; 980 981 struct intel_atomic_helper { 982 struct llist_head free_list; 983 struct work_struct free_work; 984 } atomic_helper; 985 986 bool mchbar_need_disable; 987 988 struct intel_l3_parity l3_parity; 989 990 /* 991 * HTI (aka HDPORT) state read during initial hw readout. Most 992 * platforms don't have HTI, so this will just stay 0. Those that do 993 * will use this later to figure out which PLLs and PHYs are unavailable 994 * for driver usage. 995 */ 996 u32 hti_state; 997 998 /* 999 * edram size in MB. 1000 * Cannot be determined by PCIID. You must always read a register. 1001 */ 1002 u32 edram_size_mb; 1003 1004 struct i915_power_domains power_domains; 1005 1006 struct i915_gpu_error gpu_error; 1007 1008 struct drm_i915_gem_object *vlv_pctx; 1009 1010 /* list of fbdev register on this device */ 1011 struct intel_fbdev *fbdev; 1012 struct work_struct fbdev_suspend_work; 1013 1014 struct drm_property *broadcast_rgb_property; 1015 struct drm_property *force_audio_property; 1016 1017 /* hda/i915 audio component */ 1018 struct i915_audio_component *audio_component; 1019 bool audio_component_registered; 1020 /** 1021 * av_mutex - mutex for audio/video sync 1022 * 1023 */ 1024 struct mutex av_mutex; 1025 int audio_power_refcount; 1026 u32 audio_freq_cntrl; 1027 1028 u32 fdi_rx_config; 1029 1030 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1031 u32 chv_phy_control; 1032 /* 1033 * Shadows for CHV DPLL_MD regs to keep the state 1034 * checker somewhat working in the presence hardware 1035 * crappiness (can't read out DPLL_MD for pipes B & C). 1036 */ 1037 u32 chv_dpll_md[I915_MAX_PIPES]; 1038 u32 bxt_phy_grc; 1039 1040 u32 suspend_count; 1041 bool power_domains_suspended; 1042 struct i915_suspend_saved_registers regfile; 1043 struct vlv_s0ix_state *vlv_s0ix_state; 1044 1045 enum { 1046 I915_SAGV_UNKNOWN = 0, 1047 I915_SAGV_DISABLED, 1048 I915_SAGV_ENABLED, 1049 I915_SAGV_NOT_CONTROLLED 1050 } sagv_status; 1051 1052 u32 sagv_block_time_us; 1053 1054 struct { 1055 /* 1056 * Raw watermark latency values: 1057 * in 0.1us units for WM0, 1058 * in 0.5us units for WM1+. 1059 */ 1060 /* primary */ 1061 u16 pri_latency[5]; 1062 /* sprite */ 1063 u16 spr_latency[5]; 1064 /* cursor */ 1065 u16 cur_latency[5]; 1066 /* 1067 * Raw watermark memory latency values 1068 * for SKL for all 8 levels 1069 * in 1us units. 1070 */ 1071 u16 skl_latency[8]; 1072 1073 /* current hardware state */ 1074 union { 1075 struct ilk_wm_values hw; 1076 struct vlv_wm_values vlv; 1077 struct g4x_wm_values g4x; 1078 }; 1079 1080 u8 max_level; 1081 1082 /* 1083 * Should be held around atomic WM register writing; also 1084 * protects * intel_crtc->wm.active and 1085 * crtc_state->wm.need_postvbl_update. 1086 */ 1087 struct mutex wm_mutex; 1088 } wm; 1089 1090 struct dram_info { 1091 bool wm_lv_0_adjust_needed; 1092 u8 num_channels; 1093 bool symmetric_memory; 1094 enum intel_dram_type { 1095 INTEL_DRAM_UNKNOWN, 1096 INTEL_DRAM_DDR3, 1097 INTEL_DRAM_DDR4, 1098 INTEL_DRAM_LPDDR3, 1099 INTEL_DRAM_LPDDR4, 1100 INTEL_DRAM_DDR5, 1101 INTEL_DRAM_LPDDR5, 1102 } type; 1103 u8 num_qgv_points; 1104 } dram_info; 1105 1106 struct intel_bw_info { 1107 /* for each QGV point */ 1108 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1109 u8 num_qgv_points; 1110 u8 num_planes; 1111 } max_bw[6]; 1112 1113 struct intel_global_obj bw_obj; 1114 1115 struct intel_runtime_pm runtime_pm; 1116 1117 struct i915_perf perf; 1118 1119 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1120 struct intel_gt gt; 1121 1122 struct { 1123 struct i915_gem_contexts { 1124 spinlock_t lock; /* locks list */ 1125 struct list_head list; 1126 } contexts; 1127 1128 /* 1129 * We replace the local file with a global mappings as the 1130 * backing storage for the mmap is on the device and not 1131 * on the struct file, and we do not want to prolong the 1132 * lifetime of the local fd. To minimise the number of 1133 * anonymous inodes we create, we use a global singleton to 1134 * share the global mapping. 1135 */ 1136 struct file *mmap_singleton; 1137 } gem; 1138 1139 u8 framestart_delay; 1140 1141 u8 pch_ssc_use; 1142 1143 /* For i915gm/i945gm vblank irq workaround */ 1144 u8 vblank_enabled; 1145 1146 /* perform PHY state sanity checks? */ 1147 bool chv_phy_assert[2]; 1148 1149 bool ipc_enabled; 1150 1151 /* Used to save the pipe-to-encoder mapping for audio */ 1152 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1153 1154 /* necessary resource sharing with HDMI LPE audio driver. */ 1155 struct { 1156 struct platform_device *platdev; 1157 int irq; 1158 } lpe_audio; 1159 1160 struct i915_pmu pmu; 1161 1162 struct i915_hdcp_comp_master *hdcp_master; 1163 bool hdcp_comp_added; 1164 1165 /* Mutex to protect the above hdcp component related values. */ 1166 struct mutex hdcp_comp_mutex; 1167 1168 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1169 1170 /* 1171 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1172 * will be rejected. Instead look for a better place. 1173 */ 1174 }; 1175 1176 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1177 { 1178 return container_of(dev, struct drm_i915_private, drm); 1179 } 1180 1181 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1182 { 1183 return dev_get_drvdata(kdev); 1184 } 1185 1186 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1187 { 1188 return pci_get_drvdata(pdev); 1189 } 1190 1191 /* Simple iterator over all initialised engines */ 1192 #define for_each_engine(engine__, dev_priv__, id__) \ 1193 for ((id__) = 0; \ 1194 (id__) < I915_NUM_ENGINES; \ 1195 (id__)++) \ 1196 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1197 1198 /* Iterator over subset of engines selected by mask */ 1199 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1200 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 1201 (tmp__) ? \ 1202 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1203 0;) 1204 1205 #define rb_to_uabi_engine(rb) \ 1206 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1207 1208 #define for_each_uabi_engine(engine__, i915__) \ 1209 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1210 (engine__); \ 1211 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1212 1213 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 1214 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 1215 (engine__) && (engine__)->uabi_class == (class__); \ 1216 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1217 1218 #define I915_GTT_OFFSET_NONE ((u32)-1) 1219 1220 /* 1221 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1222 * considered to be the frontbuffer for the given plane interface-wise. This 1223 * doesn't mean that the hw necessarily already scans it out, but that any 1224 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1225 * 1226 * We have one bit per pipe and per scanout plane type. 1227 */ 1228 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1229 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1230 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1231 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1232 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1233 }) 1234 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1235 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1236 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1237 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1238 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1239 1240 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1241 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1242 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1243 1244 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1245 1246 /* 1247 * Deprecated: this will be replaced by individual IP checks: 1248 * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() 1249 */ 1250 #define INTEL_GEN(dev_priv) GRAPHICS_VER(dev_priv) 1251 /* 1252 * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as 1253 * appropriate. 1254 */ 1255 #define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e)) 1256 /* 1257 * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate. 1258 */ 1259 #define IS_GEN(dev_priv, n) (GRAPHICS_VER(dev_priv) == (n)) 1260 1261 #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver) 1262 #define IS_GRAPHICS_VER(i915, from, until) \ 1263 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 1264 1265 #define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver) 1266 #define IS_MEDIA_VER(i915, from, until) \ 1267 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 1268 1269 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver) 1270 #define IS_DISPLAY_VER(i915, from, until) \ 1271 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 1272 1273 #define REVID_FOREVER 0xff 1274 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) 1275 1276 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1277 1278 /* 1279 * Return true if revision is in range [since,until] inclusive. 1280 * 1281 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1282 */ 1283 #define IS_REVID(p, since, until) \ 1284 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1285 1286 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 1287 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step) 1288 1289 #define IS_DISPLAY_STEP(__i915, since, until) \ 1290 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 1291 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until)) 1292 1293 #define IS_GT_STEP(__i915, since, until) \ 1294 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \ 1295 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until)) 1296 1297 static __always_inline unsigned int 1298 __platform_mask_index(const struct intel_runtime_info *info, 1299 enum intel_platform p) 1300 { 1301 const unsigned int pbits = 1302 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1303 1304 /* Expand the platform_mask array if this fails. */ 1305 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1306 pbits * ARRAY_SIZE(info->platform_mask)); 1307 1308 return p / pbits; 1309 } 1310 1311 static __always_inline unsigned int 1312 __platform_mask_bit(const struct intel_runtime_info *info, 1313 enum intel_platform p) 1314 { 1315 const unsigned int pbits = 1316 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1317 1318 return p % pbits + INTEL_SUBPLATFORM_BITS; 1319 } 1320 1321 static inline u32 1322 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1323 { 1324 const unsigned int pi = __platform_mask_index(info, p); 1325 1326 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 1327 } 1328 1329 static __always_inline bool 1330 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1331 { 1332 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1333 const unsigned int pi = __platform_mask_index(info, p); 1334 const unsigned int pb = __platform_mask_bit(info, p); 1335 1336 BUILD_BUG_ON(!__builtin_constant_p(p)); 1337 1338 return info->platform_mask[pi] & BIT(pb); 1339 } 1340 1341 static __always_inline bool 1342 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1343 enum intel_platform p, unsigned int s) 1344 { 1345 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1346 const unsigned int pi = __platform_mask_index(info, p); 1347 const unsigned int pb = __platform_mask_bit(info, p); 1348 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1349 const u32 mask = info->platform_mask[pi]; 1350 1351 BUILD_BUG_ON(!__builtin_constant_p(p)); 1352 BUILD_BUG_ON(!__builtin_constant_p(s)); 1353 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1354 1355 /* Shift and test on the MSB position so sign flag can be used. */ 1356 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1357 } 1358 1359 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1360 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1361 1362 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1363 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1364 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1365 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1366 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1367 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1368 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1369 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1370 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1371 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1372 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1373 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1374 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1375 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1376 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1377 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1378 #define IS_IRONLAKE_M(dev_priv) \ 1379 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1380 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) 1381 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1382 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1383 INTEL_INFO(dev_priv)->gt == 1) 1384 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1385 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1386 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1387 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1388 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1389 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1390 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1391 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1392 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1393 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 1394 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1395 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1396 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 1397 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1398 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1399 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 1400 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 1401 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) 1402 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) 1403 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1404 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1405 #define IS_BDW_ULT(dev_priv) \ 1406 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1407 #define IS_BDW_ULX(dev_priv) \ 1408 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1409 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1410 INTEL_INFO(dev_priv)->gt == 3) 1411 #define IS_HSW_ULT(dev_priv) \ 1412 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1413 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1414 INTEL_INFO(dev_priv)->gt == 3) 1415 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1416 INTEL_INFO(dev_priv)->gt == 1) 1417 /* ULX machines are also considered ULT. */ 1418 #define IS_HSW_ULX(dev_priv) \ 1419 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1420 #define IS_SKL_ULT(dev_priv) \ 1421 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1422 #define IS_SKL_ULX(dev_priv) \ 1423 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1424 #define IS_KBL_ULT(dev_priv) \ 1425 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1426 #define IS_KBL_ULX(dev_priv) \ 1427 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1428 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1429 INTEL_INFO(dev_priv)->gt == 2) 1430 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1431 INTEL_INFO(dev_priv)->gt == 3) 1432 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1433 INTEL_INFO(dev_priv)->gt == 4) 1434 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1435 INTEL_INFO(dev_priv)->gt == 2) 1436 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1437 INTEL_INFO(dev_priv)->gt == 3) 1438 #define IS_CFL_ULT(dev_priv) \ 1439 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1440 #define IS_CFL_ULX(dev_priv) \ 1441 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1442 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1443 INTEL_INFO(dev_priv)->gt == 2) 1444 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1445 INTEL_INFO(dev_priv)->gt == 3) 1446 1447 #define IS_CML_ULT(dev_priv) \ 1448 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 1449 #define IS_CML_ULX(dev_priv) \ 1450 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 1451 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 1452 INTEL_INFO(dev_priv)->gt == 2) 1453 1454 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1455 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1456 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1457 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1458 1459 #define IS_TGL_U(dev_priv) \ 1460 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) 1461 1462 #define IS_TGL_Y(dev_priv) \ 1463 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) 1464 1465 #define SKL_REVID_A0 0x0 1466 #define SKL_REVID_B0 0x1 1467 #define SKL_REVID_C0 0x2 1468 #define SKL_REVID_D0 0x3 1469 #define SKL_REVID_E0 0x4 1470 #define SKL_REVID_F0 0x5 1471 #define SKL_REVID_G0 0x6 1472 #define SKL_REVID_H0 0x7 1473 1474 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1475 1476 #define BXT_REVID_A0 0x0 1477 #define BXT_REVID_A1 0x1 1478 #define BXT_REVID_B0 0x3 1479 #define BXT_REVID_B_LAST 0x8 1480 #define BXT_REVID_C0 0x9 1481 1482 #define IS_BXT_REVID(dev_priv, since, until) \ 1483 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1484 1485 #define IS_KBL_GT_STEP(dev_priv, since, until) \ 1486 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until)) 1487 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ 1488 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) 1489 1490 #define GLK_REVID_A0 0x0 1491 #define GLK_REVID_A1 0x1 1492 #define GLK_REVID_A2 0x2 1493 #define GLK_REVID_B0 0x3 1494 1495 #define IS_GLK_REVID(dev_priv, since, until) \ 1496 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1497 1498 #define CNL_REVID_A0 0x0 1499 #define CNL_REVID_B0 0x1 1500 #define CNL_REVID_C0 0x2 1501 1502 #define IS_CNL_REVID(p, since, until) \ 1503 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1504 1505 #define ICL_REVID_A0 0x0 1506 #define ICL_REVID_A2 0x1 1507 #define ICL_REVID_B0 0x3 1508 #define ICL_REVID_B2 0x4 1509 #define ICL_REVID_C0 0x5 1510 1511 #define IS_ICL_REVID(p, since, until) \ 1512 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1513 1514 #define EHL_REVID_A0 0x0 1515 #define EHL_REVID_B0 0x1 1516 1517 #define IS_JSL_EHL_REVID(p, since, until) \ 1518 (IS_JSL_EHL(p) && IS_REVID(p, since, until)) 1519 1520 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ 1521 (IS_TIGERLAKE(__i915) && \ 1522 IS_DISPLAY_STEP(__i915, since, until)) 1523 1524 #define IS_TGL_UY_GT_STEP(__i915, since, until) \ 1525 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ 1526 IS_GT_STEP(__i915, since, until)) 1527 1528 #define IS_TGL_GT_STEP(__i915, since, until) \ 1529 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ 1530 IS_GT_STEP(__i915, since, until)) 1531 1532 #define RKL_REVID_A0 0x0 1533 #define RKL_REVID_B0 0x1 1534 #define RKL_REVID_C0 0x4 1535 1536 #define IS_RKL_REVID(p, since, until) \ 1537 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) 1538 1539 #define DG1_REVID_A0 0x0 1540 #define DG1_REVID_B0 0x1 1541 1542 #define IS_DG1_REVID(p, since, until) \ 1543 (IS_DG1(p) && IS_REVID(p, since, until)) 1544 1545 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ 1546 (IS_ALDERLAKE_S(__i915) && \ 1547 IS_DISPLAY_STEP(__i915, since, until)) 1548 1549 #define IS_ADLS_GT_STEP(__i915, since, until) \ 1550 (IS_ALDERLAKE_S(__i915) && \ 1551 IS_GT_STEP(__i915, since, until)) 1552 1553 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ 1554 (IS_ALDERLAKE_P(__i915) && \ 1555 IS_DISPLAY_STEP(__i915, since, until)) 1556 1557 #define IS_ADLP_GT_STEP(__i915, since, until) \ 1558 (IS_ALDERLAKE_P(__i915) && \ 1559 IS_GT_STEP(__i915, since, until)) 1560 1561 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1562 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1563 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1564 1565 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 1566 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 1567 1568 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ 1569 unsigned int first__ = (first); \ 1570 unsigned int count__ = (count); \ 1571 ((gt)->info.engine_mask & \ 1572 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1573 }) 1574 #define VDBOX_MASK(gt) \ 1575 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 1576 #define VEBOX_MASK(gt) \ 1577 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 1578 1579 /* 1580 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1581 * All later gens can run the final buffer from the ppgtt 1582 */ 1583 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1584 1585 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1586 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1587 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1588 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1589 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 1590 1591 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1592 1593 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1594 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1595 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1596 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1597 1598 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq) 1599 1600 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1601 1602 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1603 #define HAS_PPGTT(dev_priv) \ 1604 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1605 #define HAS_FULL_PPGTT(dev_priv) \ 1606 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1607 1608 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1609 GEM_BUG_ON((sizes) == 0); \ 1610 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1611 }) 1612 1613 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1614 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1615 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1616 1617 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1618 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1619 1620 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1621 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1622 1623 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1624 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1625 (IS_CANNONLAKE(dev_priv) || \ 1626 IS_SKL_GT3(dev_priv) || \ 1627 IS_SKL_GT4(dev_priv)) 1628 1629 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1630 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1631 IS_GEMINILAKE(dev_priv) || \ 1632 IS_KABYLAKE(dev_priv)) 1633 1634 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1635 * rows, which changed the alignment requirements and fence programming. 1636 */ 1637 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1638 !(IS_I915G(dev_priv) || \ 1639 IS_I915GM(dev_priv))) 1640 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1641 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1642 1643 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1644 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1645 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1646 1647 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1648 1649 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1650 1651 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1652 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) 1653 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1654 #define HAS_PSR_HW_TRACKING(dev_priv) \ 1655 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 1656 #define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) 1657 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 1658 1659 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1660 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1661 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1662 1663 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1664 1665 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1666 1667 #define HAS_MSO(i915) (INTEL_GEN(i915) >= 12) 1668 1669 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1670 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1671 1672 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1673 1674 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1675 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1676 1677 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1678 1679 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1680 1681 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1682 1683 1684 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1685 1686 #define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10)) 1687 1688 /* DPF == dynamic parity feature */ 1689 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1690 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1691 2 : HAS_L3_DPF(dev_priv)) 1692 1693 #define GT_FREQUENCY_MULTIPLIER 50 1694 #define GEN9_FREQ_SCALER 3 1695 1696 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1697 1698 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1699 1700 #define HAS_VRR(i915) (INTEL_GEN(i915) >= 12) 1701 1702 /* Only valid when HAS_DISPLAY() is true */ 1703 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 1704 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) 1705 1706 static inline bool run_as_guest(void) 1707 { 1708 return !hypervisor_is_type(X86_HYPER_NATIVE); 1709 } 1710 1711 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ 1712 IS_ALDERLAKE_S(dev_priv)) 1713 1714 static inline bool intel_vtd_active(void) 1715 { 1716 #ifdef CONFIG_INTEL_IOMMU 1717 if (intel_iommu_gfx_mapped) 1718 return true; 1719 #endif 1720 1721 /* Running as a guest, we assume the host is enforcing VT'd */ 1722 return run_as_guest(); 1723 } 1724 1725 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1726 { 1727 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1728 } 1729 1730 static inline bool 1731 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) 1732 { 1733 return IS_BROXTON(i915) && intel_vtd_active(); 1734 } 1735 1736 static inline bool 1737 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) 1738 { 1739 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); 1740 } 1741 1742 /* i915_drv.c */ 1743 extern const struct dev_pm_ops i915_pm_ops; 1744 1745 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1746 void i915_driver_remove(struct drm_i915_private *i915); 1747 void i915_driver_shutdown(struct drm_i915_private *i915); 1748 1749 int i915_resume_switcheroo(struct drm_i915_private *i915); 1750 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1751 1752 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1753 struct drm_file *file_priv); 1754 1755 /* i915_gem.c */ 1756 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1757 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1758 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1759 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1760 1761 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1762 1763 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1764 { 1765 /* 1766 * A single pass should suffice to release all the freed objects (along 1767 * most call paths) , but be a little more paranoid in that freeing 1768 * the objects does take a little amount of time, during which the rcu 1769 * callbacks could have added new objects into the freed list, and 1770 * armed the work again. 1771 */ 1772 while (atomic_read(&i915->mm.free_count)) { 1773 flush_work(&i915->mm.free_work); 1774 rcu_barrier(); 1775 } 1776 } 1777 1778 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1779 { 1780 /* 1781 * Similar to objects above (see i915_gem_drain_freed-objects), in 1782 * general we have workers that are armed by RCU and then rearm 1783 * themselves in their callbacks. To be paranoid, we need to 1784 * drain the workqueue a second time after waiting for the RCU 1785 * grace period so that we catch work queued via RCU from the first 1786 * pass. As neither drain_workqueue() nor flush_workqueue() report 1787 * a result, we make an assumption that we only don't require more 1788 * than 3 passes to catch all _recursive_ RCU delayed work. 1789 * 1790 */ 1791 int pass = 3; 1792 do { 1793 flush_workqueue(i915->wq); 1794 rcu_barrier(); 1795 i915_gem_drain_freed_objects(i915); 1796 } while (--pass); 1797 drain_workqueue(i915->wq); 1798 } 1799 1800 struct i915_vma * __must_check 1801 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, 1802 struct i915_gem_ww_ctx *ww, 1803 const struct i915_ggtt_view *view, 1804 u64 size, u64 alignment, u64 flags); 1805 1806 static inline struct i915_vma * __must_check 1807 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1808 const struct i915_ggtt_view *view, 1809 u64 size, u64 alignment, u64 flags) 1810 { 1811 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); 1812 } 1813 1814 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1815 unsigned long flags); 1816 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1817 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1818 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2) 1819 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) 1820 1821 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1822 1823 int i915_gem_dumb_create(struct drm_file *file_priv, 1824 struct drm_device *dev, 1825 struct drm_mode_create_dumb *args); 1826 1827 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1828 1829 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1830 { 1831 return atomic_read(&error->reset_count); 1832 } 1833 1834 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1835 const struct intel_engine_cs *engine) 1836 { 1837 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1838 } 1839 1840 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1841 void i915_gem_driver_register(struct drm_i915_private *i915); 1842 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1843 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1844 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1845 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1846 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1847 void i915_gem_resume(struct drm_i915_private *dev_priv); 1848 1849 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1850 1851 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1852 enum i915_cache_level cache_level); 1853 1854 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1855 struct dma_buf *dma_buf); 1856 1857 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1858 1859 static inline struct i915_gem_context * 1860 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1861 { 1862 return xa_load(&file_priv->context_xa, id); 1863 } 1864 1865 static inline struct i915_gem_context * 1866 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1867 { 1868 struct i915_gem_context *ctx; 1869 1870 rcu_read_lock(); 1871 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1872 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1873 ctx = NULL; 1874 rcu_read_unlock(); 1875 1876 return ctx; 1877 } 1878 1879 /* i915_gem_evict.c */ 1880 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1881 u64 min_size, u64 alignment, 1882 unsigned long color, 1883 u64 start, u64 end, 1884 unsigned flags); 1885 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1886 struct drm_mm_node *node, 1887 unsigned int flags); 1888 int i915_gem_evict_vm(struct i915_address_space *vm); 1889 1890 /* i915_gem_internal.c */ 1891 struct drm_i915_gem_object * 1892 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1893 phys_addr_t size); 1894 1895 /* i915_gem_tiling.c */ 1896 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1897 { 1898 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1899 1900 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1901 i915_gem_object_is_tiled(obj); 1902 } 1903 1904 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1905 unsigned int tiling, unsigned int stride); 1906 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1907 unsigned int tiling, unsigned int stride); 1908 1909 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1910 1911 /* i915_cmd_parser.c */ 1912 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1913 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1914 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1915 unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length, 1916 bool trampoline); 1917 1918 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1919 struct i915_vma *batch, 1920 unsigned long batch_offset, 1921 unsigned long batch_length, 1922 struct i915_vma *shadow, 1923 unsigned long *jump_whitelist, 1924 void *shadow_map, 1925 const void *batch_map); 1926 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1927 1928 /* intel_device_info.c */ 1929 static inline struct intel_device_info * 1930 mkwrite_device_info(struct drm_i915_private *dev_priv) 1931 { 1932 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1933 } 1934 1935 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1936 struct drm_file *file); 1937 1938 /* i915_mm.c */ 1939 int remap_io_sg(struct vm_area_struct *vma, 1940 unsigned long addr, unsigned long size, 1941 struct scatterlist *sgl, resource_size_t iobase); 1942 1943 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1944 { 1945 if (INTEL_GEN(i915) >= 10) 1946 return CNL_HWS_CSB_WRITE_INDEX; 1947 else 1948 return I915_HWS_CSB_WRITE_INDEX; 1949 } 1950 1951 static inline enum i915_map_type 1952 i915_coherent_map_type(struct drm_i915_private *i915, 1953 struct drm_i915_gem_object *obj, bool always_coherent) 1954 { 1955 if (i915_gem_object_is_lmem(obj)) 1956 return I915_MAP_WC; 1957 if (HAS_LLC(i915) || always_coherent) 1958 return I915_MAP_WB; 1959 else 1960 return I915_MAP_WC; 1961 } 1962 1963 #endif 1964