1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/dma-resv.h> 47 #include <linux/shmem_fs.h> 48 #include <linux/stackdepot.h> 49 #include <linux/xarray.h> 50 51 #include <drm/intel-gtt.h> 52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 53 #include <drm/drm_gem.h> 54 #include <drm/drm_auth.h> 55 #include <drm/drm_cache.h> 56 #include <drm/drm_util.h> 57 #include <drm/drm_dsc.h> 58 #include <drm/drm_atomic.h> 59 #include <drm/drm_connector.h> 60 #include <drm/i915_mei_hdcp_interface.h> 61 62 #include "i915_params.h" 63 #include "i915_reg.h" 64 #include "i915_utils.h" 65 66 #include "display/intel_bios.h" 67 #include "display/intel_display.h" 68 #include "display/intel_display_power.h" 69 #include "display/intel_dpll_mgr.h" 70 #include "display/intel_dsb.h" 71 #include "display/intel_frontbuffer.h" 72 #include "display/intel_global_state.h" 73 #include "display/intel_gmbus.h" 74 #include "display/intel_opregion.h" 75 76 #include "gem/i915_gem_context_types.h" 77 #include "gem/i915_gem_shrinker.h" 78 #include "gem/i915_gem_stolen.h" 79 80 #include "gt/intel_lrc.h" 81 #include "gt/intel_engine.h" 82 #include "gt/intel_gt_types.h" 83 #include "gt/intel_workarounds.h" 84 #include "gt/uc/intel_uc.h" 85 86 #include "intel_device_info.h" 87 #include "intel_pch.h" 88 #include "intel_runtime_pm.h" 89 #include "intel_memory_region.h" 90 #include "intel_uncore.h" 91 #include "intel_wakeref.h" 92 #include "intel_wopcm.h" 93 94 #include "i915_gem.h" 95 #include "i915_gem_gtt.h" 96 #include "i915_gpu_error.h" 97 #include "i915_perf_types.h" 98 #include "i915_request.h" 99 #include "i915_scheduler.h" 100 #include "gt/intel_timeline.h" 101 #include "i915_vma.h" 102 #include "i915_irq.h" 103 104 #include "intel_region_lmem.h" 105 106 /* General customization: 107 */ 108 109 #define DRIVER_NAME "i915" 110 #define DRIVER_DESC "Intel Graphics" 111 #define DRIVER_DATE "20200515" 112 #define DRIVER_TIMESTAMP 1589543364 113 114 struct drm_i915_gem_object; 115 116 /* 117 * The code assumes that the hpd_pins below have consecutive values and 118 * starting with HPD_PORT_A, the HPD pin associated with any port can be 119 * retrieved by adding the corresponding port (or phy) enum value to 120 * HPD_PORT_A in most cases. For example: 121 * HPD_PORT_C = HPD_PORT_A + PHY_C - PHY_A 122 */ 123 enum hpd_pin { 124 HPD_NONE = 0, 125 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 126 HPD_CRT, 127 HPD_SDVO_B, 128 HPD_SDVO_C, 129 HPD_PORT_A, 130 HPD_PORT_B, 131 HPD_PORT_C, 132 HPD_PORT_D, 133 HPD_PORT_E, 134 HPD_PORT_F, 135 HPD_PORT_G, 136 HPD_PORT_H, 137 HPD_PORT_I, 138 139 HPD_NUM_PINS 140 }; 141 142 #define for_each_hpd_pin(__pin) \ 143 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 144 145 /* Threshold == 5 for long IRQs, 50 for short */ 146 #define HPD_STORM_DEFAULT_THRESHOLD 50 147 148 struct i915_hotplug { 149 struct delayed_work hotplug_work; 150 151 const u32 *hpd, *pch_hpd; 152 153 struct { 154 unsigned long last_jiffies; 155 int count; 156 enum { 157 HPD_ENABLED = 0, 158 HPD_DISABLED = 1, 159 HPD_MARK_DISABLED = 2 160 } state; 161 } stats[HPD_NUM_PINS]; 162 u32 event_bits; 163 u32 retry_bits; 164 struct delayed_work reenable_work; 165 166 u32 long_port_mask; 167 u32 short_port_mask; 168 struct work_struct dig_port_work; 169 170 struct work_struct poll_init_work; 171 bool poll_enabled; 172 173 unsigned int hpd_storm_threshold; 174 /* Whether or not to count short HPD IRQs in HPD storms */ 175 u8 hpd_short_storm_enabled; 176 177 /* 178 * if we get a HPD irq from DP and a HPD irq from non-DP 179 * the non-DP HPD could block the workqueue on a mode config 180 * mutex getting, that userspace may have taken. However 181 * userspace is waiting on the DP workqueue to run which is 182 * blocked behind the non-DP one. 183 */ 184 struct workqueue_struct *dp_wq; 185 }; 186 187 #define I915_GEM_GPU_DOMAINS \ 188 (I915_GEM_DOMAIN_RENDER | \ 189 I915_GEM_DOMAIN_SAMPLER | \ 190 I915_GEM_DOMAIN_COMMAND | \ 191 I915_GEM_DOMAIN_INSTRUCTION | \ 192 I915_GEM_DOMAIN_VERTEX) 193 194 struct drm_i915_private; 195 struct i915_mm_struct; 196 struct i915_mmu_object; 197 198 struct drm_i915_file_private { 199 struct drm_i915_private *dev_priv; 200 201 union { 202 struct drm_file *file; 203 struct rcu_head rcu; 204 }; 205 206 struct { 207 spinlock_t lock; 208 struct list_head request_list; 209 } mm; 210 211 struct xarray context_xa; 212 struct xarray vm_xa; 213 214 unsigned int bsd_engine; 215 216 /* 217 * Every context ban increments per client ban score. Also 218 * hangs in short succession increments ban score. If ban threshold 219 * is reached, client is considered banned and submitting more work 220 * will fail. This is a stop gap measure to limit the badly behaving 221 * clients access to gpu. Note that unbannable contexts never increment 222 * the client ban score. 223 */ 224 #define I915_CLIENT_SCORE_HANG_FAST 1 225 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 226 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 227 #define I915_CLIENT_SCORE_BANNED 9 228 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 229 atomic_t ban_score; 230 unsigned long hang_timestamp; 231 }; 232 233 /* Interface history: 234 * 235 * 1.1: Original. 236 * 1.2: Add Power Management 237 * 1.3: Add vblank support 238 * 1.4: Fix cmdbuffer path, add heap destroy 239 * 1.5: Add vblank pipe configuration 240 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 241 * - Support vertical blank on secondary display pipe 242 */ 243 #define DRIVER_MAJOR 1 244 #define DRIVER_MINOR 6 245 #define DRIVER_PATCHLEVEL 0 246 247 struct intel_overlay; 248 struct intel_overlay_error_state; 249 250 struct sdvo_device_mapping { 251 u8 initialized; 252 u8 dvo_port; 253 u8 slave_addr; 254 u8 dvo_wiring; 255 u8 i2c_pin; 256 u8 ddc_pin; 257 }; 258 259 struct intel_connector; 260 struct intel_encoder; 261 struct intel_atomic_state; 262 struct intel_cdclk_config; 263 struct intel_cdclk_state; 264 struct intel_cdclk_vals; 265 struct intel_initial_plane_config; 266 struct intel_crtc; 267 struct intel_limit; 268 struct dpll; 269 270 struct drm_i915_display_funcs { 271 void (*get_cdclk)(struct drm_i915_private *dev_priv, 272 struct intel_cdclk_config *cdclk_config); 273 void (*set_cdclk)(struct drm_i915_private *dev_priv, 274 const struct intel_cdclk_config *cdclk_config, 275 enum pipe pipe); 276 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 277 enum i9xx_plane_id i9xx_plane); 278 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 279 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 280 void (*initial_watermarks)(struct intel_atomic_state *state, 281 struct intel_crtc *crtc); 282 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 283 struct intel_crtc *crtc); 284 void (*optimize_watermarks)(struct intel_atomic_state *state, 285 struct intel_crtc *crtc); 286 int (*compute_global_watermarks)(struct intel_atomic_state *state); 287 void (*update_wm)(struct intel_crtc *crtc); 288 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 289 u8 (*calc_voltage_level)(int cdclk); 290 /* Returns the active state of the crtc, and if the crtc is active, 291 * fills out the pipe-config with the hw state. */ 292 bool (*get_pipe_config)(struct intel_crtc *, 293 struct intel_crtc_state *); 294 void (*get_initial_plane_config)(struct intel_crtc *, 295 struct intel_initial_plane_config *); 296 int (*crtc_compute_clock)(struct intel_crtc *crtc, 297 struct intel_crtc_state *crtc_state); 298 void (*crtc_enable)(struct intel_atomic_state *state, 299 struct intel_crtc *crtc); 300 void (*crtc_disable)(struct intel_atomic_state *state, 301 struct intel_crtc *crtc); 302 void (*commit_modeset_enables)(struct intel_atomic_state *state); 303 void (*commit_modeset_disables)(struct intel_atomic_state *state); 304 void (*audio_codec_enable)(struct intel_encoder *encoder, 305 const struct intel_crtc_state *crtc_state, 306 const struct drm_connector_state *conn_state); 307 void (*audio_codec_disable)(struct intel_encoder *encoder, 308 const struct intel_crtc_state *old_crtc_state, 309 const struct drm_connector_state *old_conn_state); 310 void (*fdi_link_train)(struct intel_crtc *crtc, 311 const struct intel_crtc_state *crtc_state); 312 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 313 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 314 /* clock updates for mode set */ 315 /* cursor updates */ 316 /* render clock increase/decrease */ 317 /* display clock increase/decrease */ 318 /* pll clock increase/decrease */ 319 320 int (*color_check)(struct intel_crtc_state *crtc_state); 321 /* 322 * Program double buffered color management registers during 323 * vblank evasion. The registers should then latch during the 324 * next vblank start, alongside any other double buffered registers 325 * involved with the same commit. 326 */ 327 void (*color_commit)(const struct intel_crtc_state *crtc_state); 328 /* 329 * Load LUTs (and other single buffered color management 330 * registers). Will (hopefully) be called during the vblank 331 * following the latching of any double buffered registers 332 * involved with the same commit. 333 */ 334 void (*load_luts)(const struct intel_crtc_state *crtc_state); 335 void (*read_luts)(struct intel_crtc_state *crtc_state); 336 }; 337 338 struct intel_csr { 339 struct work_struct work; 340 const char *fw_path; 341 u32 required_version; 342 u32 max_fw_size; /* bytes */ 343 u32 *dmc_payload; 344 u32 dmc_fw_size; /* dwords */ 345 u32 version; 346 u32 mmio_count; 347 i915_reg_t mmioaddr[20]; 348 u32 mmiodata[20]; 349 u32 dc_state; 350 u32 target_dc_state; 351 u32 allowed_dc_mask; 352 intel_wakeref_t wakeref; 353 }; 354 355 enum i915_cache_level { 356 I915_CACHE_NONE = 0, 357 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 358 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 359 caches, eg sampler/render caches, and the 360 large Last-Level-Cache. LLC is coherent with 361 the CPU, but L3 is only visible to the GPU. */ 362 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 363 }; 364 365 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 366 367 struct intel_fbc { 368 /* This is always the inner lock when overlapping with struct_mutex and 369 * it's the outer lock when overlapping with stolen_lock. */ 370 struct mutex lock; 371 unsigned threshold; 372 unsigned int possible_framebuffer_bits; 373 unsigned int busy_bits; 374 struct intel_crtc *crtc; 375 376 struct drm_mm_node compressed_fb; 377 struct drm_mm_node *compressed_llb; 378 379 bool false_color; 380 381 bool active; 382 bool activated; 383 bool flip_pending; 384 385 bool underrun_detected; 386 struct work_struct underrun_work; 387 388 /* 389 * Due to the atomic rules we can't access some structures without the 390 * appropriate locking, so we cache information here in order to avoid 391 * these problems. 392 */ 393 struct intel_fbc_state_cache { 394 struct { 395 unsigned int mode_flags; 396 u32 hsw_bdw_pixel_rate; 397 } crtc; 398 399 struct { 400 unsigned int rotation; 401 int src_w; 402 int src_h; 403 bool visible; 404 /* 405 * Display surface base address adjustement for 406 * pageflips. Note that on gen4+ this only adjusts up 407 * to a tile, offsets within a tile are handled in 408 * the hw itself (with the TILEOFF register). 409 */ 410 int adjusted_x; 411 int adjusted_y; 412 413 u16 pixel_blend_mode; 414 } plane; 415 416 struct { 417 const struct drm_format_info *format; 418 unsigned int stride; 419 u64 modifier; 420 } fb; 421 422 unsigned int fence_y_offset; 423 u16 gen9_wa_cfb_stride; 424 s8 fence_id; 425 } state_cache; 426 427 /* 428 * This structure contains everything that's relevant to program the 429 * hardware registers. When we want to figure out if we need to disable 430 * and re-enable FBC for a new configuration we just check if there's 431 * something different in the struct. The genx_fbc_activate functions 432 * are supposed to read from it in order to program the registers. 433 */ 434 struct intel_fbc_reg_params { 435 struct { 436 enum pipe pipe; 437 enum i9xx_plane_id i9xx_plane; 438 } crtc; 439 440 struct { 441 const struct drm_format_info *format; 442 unsigned int stride; 443 u64 modifier; 444 } fb; 445 446 int cfb_size; 447 unsigned int fence_y_offset; 448 u16 gen9_wa_cfb_stride; 449 s8 fence_id; 450 bool plane_visible; 451 } params; 452 453 const char *no_fbc_reason; 454 }; 455 456 /* 457 * HIGH_RR is the highest eDP panel refresh rate read from EDID 458 * LOW_RR is the lowest eDP panel refresh rate found from EDID 459 * parsing for same resolution. 460 */ 461 enum drrs_refresh_rate_type { 462 DRRS_HIGH_RR, 463 DRRS_LOW_RR, 464 DRRS_MAX_RR, /* RR count */ 465 }; 466 467 enum drrs_support_type { 468 DRRS_NOT_SUPPORTED = 0, 469 STATIC_DRRS_SUPPORT = 1, 470 SEAMLESS_DRRS_SUPPORT = 2 471 }; 472 473 struct intel_dp; 474 struct i915_drrs { 475 struct mutex mutex; 476 struct delayed_work work; 477 struct intel_dp *dp; 478 unsigned busy_frontbuffer_bits; 479 enum drrs_refresh_rate_type refresh_rate_type; 480 enum drrs_support_type type; 481 }; 482 483 struct i915_psr { 484 struct mutex lock; 485 486 #define I915_PSR_DEBUG_MODE_MASK 0x0f 487 #define I915_PSR_DEBUG_DEFAULT 0x00 488 #define I915_PSR_DEBUG_DISABLE 0x01 489 #define I915_PSR_DEBUG_ENABLE 0x02 490 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 491 #define I915_PSR_DEBUG_IRQ 0x10 492 493 u32 debug; 494 bool sink_support; 495 bool enabled; 496 struct intel_dp *dp; 497 enum pipe pipe; 498 enum transcoder transcoder; 499 bool active; 500 struct work_struct work; 501 unsigned busy_frontbuffer_bits; 502 bool sink_psr2_support; 503 bool link_standby; 504 bool colorimetry_support; 505 bool psr2_enabled; 506 u8 sink_sync_latency; 507 ktime_t last_entry_attempt; 508 ktime_t last_exit; 509 bool sink_not_reliable; 510 bool irq_aux_error; 511 u16 su_x_granularity; 512 bool dc3co_enabled; 513 u32 dc3co_exit_delay; 514 struct delayed_work dc3co_work; 515 bool force_mode_changed; 516 struct drm_dp_vsc_sdp vsc; 517 }; 518 519 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 520 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 521 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 522 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 523 #define QUIRK_INCREASE_T12_DELAY (1<<6) 524 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 525 526 struct intel_fbdev; 527 struct intel_fbc_work; 528 529 struct intel_gmbus { 530 struct i2c_adapter adapter; 531 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 532 u32 force_bit; 533 u32 reg0; 534 i915_reg_t gpio_reg; 535 struct i2c_algo_bit_data bit_algo; 536 struct drm_i915_private *dev_priv; 537 }; 538 539 struct i915_suspend_saved_registers { 540 u32 saveDSPARB; 541 u32 saveFBC_CONTROL; 542 u32 saveCACHE_MODE_0; 543 u32 saveMI_ARB_STATE; 544 u32 saveSWF0[16]; 545 u32 saveSWF1[16]; 546 u32 saveSWF3[3]; 547 u32 savePCH_PORT_HOTPLUG; 548 u16 saveGCDGMBUS; 549 }; 550 551 struct vlv_s0ix_state; 552 553 #define MAX_L3_SLICES 2 554 struct intel_l3_parity { 555 u32 *remap_info[MAX_L3_SLICES]; 556 struct work_struct error_work; 557 int which_slice; 558 }; 559 560 struct i915_gem_mm { 561 /** Memory allocator for GTT stolen memory */ 562 struct drm_mm stolen; 563 /** Protects the usage of the GTT stolen memory allocator. This is 564 * always the inner lock when overlapping with struct_mutex. */ 565 struct mutex stolen_lock; 566 567 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 568 spinlock_t obj_lock; 569 570 /** 571 * List of objects which are purgeable. 572 */ 573 struct list_head purge_list; 574 575 /** 576 * List of objects which have allocated pages and are shrinkable. 577 */ 578 struct list_head shrink_list; 579 580 /** 581 * List of objects which are pending destruction. 582 */ 583 struct llist_head free_list; 584 struct work_struct free_work; 585 /** 586 * Count of objects pending destructions. Used to skip needlessly 587 * waiting on an RCU barrier if no objects are waiting to be freed. 588 */ 589 atomic_t free_count; 590 591 /** 592 * Small stash of WC pages 593 */ 594 struct pagestash wc_stash; 595 596 /** 597 * tmpfs instance used for shmem backed objects 598 */ 599 struct vfsmount *gemfs; 600 601 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 602 603 struct notifier_block oom_notifier; 604 struct notifier_block vmap_notifier; 605 struct shrinker shrinker; 606 607 /** 608 * Workqueue to fault in userptr pages, flushed by the execbuf 609 * when required but otherwise left to userspace to try again 610 * on EAGAIN. 611 */ 612 struct workqueue_struct *userptr_wq; 613 614 /* shrinker accounting, also useful for userland debugging */ 615 u64 shrink_memory; 616 u32 shrink_count; 617 }; 618 619 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 620 621 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 622 u64 context); 623 624 static inline unsigned long 625 i915_fence_timeout(const struct drm_i915_private *i915) 626 { 627 return i915_fence_context_timeout(i915, U64_MAX); 628 } 629 630 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 631 #define I915_NUM_QGV_POINTS 8 632 633 struct ddi_vbt_port_info { 634 /* Non-NULL if port present. */ 635 const struct child_device_config *child; 636 637 int max_tmds_clock; 638 639 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 640 u8 hdmi_level_shift; 641 u8 hdmi_level_shift_set:1; 642 643 u8 supports_dvi:1; 644 u8 supports_hdmi:1; 645 u8 supports_dp:1; 646 u8 supports_edp:1; 647 u8 supports_typec_usb:1; 648 u8 supports_tbt:1; 649 650 u8 alternate_aux_channel; 651 u8 alternate_ddc_pin; 652 653 u8 dp_boost_level; 654 u8 hdmi_boost_level; 655 int dp_max_link_rate; /* 0 for not limited by VBT */ 656 }; 657 658 enum psr_lines_to_wait { 659 PSR_0_LINES_TO_WAIT = 0, 660 PSR_1_LINE_TO_WAIT, 661 PSR_4_LINES_TO_WAIT, 662 PSR_8_LINES_TO_WAIT 663 }; 664 665 struct intel_vbt_data { 666 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 667 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 668 669 /* Feature bits */ 670 unsigned int int_tv_support:1; 671 unsigned int lvds_dither:1; 672 unsigned int int_crt_support:1; 673 unsigned int lvds_use_ssc:1; 674 unsigned int int_lvds_support:1; 675 unsigned int display_clock_mode:1; 676 unsigned int fdi_rx_polarity_inverted:1; 677 unsigned int panel_type:4; 678 int lvds_ssc_freq; 679 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 680 enum drm_panel_orientation orientation; 681 682 enum drrs_support_type drrs_type; 683 684 struct { 685 int rate; 686 int lanes; 687 int preemphasis; 688 int vswing; 689 bool low_vswing; 690 bool initialized; 691 int bpp; 692 struct edp_power_seq pps; 693 } edp; 694 695 struct { 696 bool enable; 697 bool full_link; 698 bool require_aux_wakeup; 699 int idle_frames; 700 enum psr_lines_to_wait lines_to_wait; 701 int tp1_wakeup_time_us; 702 int tp2_tp3_wakeup_time_us; 703 int psr2_tp2_tp3_wakeup_time_us; 704 } psr; 705 706 struct { 707 u16 pwm_freq_hz; 708 bool present; 709 bool active_low_pwm; 710 u8 min_brightness; /* min_brightness/255 of max */ 711 u8 controller; /* brightness controller number */ 712 enum intel_backlight_type type; 713 } backlight; 714 715 /* MIPI DSI */ 716 struct { 717 u16 panel_id; 718 struct mipi_config *config; 719 struct mipi_pps_data *pps; 720 u16 bl_ports; 721 u16 cabc_ports; 722 u8 seq_version; 723 u32 size; 724 u8 *data; 725 const u8 *sequence[MIPI_SEQ_MAX]; 726 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 727 enum drm_panel_orientation orientation; 728 } dsi; 729 730 int crt_ddc_pin; 731 732 struct list_head display_devices; 733 734 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 735 struct sdvo_device_mapping sdvo_mappings[2]; 736 }; 737 738 enum intel_ddb_partitioning { 739 INTEL_DDB_PART_1_2, 740 INTEL_DDB_PART_5_6, /* IVB+ */ 741 }; 742 743 struct ilk_wm_values { 744 u32 wm_pipe[3]; 745 u32 wm_lp[3]; 746 u32 wm_lp_spr[3]; 747 bool enable_fbc_wm; 748 enum intel_ddb_partitioning partitioning; 749 }; 750 751 struct g4x_pipe_wm { 752 u16 plane[I915_MAX_PLANES]; 753 u16 fbc; 754 }; 755 756 struct g4x_sr_wm { 757 u16 plane; 758 u16 cursor; 759 u16 fbc; 760 }; 761 762 struct vlv_wm_ddl_values { 763 u8 plane[I915_MAX_PLANES]; 764 }; 765 766 struct vlv_wm_values { 767 struct g4x_pipe_wm pipe[3]; 768 struct g4x_sr_wm sr; 769 struct vlv_wm_ddl_values ddl[3]; 770 u8 level; 771 bool cxsr; 772 }; 773 774 struct g4x_wm_values { 775 struct g4x_pipe_wm pipe[2]; 776 struct g4x_sr_wm sr; 777 struct g4x_sr_wm hpll; 778 bool cxsr; 779 bool hpll_en; 780 bool fbc_en; 781 }; 782 783 struct skl_ddb_entry { 784 u16 start, end; /* in number of blocks, 'end' is exclusive */ 785 }; 786 787 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 788 { 789 return entry->end - entry->start; 790 } 791 792 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 793 const struct skl_ddb_entry *e2) 794 { 795 if (e1->start == e2->start && e1->end == e2->end) 796 return true; 797 798 return false; 799 } 800 801 struct i915_frontbuffer_tracking { 802 spinlock_t lock; 803 804 /* 805 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 806 * scheduled flips. 807 */ 808 unsigned busy_bits; 809 unsigned flip_bits; 810 }; 811 812 struct i915_virtual_gpu { 813 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 814 bool active; 815 u32 caps; 816 }; 817 818 struct intel_cdclk_config { 819 unsigned int cdclk, vco, ref, bypass; 820 u8 voltage_level; 821 }; 822 823 struct i915_selftest_stash { 824 atomic_t counter; 825 }; 826 827 struct drm_i915_private { 828 struct drm_device drm; 829 830 /* FIXME: Device release actions should all be moved to drmm_ */ 831 bool do_release; 832 833 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 834 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 835 struct intel_driver_caps caps; 836 837 /** 838 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 839 * end of stolen which we can optionally use to create GEM objects 840 * backed by stolen memory. Note that stolen_usable_size tells us 841 * exactly how much of this we are actually allowed to use, given that 842 * some portion of it is in fact reserved for use by hardware functions. 843 */ 844 struct resource dsm; 845 /** 846 * Reseved portion of Data Stolen Memory 847 */ 848 struct resource dsm_reserved; 849 850 /* 851 * Stolen memory is segmented in hardware with different portions 852 * offlimits to certain functions. 853 * 854 * The drm_mm is initialised to the total accessible range, as found 855 * from the PCI config. On Broadwell+, this is further restricted to 856 * avoid the first page! The upper end of stolen memory is reserved for 857 * hardware functions and similarly removed from the accessible range. 858 */ 859 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 860 861 struct intel_uncore uncore; 862 struct intel_uncore_mmio_debug mmio_debug; 863 864 struct i915_virtual_gpu vgpu; 865 866 struct intel_gvt *gvt; 867 868 struct intel_wopcm wopcm; 869 870 struct intel_csr csr; 871 872 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 873 874 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 875 * controller on different i2c buses. */ 876 struct mutex gmbus_mutex; 877 878 /** 879 * Base address of where the gmbus and gpio blocks are located (either 880 * on PCH or on SoC for platforms without PCH). 881 */ 882 u32 gpio_mmio_base; 883 884 u32 hsw_psr_mmio_adjust; 885 886 /* MMIO base address for MIPI regs */ 887 u32 mipi_mmio_base; 888 889 u32 pps_mmio_base; 890 891 wait_queue_head_t gmbus_wait_queue; 892 893 struct pci_dev *bridge_dev; 894 895 struct rb_root uabi_engines; 896 897 struct resource mch_res; 898 899 /* protects the irq masks */ 900 spinlock_t irq_lock; 901 902 bool display_irqs_enabled; 903 904 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 905 struct pm_qos_request pm_qos; 906 907 /* Sideband mailbox protection */ 908 struct mutex sb_lock; 909 struct pm_qos_request sb_qos; 910 911 /** Cached value of IMR to avoid reads in updating the bitfield */ 912 union { 913 u32 irq_mask; 914 u32 de_irq_mask[I915_MAX_PIPES]; 915 }; 916 u32 pipestat_irq_mask[I915_MAX_PIPES]; 917 918 struct i915_hotplug hotplug; 919 struct intel_fbc fbc; 920 struct i915_drrs drrs; 921 struct intel_opregion opregion; 922 struct intel_vbt_data vbt; 923 924 bool preserve_bios_swizzle; 925 926 /* overlay */ 927 struct intel_overlay *overlay; 928 929 /* backlight registers and fields in struct intel_panel */ 930 struct mutex backlight_lock; 931 932 /* protects panel power sequencer state */ 933 struct mutex pps_mutex; 934 935 unsigned int fsb_freq, mem_freq, is_ddr3; 936 unsigned int skl_preferred_vco_freq; 937 unsigned int max_cdclk_freq; 938 939 unsigned int max_dotclk_freq; 940 unsigned int hpll_freq; 941 unsigned int fdi_pll_freq; 942 unsigned int czclk_freq; 943 944 struct { 945 /* The current hardware cdclk configuration */ 946 struct intel_cdclk_config hw; 947 948 /* cdclk, divider, and ratio table from bspec */ 949 const struct intel_cdclk_vals *table; 950 951 struct intel_global_obj obj; 952 } cdclk; 953 954 /** 955 * wq - Driver workqueue for GEM. 956 * 957 * NOTE: Work items scheduled here are not allowed to grab any modeset 958 * locks, for otherwise the flushing done in the pageflip code will 959 * result in deadlocks. 960 */ 961 struct workqueue_struct *wq; 962 963 /* ordered wq for modesets */ 964 struct workqueue_struct *modeset_wq; 965 /* unbound hipri wq for page flips/plane updates */ 966 struct workqueue_struct *flip_wq; 967 968 /* Display functions */ 969 struct drm_i915_display_funcs display; 970 971 /* PCH chipset type */ 972 enum intel_pch pch_type; 973 unsigned short pch_id; 974 975 unsigned long quirks; 976 977 struct drm_atomic_state *modeset_restore_state; 978 struct drm_modeset_acquire_ctx reset_ctx; 979 980 struct i915_ggtt ggtt; /* VM representing the global address space */ 981 982 struct i915_gem_mm mm; 983 DECLARE_HASHTABLE(mm_structs, 7); 984 struct mutex mm_lock; 985 986 /* Kernel Modesetting */ 987 988 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 989 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 990 991 /** 992 * dpll and cdclk state is protected by connection_mutex 993 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 994 * Must be global rather than per dpll, because on some platforms plls 995 * share registers. 996 */ 997 struct { 998 struct mutex lock; 999 1000 int num_shared_dpll; 1001 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1002 const struct intel_dpll_mgr *mgr; 1003 1004 struct { 1005 int nssc; 1006 int ssc; 1007 } ref_clks; 1008 } dpll; 1009 1010 struct list_head global_obj_list; 1011 1012 /* 1013 * For reading active_pipes holding any crtc lock is 1014 * sufficient, for writing must hold all of them. 1015 */ 1016 u8 active_pipes; 1017 1018 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1019 1020 struct i915_wa_list gt_wa_list; 1021 1022 struct i915_frontbuffer_tracking fb_tracking; 1023 1024 struct intel_atomic_helper { 1025 struct llist_head free_list; 1026 struct work_struct free_work; 1027 } atomic_helper; 1028 1029 bool mchbar_need_disable; 1030 1031 struct intel_l3_parity l3_parity; 1032 1033 /* 1034 * edram size in MB. 1035 * Cannot be determined by PCIID. You must always read a register. 1036 */ 1037 u32 edram_size_mb; 1038 1039 struct i915_power_domains power_domains; 1040 1041 struct i915_psr psr; 1042 1043 struct i915_gpu_error gpu_error; 1044 1045 struct drm_i915_gem_object *vlv_pctx; 1046 1047 /* list of fbdev register on this device */ 1048 struct intel_fbdev *fbdev; 1049 struct work_struct fbdev_suspend_work; 1050 1051 struct drm_property *broadcast_rgb_property; 1052 struct drm_property *force_audio_property; 1053 1054 /* hda/i915 audio component */ 1055 struct i915_audio_component *audio_component; 1056 bool audio_component_registered; 1057 /** 1058 * av_mutex - mutex for audio/video sync 1059 * 1060 */ 1061 struct mutex av_mutex; 1062 int audio_power_refcount; 1063 u32 audio_freq_cntrl; 1064 1065 u32 fdi_rx_config; 1066 1067 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1068 u32 chv_phy_control; 1069 /* 1070 * Shadows for CHV DPLL_MD regs to keep the state 1071 * checker somewhat working in the presence hardware 1072 * crappiness (can't read out DPLL_MD for pipes B & C). 1073 */ 1074 u32 chv_dpll_md[I915_MAX_PIPES]; 1075 u32 bxt_phy_grc; 1076 1077 u32 suspend_count; 1078 bool power_domains_suspended; 1079 struct i915_suspend_saved_registers regfile; 1080 struct vlv_s0ix_state *vlv_s0ix_state; 1081 1082 enum { 1083 I915_SAGV_UNKNOWN = 0, 1084 I915_SAGV_DISABLED, 1085 I915_SAGV_ENABLED, 1086 I915_SAGV_NOT_CONTROLLED 1087 } sagv_status; 1088 1089 u32 sagv_block_time_us; 1090 1091 struct { 1092 /* 1093 * Raw watermark latency values: 1094 * in 0.1us units for WM0, 1095 * in 0.5us units for WM1+. 1096 */ 1097 /* primary */ 1098 u16 pri_latency[5]; 1099 /* sprite */ 1100 u16 spr_latency[5]; 1101 /* cursor */ 1102 u16 cur_latency[5]; 1103 /* 1104 * Raw watermark memory latency values 1105 * for SKL for all 8 levels 1106 * in 1us units. 1107 */ 1108 u16 skl_latency[8]; 1109 1110 /* current hardware state */ 1111 union { 1112 struct ilk_wm_values hw; 1113 struct vlv_wm_values vlv; 1114 struct g4x_wm_values g4x; 1115 }; 1116 1117 u8 max_level; 1118 1119 /* 1120 * Should be held around atomic WM register writing; also 1121 * protects * intel_crtc->wm.active and 1122 * crtc_state->wm.need_postvbl_update. 1123 */ 1124 struct mutex wm_mutex; 1125 1126 /* 1127 * Set during HW readout of watermarks/DDB. Some platforms 1128 * need to know when we're still using BIOS-provided values 1129 * (which we don't fully trust). 1130 */ 1131 bool distrust_bios_wm; 1132 } wm; 1133 1134 u8 enabled_dbuf_slices_mask; /* GEN11 has configurable 2 slices */ 1135 1136 struct dram_info { 1137 bool valid; 1138 bool is_16gb_dimm; 1139 u8 num_channels; 1140 u8 ranks; 1141 u32 bandwidth_kbps; 1142 bool symmetric_memory; 1143 enum intel_dram_type { 1144 INTEL_DRAM_UNKNOWN, 1145 INTEL_DRAM_DDR3, 1146 INTEL_DRAM_DDR4, 1147 INTEL_DRAM_LPDDR3, 1148 INTEL_DRAM_LPDDR4 1149 } type; 1150 } dram_info; 1151 1152 struct intel_bw_info { 1153 /* for each QGV point */ 1154 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1155 u8 num_qgv_points; 1156 u8 num_planes; 1157 } max_bw[6]; 1158 1159 struct intel_global_obj bw_obj; 1160 1161 struct intel_runtime_pm runtime_pm; 1162 1163 struct i915_perf perf; 1164 1165 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1166 struct intel_gt gt; 1167 1168 struct { 1169 struct i915_gem_contexts { 1170 spinlock_t lock; /* locks list */ 1171 struct list_head list; 1172 1173 struct llist_head free_list; 1174 struct work_struct free_work; 1175 } contexts; 1176 1177 /* 1178 * We replace the local file with a global mappings as the 1179 * backing storage for the mmap is on the device and not 1180 * on the struct file, and we do not want to prolong the 1181 * lifetime of the local fd. To minimise the number of 1182 * anonymous inodes we create, we use a global singleton to 1183 * share the global mapping. 1184 */ 1185 struct file *mmap_singleton; 1186 } gem; 1187 1188 u8 pch_ssc_use; 1189 1190 /* For i915gm/i945gm vblank irq workaround */ 1191 u8 vblank_enabled; 1192 1193 /* perform PHY state sanity checks? */ 1194 bool chv_phy_assert[2]; 1195 1196 bool ipc_enabled; 1197 1198 /* Used to save the pipe-to-encoder mapping for audio */ 1199 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1200 1201 /* necessary resource sharing with HDMI LPE audio driver. */ 1202 struct { 1203 struct platform_device *platdev; 1204 int irq; 1205 } lpe_audio; 1206 1207 struct i915_pmu pmu; 1208 1209 struct i915_hdcp_comp_master *hdcp_master; 1210 bool hdcp_comp_added; 1211 1212 /* Mutex to protect the above hdcp component related values. */ 1213 struct mutex hdcp_comp_mutex; 1214 1215 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1216 1217 /* 1218 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1219 * will be rejected. Instead look for a better place. 1220 */ 1221 }; 1222 1223 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1224 { 1225 return container_of(dev, struct drm_i915_private, drm); 1226 } 1227 1228 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1229 { 1230 return dev_get_drvdata(kdev); 1231 } 1232 1233 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1234 { 1235 return pci_get_drvdata(pdev); 1236 } 1237 1238 /* Simple iterator over all initialised engines */ 1239 #define for_each_engine(engine__, dev_priv__, id__) \ 1240 for ((id__) = 0; \ 1241 (id__) < I915_NUM_ENGINES; \ 1242 (id__)++) \ 1243 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1244 1245 /* Iterator over subset of engines selected by mask */ 1246 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1247 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ 1248 (tmp__) ? \ 1249 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1250 0;) 1251 1252 #define rb_to_uabi_engine(rb) \ 1253 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1254 1255 #define for_each_uabi_engine(engine__, i915__) \ 1256 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1257 (engine__); \ 1258 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1259 1260 #define I915_GTT_OFFSET_NONE ((u32)-1) 1261 1262 /* 1263 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1264 * considered to be the frontbuffer for the given plane interface-wise. This 1265 * doesn't mean that the hw necessarily already scans it out, but that any 1266 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1267 * 1268 * We have one bit per pipe and per scanout plane type. 1269 */ 1270 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1271 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1272 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1273 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1274 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1275 }) 1276 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1277 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1278 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1279 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1280 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1281 1282 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1283 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1284 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1285 1286 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1287 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1288 1289 #define REVID_FOREVER 0xff 1290 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1291 1292 #define INTEL_GEN_MASK(s, e) ( \ 1293 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1294 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1295 GENMASK((e) - 1, (s) - 1)) 1296 1297 /* Returns true if Gen is in inclusive range [Start, End] */ 1298 #define IS_GEN_RANGE(dev_priv, s, e) \ 1299 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1300 1301 #define IS_GEN(dev_priv, n) \ 1302 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1303 INTEL_INFO(dev_priv)->gen == (n)) 1304 1305 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1306 1307 /* 1308 * Return true if revision is in range [since,until] inclusive. 1309 * 1310 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1311 */ 1312 #define IS_REVID(p, since, until) \ 1313 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1314 1315 static __always_inline unsigned int 1316 __platform_mask_index(const struct intel_runtime_info *info, 1317 enum intel_platform p) 1318 { 1319 const unsigned int pbits = 1320 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1321 1322 /* Expand the platform_mask array if this fails. */ 1323 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1324 pbits * ARRAY_SIZE(info->platform_mask)); 1325 1326 return p / pbits; 1327 } 1328 1329 static __always_inline unsigned int 1330 __platform_mask_bit(const struct intel_runtime_info *info, 1331 enum intel_platform p) 1332 { 1333 const unsigned int pbits = 1334 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1335 1336 return p % pbits + INTEL_SUBPLATFORM_BITS; 1337 } 1338 1339 static inline u32 1340 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1341 { 1342 const unsigned int pi = __platform_mask_index(info, p); 1343 1344 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1345 } 1346 1347 static __always_inline bool 1348 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1349 { 1350 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1351 const unsigned int pi = __platform_mask_index(info, p); 1352 const unsigned int pb = __platform_mask_bit(info, p); 1353 1354 BUILD_BUG_ON(!__builtin_constant_p(p)); 1355 1356 return info->platform_mask[pi] & BIT(pb); 1357 } 1358 1359 static __always_inline bool 1360 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1361 enum intel_platform p, unsigned int s) 1362 { 1363 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1364 const unsigned int pi = __platform_mask_index(info, p); 1365 const unsigned int pb = __platform_mask_bit(info, p); 1366 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1367 const u32 mask = info->platform_mask[pi]; 1368 1369 BUILD_BUG_ON(!__builtin_constant_p(p)); 1370 BUILD_BUG_ON(!__builtin_constant_p(s)); 1371 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1372 1373 /* Shift and test on the MSB position so sign flag can be used. */ 1374 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1375 } 1376 1377 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1378 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1379 1380 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1381 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1382 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1383 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1384 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1385 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1386 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1387 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1388 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1389 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1390 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1391 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1392 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1393 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1394 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1395 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1396 #define IS_IRONLAKE_M(dev_priv) \ 1397 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1398 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1399 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1400 INTEL_INFO(dev_priv)->gt == 1) 1401 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1402 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1403 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1404 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1405 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1406 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1407 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1408 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1409 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1410 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1411 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1412 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1413 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1414 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1415 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1416 #define IS_BDW_ULT(dev_priv) \ 1417 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1418 #define IS_BDW_ULX(dev_priv) \ 1419 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1420 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1421 INTEL_INFO(dev_priv)->gt == 3) 1422 #define IS_HSW_ULT(dev_priv) \ 1423 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1424 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1425 INTEL_INFO(dev_priv)->gt == 3) 1426 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1427 INTEL_INFO(dev_priv)->gt == 1) 1428 /* ULX machines are also considered ULT. */ 1429 #define IS_HSW_ULX(dev_priv) \ 1430 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1431 #define IS_SKL_ULT(dev_priv) \ 1432 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1433 #define IS_SKL_ULX(dev_priv) \ 1434 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1435 #define IS_KBL_ULT(dev_priv) \ 1436 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1437 #define IS_KBL_ULX(dev_priv) \ 1438 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1439 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1440 INTEL_INFO(dev_priv)->gt == 2) 1441 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1442 INTEL_INFO(dev_priv)->gt == 3) 1443 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1444 INTEL_INFO(dev_priv)->gt == 4) 1445 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1446 INTEL_INFO(dev_priv)->gt == 2) 1447 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1448 INTEL_INFO(dev_priv)->gt == 3) 1449 #define IS_CFL_ULT(dev_priv) \ 1450 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1451 #define IS_CFL_ULX(dev_priv) \ 1452 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1453 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1454 INTEL_INFO(dev_priv)->gt == 2) 1455 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1456 INTEL_INFO(dev_priv)->gt == 3) 1457 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1458 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1459 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1460 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1461 1462 #define SKL_REVID_A0 0x0 1463 #define SKL_REVID_B0 0x1 1464 #define SKL_REVID_C0 0x2 1465 #define SKL_REVID_D0 0x3 1466 #define SKL_REVID_E0 0x4 1467 #define SKL_REVID_F0 0x5 1468 #define SKL_REVID_G0 0x6 1469 #define SKL_REVID_H0 0x7 1470 1471 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1472 1473 #define BXT_REVID_A0 0x0 1474 #define BXT_REVID_A1 0x1 1475 #define BXT_REVID_B0 0x3 1476 #define BXT_REVID_B_LAST 0x8 1477 #define BXT_REVID_C0 0x9 1478 1479 #define IS_BXT_REVID(dev_priv, since, until) \ 1480 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1481 1482 #define KBL_REVID_A0 0x0 1483 #define KBL_REVID_B0 0x1 1484 #define KBL_REVID_C0 0x2 1485 #define KBL_REVID_D0 0x3 1486 #define KBL_REVID_E0 0x4 1487 1488 #define IS_KBL_REVID(dev_priv, since, until) \ 1489 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1490 1491 #define GLK_REVID_A0 0x0 1492 #define GLK_REVID_A1 0x1 1493 #define GLK_REVID_A2 0x2 1494 #define GLK_REVID_B0 0x3 1495 1496 #define IS_GLK_REVID(dev_priv, since, until) \ 1497 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1498 1499 #define CNL_REVID_A0 0x0 1500 #define CNL_REVID_B0 0x1 1501 #define CNL_REVID_C0 0x2 1502 1503 #define IS_CNL_REVID(p, since, until) \ 1504 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1505 1506 #define ICL_REVID_A0 0x0 1507 #define ICL_REVID_A2 0x1 1508 #define ICL_REVID_B0 0x3 1509 #define ICL_REVID_B2 0x4 1510 #define ICL_REVID_C0 0x5 1511 1512 #define IS_ICL_REVID(p, since, until) \ 1513 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1514 1515 #define EHL_REVID_A0 0x0 1516 1517 #define IS_EHL_REVID(p, since, until) \ 1518 (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until)) 1519 1520 #define TGL_REVID_A0 0x0 1521 #define TGL_REVID_B0 0x1 1522 #define TGL_REVID_C0 0x2 1523 1524 #define IS_TGL_REVID(p, since, until) \ 1525 (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) 1526 1527 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1528 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1529 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1530 1531 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 1532 1533 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 1534 unsigned int first__ = (first); \ 1535 unsigned int count__ = (count); \ 1536 (INTEL_INFO(dev_priv)->engine_mask & \ 1537 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1538 }) 1539 #define VDBOX_MASK(dev_priv) \ 1540 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 1541 #define VEBOX_MASK(dev_priv) \ 1542 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 1543 1544 /* 1545 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1546 * All later gens can run the final buffer from the ppgtt 1547 */ 1548 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1549 1550 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1551 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1552 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1553 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1554 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 1555 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 1556 1557 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1558 1559 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1560 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1561 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1562 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1563 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 1564 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 1565 1566 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1567 1568 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1569 #define HAS_PPGTT(dev_priv) \ 1570 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1571 #define HAS_FULL_PPGTT(dev_priv) \ 1572 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1573 1574 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1575 GEM_BUG_ON((sizes) == 0); \ 1576 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1577 }) 1578 1579 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1580 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1581 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1582 1583 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1584 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1585 1586 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1587 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1588 1589 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1590 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1591 (IS_CANNONLAKE(dev_priv) || \ 1592 IS_SKL_GT3(dev_priv) || \ 1593 IS_SKL_GT4(dev_priv)) 1594 1595 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1596 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1597 IS_GEMINILAKE(dev_priv) || \ 1598 IS_KABYLAKE(dev_priv)) 1599 1600 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1601 * rows, which changed the alignment requirements and fence programming. 1602 */ 1603 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1604 !(IS_I915G(dev_priv) || \ 1605 IS_I915GM(dev_priv))) 1606 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1607 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1608 1609 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1610 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1611 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1612 1613 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1614 1615 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1616 1617 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1618 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1619 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1620 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 1621 1622 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1623 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1624 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1625 1626 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1627 1628 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1629 1630 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1631 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1632 1633 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1634 1635 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1636 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1637 1638 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1639 1640 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1641 1642 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1643 1644 1645 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1646 1647 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1648 1649 /* DPF == dynamic parity feature */ 1650 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1651 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1652 2 : HAS_L3_DPF(dev_priv)) 1653 1654 #define GT_FREQUENCY_MULTIPLIER 50 1655 #define GEN9_FREQ_SCALER 3 1656 1657 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1658 1659 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1660 1661 /* Only valid when HAS_DISPLAY() is true */ 1662 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) 1663 1664 static inline bool intel_vtd_active(void) 1665 { 1666 #ifdef CONFIG_INTEL_IOMMU 1667 if (intel_iommu_gfx_mapped) 1668 return true; 1669 #endif 1670 return false; 1671 } 1672 1673 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1674 { 1675 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1676 } 1677 1678 static inline bool 1679 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1680 { 1681 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1682 } 1683 1684 /* i915_drv.c */ 1685 extern const struct dev_pm_ops i915_pm_ops; 1686 1687 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1688 void i915_driver_remove(struct drm_i915_private *i915); 1689 1690 int i915_resume_switcheroo(struct drm_i915_private *i915); 1691 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1692 1693 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1694 struct drm_file *file_priv); 1695 1696 /* i915_gem.c */ 1697 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1698 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1699 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1700 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1701 int i915_gem_freeze(struct drm_i915_private *dev_priv); 1702 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 1703 1704 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1705 1706 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1707 { 1708 /* 1709 * A single pass should suffice to release all the freed objects (along 1710 * most call paths) , but be a little more paranoid in that freeing 1711 * the objects does take a little amount of time, during which the rcu 1712 * callbacks could have added new objects into the freed list, and 1713 * armed the work again. 1714 */ 1715 while (atomic_read(&i915->mm.free_count)) { 1716 flush_work(&i915->mm.free_work); 1717 rcu_barrier(); 1718 } 1719 } 1720 1721 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1722 { 1723 /* 1724 * Similar to objects above (see i915_gem_drain_freed-objects), in 1725 * general we have workers that are armed by RCU and then rearm 1726 * themselves in their callbacks. To be paranoid, we need to 1727 * drain the workqueue a second time after waiting for the RCU 1728 * grace period so that we catch work queued via RCU from the first 1729 * pass. As neither drain_workqueue() nor flush_workqueue() report 1730 * a result, we make an assumption that we only don't require more 1731 * than 3 passes to catch all _recursive_ RCU delayed work. 1732 * 1733 */ 1734 int pass = 3; 1735 do { 1736 flush_workqueue(i915->wq); 1737 rcu_barrier(); 1738 i915_gem_drain_freed_objects(i915); 1739 } while (--pass); 1740 drain_workqueue(i915->wq); 1741 } 1742 1743 struct i915_vma * __must_check 1744 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1745 const struct i915_ggtt_view *view, 1746 u64 size, 1747 u64 alignment, 1748 u64 flags); 1749 1750 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1751 unsigned long flags); 1752 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1753 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1754 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2) 1755 1756 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1757 1758 int i915_gem_dumb_create(struct drm_file *file_priv, 1759 struct drm_device *dev, 1760 struct drm_mode_create_dumb *args); 1761 1762 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1763 1764 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1765 { 1766 return atomic_read(&error->reset_count); 1767 } 1768 1769 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1770 const struct intel_engine_cs *engine) 1771 { 1772 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1773 } 1774 1775 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1776 void i915_gem_driver_register(struct drm_i915_private *i915); 1777 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1778 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1779 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1780 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1781 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1782 void i915_gem_resume(struct drm_i915_private *dev_priv); 1783 1784 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1785 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1786 1787 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1788 enum i915_cache_level cache_level); 1789 1790 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1791 struct dma_buf *dma_buf); 1792 1793 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1794 1795 static inline struct i915_gem_context * 1796 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1797 { 1798 return xa_load(&file_priv->context_xa, id); 1799 } 1800 1801 static inline struct i915_gem_context * 1802 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1803 { 1804 struct i915_gem_context *ctx; 1805 1806 rcu_read_lock(); 1807 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1808 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1809 ctx = NULL; 1810 rcu_read_unlock(); 1811 1812 return ctx; 1813 } 1814 1815 /* i915_gem_evict.c */ 1816 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1817 u64 min_size, u64 alignment, 1818 unsigned long color, 1819 u64 start, u64 end, 1820 unsigned flags); 1821 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1822 struct drm_mm_node *node, 1823 unsigned int flags); 1824 int i915_gem_evict_vm(struct i915_address_space *vm); 1825 1826 /* i915_gem_internal.c */ 1827 struct drm_i915_gem_object * 1828 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1829 phys_addr_t size); 1830 1831 /* i915_gem_tiling.c */ 1832 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1833 { 1834 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1835 1836 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1837 i915_gem_object_is_tiled(obj); 1838 } 1839 1840 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1841 unsigned int tiling, unsigned int stride); 1842 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1843 unsigned int tiling, unsigned int stride); 1844 1845 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1846 1847 /* i915_cmd_parser.c */ 1848 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1849 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1850 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1851 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1852 struct i915_vma *batch, 1853 u32 batch_offset, 1854 u32 batch_length, 1855 struct i915_vma *shadow, 1856 bool trampoline); 1857 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1858 1859 /* intel_device_info.c */ 1860 static inline struct intel_device_info * 1861 mkwrite_device_info(struct drm_i915_private *dev_priv) 1862 { 1863 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1864 } 1865 1866 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1867 struct drm_file *file); 1868 1869 #define __I915_REG_OP(op__, dev_priv__, ...) \ 1870 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 1871 1872 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 1873 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 1874 1875 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 1876 1877 /* These are untraced mmio-accessors that are only valid to be used inside 1878 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 1879 * controlled. 1880 * 1881 * Think twice, and think again, before using these. 1882 * 1883 * As an example, these accessors can possibly be used between: 1884 * 1885 * spin_lock_irq(&dev_priv->uncore.lock); 1886 * intel_uncore_forcewake_get__locked(); 1887 * 1888 * and 1889 * 1890 * intel_uncore_forcewake_put__locked(); 1891 * spin_unlock_irq(&dev_priv->uncore.lock); 1892 * 1893 * 1894 * Note: some registers may not need forcewake held, so 1895 * intel_uncore_forcewake_{get,put} can be omitted, see 1896 * intel_uncore_forcewake_for_reg(). 1897 * 1898 * Certain architectures will die if the same cacheline is concurrently accessed 1899 * by different clients (e.g. on Ivybridge). Access to registers should 1900 * therefore generally be serialised, by either the dev_priv->uncore.lock or 1901 * a more localised lock guarding all access to that bank of registers. 1902 */ 1903 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 1904 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 1905 1906 /* i915_mm.c */ 1907 int remap_io_mapping(struct vm_area_struct *vma, 1908 unsigned long addr, unsigned long pfn, unsigned long size, 1909 struct io_mapping *iomap); 1910 int remap_io_sg(struct vm_area_struct *vma, 1911 unsigned long addr, unsigned long size, 1912 struct scatterlist *sgl, resource_size_t iobase); 1913 1914 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1915 { 1916 if (INTEL_GEN(i915) >= 10) 1917 return CNL_HWS_CSB_WRITE_INDEX; 1918 else 1919 return I915_HWS_CSB_WRITE_INDEX; 1920 } 1921 1922 static inline enum i915_map_type 1923 i915_coherent_map_type(struct drm_i915_private *i915) 1924 { 1925 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 1926 } 1927 1928 static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val) 1929 { 1930 return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz, 1931 1000000000); 1932 } 1933 1934 static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val) 1935 { 1936 return div_u64(val * 1000000000, 1937 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz); 1938 } 1939 1940 #endif 1941