1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include "intel_lrc.h" 39 #include "i915_gem_gtt.h" 40 #include "i915_gem_render_state.h" 41 #include <linux/io-mapping.h> 42 #include <linux/i2c.h> 43 #include <linux/i2c-algo-bit.h> 44 #include <drm/intel-gtt.h> 45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 46 #include <drm/drm_gem.h> 47 #include <linux/backlight.h> 48 #include <linux/hashtable.h> 49 #include <linux/intel-iommu.h> 50 #include <linux/kref.h> 51 #include <linux/pm_qos.h> 52 53 /* General customization: 54 */ 55 56 #define DRIVER_NAME "i915" 57 #define DRIVER_DESC "Intel Graphics" 58 #define DRIVER_DATE "20150130" 59 60 #undef WARN_ON 61 /* Many gcc seem to no see through this and fall over :( */ 62 #if 0 63 #define WARN_ON(x) ({ \ 64 bool __i915_warn_cond = (x); \ 65 if (__builtin_constant_p(__i915_warn_cond)) \ 66 BUILD_BUG_ON(__i915_warn_cond); \ 67 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) 68 #else 69 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") 70 #endif 71 72 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ 73 (long) (x), __func__); 74 75 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 76 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 77 * which may not necessarily be a user visible problem. This will either 78 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 79 * enable distros and users to tailor their preferred amount of i915 abrt 80 * spam. 81 */ 82 #define I915_STATE_WARN(condition, format...) ({ \ 83 int __ret_warn_on = !!(condition); \ 84 if (unlikely(__ret_warn_on)) { \ 85 if (i915.verbose_state_checks) \ 86 WARN(1, format); \ 87 else \ 88 DRM_ERROR(format); \ 89 } \ 90 unlikely(__ret_warn_on); \ 91 }) 92 93 #define I915_STATE_WARN_ON(condition) ({ \ 94 int __ret_warn_on = !!(condition); \ 95 if (unlikely(__ret_warn_on)) { \ 96 if (i915.verbose_state_checks) \ 97 WARN(1, "WARN_ON(" #condition ")\n"); \ 98 else \ 99 DRM_ERROR("WARN_ON(" #condition ")\n"); \ 100 } \ 101 unlikely(__ret_warn_on); \ 102 }) 103 104 enum pipe { 105 INVALID_PIPE = -1, 106 PIPE_A = 0, 107 PIPE_B, 108 PIPE_C, 109 _PIPE_EDP, 110 I915_MAX_PIPES = _PIPE_EDP 111 }; 112 #define pipe_name(p) ((p) + 'A') 113 114 enum transcoder { 115 TRANSCODER_A = 0, 116 TRANSCODER_B, 117 TRANSCODER_C, 118 TRANSCODER_EDP, 119 I915_MAX_TRANSCODERS 120 }; 121 #define transcoder_name(t) ((t) + 'A') 122 123 /* 124 * This is the maximum (across all platforms) number of planes (primary + 125 * sprites) that can be active at the same time on one pipe. 126 * 127 * This value doesn't count the cursor plane. 128 */ 129 #define I915_MAX_PLANES 3 130 131 enum plane { 132 PLANE_A = 0, 133 PLANE_B, 134 PLANE_C, 135 }; 136 #define plane_name(p) ((p) + 'A') 137 138 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 139 140 enum port { 141 PORT_A = 0, 142 PORT_B, 143 PORT_C, 144 PORT_D, 145 PORT_E, 146 I915_MAX_PORTS 147 }; 148 #define port_name(p) ((p) + 'A') 149 150 #define I915_NUM_PHYS_VLV 2 151 152 enum dpio_channel { 153 DPIO_CH0, 154 DPIO_CH1 155 }; 156 157 enum dpio_phy { 158 DPIO_PHY0, 159 DPIO_PHY1 160 }; 161 162 enum intel_display_power_domain { 163 POWER_DOMAIN_PIPE_A, 164 POWER_DOMAIN_PIPE_B, 165 POWER_DOMAIN_PIPE_C, 166 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 167 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 168 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 169 POWER_DOMAIN_TRANSCODER_A, 170 POWER_DOMAIN_TRANSCODER_B, 171 POWER_DOMAIN_TRANSCODER_C, 172 POWER_DOMAIN_TRANSCODER_EDP, 173 POWER_DOMAIN_PORT_DDI_A_2_LANES, 174 POWER_DOMAIN_PORT_DDI_A_4_LANES, 175 POWER_DOMAIN_PORT_DDI_B_2_LANES, 176 POWER_DOMAIN_PORT_DDI_B_4_LANES, 177 POWER_DOMAIN_PORT_DDI_C_2_LANES, 178 POWER_DOMAIN_PORT_DDI_C_4_LANES, 179 POWER_DOMAIN_PORT_DDI_D_2_LANES, 180 POWER_DOMAIN_PORT_DDI_D_4_LANES, 181 POWER_DOMAIN_PORT_DSI, 182 POWER_DOMAIN_PORT_CRT, 183 POWER_DOMAIN_PORT_OTHER, 184 POWER_DOMAIN_VGA, 185 POWER_DOMAIN_AUDIO, 186 POWER_DOMAIN_PLLS, 187 POWER_DOMAIN_AUX_A, 188 POWER_DOMAIN_AUX_B, 189 POWER_DOMAIN_AUX_C, 190 POWER_DOMAIN_AUX_D, 191 POWER_DOMAIN_INIT, 192 193 POWER_DOMAIN_NUM, 194 }; 195 196 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 197 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 198 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 199 #define POWER_DOMAIN_TRANSCODER(tran) \ 200 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 201 (tran) + POWER_DOMAIN_TRANSCODER_A) 202 203 enum hpd_pin { 204 HPD_NONE = 0, 205 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 206 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 207 HPD_CRT, 208 HPD_SDVO_B, 209 HPD_SDVO_C, 210 HPD_PORT_B, 211 HPD_PORT_C, 212 HPD_PORT_D, 213 HPD_NUM_PINS 214 }; 215 216 #define I915_GEM_GPU_DOMAINS \ 217 (I915_GEM_DOMAIN_RENDER | \ 218 I915_GEM_DOMAIN_SAMPLER | \ 219 I915_GEM_DOMAIN_COMMAND | \ 220 I915_GEM_DOMAIN_INSTRUCTION | \ 221 I915_GEM_DOMAIN_VERTEX) 222 223 #define for_each_pipe(__dev_priv, __p) \ 224 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 225 #define for_each_plane(pipe, p) \ 226 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) 227 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 228 229 #define for_each_crtc(dev, crtc) \ 230 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 231 232 #define for_each_intel_crtc(dev, intel_crtc) \ 233 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 234 235 #define for_each_intel_encoder(dev, intel_encoder) \ 236 list_for_each_entry(intel_encoder, \ 237 &(dev)->mode_config.encoder_list, \ 238 base.head) 239 240 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 241 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 242 if ((intel_encoder)->base.crtc == (__crtc)) 243 244 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 245 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 246 if ((intel_connector)->base.encoder == (__encoder)) 247 248 #define for_each_power_domain(domain, mask) \ 249 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 250 if ((1 << (domain)) & (mask)) 251 252 struct drm_i915_private; 253 struct i915_mm_struct; 254 struct i915_mmu_object; 255 256 enum intel_dpll_id { 257 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 258 /* real shared dpll ids must be >= 0 */ 259 DPLL_ID_PCH_PLL_A = 0, 260 DPLL_ID_PCH_PLL_B = 1, 261 /* hsw/bdw */ 262 DPLL_ID_WRPLL1 = 0, 263 DPLL_ID_WRPLL2 = 1, 264 /* skl */ 265 DPLL_ID_SKL_DPLL1 = 0, 266 DPLL_ID_SKL_DPLL2 = 1, 267 DPLL_ID_SKL_DPLL3 = 2, 268 }; 269 #define I915_NUM_PLLS 3 270 271 struct intel_dpll_hw_state { 272 /* i9xx, pch plls */ 273 uint32_t dpll; 274 uint32_t dpll_md; 275 uint32_t fp0; 276 uint32_t fp1; 277 278 /* hsw, bdw */ 279 uint32_t wrpll; 280 281 /* skl */ 282 /* 283 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 284 * lower part of crtl1 and they get shifted into position when writing 285 * the register. This allows us to easily compare the state to share 286 * the DPLL. 287 */ 288 uint32_t ctrl1; 289 /* HDMI only, 0 when used for DP */ 290 uint32_t cfgcr1, cfgcr2; 291 }; 292 293 struct intel_shared_dpll_config { 294 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ 295 struct intel_dpll_hw_state hw_state; 296 }; 297 298 struct intel_shared_dpll { 299 struct intel_shared_dpll_config config; 300 struct intel_shared_dpll_config *new_config; 301 302 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 303 bool on; /* is the PLL actually active? Disabled during modeset */ 304 const char *name; 305 /* should match the index in the dev_priv->shared_dplls array */ 306 enum intel_dpll_id id; 307 /* The mode_set hook is optional and should be used together with the 308 * intel_prepare_shared_dpll function. */ 309 void (*mode_set)(struct drm_i915_private *dev_priv, 310 struct intel_shared_dpll *pll); 311 void (*enable)(struct drm_i915_private *dev_priv, 312 struct intel_shared_dpll *pll); 313 void (*disable)(struct drm_i915_private *dev_priv, 314 struct intel_shared_dpll *pll); 315 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 316 struct intel_shared_dpll *pll, 317 struct intel_dpll_hw_state *hw_state); 318 }; 319 320 #define SKL_DPLL0 0 321 #define SKL_DPLL1 1 322 #define SKL_DPLL2 2 323 #define SKL_DPLL3 3 324 325 /* Used by dp and fdi links */ 326 struct intel_link_m_n { 327 uint32_t tu; 328 uint32_t gmch_m; 329 uint32_t gmch_n; 330 uint32_t link_m; 331 uint32_t link_n; 332 }; 333 334 void intel_link_compute_m_n(int bpp, int nlanes, 335 int pixel_clock, int link_clock, 336 struct intel_link_m_n *m_n); 337 338 /* Interface history: 339 * 340 * 1.1: Original. 341 * 1.2: Add Power Management 342 * 1.3: Add vblank support 343 * 1.4: Fix cmdbuffer path, add heap destroy 344 * 1.5: Add vblank pipe configuration 345 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 346 * - Support vertical blank on secondary display pipe 347 */ 348 #define DRIVER_MAJOR 1 349 #define DRIVER_MINOR 6 350 #define DRIVER_PATCHLEVEL 0 351 352 #define WATCH_LISTS 0 353 354 struct opregion_header; 355 struct opregion_acpi; 356 struct opregion_swsci; 357 struct opregion_asle; 358 359 struct intel_opregion { 360 struct opregion_header __iomem *header; 361 struct opregion_acpi __iomem *acpi; 362 struct opregion_swsci __iomem *swsci; 363 u32 swsci_gbda_sub_functions; 364 u32 swsci_sbcb_sub_functions; 365 struct opregion_asle __iomem *asle; 366 void __iomem *vbt; 367 u32 __iomem *lid_state; 368 struct work_struct asle_work; 369 }; 370 #define OPREGION_SIZE (8*1024) 371 372 struct intel_overlay; 373 struct intel_overlay_error_state; 374 375 #define I915_FENCE_REG_NONE -1 376 #define I915_MAX_NUM_FENCES 32 377 /* 32 fences + sign bit for FENCE_REG_NONE */ 378 #define I915_MAX_NUM_FENCE_BITS 6 379 380 struct drm_i915_fence_reg { 381 struct list_head lru_list; 382 struct drm_i915_gem_object *obj; 383 int pin_count; 384 }; 385 386 struct sdvo_device_mapping { 387 u8 initialized; 388 u8 dvo_port; 389 u8 slave_addr; 390 u8 dvo_wiring; 391 u8 i2c_pin; 392 u8 ddc_pin; 393 }; 394 395 struct intel_display_error_state; 396 397 struct drm_i915_error_state { 398 struct kref ref; 399 struct timeval time; 400 401 char error_msg[128]; 402 u32 reset_count; 403 u32 suspend_count; 404 405 /* Generic register state */ 406 u32 eir; 407 u32 pgtbl_er; 408 u32 ier; 409 u32 gtier[4]; 410 u32 ccid; 411 u32 derrmr; 412 u32 forcewake; 413 u32 error; /* gen6+ */ 414 u32 err_int; /* gen7 */ 415 u32 done_reg; 416 u32 gac_eco; 417 u32 gam_ecochk; 418 u32 gab_ctl; 419 u32 gfx_mode; 420 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 421 u64 fence[I915_MAX_NUM_FENCES]; 422 struct intel_overlay_error_state *overlay; 423 struct intel_display_error_state *display; 424 struct drm_i915_error_object *semaphore_obj; 425 426 struct drm_i915_error_ring { 427 bool valid; 428 /* Software tracked state */ 429 bool waiting; 430 int hangcheck_score; 431 enum intel_ring_hangcheck_action hangcheck_action; 432 int num_requests; 433 434 /* our own tracking of ring head and tail */ 435 u32 cpu_ring_head; 436 u32 cpu_ring_tail; 437 438 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 439 440 /* Register state */ 441 u32 tail; 442 u32 head; 443 u32 ctl; 444 u32 hws; 445 u32 ipeir; 446 u32 ipehr; 447 u32 instdone; 448 u32 bbstate; 449 u32 instpm; 450 u32 instps; 451 u32 seqno; 452 u64 bbaddr; 453 u64 acthd; 454 u32 fault_reg; 455 u64 faddr; 456 u32 rc_psmi; /* sleep state */ 457 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 458 459 struct drm_i915_error_object { 460 int page_count; 461 u32 gtt_offset; 462 u32 *pages[0]; 463 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 464 465 struct drm_i915_error_request { 466 long jiffies; 467 u32 seqno; 468 u32 tail; 469 } *requests; 470 471 struct { 472 u32 gfx_mode; 473 union { 474 u64 pdp[4]; 475 u32 pp_dir_base; 476 }; 477 } vm_info; 478 479 pid_t pid; 480 char comm[TASK_COMM_LEN]; 481 } ring[I915_NUM_RINGS]; 482 483 struct drm_i915_error_buffer { 484 u32 size; 485 u32 name; 486 u32 rseqno, wseqno; 487 u32 gtt_offset; 488 u32 read_domains; 489 u32 write_domain; 490 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 491 s32 pinned:2; 492 u32 tiling:2; 493 u32 dirty:1; 494 u32 purgeable:1; 495 u32 userptr:1; 496 s32 ring:4; 497 u32 cache_level:3; 498 } **active_bo, **pinned_bo; 499 500 u32 *active_bo_count, *pinned_bo_count; 501 u32 vm_count; 502 }; 503 504 struct intel_connector; 505 struct intel_encoder; 506 struct intel_crtc_state; 507 struct intel_initial_plane_config; 508 struct intel_crtc; 509 struct intel_limit; 510 struct dpll; 511 512 struct drm_i915_display_funcs { 513 bool (*fbc_enabled)(struct drm_device *dev); 514 void (*enable_fbc)(struct drm_crtc *crtc); 515 void (*disable_fbc)(struct drm_device *dev); 516 int (*get_display_clock_speed)(struct drm_device *dev); 517 int (*get_fifo_size)(struct drm_device *dev, int plane); 518 /** 519 * find_dpll() - Find the best values for the PLL 520 * @limit: limits for the PLL 521 * @crtc: current CRTC 522 * @target: target frequency in kHz 523 * @refclk: reference clock frequency in kHz 524 * @match_clock: if provided, @best_clock P divider must 525 * match the P divider from @match_clock 526 * used for LVDS downclocking 527 * @best_clock: best PLL values found 528 * 529 * Returns true on success, false on failure. 530 */ 531 bool (*find_dpll)(const struct intel_limit *limit, 532 struct intel_crtc *crtc, 533 int target, int refclk, 534 struct dpll *match_clock, 535 struct dpll *best_clock); 536 void (*update_wm)(struct drm_crtc *crtc); 537 void (*update_sprite_wm)(struct drm_plane *plane, 538 struct drm_crtc *crtc, 539 uint32_t sprite_width, uint32_t sprite_height, 540 int pixel_size, bool enable, bool scaled); 541 void (*modeset_global_resources)(struct drm_device *dev); 542 /* Returns the active state of the crtc, and if the crtc is active, 543 * fills out the pipe-config with the hw state. */ 544 bool (*get_pipe_config)(struct intel_crtc *, 545 struct intel_crtc_state *); 546 void (*get_initial_plane_config)(struct intel_crtc *, 547 struct intel_initial_plane_config *); 548 int (*crtc_compute_clock)(struct intel_crtc *crtc, 549 struct intel_crtc_state *crtc_state); 550 void (*crtc_enable)(struct drm_crtc *crtc); 551 void (*crtc_disable)(struct drm_crtc *crtc); 552 void (*off)(struct drm_crtc *crtc); 553 void (*audio_codec_enable)(struct drm_connector *connector, 554 struct intel_encoder *encoder, 555 struct drm_display_mode *mode); 556 void (*audio_codec_disable)(struct intel_encoder *encoder); 557 void (*fdi_link_train)(struct drm_crtc *crtc); 558 void (*init_clock_gating)(struct drm_device *dev); 559 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 560 struct drm_framebuffer *fb, 561 struct drm_i915_gem_object *obj, 562 struct intel_engine_cs *ring, 563 uint32_t flags); 564 void (*update_primary_plane)(struct drm_crtc *crtc, 565 struct drm_framebuffer *fb, 566 int x, int y); 567 void (*hpd_irq_setup)(struct drm_device *dev); 568 /* clock updates for mode set */ 569 /* cursor updates */ 570 /* render clock increase/decrease */ 571 /* display clock increase/decrease */ 572 /* pll clock increase/decrease */ 573 574 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); 575 uint32_t (*get_backlight)(struct intel_connector *connector); 576 void (*set_backlight)(struct intel_connector *connector, 577 uint32_t level); 578 void (*disable_backlight)(struct intel_connector *connector); 579 void (*enable_backlight)(struct intel_connector *connector); 580 }; 581 582 enum forcewake_domain_id { 583 FW_DOMAIN_ID_RENDER = 0, 584 FW_DOMAIN_ID_BLITTER, 585 FW_DOMAIN_ID_MEDIA, 586 587 FW_DOMAIN_ID_COUNT 588 }; 589 590 enum forcewake_domains { 591 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), 592 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), 593 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), 594 FORCEWAKE_ALL = (FORCEWAKE_RENDER | 595 FORCEWAKE_BLITTER | 596 FORCEWAKE_MEDIA) 597 }; 598 599 struct intel_uncore_funcs { 600 void (*force_wake_get)(struct drm_i915_private *dev_priv, 601 enum forcewake_domains domains); 602 void (*force_wake_put)(struct drm_i915_private *dev_priv, 603 enum forcewake_domains domains); 604 605 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 606 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 607 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 608 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 609 610 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 611 uint8_t val, bool trace); 612 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 613 uint16_t val, bool trace); 614 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 615 uint32_t val, bool trace); 616 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 617 uint64_t val, bool trace); 618 }; 619 620 struct intel_uncore { 621 spinlock_t lock; /** lock is also taken in irq contexts. */ 622 623 struct intel_uncore_funcs funcs; 624 625 unsigned fifo_count; 626 enum forcewake_domains fw_domains; 627 628 struct intel_uncore_forcewake_domain { 629 struct drm_i915_private *i915; 630 enum forcewake_domain_id id; 631 unsigned wake_count; 632 struct timer_list timer; 633 u32 reg_set; 634 u32 val_set; 635 u32 val_clear; 636 u32 reg_ack; 637 u32 reg_post; 638 u32 val_reset; 639 } fw_domain[FW_DOMAIN_ID_COUNT]; 640 }; 641 642 /* Iterate over initialised fw domains */ 643 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ 644 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ 645 (i__) < FW_DOMAIN_ID_COUNT; \ 646 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ 647 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) 648 649 #define for_each_fw_domain(domain__, dev_priv__, i__) \ 650 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) 651 652 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 653 func(is_mobile) sep \ 654 func(is_i85x) sep \ 655 func(is_i915g) sep \ 656 func(is_i945gm) sep \ 657 func(is_g33) sep \ 658 func(need_gfx_hws) sep \ 659 func(is_g4x) sep \ 660 func(is_pineview) sep \ 661 func(is_broadwater) sep \ 662 func(is_crestline) sep \ 663 func(is_ivybridge) sep \ 664 func(is_valleyview) sep \ 665 func(is_haswell) sep \ 666 func(is_skylake) sep \ 667 func(is_preliminary) sep \ 668 func(has_fbc) sep \ 669 func(has_pipe_cxsr) sep \ 670 func(has_hotplug) sep \ 671 func(cursor_needs_physical) sep \ 672 func(has_overlay) sep \ 673 func(overlay_needs_physical) sep \ 674 func(supports_tv) sep \ 675 func(has_llc) sep \ 676 func(has_ddi) sep \ 677 func(has_fpga_dbg) 678 679 #define DEFINE_FLAG(name) u8 name:1 680 #define SEP_SEMICOLON ; 681 682 struct intel_device_info { 683 u32 display_mmio_offset; 684 u16 device_id; 685 u8 num_pipes:3; 686 u8 num_sprites[I915_MAX_PIPES]; 687 u8 gen; 688 u8 ring_mask; /* Rings supported by the HW */ 689 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 690 /* Register offsets for the various display pipes and transcoders */ 691 int pipe_offsets[I915_MAX_TRANSCODERS]; 692 int trans_offsets[I915_MAX_TRANSCODERS]; 693 int palette_offsets[I915_MAX_PIPES]; 694 int cursor_offsets[I915_MAX_PIPES]; 695 unsigned int eu_total; 696 }; 697 698 #undef DEFINE_FLAG 699 #undef SEP_SEMICOLON 700 701 enum i915_cache_level { 702 I915_CACHE_NONE = 0, 703 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 704 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 705 caches, eg sampler/render caches, and the 706 large Last-Level-Cache. LLC is coherent with 707 the CPU, but L3 is only visible to the GPU. */ 708 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 709 }; 710 711 struct i915_ctx_hang_stats { 712 /* This context had batch pending when hang was declared */ 713 unsigned batch_pending; 714 715 /* This context had batch active when hang was declared */ 716 unsigned batch_active; 717 718 /* Time when this context was last blamed for a GPU reset */ 719 unsigned long guilty_ts; 720 721 /* If the contexts causes a second GPU hang within this time, 722 * it is permanently banned from submitting any more work. 723 */ 724 unsigned long ban_period_seconds; 725 726 /* This context is banned to submit more work */ 727 bool banned; 728 }; 729 730 /* This must match up with the value previously used for execbuf2.rsvd1. */ 731 #define DEFAULT_CONTEXT_HANDLE 0 732 /** 733 * struct intel_context - as the name implies, represents a context. 734 * @ref: reference count. 735 * @user_handle: userspace tracking identity for this context. 736 * @remap_slice: l3 row remapping information. 737 * @file_priv: filp associated with this context (NULL for global default 738 * context). 739 * @hang_stats: information about the role of this context in possible GPU 740 * hangs. 741 * @vm: virtual memory space used by this context. 742 * @legacy_hw_ctx: render context backing object and whether it is correctly 743 * initialized (legacy ring submission mechanism only). 744 * @link: link in the global list of contexts. 745 * 746 * Contexts are memory images used by the hardware to store copies of their 747 * internal state. 748 */ 749 struct intel_context { 750 struct kref ref; 751 int user_handle; 752 uint8_t remap_slice; 753 struct drm_i915_file_private *file_priv; 754 struct i915_ctx_hang_stats hang_stats; 755 struct i915_hw_ppgtt *ppgtt; 756 757 /* Legacy ring buffer submission */ 758 struct { 759 struct drm_i915_gem_object *rcs_state; 760 bool initialized; 761 } legacy_hw_ctx; 762 763 /* Execlists */ 764 bool rcs_initialized; 765 struct { 766 struct drm_i915_gem_object *state; 767 struct intel_ringbuffer *ringbuf; 768 int pin_count; 769 } engine[I915_NUM_RINGS]; 770 771 struct list_head link; 772 }; 773 774 struct i915_fbc { 775 unsigned long size; 776 unsigned threshold; 777 unsigned int fb_id; 778 enum plane plane; 779 int y; 780 781 struct drm_mm_node compressed_fb; 782 struct drm_mm_node *compressed_llb; 783 784 bool false_color; 785 786 /* Tracks whether the HW is actually enabled, not whether the feature is 787 * possible. */ 788 bool enabled; 789 790 /* On gen8 some rings cannont perform fbc clean operation so for now 791 * we are doing this on SW with mmio. 792 * This variable works in the opposite information direction 793 * of ring->fbc_dirty telling software on frontbuffer tracking 794 * to perform the cache clean on sw side. 795 */ 796 bool need_sw_cache_clean; 797 798 struct intel_fbc_work { 799 struct delayed_work work; 800 struct drm_crtc *crtc; 801 struct drm_framebuffer *fb; 802 } *fbc_work; 803 804 enum no_fbc_reason { 805 FBC_OK, /* FBC is enabled */ 806 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 807 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 808 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 809 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 810 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 811 FBC_BAD_PLANE, /* fbc not supported on plane */ 812 FBC_NOT_TILED, /* buffer not tiled */ 813 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 814 FBC_MODULE_PARAM, 815 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 816 } no_fbc_reason; 817 }; 818 819 /** 820 * HIGH_RR is the highest eDP panel refresh rate read from EDID 821 * LOW_RR is the lowest eDP panel refresh rate found from EDID 822 * parsing for same resolution. 823 */ 824 enum drrs_refresh_rate_type { 825 DRRS_HIGH_RR, 826 DRRS_LOW_RR, 827 DRRS_MAX_RR, /* RR count */ 828 }; 829 830 enum drrs_support_type { 831 DRRS_NOT_SUPPORTED = 0, 832 STATIC_DRRS_SUPPORT = 1, 833 SEAMLESS_DRRS_SUPPORT = 2 834 }; 835 836 struct intel_dp; 837 struct i915_drrs { 838 struct mutex mutex; 839 struct delayed_work work; 840 struct intel_dp *dp; 841 unsigned busy_frontbuffer_bits; 842 enum drrs_refresh_rate_type refresh_rate_type; 843 enum drrs_support_type type; 844 }; 845 846 struct i915_psr { 847 struct mutex lock; 848 bool sink_support; 849 bool source_ok; 850 struct intel_dp *enabled; 851 bool active; 852 struct delayed_work work; 853 unsigned busy_frontbuffer_bits; 854 bool link_standby; 855 }; 856 857 enum intel_pch { 858 PCH_NONE = 0, /* No PCH present */ 859 PCH_IBX, /* Ibexpeak PCH */ 860 PCH_CPT, /* Cougarpoint PCH */ 861 PCH_LPT, /* Lynxpoint PCH */ 862 PCH_SPT, /* Sunrisepoint PCH */ 863 PCH_NOP, 864 }; 865 866 enum intel_sbi_destination { 867 SBI_ICLK, 868 SBI_MPHY, 869 }; 870 871 #define QUIRK_PIPEA_FORCE (1<<0) 872 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 873 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 874 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 875 #define QUIRK_PIPEB_FORCE (1<<4) 876 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 877 878 struct intel_fbdev; 879 struct intel_fbc_work; 880 881 struct intel_gmbus { 882 struct i2c_adapter adapter; 883 u32 force_bit; 884 u32 reg0; 885 u32 gpio_reg; 886 struct i2c_algo_bit_data bit_algo; 887 struct drm_i915_private *dev_priv; 888 }; 889 890 struct i915_suspend_saved_registers { 891 u8 saveLBB; 892 u32 saveDSPACNTR; 893 u32 saveDSPBCNTR; 894 u32 saveDSPARB; 895 u32 savePIPEACONF; 896 u32 savePIPEBCONF; 897 u32 savePIPEASRC; 898 u32 savePIPEBSRC; 899 u32 saveFPA0; 900 u32 saveFPA1; 901 u32 saveDPLL_A; 902 u32 saveDPLL_A_MD; 903 u32 saveHTOTAL_A; 904 u32 saveHBLANK_A; 905 u32 saveHSYNC_A; 906 u32 saveVTOTAL_A; 907 u32 saveVBLANK_A; 908 u32 saveVSYNC_A; 909 u32 saveBCLRPAT_A; 910 u32 saveTRANSACONF; 911 u32 saveTRANS_HTOTAL_A; 912 u32 saveTRANS_HBLANK_A; 913 u32 saveTRANS_HSYNC_A; 914 u32 saveTRANS_VTOTAL_A; 915 u32 saveTRANS_VBLANK_A; 916 u32 saveTRANS_VSYNC_A; 917 u32 savePIPEASTAT; 918 u32 saveDSPASTRIDE; 919 u32 saveDSPASIZE; 920 u32 saveDSPAPOS; 921 u32 saveDSPAADDR; 922 u32 saveDSPASURF; 923 u32 saveDSPATILEOFF; 924 u32 savePFIT_PGM_RATIOS; 925 u32 saveBLC_HIST_CTL; 926 u32 saveBLC_PWM_CTL; 927 u32 saveBLC_PWM_CTL2; 928 u32 saveBLC_CPU_PWM_CTL; 929 u32 saveBLC_CPU_PWM_CTL2; 930 u32 saveFPB0; 931 u32 saveFPB1; 932 u32 saveDPLL_B; 933 u32 saveDPLL_B_MD; 934 u32 saveHTOTAL_B; 935 u32 saveHBLANK_B; 936 u32 saveHSYNC_B; 937 u32 saveVTOTAL_B; 938 u32 saveVBLANK_B; 939 u32 saveVSYNC_B; 940 u32 saveBCLRPAT_B; 941 u32 saveTRANSBCONF; 942 u32 saveTRANS_HTOTAL_B; 943 u32 saveTRANS_HBLANK_B; 944 u32 saveTRANS_HSYNC_B; 945 u32 saveTRANS_VTOTAL_B; 946 u32 saveTRANS_VBLANK_B; 947 u32 saveTRANS_VSYNC_B; 948 u32 savePIPEBSTAT; 949 u32 saveDSPBSTRIDE; 950 u32 saveDSPBSIZE; 951 u32 saveDSPBPOS; 952 u32 saveDSPBADDR; 953 u32 saveDSPBSURF; 954 u32 saveDSPBTILEOFF; 955 u32 saveVGA0; 956 u32 saveVGA1; 957 u32 saveVGA_PD; 958 u32 saveVGACNTRL; 959 u32 saveADPA; 960 u32 saveLVDS; 961 u32 savePP_ON_DELAYS; 962 u32 savePP_OFF_DELAYS; 963 u32 saveDVOA; 964 u32 saveDVOB; 965 u32 saveDVOC; 966 u32 savePP_ON; 967 u32 savePP_OFF; 968 u32 savePP_CONTROL; 969 u32 savePP_DIVISOR; 970 u32 savePFIT_CONTROL; 971 u32 save_palette_a[256]; 972 u32 save_palette_b[256]; 973 u32 saveFBC_CONTROL; 974 u32 saveIER; 975 u32 saveIIR; 976 u32 saveIMR; 977 u32 saveDEIER; 978 u32 saveDEIMR; 979 u32 saveGTIER; 980 u32 saveGTIMR; 981 u32 saveFDI_RXA_IMR; 982 u32 saveFDI_RXB_IMR; 983 u32 saveCACHE_MODE_0; 984 u32 saveMI_ARB_STATE; 985 u32 saveSWF0[16]; 986 u32 saveSWF1[16]; 987 u32 saveSWF2[3]; 988 u8 saveMSR; 989 u8 saveSR[8]; 990 u8 saveGR[25]; 991 u8 saveAR_INDEX; 992 u8 saveAR[21]; 993 u8 saveDACMASK; 994 u8 saveCR[37]; 995 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 996 u32 saveCURACNTR; 997 u32 saveCURAPOS; 998 u32 saveCURABASE; 999 u32 saveCURBCNTR; 1000 u32 saveCURBPOS; 1001 u32 saveCURBBASE; 1002 u32 saveCURSIZE; 1003 u32 saveDP_B; 1004 u32 saveDP_C; 1005 u32 saveDP_D; 1006 u32 savePIPEA_GMCH_DATA_M; 1007 u32 savePIPEB_GMCH_DATA_M; 1008 u32 savePIPEA_GMCH_DATA_N; 1009 u32 savePIPEB_GMCH_DATA_N; 1010 u32 savePIPEA_DP_LINK_M; 1011 u32 savePIPEB_DP_LINK_M; 1012 u32 savePIPEA_DP_LINK_N; 1013 u32 savePIPEB_DP_LINK_N; 1014 u32 saveFDI_RXA_CTL; 1015 u32 saveFDI_TXA_CTL; 1016 u32 saveFDI_RXB_CTL; 1017 u32 saveFDI_TXB_CTL; 1018 u32 savePFA_CTL_1; 1019 u32 savePFB_CTL_1; 1020 u32 savePFA_WIN_SZ; 1021 u32 savePFB_WIN_SZ; 1022 u32 savePFA_WIN_POS; 1023 u32 savePFB_WIN_POS; 1024 u32 savePCH_DREF_CONTROL; 1025 u32 saveDISP_ARB_CTL; 1026 u32 savePIPEA_DATA_M1; 1027 u32 savePIPEA_DATA_N1; 1028 u32 savePIPEA_LINK_M1; 1029 u32 savePIPEA_LINK_N1; 1030 u32 savePIPEB_DATA_M1; 1031 u32 savePIPEB_DATA_N1; 1032 u32 savePIPEB_LINK_M1; 1033 u32 savePIPEB_LINK_N1; 1034 u32 saveMCHBAR_RENDER_STANDBY; 1035 u32 savePCH_PORT_HOTPLUG; 1036 u16 saveGCDGMBUS; 1037 }; 1038 1039 struct vlv_s0ix_state { 1040 /* GAM */ 1041 u32 wr_watermark; 1042 u32 gfx_prio_ctrl; 1043 u32 arb_mode; 1044 u32 gfx_pend_tlb0; 1045 u32 gfx_pend_tlb1; 1046 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 1047 u32 media_max_req_count; 1048 u32 gfx_max_req_count; 1049 u32 render_hwsp; 1050 u32 ecochk; 1051 u32 bsd_hwsp; 1052 u32 blt_hwsp; 1053 u32 tlb_rd_addr; 1054 1055 /* MBC */ 1056 u32 g3dctl; 1057 u32 gsckgctl; 1058 u32 mbctl; 1059 1060 /* GCP */ 1061 u32 ucgctl1; 1062 u32 ucgctl3; 1063 u32 rcgctl1; 1064 u32 rcgctl2; 1065 u32 rstctl; 1066 u32 misccpctl; 1067 1068 /* GPM */ 1069 u32 gfxpause; 1070 u32 rpdeuhwtc; 1071 u32 rpdeuc; 1072 u32 ecobus; 1073 u32 pwrdwnupctl; 1074 u32 rp_down_timeout; 1075 u32 rp_deucsw; 1076 u32 rcubmabdtmr; 1077 u32 rcedata; 1078 u32 spare2gh; 1079 1080 /* Display 1 CZ domain */ 1081 u32 gt_imr; 1082 u32 gt_ier; 1083 u32 pm_imr; 1084 u32 pm_ier; 1085 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 1086 1087 /* GT SA CZ domain */ 1088 u32 tilectl; 1089 u32 gt_fifoctl; 1090 u32 gtlc_wake_ctrl; 1091 u32 gtlc_survive; 1092 u32 pmwgicz; 1093 1094 /* Display 2 CZ domain */ 1095 u32 gu_ctl0; 1096 u32 gu_ctl1; 1097 u32 clock_gate_dis2; 1098 }; 1099 1100 struct intel_rps_ei { 1101 u32 cz_clock; 1102 u32 render_c0; 1103 u32 media_c0; 1104 }; 1105 1106 struct intel_gen6_power_mgmt { 1107 /* 1108 * work, interrupts_enabled and pm_iir are protected by 1109 * dev_priv->irq_lock 1110 */ 1111 struct work_struct work; 1112 bool interrupts_enabled; 1113 u32 pm_iir; 1114 1115 /* Frequencies are stored in potentially platform dependent multiples. 1116 * In other words, *_freq needs to be multiplied by X to be interesting. 1117 * Soft limits are those which are used for the dynamic reclocking done 1118 * by the driver (raise frequencies under heavy loads, and lower for 1119 * lighter loads). Hard limits are those imposed by the hardware. 1120 * 1121 * A distinction is made for overclocking, which is never enabled by 1122 * default, and is considered to be above the hard limit if it's 1123 * possible at all. 1124 */ 1125 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 1126 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 1127 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 1128 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 1129 u8 min_freq; /* AKA RPn. Minimum frequency */ 1130 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 1131 u8 rp1_freq; /* "less than" RP0 power/freqency */ 1132 u8 rp0_freq; /* Non-overclocked max frequency. */ 1133 u32 cz_freq; 1134 1135 u32 ei_interrupt_count; 1136 1137 int last_adj; 1138 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 1139 1140 bool enabled; 1141 struct delayed_work delayed_resume_work; 1142 1143 /* manual wa residency calculations */ 1144 struct intel_rps_ei up_ei, down_ei; 1145 1146 /* 1147 * Protects RPS/RC6 register access and PCU communication. 1148 * Must be taken after struct_mutex if nested. 1149 */ 1150 struct mutex hw_lock; 1151 }; 1152 1153 /* defined intel_pm.c */ 1154 extern spinlock_t mchdev_lock; 1155 1156 struct intel_ilk_power_mgmt { 1157 u8 cur_delay; 1158 u8 min_delay; 1159 u8 max_delay; 1160 u8 fmax; 1161 u8 fstart; 1162 1163 u64 last_count1; 1164 unsigned long last_time1; 1165 unsigned long chipset_power; 1166 u64 last_count2; 1167 u64 last_time2; 1168 unsigned long gfx_power; 1169 u8 corr; 1170 1171 int c_m; 1172 int r_t; 1173 1174 struct drm_i915_gem_object *pwrctx; 1175 struct drm_i915_gem_object *renderctx; 1176 }; 1177 1178 struct drm_i915_private; 1179 struct i915_power_well; 1180 1181 struct i915_power_well_ops { 1182 /* 1183 * Synchronize the well's hw state to match the current sw state, for 1184 * example enable/disable it based on the current refcount. Called 1185 * during driver init and resume time, possibly after first calling 1186 * the enable/disable handlers. 1187 */ 1188 void (*sync_hw)(struct drm_i915_private *dev_priv, 1189 struct i915_power_well *power_well); 1190 /* 1191 * Enable the well and resources that depend on it (for example 1192 * interrupts located on the well). Called after the 0->1 refcount 1193 * transition. 1194 */ 1195 void (*enable)(struct drm_i915_private *dev_priv, 1196 struct i915_power_well *power_well); 1197 /* 1198 * Disable the well and resources that depend on it. Called after 1199 * the 1->0 refcount transition. 1200 */ 1201 void (*disable)(struct drm_i915_private *dev_priv, 1202 struct i915_power_well *power_well); 1203 /* Returns the hw enabled state. */ 1204 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1205 struct i915_power_well *power_well); 1206 }; 1207 1208 /* Power well structure for haswell */ 1209 struct i915_power_well { 1210 const char *name; 1211 bool always_on; 1212 /* power well enable/disable usage count */ 1213 int count; 1214 /* cached hw enabled state */ 1215 bool hw_enabled; 1216 unsigned long domains; 1217 unsigned long data; 1218 const struct i915_power_well_ops *ops; 1219 }; 1220 1221 struct i915_power_domains { 1222 /* 1223 * Power wells needed for initialization at driver init and suspend 1224 * time are on. They are kept on until after the first modeset. 1225 */ 1226 bool init_power_on; 1227 bool initializing; 1228 int power_well_count; 1229 1230 struct mutex lock; 1231 int domain_use_count[POWER_DOMAIN_NUM]; 1232 struct i915_power_well *power_wells; 1233 }; 1234 1235 #define MAX_L3_SLICES 2 1236 struct intel_l3_parity { 1237 u32 *remap_info[MAX_L3_SLICES]; 1238 struct work_struct error_work; 1239 int which_slice; 1240 }; 1241 1242 struct i915_gem_batch_pool { 1243 struct drm_device *dev; 1244 struct list_head cache_list; 1245 }; 1246 1247 struct i915_gem_mm { 1248 /** Memory allocator for GTT stolen memory */ 1249 struct drm_mm stolen; 1250 /** List of all objects in gtt_space. Used to restore gtt 1251 * mappings on resume */ 1252 struct list_head bound_list; 1253 /** 1254 * List of objects which are not bound to the GTT (thus 1255 * are idle and not used by the GPU) but still have 1256 * (presumably uncached) pages still attached. 1257 */ 1258 struct list_head unbound_list; 1259 1260 /* 1261 * A pool of objects to use as shadow copies of client batch buffers 1262 * when the command parser is enabled. Prevents the client from 1263 * modifying the batch contents after software parsing. 1264 */ 1265 struct i915_gem_batch_pool batch_pool; 1266 1267 /** Usable portion of the GTT for GEM */ 1268 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1269 1270 /** PPGTT used for aliasing the PPGTT with the GTT */ 1271 struct i915_hw_ppgtt *aliasing_ppgtt; 1272 1273 struct notifier_block oom_notifier; 1274 struct shrinker shrinker; 1275 bool shrinker_no_lock_stealing; 1276 1277 /** LRU list of objects with fence regs on them. */ 1278 struct list_head fence_list; 1279 1280 /** 1281 * We leave the user IRQ off as much as possible, 1282 * but this means that requests will finish and never 1283 * be retired once the system goes idle. Set a timer to 1284 * fire periodically while the ring is running. When it 1285 * fires, go retire requests. 1286 */ 1287 struct delayed_work retire_work; 1288 1289 /** 1290 * When we detect an idle GPU, we want to turn on 1291 * powersaving features. So once we see that there 1292 * are no more requests outstanding and no more 1293 * arrive within a small period of time, we fire 1294 * off the idle_work. 1295 */ 1296 struct delayed_work idle_work; 1297 1298 /** 1299 * Are we in a non-interruptible section of code like 1300 * modesetting? 1301 */ 1302 bool interruptible; 1303 1304 /** 1305 * Is the GPU currently considered idle, or busy executing userspace 1306 * requests? Whilst idle, we attempt to power down the hardware and 1307 * display clocks. In order to reduce the effect on performance, there 1308 * is a slight delay before we do so. 1309 */ 1310 bool busy; 1311 1312 /* the indicator for dispatch video commands on two BSD rings */ 1313 int bsd_ring_dispatch_index; 1314 1315 /** Bit 6 swizzling required for X tiling */ 1316 uint32_t bit_6_swizzle_x; 1317 /** Bit 6 swizzling required for Y tiling */ 1318 uint32_t bit_6_swizzle_y; 1319 1320 /* accounting, useful for userland debugging */ 1321 spinlock_t object_stat_lock; 1322 size_t object_memory; 1323 u32 object_count; 1324 }; 1325 1326 struct drm_i915_error_state_buf { 1327 struct drm_i915_private *i915; 1328 unsigned bytes; 1329 unsigned size; 1330 int err; 1331 u8 *buf; 1332 loff_t start; 1333 loff_t pos; 1334 }; 1335 1336 struct i915_error_state_file_priv { 1337 struct drm_device *dev; 1338 struct drm_i915_error_state *error; 1339 }; 1340 1341 struct i915_gpu_error { 1342 /* For hangcheck timer */ 1343 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1344 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1345 /* Hang gpu twice in this window and your context gets banned */ 1346 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1347 1348 struct workqueue_struct *hangcheck_wq; 1349 struct delayed_work hangcheck_work; 1350 1351 /* For reset and error_state handling. */ 1352 spinlock_t lock; 1353 /* Protected by the above dev->gpu_error.lock. */ 1354 struct drm_i915_error_state *first_error; 1355 1356 unsigned long missed_irq_rings; 1357 1358 /** 1359 * State variable controlling the reset flow and count 1360 * 1361 * This is a counter which gets incremented when reset is triggered, 1362 * and again when reset has been handled. So odd values (lowest bit set) 1363 * means that reset is in progress and even values that 1364 * (reset_counter >> 1):th reset was successfully completed. 1365 * 1366 * If reset is not completed succesfully, the I915_WEDGE bit is 1367 * set meaning that hardware is terminally sour and there is no 1368 * recovery. All waiters on the reset_queue will be woken when 1369 * that happens. 1370 * 1371 * This counter is used by the wait_seqno code to notice that reset 1372 * event happened and it needs to restart the entire ioctl (since most 1373 * likely the seqno it waited for won't ever signal anytime soon). 1374 * 1375 * This is important for lock-free wait paths, where no contended lock 1376 * naturally enforces the correct ordering between the bail-out of the 1377 * waiter and the gpu reset work code. 1378 */ 1379 atomic_t reset_counter; 1380 1381 #define I915_RESET_IN_PROGRESS_FLAG 1 1382 #define I915_WEDGED (1 << 31) 1383 1384 /** 1385 * Waitqueue to signal when the reset has completed. Used by clients 1386 * that wait for dev_priv->mm.wedged to settle. 1387 */ 1388 wait_queue_head_t reset_queue; 1389 1390 /* Userspace knobs for gpu hang simulation; 1391 * combines both a ring mask, and extra flags 1392 */ 1393 u32 stop_rings; 1394 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1395 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1396 1397 /* For missed irq/seqno simulation. */ 1398 unsigned int test_irq_rings; 1399 1400 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 1401 bool reload_in_reset; 1402 }; 1403 1404 enum modeset_restore { 1405 MODESET_ON_LID_OPEN, 1406 MODESET_DONE, 1407 MODESET_SUSPENDED, 1408 }; 1409 1410 struct ddi_vbt_port_info { 1411 /* 1412 * This is an index in the HDMI/DVI DDI buffer translation table. 1413 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1414 * populate this field. 1415 */ 1416 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1417 uint8_t hdmi_level_shift; 1418 1419 uint8_t supports_dvi:1; 1420 uint8_t supports_hdmi:1; 1421 uint8_t supports_dp:1; 1422 }; 1423 1424 enum psr_lines_to_wait { 1425 PSR_0_LINES_TO_WAIT = 0, 1426 PSR_1_LINE_TO_WAIT, 1427 PSR_4_LINES_TO_WAIT, 1428 PSR_8_LINES_TO_WAIT 1429 }; 1430 1431 struct intel_vbt_data { 1432 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1433 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1434 1435 /* Feature bits */ 1436 unsigned int int_tv_support:1; 1437 unsigned int lvds_dither:1; 1438 unsigned int lvds_vbt:1; 1439 unsigned int int_crt_support:1; 1440 unsigned int lvds_use_ssc:1; 1441 unsigned int display_clock_mode:1; 1442 unsigned int fdi_rx_polarity_inverted:1; 1443 unsigned int has_mipi:1; 1444 int lvds_ssc_freq; 1445 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1446 1447 enum drrs_support_type drrs_type; 1448 1449 /* eDP */ 1450 int edp_rate; 1451 int edp_lanes; 1452 int edp_preemphasis; 1453 int edp_vswing; 1454 bool edp_initialized; 1455 bool edp_support; 1456 int edp_bpp; 1457 struct edp_power_seq edp_pps; 1458 1459 struct { 1460 bool full_link; 1461 bool require_aux_wakeup; 1462 int idle_frames; 1463 enum psr_lines_to_wait lines_to_wait; 1464 int tp1_wakeup_time; 1465 int tp2_tp3_wakeup_time; 1466 } psr; 1467 1468 struct { 1469 u16 pwm_freq_hz; 1470 bool present; 1471 bool active_low_pwm; 1472 u8 min_brightness; /* min_brightness/255 of max */ 1473 } backlight; 1474 1475 /* MIPI DSI */ 1476 struct { 1477 u16 port; 1478 u16 panel_id; 1479 struct mipi_config *config; 1480 struct mipi_pps_data *pps; 1481 u8 seq_version; 1482 u32 size; 1483 u8 *data; 1484 u8 *sequence[MIPI_SEQ_MAX]; 1485 } dsi; 1486 1487 int crt_ddc_pin; 1488 1489 int child_dev_num; 1490 union child_device_config *child_dev; 1491 1492 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1493 }; 1494 1495 enum intel_ddb_partitioning { 1496 INTEL_DDB_PART_1_2, 1497 INTEL_DDB_PART_5_6, /* IVB+ */ 1498 }; 1499 1500 struct intel_wm_level { 1501 bool enable; 1502 uint32_t pri_val; 1503 uint32_t spr_val; 1504 uint32_t cur_val; 1505 uint32_t fbc_val; 1506 }; 1507 1508 struct ilk_wm_values { 1509 uint32_t wm_pipe[3]; 1510 uint32_t wm_lp[3]; 1511 uint32_t wm_lp_spr[3]; 1512 uint32_t wm_linetime[3]; 1513 bool enable_fbc_wm; 1514 enum intel_ddb_partitioning partitioning; 1515 }; 1516 1517 struct skl_ddb_entry { 1518 uint16_t start, end; /* in number of blocks, 'end' is exclusive */ 1519 }; 1520 1521 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) 1522 { 1523 return entry->end - entry->start; 1524 } 1525 1526 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 1527 const struct skl_ddb_entry *e2) 1528 { 1529 if (e1->start == e2->start && e1->end == e2->end) 1530 return true; 1531 1532 return false; 1533 } 1534 1535 struct skl_ddb_allocation { 1536 struct skl_ddb_entry pipe[I915_MAX_PIPES]; 1537 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; 1538 struct skl_ddb_entry cursor[I915_MAX_PIPES]; 1539 }; 1540 1541 struct skl_wm_values { 1542 bool dirty[I915_MAX_PIPES]; 1543 struct skl_ddb_allocation ddb; 1544 uint32_t wm_linetime[I915_MAX_PIPES]; 1545 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; 1546 uint32_t cursor[I915_MAX_PIPES][8]; 1547 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; 1548 uint32_t cursor_trans[I915_MAX_PIPES]; 1549 }; 1550 1551 struct skl_wm_level { 1552 bool plane_en[I915_MAX_PLANES]; 1553 bool cursor_en; 1554 uint16_t plane_res_b[I915_MAX_PLANES]; 1555 uint8_t plane_res_l[I915_MAX_PLANES]; 1556 uint16_t cursor_res_b; 1557 uint8_t cursor_res_l; 1558 }; 1559 1560 /* 1561 * This struct helps tracking the state needed for runtime PM, which puts the 1562 * device in PCI D3 state. Notice that when this happens, nothing on the 1563 * graphics device works, even register access, so we don't get interrupts nor 1564 * anything else. 1565 * 1566 * Every piece of our code that needs to actually touch the hardware needs to 1567 * either call intel_runtime_pm_get or call intel_display_power_get with the 1568 * appropriate power domain. 1569 * 1570 * Our driver uses the autosuspend delay feature, which means we'll only really 1571 * suspend if we stay with zero refcount for a certain amount of time. The 1572 * default value is currently very conservative (see intel_runtime_pm_enable), but 1573 * it can be changed with the standard runtime PM files from sysfs. 1574 * 1575 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1576 * goes back to false exactly before we reenable the IRQs. We use this variable 1577 * to check if someone is trying to enable/disable IRQs while they're supposed 1578 * to be disabled. This shouldn't happen and we'll print some error messages in 1579 * case it happens. 1580 * 1581 * For more, read the Documentation/power/runtime_pm.txt. 1582 */ 1583 struct i915_runtime_pm { 1584 bool suspended; 1585 bool irqs_enabled; 1586 }; 1587 1588 enum intel_pipe_crc_source { 1589 INTEL_PIPE_CRC_SOURCE_NONE, 1590 INTEL_PIPE_CRC_SOURCE_PLANE1, 1591 INTEL_PIPE_CRC_SOURCE_PLANE2, 1592 INTEL_PIPE_CRC_SOURCE_PF, 1593 INTEL_PIPE_CRC_SOURCE_PIPE, 1594 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1595 INTEL_PIPE_CRC_SOURCE_TV, 1596 INTEL_PIPE_CRC_SOURCE_DP_B, 1597 INTEL_PIPE_CRC_SOURCE_DP_C, 1598 INTEL_PIPE_CRC_SOURCE_DP_D, 1599 INTEL_PIPE_CRC_SOURCE_AUTO, 1600 INTEL_PIPE_CRC_SOURCE_MAX, 1601 }; 1602 1603 struct intel_pipe_crc_entry { 1604 uint32_t frame; 1605 uint32_t crc[5]; 1606 }; 1607 1608 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1609 struct intel_pipe_crc { 1610 spinlock_t lock; 1611 bool opened; /* exclusive access to the result file */ 1612 struct intel_pipe_crc_entry *entries; 1613 enum intel_pipe_crc_source source; 1614 int head, tail; 1615 wait_queue_head_t wq; 1616 }; 1617 1618 struct i915_frontbuffer_tracking { 1619 struct mutex lock; 1620 1621 /* 1622 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1623 * scheduled flips. 1624 */ 1625 unsigned busy_bits; 1626 unsigned flip_bits; 1627 }; 1628 1629 struct i915_wa_reg { 1630 u32 addr; 1631 u32 value; 1632 /* bitmask representing WA bits */ 1633 u32 mask; 1634 }; 1635 1636 #define I915_MAX_WA_REGS 16 1637 1638 struct i915_workarounds { 1639 struct i915_wa_reg reg[I915_MAX_WA_REGS]; 1640 u32 count; 1641 }; 1642 1643 struct drm_i915_private { 1644 struct drm_device *dev; 1645 struct kmem_cache *slab; 1646 1647 const struct intel_device_info info; 1648 1649 int relative_constants_mode; 1650 1651 void __iomem *regs; 1652 1653 struct intel_uncore uncore; 1654 1655 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 1656 1657 1658 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1659 * controller on different i2c buses. */ 1660 struct mutex gmbus_mutex; 1661 1662 /** 1663 * Base address of the gmbus and gpio block. 1664 */ 1665 uint32_t gpio_mmio_base; 1666 1667 /* MMIO base address for MIPI regs */ 1668 uint32_t mipi_mmio_base; 1669 1670 wait_queue_head_t gmbus_wait_queue; 1671 1672 struct pci_dev *bridge_dev; 1673 struct intel_engine_cs ring[I915_NUM_RINGS]; 1674 struct drm_i915_gem_object *semaphore_obj; 1675 uint32_t last_seqno, next_seqno; 1676 1677 struct drm_dma_handle *status_page_dmah; 1678 struct resource mch_res; 1679 1680 /* protects the irq masks */ 1681 spinlock_t irq_lock; 1682 1683 /* protects the mmio flip data */ 1684 spinlock_t mmio_flip_lock; 1685 1686 bool display_irqs_enabled; 1687 1688 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1689 struct pm_qos_request pm_qos; 1690 1691 /* DPIO indirect register protection */ 1692 struct mutex dpio_lock; 1693 1694 /** Cached value of IMR to avoid reads in updating the bitfield */ 1695 union { 1696 u32 irq_mask; 1697 u32 de_irq_mask[I915_MAX_PIPES]; 1698 }; 1699 u32 gt_irq_mask; 1700 u32 pm_irq_mask; 1701 u32 pm_rps_events; 1702 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1703 1704 struct work_struct hotplug_work; 1705 struct { 1706 unsigned long hpd_last_jiffies; 1707 int hpd_cnt; 1708 enum { 1709 HPD_ENABLED = 0, 1710 HPD_DISABLED = 1, 1711 HPD_MARK_DISABLED = 2 1712 } hpd_mark; 1713 } hpd_stats[HPD_NUM_PINS]; 1714 u32 hpd_event_bits; 1715 struct delayed_work hotplug_reenable_work; 1716 1717 struct i915_fbc fbc; 1718 struct i915_drrs drrs; 1719 struct intel_opregion opregion; 1720 struct intel_vbt_data vbt; 1721 1722 bool preserve_bios_swizzle; 1723 1724 /* overlay */ 1725 struct intel_overlay *overlay; 1726 1727 /* backlight registers and fields in struct intel_panel */ 1728 struct mutex backlight_lock; 1729 1730 /* LVDS info */ 1731 bool no_aux_handshake; 1732 1733 /* protects panel power sequencer state */ 1734 struct mutex pps_mutex; 1735 1736 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1737 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1738 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1739 1740 unsigned int fsb_freq, mem_freq, is_ddr3; 1741 unsigned int vlv_cdclk_freq; 1742 unsigned int hpll_freq; 1743 1744 /** 1745 * wq - Driver workqueue for GEM. 1746 * 1747 * NOTE: Work items scheduled here are not allowed to grab any modeset 1748 * locks, for otherwise the flushing done in the pageflip code will 1749 * result in deadlocks. 1750 */ 1751 struct workqueue_struct *wq; 1752 1753 /* Display functions */ 1754 struct drm_i915_display_funcs display; 1755 1756 /* PCH chipset type */ 1757 enum intel_pch pch_type; 1758 unsigned short pch_id; 1759 1760 unsigned long quirks; 1761 1762 enum modeset_restore modeset_restore; 1763 struct mutex modeset_restore_lock; 1764 1765 struct list_head vm_list; /* Global list of all address spaces */ 1766 struct i915_gtt gtt; /* VM representing the global address space */ 1767 1768 struct i915_gem_mm mm; 1769 DECLARE_HASHTABLE(mm_structs, 7); 1770 struct mutex mm_lock; 1771 1772 /* Kernel Modesetting */ 1773 1774 struct sdvo_device_mapping sdvo_mappings[2]; 1775 1776 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1777 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1778 wait_queue_head_t pending_flip_queue; 1779 1780 #ifdef CONFIG_DEBUG_FS 1781 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1782 #endif 1783 1784 int num_shared_dpll; 1785 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1786 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1787 1788 struct i915_workarounds workarounds; 1789 1790 /* Reclocking support */ 1791 bool render_reclock_avail; 1792 bool lvds_downclock_avail; 1793 /* indicates the reduced downclock for LVDS*/ 1794 int lvds_downclock; 1795 1796 struct i915_frontbuffer_tracking fb_tracking; 1797 1798 u16 orig_clock; 1799 1800 bool mchbar_need_disable; 1801 1802 struct intel_l3_parity l3_parity; 1803 1804 /* Cannot be determined by PCIID. You must always read a register. */ 1805 size_t ellc_size; 1806 1807 /* gen6+ rps state */ 1808 struct intel_gen6_power_mgmt rps; 1809 1810 /* ilk-only ips/rps state. Everything in here is protected by the global 1811 * mchdev_lock in intel_pm.c */ 1812 struct intel_ilk_power_mgmt ips; 1813 1814 struct i915_power_domains power_domains; 1815 1816 struct i915_psr psr; 1817 1818 struct i915_gpu_error gpu_error; 1819 1820 struct drm_i915_gem_object *vlv_pctx; 1821 1822 #ifdef CONFIG_DRM_I915_FBDEV 1823 /* list of fbdev register on this device */ 1824 struct intel_fbdev *fbdev; 1825 struct work_struct fbdev_suspend_work; 1826 #endif 1827 1828 struct drm_property *broadcast_rgb_property; 1829 struct drm_property *force_audio_property; 1830 1831 /* hda/i915 audio component */ 1832 bool audio_component_registered; 1833 1834 uint32_t hw_context_size; 1835 struct list_head context_list; 1836 1837 u32 fdi_rx_config; 1838 1839 u32 suspend_count; 1840 struct i915_suspend_saved_registers regfile; 1841 struct vlv_s0ix_state vlv_s0ix_state; 1842 1843 struct { 1844 /* 1845 * Raw watermark latency values: 1846 * in 0.1us units for WM0, 1847 * in 0.5us units for WM1+. 1848 */ 1849 /* primary */ 1850 uint16_t pri_latency[5]; 1851 /* sprite */ 1852 uint16_t spr_latency[5]; 1853 /* cursor */ 1854 uint16_t cur_latency[5]; 1855 /* 1856 * Raw watermark memory latency values 1857 * for SKL for all 8 levels 1858 * in 1us units. 1859 */ 1860 uint16_t skl_latency[8]; 1861 1862 /* 1863 * The skl_wm_values structure is a bit too big for stack 1864 * allocation, so we keep the staging struct where we store 1865 * intermediate results here instead. 1866 */ 1867 struct skl_wm_values skl_results; 1868 1869 /* current hardware state */ 1870 union { 1871 struct ilk_wm_values hw; 1872 struct skl_wm_values skl_hw; 1873 }; 1874 } wm; 1875 1876 struct i915_runtime_pm pm; 1877 1878 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; 1879 u32 long_hpd_port_mask; 1880 u32 short_hpd_port_mask; 1881 struct work_struct dig_port_work; 1882 1883 /* 1884 * if we get a HPD irq from DP and a HPD irq from non-DP 1885 * the non-DP HPD could block the workqueue on a mode config 1886 * mutex getting, that userspace may have taken. However 1887 * userspace is waiting on the DP workqueue to run which is 1888 * blocked behind the non-DP one. 1889 */ 1890 struct workqueue_struct *dp_wq; 1891 1892 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1893 struct { 1894 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, 1895 struct intel_engine_cs *ring, 1896 struct intel_context *ctx, 1897 struct drm_i915_gem_execbuffer2 *args, 1898 struct list_head *vmas, 1899 struct drm_i915_gem_object *batch_obj, 1900 u64 exec_start, u32 flags); 1901 int (*init_rings)(struct drm_device *dev); 1902 void (*cleanup_ring)(struct intel_engine_cs *ring); 1903 void (*stop_ring)(struct intel_engine_cs *ring); 1904 } gt; 1905 1906 uint32_t request_uniq; 1907 1908 /* 1909 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1910 * will be rejected. Instead look for a better place. 1911 */ 1912 }; 1913 1914 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1915 { 1916 return dev->dev_private; 1917 } 1918 1919 static inline struct drm_i915_private *dev_to_i915(struct device *dev) 1920 { 1921 return to_i915(dev_get_drvdata(dev)); 1922 } 1923 1924 /* Iterate over initialised rings */ 1925 #define for_each_ring(ring__, dev_priv__, i__) \ 1926 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1927 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1928 1929 enum hdmi_force_audio { 1930 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1931 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1932 HDMI_AUDIO_AUTO, /* trust EDID */ 1933 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1934 }; 1935 1936 #define I915_GTT_OFFSET_NONE ((u32)-1) 1937 1938 struct drm_i915_gem_object_ops { 1939 /* Interface between the GEM object and its backing storage. 1940 * get_pages() is called once prior to the use of the associated set 1941 * of pages before to binding them into the GTT, and put_pages() is 1942 * called after we no longer need them. As we expect there to be 1943 * associated cost with migrating pages between the backing storage 1944 * and making them available for the GPU (e.g. clflush), we may hold 1945 * onto the pages after they are no longer referenced by the GPU 1946 * in case they may be used again shortly (for example migrating the 1947 * pages to a different memory domain within the GTT). put_pages() 1948 * will therefore most likely be called when the object itself is 1949 * being released or under memory pressure (where we attempt to 1950 * reap pages for the shrinker). 1951 */ 1952 int (*get_pages)(struct drm_i915_gem_object *); 1953 void (*put_pages)(struct drm_i915_gem_object *); 1954 int (*dmabuf_export)(struct drm_i915_gem_object *); 1955 void (*release)(struct drm_i915_gem_object *); 1956 }; 1957 1958 /* 1959 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1960 * considered to be the frontbuffer for the given plane interface-vise. This 1961 * doesn't mean that the hw necessarily already scans it out, but that any 1962 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1963 * 1964 * We have one bit per pipe and per scanout plane type. 1965 */ 1966 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 1967 #define INTEL_FRONTBUFFER_BITS \ 1968 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 1969 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 1970 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1971 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 1972 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1973 #define INTEL_FRONTBUFFER_SPRITE(pipe) \ 1974 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1975 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1976 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1977 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1978 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1979 1980 struct drm_i915_gem_object { 1981 struct drm_gem_object base; 1982 1983 const struct drm_i915_gem_object_ops *ops; 1984 1985 /** List of VMAs backed by this object */ 1986 struct list_head vma_list; 1987 1988 /** Stolen memory for this object, instead of being backed by shmem. */ 1989 struct drm_mm_node *stolen; 1990 struct list_head global_list; 1991 1992 struct list_head ring_list; 1993 /** Used in execbuf to temporarily hold a ref */ 1994 struct list_head obj_exec_link; 1995 1996 struct list_head batch_pool_list; 1997 1998 /** 1999 * This is set if the object is on the active lists (has pending 2000 * rendering and so a non-zero seqno), and is not set if it i s on 2001 * inactive (ready to be unbound) list. 2002 */ 2003 unsigned int active:1; 2004 2005 /** 2006 * This is set if the object has been written to since last bound 2007 * to the GTT 2008 */ 2009 unsigned int dirty:1; 2010 2011 /** 2012 * Fence register bits (if any) for this object. Will be set 2013 * as needed when mapped into the GTT. 2014 * Protected by dev->struct_mutex. 2015 */ 2016 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 2017 2018 /** 2019 * Advice: are the backing pages purgeable? 2020 */ 2021 unsigned int madv:2; 2022 2023 /** 2024 * Current tiling mode for the object. 2025 */ 2026 unsigned int tiling_mode:2; 2027 /** 2028 * Whether the tiling parameters for the currently associated fence 2029 * register have changed. Note that for the purposes of tracking 2030 * tiling changes we also treat the unfenced register, the register 2031 * slot that the object occupies whilst it executes a fenced 2032 * command (such as BLT on gen2/3), as a "fence". 2033 */ 2034 unsigned int fence_dirty:1; 2035 2036 /** 2037 * Is the object at the current location in the gtt mappable and 2038 * fenceable? Used to avoid costly recalculations. 2039 */ 2040 unsigned int map_and_fenceable:1; 2041 2042 /** 2043 * Whether the current gtt mapping needs to be mappable (and isn't just 2044 * mappable by accident). Track pin and fault separate for a more 2045 * accurate mappable working set. 2046 */ 2047 unsigned int fault_mappable:1; 2048 unsigned int pin_mappable:1; 2049 unsigned int pin_display:1; 2050 2051 /* 2052 * Is the object to be mapped as read-only to the GPU 2053 * Only honoured if hardware has relevant pte bit 2054 */ 2055 unsigned long gt_ro:1; 2056 unsigned int cache_level:3; 2057 unsigned int cache_dirty:1; 2058 2059 unsigned int has_dma_mapping:1; 2060 2061 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 2062 2063 struct sg_table *pages; 2064 int pages_pin_count; 2065 2066 /* prime dma-buf support */ 2067 void *dma_buf_vmapping; 2068 int vmapping_count; 2069 2070 /** Breadcrumb of last rendering to the buffer. */ 2071 struct drm_i915_gem_request *last_read_req; 2072 struct drm_i915_gem_request *last_write_req; 2073 /** Breadcrumb of last fenced GPU access to the buffer. */ 2074 struct drm_i915_gem_request *last_fenced_req; 2075 2076 /** Current tiling stride for the object, if it's tiled. */ 2077 uint32_t stride; 2078 2079 /** References from framebuffers, locks out tiling changes. */ 2080 unsigned long framebuffer_references; 2081 2082 /** Record of address bit 17 of each page at last unbind. */ 2083 unsigned long *bit_17; 2084 2085 union { 2086 /** for phy allocated objects */ 2087 struct drm_dma_handle *phys_handle; 2088 2089 struct i915_gem_userptr { 2090 uintptr_t ptr; 2091 unsigned read_only :1; 2092 unsigned workers :4; 2093 #define I915_GEM_USERPTR_MAX_WORKERS 15 2094 2095 struct i915_mm_struct *mm; 2096 struct i915_mmu_object *mmu_object; 2097 struct work_struct *work; 2098 } userptr; 2099 }; 2100 }; 2101 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 2102 2103 void i915_gem_track_fb(struct drm_i915_gem_object *old, 2104 struct drm_i915_gem_object *new, 2105 unsigned frontbuffer_bits); 2106 2107 /** 2108 * Request queue structure. 2109 * 2110 * The request queue allows us to note sequence numbers that have been emitted 2111 * and may be associated with active buffers to be retired. 2112 * 2113 * By keeping this list, we can avoid having to do questionable sequence 2114 * number comparisons on buffer last_read|write_seqno. It also allows an 2115 * emission time to be associated with the request for tracking how far ahead 2116 * of the GPU the submission is. 2117 * 2118 * The requests are reference counted, so upon creation they should have an 2119 * initial reference taken using kref_init 2120 */ 2121 struct drm_i915_gem_request { 2122 struct kref ref; 2123 2124 /** On Which ring this request was generated */ 2125 struct intel_engine_cs *ring; 2126 2127 /** GEM sequence number associated with this request. */ 2128 uint32_t seqno; 2129 2130 /** Position in the ringbuffer of the start of the request */ 2131 u32 head; 2132 2133 /** 2134 * Position in the ringbuffer of the start of the postfix. 2135 * This is required to calculate the maximum available ringbuffer 2136 * space without overwriting the postfix. 2137 */ 2138 u32 postfix; 2139 2140 /** Position in the ringbuffer of the end of the whole request */ 2141 u32 tail; 2142 2143 /** 2144 * Context related to this request 2145 * Contexts are refcounted, so when this request is associated with a 2146 * context, we must increment the context's refcount, to guarantee that 2147 * it persists while any request is linked to it. Requests themselves 2148 * are also refcounted, so the request will only be freed when the last 2149 * reference to it is dismissed, and the code in 2150 * i915_gem_request_free() will then decrement the refcount on the 2151 * context. 2152 */ 2153 struct intel_context *ctx; 2154 2155 /** Batch buffer related to this request if any */ 2156 struct drm_i915_gem_object *batch_obj; 2157 2158 /** Time at which this request was emitted, in jiffies. */ 2159 unsigned long emitted_jiffies; 2160 2161 /** global list entry for this request */ 2162 struct list_head list; 2163 2164 struct drm_i915_file_private *file_priv; 2165 /** file_priv list entry for this request */ 2166 struct list_head client_list; 2167 2168 uint32_t uniq; 2169 2170 /** 2171 * The ELSP only accepts two elements at a time, so we queue 2172 * context/tail pairs on a given queue (ring->execlist_queue) until the 2173 * hardware is available. The queue serves a double purpose: we also use 2174 * it to keep track of the up to 2 contexts currently in the hardware 2175 * (usually one in execution and the other queued up by the GPU): We 2176 * only remove elements from the head of the queue when the hardware 2177 * informs us that an element has been completed. 2178 * 2179 * All accesses to the queue are mediated by a spinlock 2180 * (ring->execlist_lock). 2181 */ 2182 2183 /** Execlist link in the submission queue.*/ 2184 struct list_head execlist_link; 2185 2186 /** Execlists no. of times this request has been sent to the ELSP */ 2187 int elsp_submitted; 2188 2189 }; 2190 2191 void i915_gem_request_free(struct kref *req_ref); 2192 2193 static inline uint32_t 2194 i915_gem_request_get_seqno(struct drm_i915_gem_request *req) 2195 { 2196 return req ? req->seqno : 0; 2197 } 2198 2199 static inline struct intel_engine_cs * 2200 i915_gem_request_get_ring(struct drm_i915_gem_request *req) 2201 { 2202 return req ? req->ring : NULL; 2203 } 2204 2205 static inline void 2206 i915_gem_request_reference(struct drm_i915_gem_request *req) 2207 { 2208 kref_get(&req->ref); 2209 } 2210 2211 static inline void 2212 i915_gem_request_unreference(struct drm_i915_gem_request *req) 2213 { 2214 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); 2215 kref_put(&req->ref, i915_gem_request_free); 2216 } 2217 2218 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, 2219 struct drm_i915_gem_request *src) 2220 { 2221 if (src) 2222 i915_gem_request_reference(src); 2223 2224 if (*pdst) 2225 i915_gem_request_unreference(*pdst); 2226 2227 *pdst = src; 2228 } 2229 2230 /* 2231 * XXX: i915_gem_request_completed should be here but currently needs the 2232 * definition of i915_seqno_passed() which is below. It will be moved in 2233 * a later patch when the call to i915_seqno_passed() is obsoleted... 2234 */ 2235 2236 struct drm_i915_file_private { 2237 struct drm_i915_private *dev_priv; 2238 struct drm_file *file; 2239 2240 struct { 2241 spinlock_t lock; 2242 struct list_head request_list; 2243 struct delayed_work idle_work; 2244 } mm; 2245 struct idr context_idr; 2246 2247 atomic_t rps_wait_boost; 2248 struct intel_engine_cs *bsd_ring; 2249 }; 2250 2251 /* 2252 * A command that requires special handling by the command parser. 2253 */ 2254 struct drm_i915_cmd_descriptor { 2255 /* 2256 * Flags describing how the command parser processes the command. 2257 * 2258 * CMD_DESC_FIXED: The command has a fixed length if this is set, 2259 * a length mask if not set 2260 * CMD_DESC_SKIP: The command is allowed but does not follow the 2261 * standard length encoding for the opcode range in 2262 * which it falls 2263 * CMD_DESC_REJECT: The command is never allowed 2264 * CMD_DESC_REGISTER: The command should be checked against the 2265 * register whitelist for the appropriate ring 2266 * CMD_DESC_MASTER: The command is allowed if the submitting process 2267 * is the DRM master 2268 */ 2269 u32 flags; 2270 #define CMD_DESC_FIXED (1<<0) 2271 #define CMD_DESC_SKIP (1<<1) 2272 #define CMD_DESC_REJECT (1<<2) 2273 #define CMD_DESC_REGISTER (1<<3) 2274 #define CMD_DESC_BITMASK (1<<4) 2275 #define CMD_DESC_MASTER (1<<5) 2276 2277 /* 2278 * The command's unique identification bits and the bitmask to get them. 2279 * This isn't strictly the opcode field as defined in the spec and may 2280 * also include type, subtype, and/or subop fields. 2281 */ 2282 struct { 2283 u32 value; 2284 u32 mask; 2285 } cmd; 2286 2287 /* 2288 * The command's length. The command is either fixed length (i.e. does 2289 * not include a length field) or has a length field mask. The flag 2290 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 2291 * a length mask. All command entries in a command table must include 2292 * length information. 2293 */ 2294 union { 2295 u32 fixed; 2296 u32 mask; 2297 } length; 2298 2299 /* 2300 * Describes where to find a register address in the command to check 2301 * against the ring's register whitelist. Only valid if flags has the 2302 * CMD_DESC_REGISTER bit set. 2303 */ 2304 struct { 2305 u32 offset; 2306 u32 mask; 2307 } reg; 2308 2309 #define MAX_CMD_DESC_BITMASKS 3 2310 /* 2311 * Describes command checks where a particular dword is masked and 2312 * compared against an expected value. If the command does not match 2313 * the expected value, the parser rejects it. Only valid if flags has 2314 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2315 * are valid. 2316 * 2317 * If the check specifies a non-zero condition_mask then the parser 2318 * only performs the check when the bits specified by condition_mask 2319 * are non-zero. 2320 */ 2321 struct { 2322 u32 offset; 2323 u32 mask; 2324 u32 expected; 2325 u32 condition_offset; 2326 u32 condition_mask; 2327 } bits[MAX_CMD_DESC_BITMASKS]; 2328 }; 2329 2330 /* 2331 * A table of commands requiring special handling by the command parser. 2332 * 2333 * Each ring has an array of tables. Each table consists of an array of command 2334 * descriptors, which must be sorted with command opcodes in ascending order. 2335 */ 2336 struct drm_i915_cmd_table { 2337 const struct drm_i915_cmd_descriptor *table; 2338 int count; 2339 }; 2340 2341 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2342 #define __I915__(p) ({ \ 2343 struct drm_i915_private *__p; \ 2344 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2345 __p = (struct drm_i915_private *)p; \ 2346 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2347 __p = to_i915((struct drm_device *)p); \ 2348 else \ 2349 BUILD_BUG(); \ 2350 __p; \ 2351 }) 2352 #define INTEL_INFO(p) (&__I915__(p)->info) 2353 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2354 2355 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2356 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2357 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2358 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2359 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2360 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2361 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2362 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2363 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2364 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2365 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2366 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2367 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2368 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2369 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2370 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2371 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2372 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2373 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2374 INTEL_DEVID(dev) == 0x0152 || \ 2375 INTEL_DEVID(dev) == 0x015a) 2376 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ 2377 INTEL_DEVID(dev) == 0x0106 || \ 2378 INTEL_DEVID(dev) == 0x010A) 2379 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2380 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2381 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2382 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2383 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) 2384 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2385 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2386 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2387 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2388 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2389 (INTEL_DEVID(dev) & 0xf) == 0xb || \ 2390 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2391 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2392 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2393 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2394 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2395 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2396 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2397 /* ULX machines are also considered ULT. */ 2398 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2399 INTEL_DEVID(dev) == 0x0A1E) 2400 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2401 2402 /* 2403 * The genX designation typically refers to the render engine, so render 2404 * capability related checks should use IS_GEN, while display and other checks 2405 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2406 * chips, etc.). 2407 */ 2408 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2409 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2410 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2411 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2412 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2413 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2414 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2415 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) 2416 2417 #define RENDER_RING (1<<RCS) 2418 #define BSD_RING (1<<VCS) 2419 #define BLT_RING (1<<BCS) 2420 #define VEBOX_RING (1<<VECS) 2421 #define BSD2_RING (1<<VCS2) 2422 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2423 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2424 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2425 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2426 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2427 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2428 __I915__(dev)->ellc_size) 2429 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2430 2431 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2432 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) 2433 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2434 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) 2435 2436 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2437 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2438 2439 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2440 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2441 /* 2442 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2443 * even when in MSI mode. This results in spurious interrupt warnings if the 2444 * legacy irq no. is shared with another device. The kernel then disables that 2445 * interrupt source and so prevents the other device from working properly. 2446 */ 2447 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2448 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2449 2450 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2451 * rows, which changed the alignment requirements and fence programming. 2452 */ 2453 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2454 IS_I915GM(dev))) 2455 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 2456 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2457 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2458 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2459 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2460 2461 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2462 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2463 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2464 2465 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) 2466 2467 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2468 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2469 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ 2470 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ 2471 IS_SKYLAKE(dev)) 2472 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2473 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2474 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) 2475 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) 2476 2477 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2478 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2479 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2480 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2481 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2482 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2483 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 2484 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 2485 2486 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) 2487 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) 2488 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2489 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2490 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2491 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2492 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2493 2494 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2495 2496 /* DPF == dynamic parity feature */ 2497 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2498 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2499 2500 #define GT_FREQUENCY_MULTIPLIER 50 2501 2502 #include "i915_trace.h" 2503 2504 extern const struct drm_ioctl_desc i915_ioctls[]; 2505 extern int i915_max_ioctl; 2506 2507 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); 2508 extern int i915_resume_legacy(struct drm_device *dev); 2509 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 2510 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 2511 2512 /* i915_params.c */ 2513 struct i915_params { 2514 int modeset; 2515 int panel_ignore_lid; 2516 unsigned int powersave; 2517 int semaphores; 2518 unsigned int lvds_downclock; 2519 int lvds_channel_mode; 2520 int panel_use_ssc; 2521 int vbt_sdvo_panel_type; 2522 int enable_rc6; 2523 int enable_fbc; 2524 int enable_ppgtt; 2525 int enable_execlists; 2526 int enable_psr; 2527 unsigned int preliminary_hw_support; 2528 int disable_power_well; 2529 int enable_ips; 2530 int invert_brightness; 2531 int enable_cmd_parser; 2532 /* leave bools at the end to not create holes */ 2533 bool enable_hangcheck; 2534 bool fastboot; 2535 bool prefault_disable; 2536 bool reset; 2537 bool disable_display; 2538 bool disable_vtd_wa; 2539 int use_mmio_flip; 2540 bool mmio_debug; 2541 bool verbose_state_checks; 2542 bool nuclear_pageflip; 2543 }; 2544 extern struct i915_params i915 __read_mostly; 2545 2546 /* i915_dma.c */ 2547 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2548 extern int i915_driver_unload(struct drm_device *); 2549 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2550 extern void i915_driver_lastclose(struct drm_device * dev); 2551 extern void i915_driver_preclose(struct drm_device *dev, 2552 struct drm_file *file); 2553 extern void i915_driver_postclose(struct drm_device *dev, 2554 struct drm_file *file); 2555 extern int i915_driver_device_is_agp(struct drm_device * dev); 2556 #ifdef CONFIG_COMPAT 2557 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2558 unsigned long arg); 2559 #endif 2560 extern int intel_gpu_reset(struct drm_device *dev); 2561 extern int i915_reset(struct drm_device *dev); 2562 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2563 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2564 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2565 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2566 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2567 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2568 2569 /* i915_irq.c */ 2570 void i915_queue_hangcheck(struct drm_device *dev); 2571 __printf(3, 4) 2572 void i915_handle_error(struct drm_device *dev, bool wedged, 2573 const char *fmt, ...); 2574 2575 extern void intel_irq_init(struct drm_i915_private *dev_priv); 2576 extern void intel_hpd_init(struct drm_i915_private *dev_priv); 2577 int intel_irq_install(struct drm_i915_private *dev_priv); 2578 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 2579 2580 extern void intel_uncore_sanitize(struct drm_device *dev); 2581 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2582 bool restore_forcewake); 2583 extern void intel_uncore_init(struct drm_device *dev); 2584 extern void intel_uncore_check_errors(struct drm_device *dev); 2585 extern void intel_uncore_fini(struct drm_device *dev); 2586 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); 2587 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); 2588 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 2589 enum forcewake_domains domains); 2590 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 2591 enum forcewake_domains domains); 2592 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); 2593 2594 void 2595 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2596 u32 status_mask); 2597 2598 void 2599 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2600 u32 status_mask); 2601 2602 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2603 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2604 void 2605 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2606 void 2607 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2608 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 2609 uint32_t interrupt_mask, 2610 uint32_t enabled_irq_mask); 2611 #define ibx_enable_display_interrupt(dev_priv, bits) \ 2612 ibx_display_interrupt_update((dev_priv), (bits), (bits)) 2613 #define ibx_disable_display_interrupt(dev_priv, bits) \ 2614 ibx_display_interrupt_update((dev_priv), (bits), 0) 2615 2616 /* i915_gem.c */ 2617 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2618 struct drm_file *file_priv); 2619 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2620 struct drm_file *file_priv); 2621 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2622 struct drm_file *file_priv); 2623 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2624 struct drm_file *file_priv); 2625 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2626 struct drm_file *file_priv); 2627 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2628 struct drm_file *file_priv); 2629 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2630 struct drm_file *file_priv); 2631 void i915_gem_execbuffer_move_to_active(struct list_head *vmas, 2632 struct intel_engine_cs *ring); 2633 void i915_gem_execbuffer_retire_commands(struct drm_device *dev, 2634 struct drm_file *file, 2635 struct intel_engine_cs *ring, 2636 struct drm_i915_gem_object *obj); 2637 int i915_gem_ringbuffer_submission(struct drm_device *dev, 2638 struct drm_file *file, 2639 struct intel_engine_cs *ring, 2640 struct intel_context *ctx, 2641 struct drm_i915_gem_execbuffer2 *args, 2642 struct list_head *vmas, 2643 struct drm_i915_gem_object *batch_obj, 2644 u64 exec_start, u32 flags); 2645 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2646 struct drm_file *file_priv); 2647 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2648 struct drm_file *file_priv); 2649 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2650 struct drm_file *file_priv); 2651 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2652 struct drm_file *file); 2653 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2654 struct drm_file *file); 2655 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2656 struct drm_file *file_priv); 2657 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2658 struct drm_file *file_priv); 2659 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2660 struct drm_file *file_priv); 2661 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2662 struct drm_file *file_priv); 2663 int i915_gem_init_userptr(struct drm_device *dev); 2664 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2665 struct drm_file *file); 2666 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2667 struct drm_file *file_priv); 2668 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2669 struct drm_file *file_priv); 2670 void i915_gem_load(struct drm_device *dev); 2671 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 2672 long target, 2673 unsigned flags); 2674 #define I915_SHRINK_PURGEABLE 0x1 2675 #define I915_SHRINK_UNBOUND 0x2 2676 #define I915_SHRINK_BOUND 0x4 2677 void *i915_gem_object_alloc(struct drm_device *dev); 2678 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2679 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2680 const struct drm_i915_gem_object_ops *ops); 2681 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2682 size_t size); 2683 void i915_init_vm(struct drm_i915_private *dev_priv, 2684 struct i915_address_space *vm); 2685 void i915_gem_free_object(struct drm_gem_object *obj); 2686 void i915_gem_vma_destroy(struct i915_vma *vma); 2687 2688 #define PIN_MAPPABLE 0x1 2689 #define PIN_NONBLOCK 0x2 2690 #define PIN_GLOBAL 0x4 2691 #define PIN_OFFSET_BIAS 0x8 2692 #define PIN_OFFSET_MASK (~4095) 2693 int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj, 2694 struct i915_address_space *vm, 2695 uint32_t alignment, 2696 uint64_t flags, 2697 const struct i915_ggtt_view *view); 2698 static inline 2699 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2700 struct i915_address_space *vm, 2701 uint32_t alignment, 2702 uint64_t flags) 2703 { 2704 return i915_gem_object_pin_view(obj, vm, alignment, flags, 2705 &i915_ggtt_view_normal); 2706 } 2707 2708 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 2709 u32 flags); 2710 int __must_check i915_vma_unbind(struct i915_vma *vma); 2711 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2712 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2713 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2714 2715 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2716 int *needs_clflush); 2717 2718 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2719 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2720 { 2721 struct sg_page_iter sg_iter; 2722 2723 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 2724 return sg_page_iter_page(&sg_iter); 2725 2726 return NULL; 2727 } 2728 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2729 { 2730 BUG_ON(obj->pages == NULL); 2731 obj->pages_pin_count++; 2732 } 2733 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2734 { 2735 BUG_ON(obj->pages_pin_count == 0); 2736 obj->pages_pin_count--; 2737 } 2738 2739 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2740 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2741 struct intel_engine_cs *to); 2742 void i915_vma_move_to_active(struct i915_vma *vma, 2743 struct intel_engine_cs *ring); 2744 int i915_gem_dumb_create(struct drm_file *file_priv, 2745 struct drm_device *dev, 2746 struct drm_mode_create_dumb *args); 2747 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2748 uint32_t handle, uint64_t *offset); 2749 /** 2750 * Returns true if seq1 is later than seq2. 2751 */ 2752 static inline bool 2753 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2754 { 2755 return (int32_t)(seq1 - seq2) >= 0; 2756 } 2757 2758 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, 2759 bool lazy_coherency) 2760 { 2761 u32 seqno; 2762 2763 BUG_ON(req == NULL); 2764 2765 seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2766 2767 return i915_seqno_passed(seqno, req->seqno); 2768 } 2769 2770 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2771 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2772 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2773 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2774 2775 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2776 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2777 2778 struct drm_i915_gem_request * 2779 i915_gem_find_active_request(struct intel_engine_cs *ring); 2780 2781 bool i915_gem_retire_requests(struct drm_device *dev); 2782 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2783 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2784 bool interruptible); 2785 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); 2786 2787 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2788 { 2789 return unlikely(atomic_read(&error->reset_counter) 2790 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2791 } 2792 2793 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2794 { 2795 return atomic_read(&error->reset_counter) & I915_WEDGED; 2796 } 2797 2798 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2799 { 2800 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2801 } 2802 2803 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2804 { 2805 return dev_priv->gpu_error.stop_rings == 0 || 2806 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2807 } 2808 2809 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2810 { 2811 return dev_priv->gpu_error.stop_rings == 0 || 2812 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2813 } 2814 2815 void i915_gem_reset(struct drm_device *dev); 2816 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2817 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2818 int __must_check i915_gem_init(struct drm_device *dev); 2819 int i915_gem_init_rings(struct drm_device *dev); 2820 int __must_check i915_gem_init_hw(struct drm_device *dev); 2821 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2822 void i915_gem_init_swizzling(struct drm_device *dev); 2823 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2824 int __must_check i915_gpu_idle(struct drm_device *dev); 2825 int __must_check i915_gem_suspend(struct drm_device *dev); 2826 int __i915_add_request(struct intel_engine_cs *ring, 2827 struct drm_file *file, 2828 struct drm_i915_gem_object *batch_obj); 2829 #define i915_add_request(ring) \ 2830 __i915_add_request(ring, NULL, NULL) 2831 int __i915_wait_request(struct drm_i915_gem_request *req, 2832 unsigned reset_counter, 2833 bool interruptible, 2834 s64 *timeout, 2835 struct drm_i915_file_private *file_priv); 2836 int __must_check i915_wait_request(struct drm_i915_gem_request *req); 2837 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 2838 int __must_check 2839 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2840 bool write); 2841 int __must_check 2842 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2843 int __must_check 2844 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2845 u32 alignment, 2846 struct intel_engine_cs *pipelined); 2847 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2848 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2849 int align); 2850 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2851 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2852 2853 uint32_t 2854 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2855 uint32_t 2856 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2857 int tiling_mode, bool fenced); 2858 2859 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2860 enum i915_cache_level cache_level); 2861 2862 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2863 struct dma_buf *dma_buf); 2864 2865 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2866 struct drm_gem_object *gem_obj, int flags); 2867 2868 void i915_gem_restore_fences(struct drm_device *dev); 2869 2870 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o, 2871 struct i915_address_space *vm, 2872 enum i915_ggtt_view_type view); 2873 static inline 2874 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2875 struct i915_address_space *vm) 2876 { 2877 return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL); 2878 } 2879 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2880 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o, 2881 struct i915_address_space *vm, 2882 enum i915_ggtt_view_type view); 2883 static inline 2884 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2885 struct i915_address_space *vm) 2886 { 2887 return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL); 2888 } 2889 2890 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2891 struct i915_address_space *vm); 2892 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj, 2893 struct i915_address_space *vm, 2894 const struct i915_ggtt_view *view); 2895 static inline 2896 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2897 struct i915_address_space *vm) 2898 { 2899 return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal); 2900 } 2901 2902 struct i915_vma * 2903 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj, 2904 struct i915_address_space *vm, 2905 const struct i915_ggtt_view *view); 2906 2907 static inline 2908 struct i915_vma * 2909 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2910 struct i915_address_space *vm) 2911 { 2912 return i915_gem_obj_lookup_or_create_vma_view(obj, vm, 2913 &i915_ggtt_view_normal); 2914 } 2915 2916 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2917 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { 2918 struct i915_vma *vma; 2919 list_for_each_entry(vma, &obj->vma_list, vma_link) 2920 if (vma->pin_count > 0) 2921 return true; 2922 return false; 2923 } 2924 2925 /* Some GGTT VM helpers */ 2926 #define i915_obj_to_ggtt(obj) \ 2927 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2928 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2929 { 2930 struct i915_address_space *ggtt = 2931 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2932 return vm == ggtt; 2933 } 2934 2935 static inline struct i915_hw_ppgtt * 2936 i915_vm_to_ppgtt(struct i915_address_space *vm) 2937 { 2938 WARN_ON(i915_is_ggtt(vm)); 2939 2940 return container_of(vm, struct i915_hw_ppgtt, base); 2941 } 2942 2943 2944 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2945 { 2946 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); 2947 } 2948 2949 static inline unsigned long 2950 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2951 { 2952 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); 2953 } 2954 2955 static inline unsigned long 2956 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2957 { 2958 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); 2959 } 2960 2961 static inline int __must_check 2962 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2963 uint32_t alignment, 2964 unsigned flags) 2965 { 2966 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), 2967 alignment, flags | PIN_GLOBAL); 2968 } 2969 2970 static inline int 2971 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2972 { 2973 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 2974 } 2975 2976 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); 2977 2978 /* i915_gem_context.c */ 2979 int __must_check i915_gem_context_init(struct drm_device *dev); 2980 void i915_gem_context_fini(struct drm_device *dev); 2981 void i915_gem_context_reset(struct drm_device *dev); 2982 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 2983 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 2984 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2985 int i915_switch_context(struct intel_engine_cs *ring, 2986 struct intel_context *to); 2987 struct intel_context * 2988 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 2989 void i915_gem_context_free(struct kref *ctx_ref); 2990 struct drm_i915_gem_object * 2991 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); 2992 static inline void i915_gem_context_reference(struct intel_context *ctx) 2993 { 2994 kref_get(&ctx->ref); 2995 } 2996 2997 static inline void i915_gem_context_unreference(struct intel_context *ctx) 2998 { 2999 kref_put(&ctx->ref, i915_gem_context_free); 3000 } 3001 3002 static inline bool i915_gem_context_is_default(const struct intel_context *c) 3003 { 3004 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 3005 } 3006 3007 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 3008 struct drm_file *file); 3009 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 3010 struct drm_file *file); 3011 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 3012 struct drm_file *file_priv); 3013 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 3014 struct drm_file *file_priv); 3015 3016 /* i915_gem_evict.c */ 3017 int __must_check i915_gem_evict_something(struct drm_device *dev, 3018 struct i915_address_space *vm, 3019 int min_size, 3020 unsigned alignment, 3021 unsigned cache_level, 3022 unsigned long start, 3023 unsigned long end, 3024 unsigned flags); 3025 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 3026 int i915_gem_evict_everything(struct drm_device *dev); 3027 3028 /* belongs in i915_gem_gtt.h */ 3029 static inline void i915_gem_chipset_flush(struct drm_device *dev) 3030 { 3031 if (INTEL_INFO(dev)->gen < 6) 3032 intel_gtt_chipset_flush(); 3033 } 3034 3035 /* i915_gem_stolen.c */ 3036 int i915_gem_init_stolen(struct drm_device *dev); 3037 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); 3038 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 3039 void i915_gem_cleanup_stolen(struct drm_device *dev); 3040 struct drm_i915_gem_object * 3041 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 3042 struct drm_i915_gem_object * 3043 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 3044 u32 stolen_offset, 3045 u32 gtt_offset, 3046 u32 size); 3047 3048 /* i915_gem_tiling.c */ 3049 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 3050 { 3051 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 3052 3053 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 3054 obj->tiling_mode != I915_TILING_NONE; 3055 } 3056 3057 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 3058 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 3059 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 3060 3061 /* i915_gem_debug.c */ 3062 #if WATCH_LISTS 3063 int i915_verify_lists(struct drm_device *dev); 3064 #else 3065 #define i915_verify_lists(dev) 0 3066 #endif 3067 3068 /* i915_debugfs.c */ 3069 int i915_debugfs_init(struct drm_minor *minor); 3070 void i915_debugfs_cleanup(struct drm_minor *minor); 3071 #ifdef CONFIG_DEBUG_FS 3072 void intel_display_crc_init(struct drm_device *dev); 3073 #else 3074 static inline void intel_display_crc_init(struct drm_device *dev) {} 3075 #endif 3076 3077 /* i915_gpu_error.c */ 3078 __printf(2, 3) 3079 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 3080 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 3081 const struct i915_error_state_file_priv *error); 3082 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 3083 struct drm_i915_private *i915, 3084 size_t count, loff_t pos); 3085 static inline void i915_error_state_buf_release( 3086 struct drm_i915_error_state_buf *eb) 3087 { 3088 kfree(eb->buf); 3089 } 3090 void i915_capture_error_state(struct drm_device *dev, bool wedge, 3091 const char *error_msg); 3092 void i915_error_state_get(struct drm_device *dev, 3093 struct i915_error_state_file_priv *error_priv); 3094 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 3095 void i915_destroy_error_state(struct drm_device *dev); 3096 3097 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 3098 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 3099 3100 /* i915_gem_batch_pool.c */ 3101 void i915_gem_batch_pool_init(struct drm_device *dev, 3102 struct i915_gem_batch_pool *pool); 3103 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool); 3104 struct drm_i915_gem_object* 3105 i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size); 3106 3107 /* i915_cmd_parser.c */ 3108 int i915_cmd_parser_get_version(void); 3109 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 3110 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 3111 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 3112 int i915_parse_cmds(struct intel_engine_cs *ring, 3113 struct drm_i915_gem_object *batch_obj, 3114 struct drm_i915_gem_object *shadow_batch_obj, 3115 u32 batch_start_offset, 3116 u32 batch_len, 3117 bool is_master); 3118 3119 /* i915_suspend.c */ 3120 extern int i915_save_state(struct drm_device *dev); 3121 extern int i915_restore_state(struct drm_device *dev); 3122 3123 /* i915_ums.c */ 3124 void i915_save_display_reg(struct drm_device *dev); 3125 void i915_restore_display_reg(struct drm_device *dev); 3126 3127 /* i915_sysfs.c */ 3128 void i915_setup_sysfs(struct drm_device *dev_priv); 3129 void i915_teardown_sysfs(struct drm_device *dev_priv); 3130 3131 /* intel_i2c.c */ 3132 extern int intel_setup_gmbus(struct drm_device *dev); 3133 extern void intel_teardown_gmbus(struct drm_device *dev); 3134 static inline bool intel_gmbus_is_port_valid(unsigned port) 3135 { 3136 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 3137 } 3138 3139 extern struct i2c_adapter *intel_gmbus_get_adapter( 3140 struct drm_i915_private *dev_priv, unsigned port); 3141 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 3142 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 3143 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 3144 { 3145 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 3146 } 3147 extern void intel_i2c_reset(struct drm_device *dev); 3148 3149 /* intel_opregion.c */ 3150 #ifdef CONFIG_ACPI 3151 extern int intel_opregion_setup(struct drm_device *dev); 3152 extern void intel_opregion_init(struct drm_device *dev); 3153 extern void intel_opregion_fini(struct drm_device *dev); 3154 extern void intel_opregion_asle_intr(struct drm_device *dev); 3155 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 3156 bool enable); 3157 extern int intel_opregion_notify_adapter(struct drm_device *dev, 3158 pci_power_t state); 3159 #else 3160 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 3161 static inline void intel_opregion_init(struct drm_device *dev) { return; } 3162 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 3163 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 3164 static inline int 3165 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 3166 { 3167 return 0; 3168 } 3169 static inline int 3170 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 3171 { 3172 return 0; 3173 } 3174 #endif 3175 3176 /* intel_acpi.c */ 3177 #ifdef CONFIG_ACPI 3178 extern void intel_register_dsm_handler(void); 3179 extern void intel_unregister_dsm_handler(void); 3180 #else 3181 static inline void intel_register_dsm_handler(void) { return; } 3182 static inline void intel_unregister_dsm_handler(void) { return; } 3183 #endif /* CONFIG_ACPI */ 3184 3185 /* modesetting */ 3186 extern void intel_modeset_init_hw(struct drm_device *dev); 3187 extern void intel_modeset_init(struct drm_device *dev); 3188 extern void intel_modeset_gem_init(struct drm_device *dev); 3189 extern void intel_modeset_cleanup(struct drm_device *dev); 3190 extern void intel_connector_unregister(struct intel_connector *); 3191 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 3192 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 3193 bool force_restore); 3194 extern void i915_redisable_vga(struct drm_device *dev); 3195 extern void i915_redisable_vga_power_on(struct drm_device *dev); 3196 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 3197 extern void intel_init_pch_refclk(struct drm_device *dev); 3198 extern void gen6_set_rps(struct drm_device *dev, u8 val); 3199 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 3200 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 3201 bool enable); 3202 extern void intel_detect_pch(struct drm_device *dev); 3203 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 3204 extern int intel_enable_rc6(const struct drm_device *dev); 3205 3206 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 3207 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 3208 struct drm_file *file); 3209 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 3210 struct drm_file *file); 3211 3212 void intel_notify_mmio_flip(struct intel_engine_cs *ring); 3213 3214 /* overlay */ 3215 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 3216 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 3217 struct intel_overlay_error_state *error); 3218 3219 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 3220 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 3221 struct drm_device *dev, 3222 struct intel_display_error_state *error); 3223 3224 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3225 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 3226 3227 /* intel_sideband.c */ 3228 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); 3229 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); 3230 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 3231 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 3232 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3233 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 3234 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3235 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 3236 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3237 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 3238 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3239 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 3240 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3241 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 3242 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 3243 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 3244 enum intel_sbi_destination destination); 3245 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 3246 enum intel_sbi_destination destination); 3247 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 3248 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3249 3250 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); 3251 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 3252 3253 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 3254 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 3255 3256 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 3257 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 3258 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 3259 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 3260 3261 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 3262 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 3263 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 3264 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 3265 3266 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 3267 * will be implemented using 2 32-bit writes in an arbitrary order with 3268 * an arbitrary delay between them. This can cause the hardware to 3269 * act upon the intermediate value, possibly leading to corruption and 3270 * machine death. You have been warned. 3271 */ 3272 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 3273 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 3274 3275 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 3276 u32 upper = I915_READ(upper_reg); \ 3277 u32 lower = I915_READ(lower_reg); \ 3278 u32 tmp = I915_READ(upper_reg); \ 3279 if (upper != tmp) { \ 3280 upper = tmp; \ 3281 lower = I915_READ(lower_reg); \ 3282 WARN_ON(I915_READ(upper_reg) != upper); \ 3283 } \ 3284 (u64)upper << 32 | lower; }) 3285 3286 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 3287 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 3288 3289 /* "Broadcast RGB" property */ 3290 #define INTEL_BROADCAST_RGB_AUTO 0 3291 #define INTEL_BROADCAST_RGB_FULL 1 3292 #define INTEL_BROADCAST_RGB_LIMITED 2 3293 3294 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 3295 { 3296 if (IS_VALLEYVIEW(dev)) 3297 return VLV_VGACNTRL; 3298 else if (INTEL_INFO(dev)->gen >= 5) 3299 return CPU_VGACNTRL; 3300 else 3301 return VGACNTRL; 3302 } 3303 3304 static inline void __user *to_user_ptr(u64 address) 3305 { 3306 return (void __user *)(uintptr_t)address; 3307 } 3308 3309 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 3310 { 3311 unsigned long j = msecs_to_jiffies(m); 3312 3313 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3314 } 3315 3316 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 3317 { 3318 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 3319 } 3320 3321 static inline unsigned long 3322 timespec_to_jiffies_timeout(const struct timespec *value) 3323 { 3324 unsigned long j = timespec_to_jiffies(value); 3325 3326 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3327 } 3328 3329 /* 3330 * If you need to wait X milliseconds between events A and B, but event B 3331 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 3332 * when event A happened, then just before event B you call this function and 3333 * pass the timestamp as the first argument, and X as the second argument. 3334 */ 3335 static inline void 3336 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 3337 { 3338 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 3339 3340 /* 3341 * Don't re-read the value of "jiffies" every time since it may change 3342 * behind our back and break the math. 3343 */ 3344 tmp_jiffies = jiffies; 3345 target_jiffies = timestamp_jiffies + 3346 msecs_to_jiffies_timeout(to_wait_ms); 3347 3348 if (time_after(target_jiffies, tmp_jiffies)) { 3349 remaining_jiffies = target_jiffies - tmp_jiffies; 3350 while (remaining_jiffies) 3351 remaining_jiffies = 3352 schedule_timeout_uninterruptible(remaining_jiffies); 3353 } 3354 } 3355 3356 static inline void i915_trace_irq_get(struct intel_engine_cs *ring, 3357 struct drm_i915_gem_request *req) 3358 { 3359 if (ring->trace_irq_req == NULL && ring->irq_get(ring)) 3360 i915_gem_request_assign(&ring->trace_irq_req, req); 3361 } 3362 3363 #endif 3364