1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pm_qos.h> 36 37 #include <drm/ttm/ttm_device.h> 38 39 #include "display/intel_display_limits.h" 40 #include "display/intel_display_core.h" 41 42 #include "gem/i915_gem_context_types.h" 43 #include "gem/i915_gem_shrinker.h" 44 #include "gem/i915_gem_stolen.h" 45 46 #include "gt/intel_engine.h" 47 #include "gt/intel_gt_types.h" 48 #include "gt/intel_region_lmem.h" 49 #include "gt/intel_workarounds.h" 50 #include "gt/uc/intel_uc.h" 51 52 #include "soc/intel_pch.h" 53 54 #include "i915_drm_client.h" 55 #include "i915_gem.h" 56 #include "i915_gpu_error.h" 57 #include "i915_params.h" 58 #include "i915_perf_types.h" 59 #include "i915_scheduler.h" 60 #include "i915_utils.h" 61 #include "intel_device_info.h" 62 #include "intel_memory_region.h" 63 #include "intel_runtime_pm.h" 64 #include "intel_step.h" 65 #include "intel_uncore.h" 66 67 struct drm_i915_clock_gating_funcs; 68 struct vlv_s0ix_state; 69 struct intel_pxp; 70 71 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 72 73 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 74 struct i915_dsm { 75 /* 76 * The start and end of DSM which we can optionally use to create GEM 77 * objects backed by stolen memory. 78 * 79 * Note that usable_size tells us exactly how much of this we are 80 * actually allowed to use, given that some portion of it is in fact 81 * reserved for use by hardware functions. 82 */ 83 struct resource stolen; 84 85 /* 86 * Reserved portion of DSM. 87 */ 88 struct resource reserved; 89 90 /* 91 * Total size minus reserved ranges. 92 * 93 * DSM is segmented in hardware with different portions offlimits to 94 * certain functions. 95 * 96 * The drm_mm is initialised to the total accessible range, as found 97 * from the PCI config. On Broadwell+, this is further restricted to 98 * avoid the first page! The upper end of DSM is reserved for hardware 99 * functions and similarly removed from the accessible range. 100 */ 101 resource_size_t usable_size; 102 }; 103 104 struct i915_suspend_saved_registers { 105 u32 saveDSPARB; 106 u32 saveSWF0[16]; 107 u32 saveSWF1[16]; 108 u32 saveSWF3[3]; 109 u16 saveGCDGMBUS; 110 }; 111 112 #define MAX_L3_SLICES 2 113 struct intel_l3_parity { 114 u32 *remap_info[MAX_L3_SLICES]; 115 struct work_struct error_work; 116 int which_slice; 117 }; 118 119 struct i915_gem_mm { 120 /* 121 * Shortcut for the stolen region. This points to either 122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 124 * support stolen. 125 */ 126 struct intel_memory_region *stolen_region; 127 /** Memory allocator for GTT stolen memory */ 128 struct drm_mm stolen; 129 /** Protects the usage of the GTT stolen memory allocator. This is 130 * always the inner lock when overlapping with struct_mutex. */ 131 struct mutex stolen_lock; 132 133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 134 spinlock_t obj_lock; 135 136 /** 137 * List of objects which are purgeable. 138 */ 139 struct list_head purge_list; 140 141 /** 142 * List of objects which have allocated pages and are shrinkable. 143 */ 144 struct list_head shrink_list; 145 146 /** 147 * List of objects which are pending destruction. 148 */ 149 struct llist_head free_list; 150 struct work_struct free_work; 151 /** 152 * Count of objects pending destructions. Used to skip needlessly 153 * waiting on an RCU barrier if no objects are waiting to be freed. 154 */ 155 atomic_t free_count; 156 157 /** 158 * tmpfs instance used for shmem backed objects 159 */ 160 struct vfsmount *gemfs; 161 162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 163 164 struct notifier_block oom_notifier; 165 struct notifier_block vmap_notifier; 166 struct shrinker shrinker; 167 168 #ifdef CONFIG_MMU_NOTIFIER 169 /** 170 * notifier_lock for mmu notifiers, memory may not be allocated 171 * while holding this lock. 172 */ 173 rwlock_t notifier_lock; 174 #endif 175 176 /* shrinker accounting, also useful for userland debugging */ 177 u64 shrink_memory; 178 u32 shrink_count; 179 }; 180 181 struct i915_virtual_gpu { 182 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 183 bool active; 184 u32 caps; 185 u32 *initial_mmio; 186 u8 *initial_cfg_space; 187 struct list_head entry; 188 }; 189 190 struct i915_selftest_stash { 191 atomic_t counter; 192 struct ida mock_region_instances; 193 }; 194 195 struct drm_i915_private { 196 struct drm_device drm; 197 198 struct intel_display display; 199 200 /* FIXME: Device release actions should all be moved to drmm_ */ 201 bool do_release; 202 203 /* i915 device parameters */ 204 struct i915_params params; 205 206 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 207 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 208 struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */ 209 struct intel_driver_caps caps; 210 211 struct i915_dsm dsm; 212 213 struct intel_uncore uncore; 214 struct intel_uncore_mmio_debug mmio_debug; 215 216 struct i915_virtual_gpu vgpu; 217 218 struct intel_gvt *gvt; 219 220 struct { 221 struct pci_dev *pdev; 222 struct resource mch_res; 223 bool mchbar_need_disable; 224 } gmch; 225 226 struct rb_root uabi_engines; 227 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 228 229 /* protects the irq masks */ 230 spinlock_t irq_lock; 231 232 bool display_irqs_enabled; 233 234 /* Sideband mailbox protection */ 235 struct mutex sb_lock; 236 struct pm_qos_request sb_qos; 237 238 /** Cached value of IMR to avoid reads in updating the bitfield */ 239 union { 240 u32 irq_mask; 241 u32 de_irq_mask[I915_MAX_PIPES]; 242 }; 243 u32 pipestat_irq_mask[I915_MAX_PIPES]; 244 245 bool preserve_bios_swizzle; 246 247 unsigned int fsb_freq, mem_freq, is_ddr3; 248 unsigned int skl_preferred_vco_freq; 249 250 unsigned int max_dotclk_freq; 251 unsigned int hpll_freq; 252 unsigned int czclk_freq; 253 254 /** 255 * wq - Driver workqueue for GEM. 256 * 257 * NOTE: Work items scheduled here are not allowed to grab any modeset 258 * locks, for otherwise the flushing done in the pageflip code will 259 * result in deadlocks. 260 */ 261 struct workqueue_struct *wq; 262 263 /** 264 * unordered_wq - internal workqueue for unordered work 265 * 266 * This workqueue should be used for all unordered work 267 * scheduling within i915, which used to be scheduled on the 268 * system_wq before moving to a driver instance due 269 * deprecation of flush_scheduled_work(). 270 */ 271 struct workqueue_struct *unordered_wq; 272 273 /* pm private clock gating functions */ 274 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 275 276 /* PCH chipset type */ 277 enum intel_pch pch_type; 278 unsigned short pch_id; 279 280 unsigned long gem_quirks; 281 282 struct i915_gem_mm mm; 283 284 struct intel_l3_parity l3_parity; 285 286 /* 287 * edram size in MB. 288 * Cannot be determined by PCIID. You must always read a register. 289 */ 290 u32 edram_size_mb; 291 292 struct i915_gpu_error gpu_error; 293 294 u32 suspend_count; 295 struct i915_suspend_saved_registers regfile; 296 struct vlv_s0ix_state *vlv_s0ix_state; 297 298 struct dram_info { 299 bool wm_lv_0_adjust_needed; 300 u8 num_channels; 301 bool symmetric_memory; 302 enum intel_dram_type { 303 INTEL_DRAM_UNKNOWN, 304 INTEL_DRAM_DDR3, 305 INTEL_DRAM_DDR4, 306 INTEL_DRAM_LPDDR3, 307 INTEL_DRAM_LPDDR4, 308 INTEL_DRAM_DDR5, 309 INTEL_DRAM_LPDDR5, 310 } type; 311 u8 num_qgv_points; 312 u8 num_psf_gv_points; 313 } dram_info; 314 315 struct intel_runtime_pm runtime_pm; 316 317 struct i915_perf perf; 318 319 struct i915_hwmon *hwmon; 320 321 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 322 struct intel_gt gt0; 323 324 /* 325 * i915->gt[0] == &i915->gt0 326 */ 327 #define I915_MAX_GT 2 328 struct intel_gt *gt[I915_MAX_GT]; 329 330 struct kobject *sysfs_gt; 331 332 /* Quick lookup of media GT (current platforms only have one) */ 333 struct intel_gt *media_gt; 334 335 struct { 336 struct i915_gem_contexts { 337 spinlock_t lock; /* locks list */ 338 struct list_head list; 339 } contexts; 340 341 /* 342 * We replace the local file with a global mappings as the 343 * backing storage for the mmap is on the device and not 344 * on the struct file, and we do not want to prolong the 345 * lifetime of the local fd. To minimise the number of 346 * anonymous inodes we create, we use a global singleton to 347 * share the global mapping. 348 */ 349 struct file *mmap_singleton; 350 } gem; 351 352 struct intel_pxp *pxp; 353 354 /* For i915gm/i945gm vblank irq workaround */ 355 u8 vblank_enabled; 356 357 bool irq_enabled; 358 359 struct i915_pmu pmu; 360 361 /* The TTM device structure. */ 362 struct ttm_device bdev; 363 364 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 365 366 /* 367 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 368 * will be rejected. Instead look for a better place. 369 */ 370 }; 371 372 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 373 { 374 return container_of(dev, struct drm_i915_private, drm); 375 } 376 377 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 378 { 379 return dev_get_drvdata(kdev); 380 } 381 382 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 383 { 384 return pci_get_drvdata(pdev); 385 } 386 387 static inline struct intel_gt *to_gt(struct drm_i915_private *i915) 388 { 389 return &i915->gt0; 390 } 391 392 /* Simple iterator over all initialised engines */ 393 #define for_each_engine(engine__, gt__, id__) \ 394 for ((id__) = 0; \ 395 (id__) < I915_NUM_ENGINES; \ 396 (id__)++) \ 397 for_each_if ((engine__) = (gt__)->engine[(id__)]) 398 399 /* Iterator over subset of engines selected by mask */ 400 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 401 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 402 (tmp__) ? \ 403 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 404 0;) 405 406 #define rb_to_uabi_engine(rb) \ 407 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 408 409 #define for_each_uabi_engine(engine__, i915__) \ 410 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 411 (engine__); \ 412 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 413 414 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 415 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 416 (engine__) && (engine__)->uabi_class == (class__); \ 417 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 418 419 #define INTEL_INFO(i915) (&(i915)->__info) 420 #define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display) 421 #define RUNTIME_INFO(i915) (&(i915)->__runtime) 422 #define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime) 423 #define DRIVER_CAPS(i915) (&(i915)->caps) 424 425 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 426 427 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 428 429 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 430 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 431 RUNTIME_INFO(i915)->graphics.ip.rel) 432 #define IS_GRAPHICS_VER(i915, from, until) \ 433 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 434 435 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 436 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 437 RUNTIME_INFO(i915)->media.ip.rel) 438 #define IS_MEDIA_VER(i915, from, until) \ 439 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 440 441 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 442 #define IS_DISPLAY_VER(i915, from, until) \ 443 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 444 445 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 446 447 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 448 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 449 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 450 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 451 452 #define IS_DISPLAY_STEP(__i915, since, until) \ 453 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 454 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 455 456 #define IS_GRAPHICS_STEP(__i915, since, until) \ 457 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 458 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 459 460 #define IS_MEDIA_STEP(__i915, since, until) \ 461 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 462 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 463 464 #define IS_BASEDIE_STEP(__i915, since, until) \ 465 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 466 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 467 468 static __always_inline unsigned int 469 __platform_mask_index(const struct intel_runtime_info *info, 470 enum intel_platform p) 471 { 472 const unsigned int pbits = 473 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 474 475 /* Expand the platform_mask array if this fails. */ 476 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 477 pbits * ARRAY_SIZE(info->platform_mask)); 478 479 return p / pbits; 480 } 481 482 static __always_inline unsigned int 483 __platform_mask_bit(const struct intel_runtime_info *info, 484 enum intel_platform p) 485 { 486 const unsigned int pbits = 487 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 488 489 return p % pbits + INTEL_SUBPLATFORM_BITS; 490 } 491 492 static inline u32 493 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 494 { 495 const unsigned int pi = __platform_mask_index(info, p); 496 497 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 498 } 499 500 static __always_inline bool 501 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 502 { 503 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 504 const unsigned int pi = __platform_mask_index(info, p); 505 const unsigned int pb = __platform_mask_bit(info, p); 506 507 BUILD_BUG_ON(!__builtin_constant_p(p)); 508 509 return info->platform_mask[pi] & BIT(pb); 510 } 511 512 static __always_inline bool 513 IS_SUBPLATFORM(const struct drm_i915_private *i915, 514 enum intel_platform p, unsigned int s) 515 { 516 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 517 const unsigned int pi = __platform_mask_index(info, p); 518 const unsigned int pb = __platform_mask_bit(info, p); 519 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 520 const u32 mask = info->platform_mask[pi]; 521 522 BUILD_BUG_ON(!__builtin_constant_p(p)); 523 BUILD_BUG_ON(!__builtin_constant_p(s)); 524 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 525 526 /* Shift and test on the MSB position so sign flag can be used. */ 527 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 528 } 529 530 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 531 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 532 533 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 534 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 535 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 536 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 537 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 538 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 539 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 540 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 541 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 542 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 543 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 544 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 545 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 546 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 547 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 548 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 549 #define IS_IRONLAKE_M(i915) \ 550 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 551 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 552 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 553 #define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ 554 INTEL_INFO(i915)->gt == 1) 555 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 556 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 557 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 558 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 559 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 560 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 561 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 562 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 563 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 564 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 565 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 566 #define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \ 567 IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) 568 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 569 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 570 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 571 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 572 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 573 #define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV) 574 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 575 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) 576 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 577 578 #define IS_METEORLAKE_M(i915) \ 579 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) 580 #define IS_METEORLAKE_P(i915) \ 581 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) 582 #define IS_DG2_G10(i915) \ 583 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 584 #define IS_DG2_G11(i915) \ 585 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 586 #define IS_DG2_G12(i915) \ 587 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 588 #define IS_ADLS_RPLS(i915) \ 589 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 590 #define IS_ADLP_N(i915) \ 591 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 592 #define IS_ADLP_RPLP(i915) \ 593 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 594 #define IS_ADLP_RPLU(i915) \ 595 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 596 #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 597 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 598 #define IS_BDW_ULT(i915) \ 599 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 600 #define IS_BDW_ULX(i915) \ 601 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 602 #define IS_BDW_GT3(i915) (IS_BROADWELL(i915) && \ 603 INTEL_INFO(i915)->gt == 3) 604 #define IS_HSW_ULT(i915) \ 605 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 606 #define IS_HSW_GT3(i915) (IS_HASWELL(i915) && \ 607 INTEL_INFO(i915)->gt == 3) 608 #define IS_HSW_GT1(i915) (IS_HASWELL(i915) && \ 609 INTEL_INFO(i915)->gt == 1) 610 /* ULX machines are also considered ULT. */ 611 #define IS_HSW_ULX(i915) \ 612 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 613 #define IS_SKL_ULT(i915) \ 614 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 615 #define IS_SKL_ULX(i915) \ 616 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 617 #define IS_KBL_ULT(i915) \ 618 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 619 #define IS_KBL_ULX(i915) \ 620 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 621 #define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \ 622 INTEL_INFO(i915)->gt == 2) 623 #define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \ 624 INTEL_INFO(i915)->gt == 3) 625 #define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \ 626 INTEL_INFO(i915)->gt == 4) 627 #define IS_KBL_GT2(i915) (IS_KABYLAKE(i915) && \ 628 INTEL_INFO(i915)->gt == 2) 629 #define IS_KBL_GT3(i915) (IS_KABYLAKE(i915) && \ 630 INTEL_INFO(i915)->gt == 3) 631 #define IS_CFL_ULT(i915) \ 632 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 633 #define IS_CFL_ULX(i915) \ 634 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 635 #define IS_CFL_GT2(i915) (IS_COFFEELAKE(i915) && \ 636 INTEL_INFO(i915)->gt == 2) 637 #define IS_CFL_GT3(i915) (IS_COFFEELAKE(i915) && \ 638 INTEL_INFO(i915)->gt == 3) 639 640 #define IS_CML_ULT(i915) \ 641 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 642 #define IS_CML_ULX(i915) \ 643 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 644 #define IS_CML_GT2(i915) (IS_COMETLAKE(i915) && \ 645 INTEL_INFO(i915)->gt == 2) 646 647 #define IS_ICL_WITH_PORT_F(i915) \ 648 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 649 650 #define IS_TGL_UY(i915) \ 651 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 652 653 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) 654 655 #define IS_KBL_GRAPHICS_STEP(i915, since, until) \ 656 (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) 657 #define IS_KBL_DISPLAY_STEP(i915, since, until) \ 658 (IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until)) 659 660 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \ 661 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) 662 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ 663 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until)) 664 665 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ 666 (IS_TIGERLAKE(__i915) && \ 667 IS_DISPLAY_STEP(__i915, since, until)) 668 669 #define IS_RKL_DISPLAY_STEP(p, since, until) \ 670 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) 671 672 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ 673 (IS_ALDERLAKE_S(__i915) && \ 674 IS_DISPLAY_STEP(__i915, since, until)) 675 676 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \ 677 (IS_ALDERLAKE_S(__i915) && \ 678 IS_GRAPHICS_STEP(__i915, since, until)) 679 680 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ 681 (IS_ALDERLAKE_P(__i915) && \ 682 IS_DISPLAY_STEP(__i915, since, until)) 683 684 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ 685 (IS_ALDERLAKE_P(__i915) && \ 686 IS_GRAPHICS_STEP(__i915, since, until)) 687 688 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ 689 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) 690 691 #define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \ 692 (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \ 693 IS_GRAPHICS_STEP(__i915, since, until)) 694 695 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \ 696 (IS_METEORLAKE(__i915) && \ 697 IS_DISPLAY_STEP(__i915, since, until)) 698 699 #define IS_MTL_MEDIA_STEP(__i915, since, until) \ 700 (IS_METEORLAKE(__i915) && \ 701 IS_MEDIA_STEP(__i915, since, until)) 702 703 /* 704 * DG2 hardware steppings are a bit unusual. The hardware design was forked to 705 * create three variants (G10, G11, and G12) which each have distinct 706 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT 707 * stepping back to "A0" for their first iterations, even though they're more 708 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of 709 * functionality and workarounds. However the display stepping does not reset 710 * in the same manner --- a specific stepping like "B0" has a consistent 711 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. 712 * 713 * TLDR: All GT workarounds and stepping-specific logic must be applied in 714 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds 715 * and stepping-specific logic will be applied with a general DG2-wide stepping 716 * number. 717 */ 718 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \ 719 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ 720 IS_GRAPHICS_STEP(__i915, since, until)) 721 722 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \ 723 (IS_DG2(__i915) && \ 724 IS_DISPLAY_STEP(__i915, since, until)) 725 726 #define IS_PVC_BD_STEP(__i915, since, until) \ 727 (IS_PONTEVECCHIO(__i915) && \ 728 IS_BASEDIE_STEP(__i915, since, until)) 729 730 #define IS_PVC_CT_STEP(__i915, since, until) \ 731 (IS_PONTEVECCHIO(__i915) && \ 732 IS_GRAPHICS_STEP(__i915, since, until)) 733 734 #define IS_LP(i915) (INTEL_INFO(i915)->is_lp) 735 #define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) 736 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) 737 738 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 739 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 740 741 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ 742 unsigned int first__ = (first); \ 743 unsigned int count__ = (count); \ 744 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ 745 }) 746 747 #define ENGINE_INSTANCES_MASK(gt, first, count) \ 748 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) 749 750 #define RCS_MASK(gt) \ 751 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 752 #define BCS_MASK(gt) \ 753 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 754 #define VDBOX_MASK(gt) \ 755 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 756 #define VEBOX_MASK(gt) \ 757 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 758 #define CCS_MASK(gt) \ 759 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 760 761 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 762 763 /* 764 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 765 * All later gens can run the final buffer from the ppgtt 766 */ 767 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 768 769 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 770 #define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile) 771 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 772 #define HAS_EDRAM(i915) ((i915)->edram_size_mb) 773 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 774 #define HAS_WT(i915) HAS_EDRAM(i915) 775 776 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 777 778 #define HAS_LOGICAL_RING_CONTEXTS(i915) \ 779 (INTEL_INFO(i915)->has_logical_ring_contexts) 780 #define HAS_LOGICAL_RING_ELSQ(i915) \ 781 (INTEL_INFO(i915)->has_logical_ring_elsq) 782 783 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 784 785 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 786 #define HAS_PPGTT(i915) \ 787 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 788 #define HAS_FULL_PPGTT(i915) \ 789 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 790 791 #define HAS_PAGE_SIZES(i915, sizes) ({ \ 792 GEM_BUG_ON((sizes) == 0); \ 793 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 794 }) 795 796 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 797 #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) 798 799 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 800 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 801 802 /* WaRsDisableCoarsePowerGating:skl,cnl */ 803 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 804 (IS_SKL_GT3(i915) || IS_SKL_GT4(i915)) 805 806 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 807 * rows, which changed the alignment requirements and fence programming. 808 */ 809 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 810 !(IS_I915G(i915) || IS_I915GM(i915))) 811 812 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 813 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 814 #define HAS_RC6pp(i915) (false) /* HW was never validated */ 815 816 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 817 818 #define HAS_HECI_PXP(i915) \ 819 (INTEL_INFO(i915)->has_heci_pxp) 820 821 #define HAS_HECI_GSCFI(i915) \ 822 (INTEL_INFO(i915)->has_heci_gscfi) 823 824 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 825 826 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 827 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 828 829 #define HAS_OA_BPC_REPORTING(i915) \ 830 (INTEL_INFO(i915)->has_oa_bpc_reporting) 831 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 832 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 833 #define HAS_OAM(i915) \ 834 (INTEL_INFO(i915)->has_oam) 835 836 /* 837 * Set this flag, when platform requires 64K GTT page sizes or larger for 838 * device local memory access. 839 */ 840 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 841 842 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i)) 843 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 844 845 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 846 847 /* 848 * Platform has the dedicated compression control state for each lmem surfaces 849 * stored in lmem to support the 3D and media compression formats. 850 */ 851 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 852 853 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 854 855 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 856 857 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 858 859 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 860 861 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 862 863 /* DPF == dynamic parity feature */ 864 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 865 #define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \ 866 2 : HAS_L3_DPF(i915)) 867 868 /* Only valid when HAS_DISPLAY() is true */ 869 #define INTEL_DISPLAY_ENABLED(i915) \ 870 (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ 871 !(i915)->params.disable_display && \ 872 !intel_opregion_headless_sku(i915)) 873 874 #define HAS_GUC_DEPRIVILEGE(i915) \ 875 (INTEL_INFO(i915)->has_guc_deprivilege) 876 877 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 878 879 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 880 881 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 882 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 883 884 #endif 885