1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <drm/intel-gtt.h> 42 #include <linux/backlight.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/pm_qos.h> 46 47 /* General customization: 48 */ 49 50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 51 52 #define DRIVER_NAME "i915" 53 #define DRIVER_DESC "Intel Graphics" 54 #define DRIVER_DATE "20080730" 55 56 enum pipe { 57 PIPE_A = 0, 58 PIPE_B, 59 PIPE_C, 60 I915_MAX_PIPES 61 }; 62 #define pipe_name(p) ((p) + 'A') 63 64 enum transcoder { 65 TRANSCODER_A = 0, 66 TRANSCODER_B, 67 TRANSCODER_C, 68 TRANSCODER_EDP = 0xF, 69 }; 70 #define transcoder_name(t) ((t) + 'A') 71 72 enum plane { 73 PLANE_A = 0, 74 PLANE_B, 75 PLANE_C, 76 }; 77 #define plane_name(p) ((p) + 'A') 78 79 enum port { 80 PORT_A = 0, 81 PORT_B, 82 PORT_C, 83 PORT_D, 84 PORT_E, 85 I915_MAX_PORTS 86 }; 87 #define port_name(p) ((p) + 'A') 88 89 #define I915_GEM_GPU_DOMAINS \ 90 (I915_GEM_DOMAIN_RENDER | \ 91 I915_GEM_DOMAIN_SAMPLER | \ 92 I915_GEM_DOMAIN_COMMAND | \ 93 I915_GEM_DOMAIN_INSTRUCTION | \ 94 I915_GEM_DOMAIN_VERTEX) 95 96 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 97 98 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 99 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 100 if ((intel_encoder)->base.crtc == (__crtc)) 101 102 struct intel_pch_pll { 103 int refcount; /* count of number of CRTCs sharing this PLL */ 104 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 105 bool on; /* is the PLL actually active? Disabled during modeset */ 106 int pll_reg; 107 int fp0_reg; 108 int fp1_reg; 109 }; 110 #define I915_NUM_PLLS 2 111 112 /* Used by dp and fdi links */ 113 struct intel_link_m_n { 114 uint32_t tu; 115 uint32_t gmch_m; 116 uint32_t gmch_n; 117 uint32_t link_m; 118 uint32_t link_n; 119 }; 120 121 void intel_link_compute_m_n(int bpp, int nlanes, 122 int pixel_clock, int link_clock, 123 struct intel_link_m_n *m_n); 124 125 struct intel_ddi_plls { 126 int spll_refcount; 127 int wrpll1_refcount; 128 int wrpll2_refcount; 129 }; 130 131 /* Interface history: 132 * 133 * 1.1: Original. 134 * 1.2: Add Power Management 135 * 1.3: Add vblank support 136 * 1.4: Fix cmdbuffer path, add heap destroy 137 * 1.5: Add vblank pipe configuration 138 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 139 * - Support vertical blank on secondary display pipe 140 */ 141 #define DRIVER_MAJOR 1 142 #define DRIVER_MINOR 6 143 #define DRIVER_PATCHLEVEL 0 144 145 #define WATCH_COHERENCY 0 146 #define WATCH_LISTS 0 147 #define WATCH_GTT 0 148 149 #define I915_GEM_PHYS_CURSOR_0 1 150 #define I915_GEM_PHYS_CURSOR_1 2 151 #define I915_GEM_PHYS_OVERLAY_REGS 3 152 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 153 154 struct drm_i915_gem_phys_object { 155 int id; 156 struct page **page_list; 157 drm_dma_handle_t *handle; 158 struct drm_i915_gem_object *cur_obj; 159 }; 160 161 struct opregion_header; 162 struct opregion_acpi; 163 struct opregion_swsci; 164 struct opregion_asle; 165 struct drm_i915_private; 166 167 struct intel_opregion { 168 struct opregion_header __iomem *header; 169 struct opregion_acpi __iomem *acpi; 170 struct opregion_swsci __iomem *swsci; 171 struct opregion_asle __iomem *asle; 172 void __iomem *vbt; 173 u32 __iomem *lid_state; 174 }; 175 #define OPREGION_SIZE (8*1024) 176 177 struct intel_overlay; 178 struct intel_overlay_error_state; 179 180 struct drm_i915_master_private { 181 drm_local_map_t *sarea; 182 struct _drm_i915_sarea *sarea_priv; 183 }; 184 #define I915_FENCE_REG_NONE -1 185 #define I915_MAX_NUM_FENCES 16 186 /* 16 fences + sign bit for FENCE_REG_NONE */ 187 #define I915_MAX_NUM_FENCE_BITS 5 188 189 struct drm_i915_fence_reg { 190 struct list_head lru_list; 191 struct drm_i915_gem_object *obj; 192 int pin_count; 193 }; 194 195 struct sdvo_device_mapping { 196 u8 initialized; 197 u8 dvo_port; 198 u8 slave_addr; 199 u8 dvo_wiring; 200 u8 i2c_pin; 201 u8 ddc_pin; 202 }; 203 204 struct intel_display_error_state; 205 206 struct drm_i915_error_state { 207 struct kref ref; 208 u32 eir; 209 u32 pgtbl_er; 210 u32 ier; 211 u32 ccid; 212 u32 derrmr; 213 u32 forcewake; 214 bool waiting[I915_NUM_RINGS]; 215 u32 pipestat[I915_MAX_PIPES]; 216 u32 tail[I915_NUM_RINGS]; 217 u32 head[I915_NUM_RINGS]; 218 u32 ctl[I915_NUM_RINGS]; 219 u32 ipeir[I915_NUM_RINGS]; 220 u32 ipehr[I915_NUM_RINGS]; 221 u32 instdone[I915_NUM_RINGS]; 222 u32 acthd[I915_NUM_RINGS]; 223 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 224 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 225 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 226 /* our own tracking of ring head and tail */ 227 u32 cpu_ring_head[I915_NUM_RINGS]; 228 u32 cpu_ring_tail[I915_NUM_RINGS]; 229 u32 error; /* gen6+ */ 230 u32 err_int; /* gen7 */ 231 u32 instpm[I915_NUM_RINGS]; 232 u32 instps[I915_NUM_RINGS]; 233 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 234 u32 seqno[I915_NUM_RINGS]; 235 u64 bbaddr; 236 u32 fault_reg[I915_NUM_RINGS]; 237 u32 done_reg; 238 u32 faddr[I915_NUM_RINGS]; 239 u64 fence[I915_MAX_NUM_FENCES]; 240 struct timeval time; 241 struct drm_i915_error_ring { 242 struct drm_i915_error_object { 243 int page_count; 244 u32 gtt_offset; 245 u32 *pages[0]; 246 } *ringbuffer, *batchbuffer; 247 struct drm_i915_error_request { 248 long jiffies; 249 u32 seqno; 250 u32 tail; 251 } *requests; 252 int num_requests; 253 } ring[I915_NUM_RINGS]; 254 struct drm_i915_error_buffer { 255 u32 size; 256 u32 name; 257 u32 rseqno, wseqno; 258 u32 gtt_offset; 259 u32 read_domains; 260 u32 write_domain; 261 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 262 s32 pinned:2; 263 u32 tiling:2; 264 u32 dirty:1; 265 u32 purgeable:1; 266 s32 ring:4; 267 u32 cache_level:2; 268 } *active_bo, *pinned_bo; 269 u32 active_bo_count, pinned_bo_count; 270 struct intel_overlay_error_state *overlay; 271 struct intel_display_error_state *display; 272 }; 273 274 struct drm_i915_display_funcs { 275 bool (*fbc_enabled)(struct drm_device *dev); 276 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 277 void (*disable_fbc)(struct drm_device *dev); 278 int (*get_display_clock_speed)(struct drm_device *dev); 279 int (*get_fifo_size)(struct drm_device *dev, int plane); 280 void (*update_wm)(struct drm_device *dev); 281 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 282 uint32_t sprite_width, int pixel_size); 283 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 284 struct drm_display_mode *mode); 285 void (*modeset_global_resources)(struct drm_device *dev); 286 int (*crtc_mode_set)(struct drm_crtc *crtc, 287 struct drm_display_mode *mode, 288 struct drm_display_mode *adjusted_mode, 289 int x, int y, 290 struct drm_framebuffer *old_fb); 291 void (*crtc_enable)(struct drm_crtc *crtc); 292 void (*crtc_disable)(struct drm_crtc *crtc); 293 void (*off)(struct drm_crtc *crtc); 294 void (*write_eld)(struct drm_connector *connector, 295 struct drm_crtc *crtc); 296 void (*fdi_link_train)(struct drm_crtc *crtc); 297 void (*init_clock_gating)(struct drm_device *dev); 298 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 299 struct drm_framebuffer *fb, 300 struct drm_i915_gem_object *obj); 301 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 302 int x, int y); 303 void (*hpd_irq_setup)(struct drm_device *dev); 304 /* clock updates for mode set */ 305 /* cursor updates */ 306 /* render clock increase/decrease */ 307 /* display clock increase/decrease */ 308 /* pll clock increase/decrease */ 309 }; 310 311 struct drm_i915_gt_funcs { 312 void (*force_wake_get)(struct drm_i915_private *dev_priv); 313 void (*force_wake_put)(struct drm_i915_private *dev_priv); 314 }; 315 316 #define DEV_INFO_FLAGS \ 317 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 318 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 319 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 320 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 321 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 322 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 323 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 324 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 325 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 326 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 327 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 328 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 329 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 330 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 331 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 332 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 333 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 334 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 335 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 336 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 337 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 338 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 339 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 340 DEV_INFO_FLAG(has_llc) 341 342 struct intel_device_info { 343 u32 display_mmio_offset; 344 u8 gen; 345 u8 is_mobile:1; 346 u8 is_i85x:1; 347 u8 is_i915g:1; 348 u8 is_i945gm:1; 349 u8 is_g33:1; 350 u8 need_gfx_hws:1; 351 u8 is_g4x:1; 352 u8 is_pineview:1; 353 u8 is_broadwater:1; 354 u8 is_crestline:1; 355 u8 is_ivybridge:1; 356 u8 is_valleyview:1; 357 u8 has_force_wake:1; 358 u8 is_haswell:1; 359 u8 has_fbc:1; 360 u8 has_pipe_cxsr:1; 361 u8 has_hotplug:1; 362 u8 cursor_needs_physical:1; 363 u8 has_overlay:1; 364 u8 overlay_needs_physical:1; 365 u8 supports_tv:1; 366 u8 has_bsd_ring:1; 367 u8 has_blt_ring:1; 368 u8 has_llc:1; 369 }; 370 371 enum i915_cache_level { 372 I915_CACHE_NONE = 0, 373 I915_CACHE_LLC, 374 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ 375 }; 376 377 /* The Graphics Translation Table is the way in which GEN hardware translates a 378 * Graphics Virtual Address into a Physical Address. In addition to the normal 379 * collateral associated with any va->pa translations GEN hardware also has a 380 * portion of the GTT which can be mapped by the CPU and remain both coherent 381 * and correct (in cases like swizzling). That region is referred to as GMADR in 382 * the spec. 383 */ 384 struct i915_gtt { 385 unsigned long start; /* Start offset of used GTT */ 386 size_t total; /* Total size GTT can map */ 387 size_t stolen_size; /* Total size of stolen memory */ 388 389 unsigned long mappable_end; /* End offset that we can CPU map */ 390 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 391 phys_addr_t mappable_base; /* PA of our GMADR */ 392 393 /** "Graphics Stolen Memory" holds the global PTEs */ 394 void __iomem *gsm; 395 396 bool do_idle_maps; 397 dma_addr_t scratch_page_dma; 398 struct page *scratch_page; 399 400 /* global gtt ops */ 401 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 402 size_t *stolen, phys_addr_t *mappable_base, 403 unsigned long *mappable_end); 404 void (*gtt_remove)(struct drm_device *dev); 405 void (*gtt_clear_range)(struct drm_device *dev, 406 unsigned int first_entry, 407 unsigned int num_entries); 408 void (*gtt_insert_entries)(struct drm_device *dev, 409 struct sg_table *st, 410 unsigned int pg_start, 411 enum i915_cache_level cache_level); 412 }; 413 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) 414 415 #define I915_PPGTT_PD_ENTRIES 512 416 #define I915_PPGTT_PT_ENTRIES 1024 417 struct i915_hw_ppgtt { 418 struct drm_device *dev; 419 unsigned num_pd_entries; 420 struct page **pt_pages; 421 uint32_t pd_offset; 422 dma_addr_t *pt_dma_addr; 423 dma_addr_t scratch_page_dma_addr; 424 425 /* pte functions, mirroring the interface of the global gtt. */ 426 void (*clear_range)(struct i915_hw_ppgtt *ppgtt, 427 unsigned int first_entry, 428 unsigned int num_entries); 429 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, 430 struct sg_table *st, 431 unsigned int pg_start, 432 enum i915_cache_level cache_level); 433 void (*cleanup)(struct i915_hw_ppgtt *ppgtt); 434 }; 435 436 437 /* This must match up with the value previously used for execbuf2.rsvd1. */ 438 #define DEFAULT_CONTEXT_ID 0 439 struct i915_hw_context { 440 int id; 441 bool is_initialized; 442 struct drm_i915_file_private *file_priv; 443 struct intel_ring_buffer *ring; 444 struct drm_i915_gem_object *obj; 445 }; 446 447 enum no_fbc_reason { 448 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 449 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 450 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 451 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 452 FBC_BAD_PLANE, /* fbc not supported on plane */ 453 FBC_NOT_TILED, /* buffer not tiled */ 454 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 455 FBC_MODULE_PARAM, 456 }; 457 458 enum intel_pch { 459 PCH_NONE = 0, /* No PCH present */ 460 PCH_IBX, /* Ibexpeak PCH */ 461 PCH_CPT, /* Cougarpoint PCH */ 462 PCH_LPT, /* Lynxpoint PCH */ 463 }; 464 465 enum intel_sbi_destination { 466 SBI_ICLK, 467 SBI_MPHY, 468 }; 469 470 #define QUIRK_PIPEA_FORCE (1<<0) 471 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 472 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 473 474 struct intel_fbdev; 475 struct intel_fbc_work; 476 477 struct intel_gmbus { 478 struct i2c_adapter adapter; 479 u32 force_bit; 480 u32 reg0; 481 u32 gpio_reg; 482 struct i2c_algo_bit_data bit_algo; 483 struct drm_i915_private *dev_priv; 484 }; 485 486 struct i915_suspend_saved_registers { 487 u8 saveLBB; 488 u32 saveDSPACNTR; 489 u32 saveDSPBCNTR; 490 u32 saveDSPARB; 491 u32 savePIPEACONF; 492 u32 savePIPEBCONF; 493 u32 savePIPEASRC; 494 u32 savePIPEBSRC; 495 u32 saveFPA0; 496 u32 saveFPA1; 497 u32 saveDPLL_A; 498 u32 saveDPLL_A_MD; 499 u32 saveHTOTAL_A; 500 u32 saveHBLANK_A; 501 u32 saveHSYNC_A; 502 u32 saveVTOTAL_A; 503 u32 saveVBLANK_A; 504 u32 saveVSYNC_A; 505 u32 saveBCLRPAT_A; 506 u32 saveTRANSACONF; 507 u32 saveTRANS_HTOTAL_A; 508 u32 saveTRANS_HBLANK_A; 509 u32 saveTRANS_HSYNC_A; 510 u32 saveTRANS_VTOTAL_A; 511 u32 saveTRANS_VBLANK_A; 512 u32 saveTRANS_VSYNC_A; 513 u32 savePIPEASTAT; 514 u32 saveDSPASTRIDE; 515 u32 saveDSPASIZE; 516 u32 saveDSPAPOS; 517 u32 saveDSPAADDR; 518 u32 saveDSPASURF; 519 u32 saveDSPATILEOFF; 520 u32 savePFIT_PGM_RATIOS; 521 u32 saveBLC_HIST_CTL; 522 u32 saveBLC_PWM_CTL; 523 u32 saveBLC_PWM_CTL2; 524 u32 saveBLC_CPU_PWM_CTL; 525 u32 saveBLC_CPU_PWM_CTL2; 526 u32 saveFPB0; 527 u32 saveFPB1; 528 u32 saveDPLL_B; 529 u32 saveDPLL_B_MD; 530 u32 saveHTOTAL_B; 531 u32 saveHBLANK_B; 532 u32 saveHSYNC_B; 533 u32 saveVTOTAL_B; 534 u32 saveVBLANK_B; 535 u32 saveVSYNC_B; 536 u32 saveBCLRPAT_B; 537 u32 saveTRANSBCONF; 538 u32 saveTRANS_HTOTAL_B; 539 u32 saveTRANS_HBLANK_B; 540 u32 saveTRANS_HSYNC_B; 541 u32 saveTRANS_VTOTAL_B; 542 u32 saveTRANS_VBLANK_B; 543 u32 saveTRANS_VSYNC_B; 544 u32 savePIPEBSTAT; 545 u32 saveDSPBSTRIDE; 546 u32 saveDSPBSIZE; 547 u32 saveDSPBPOS; 548 u32 saveDSPBADDR; 549 u32 saveDSPBSURF; 550 u32 saveDSPBTILEOFF; 551 u32 saveVGA0; 552 u32 saveVGA1; 553 u32 saveVGA_PD; 554 u32 saveVGACNTRL; 555 u32 saveADPA; 556 u32 saveLVDS; 557 u32 savePP_ON_DELAYS; 558 u32 savePP_OFF_DELAYS; 559 u32 saveDVOA; 560 u32 saveDVOB; 561 u32 saveDVOC; 562 u32 savePP_ON; 563 u32 savePP_OFF; 564 u32 savePP_CONTROL; 565 u32 savePP_DIVISOR; 566 u32 savePFIT_CONTROL; 567 u32 save_palette_a[256]; 568 u32 save_palette_b[256]; 569 u32 saveDPFC_CB_BASE; 570 u32 saveFBC_CFB_BASE; 571 u32 saveFBC_LL_BASE; 572 u32 saveFBC_CONTROL; 573 u32 saveFBC_CONTROL2; 574 u32 saveIER; 575 u32 saveIIR; 576 u32 saveIMR; 577 u32 saveDEIER; 578 u32 saveDEIMR; 579 u32 saveGTIER; 580 u32 saveGTIMR; 581 u32 saveFDI_RXA_IMR; 582 u32 saveFDI_RXB_IMR; 583 u32 saveCACHE_MODE_0; 584 u32 saveMI_ARB_STATE; 585 u32 saveSWF0[16]; 586 u32 saveSWF1[16]; 587 u32 saveSWF2[3]; 588 u8 saveMSR; 589 u8 saveSR[8]; 590 u8 saveGR[25]; 591 u8 saveAR_INDEX; 592 u8 saveAR[21]; 593 u8 saveDACMASK; 594 u8 saveCR[37]; 595 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 596 u32 saveCURACNTR; 597 u32 saveCURAPOS; 598 u32 saveCURABASE; 599 u32 saveCURBCNTR; 600 u32 saveCURBPOS; 601 u32 saveCURBBASE; 602 u32 saveCURSIZE; 603 u32 saveDP_B; 604 u32 saveDP_C; 605 u32 saveDP_D; 606 u32 savePIPEA_GMCH_DATA_M; 607 u32 savePIPEB_GMCH_DATA_M; 608 u32 savePIPEA_GMCH_DATA_N; 609 u32 savePIPEB_GMCH_DATA_N; 610 u32 savePIPEA_DP_LINK_M; 611 u32 savePIPEB_DP_LINK_M; 612 u32 savePIPEA_DP_LINK_N; 613 u32 savePIPEB_DP_LINK_N; 614 u32 saveFDI_RXA_CTL; 615 u32 saveFDI_TXA_CTL; 616 u32 saveFDI_RXB_CTL; 617 u32 saveFDI_TXB_CTL; 618 u32 savePFA_CTL_1; 619 u32 savePFB_CTL_1; 620 u32 savePFA_WIN_SZ; 621 u32 savePFB_WIN_SZ; 622 u32 savePFA_WIN_POS; 623 u32 savePFB_WIN_POS; 624 u32 savePCH_DREF_CONTROL; 625 u32 saveDISP_ARB_CTL; 626 u32 savePIPEA_DATA_M1; 627 u32 savePIPEA_DATA_N1; 628 u32 savePIPEA_LINK_M1; 629 u32 savePIPEA_LINK_N1; 630 u32 savePIPEB_DATA_M1; 631 u32 savePIPEB_DATA_N1; 632 u32 savePIPEB_LINK_M1; 633 u32 savePIPEB_LINK_N1; 634 u32 saveMCHBAR_RENDER_STANDBY; 635 u32 savePCH_PORT_HOTPLUG; 636 }; 637 638 struct intel_gen6_power_mgmt { 639 struct work_struct work; 640 u32 pm_iir; 641 /* lock - irqsave spinlock that protectects the work_struct and 642 * pm_iir. */ 643 spinlock_t lock; 644 645 /* The below variables an all the rps hw state are protected by 646 * dev->struct mutext. */ 647 u8 cur_delay; 648 u8 min_delay; 649 u8 max_delay; 650 651 struct delayed_work delayed_resume_work; 652 653 /* 654 * Protects RPS/RC6 register access and PCU communication. 655 * Must be taken after struct_mutex if nested. 656 */ 657 struct mutex hw_lock; 658 }; 659 660 /* defined intel_pm.c */ 661 extern spinlock_t mchdev_lock; 662 663 struct intel_ilk_power_mgmt { 664 u8 cur_delay; 665 u8 min_delay; 666 u8 max_delay; 667 u8 fmax; 668 u8 fstart; 669 670 u64 last_count1; 671 unsigned long last_time1; 672 unsigned long chipset_power; 673 u64 last_count2; 674 struct timespec last_time2; 675 unsigned long gfx_power; 676 u8 corr; 677 678 int c_m; 679 int r_t; 680 681 struct drm_i915_gem_object *pwrctx; 682 struct drm_i915_gem_object *renderctx; 683 }; 684 685 struct i915_dri1_state { 686 unsigned allow_batchbuffer : 1; 687 u32 __iomem *gfx_hws_cpu_addr; 688 689 unsigned int cpp; 690 int back_offset; 691 int front_offset; 692 int current_page; 693 int page_flipping; 694 695 uint32_t counter; 696 }; 697 698 struct intel_l3_parity { 699 u32 *remap_info; 700 struct work_struct error_work; 701 }; 702 703 struct i915_gem_mm { 704 /** Memory allocator for GTT stolen memory */ 705 struct drm_mm stolen; 706 /** Memory allocator for GTT */ 707 struct drm_mm gtt_space; 708 /** List of all objects in gtt_space. Used to restore gtt 709 * mappings on resume */ 710 struct list_head bound_list; 711 /** 712 * List of objects which are not bound to the GTT (thus 713 * are idle and not used by the GPU) but still have 714 * (presumably uncached) pages still attached. 715 */ 716 struct list_head unbound_list; 717 718 /** Usable portion of the GTT for GEM */ 719 unsigned long stolen_base; /* limited to low memory (32-bit) */ 720 721 int gtt_mtrr; 722 723 /** PPGTT used for aliasing the PPGTT with the GTT */ 724 struct i915_hw_ppgtt *aliasing_ppgtt; 725 726 struct shrinker inactive_shrinker; 727 bool shrinker_no_lock_stealing; 728 729 /** 730 * List of objects currently involved in rendering. 731 * 732 * Includes buffers having the contents of their GPU caches 733 * flushed, not necessarily primitives. last_rendering_seqno 734 * represents when the rendering involved will be completed. 735 * 736 * A reference is held on the buffer while on this list. 737 */ 738 struct list_head active_list; 739 740 /** 741 * LRU list of objects which are not in the ringbuffer and 742 * are ready to unbind, but are still in the GTT. 743 * 744 * last_rendering_seqno is 0 while an object is in this list. 745 * 746 * A reference is not held on the buffer while on this list, 747 * as merely being GTT-bound shouldn't prevent its being 748 * freed, and we'll pull it off the list in the free path. 749 */ 750 struct list_head inactive_list; 751 752 /** LRU list of objects with fence regs on them. */ 753 struct list_head fence_list; 754 755 /** 756 * We leave the user IRQ off as much as possible, 757 * but this means that requests will finish and never 758 * be retired once the system goes idle. Set a timer to 759 * fire periodically while the ring is running. When it 760 * fires, go retire requests. 761 */ 762 struct delayed_work retire_work; 763 764 /** 765 * Are we in a non-interruptible section of code like 766 * modesetting? 767 */ 768 bool interruptible; 769 770 /** 771 * Flag if the X Server, and thus DRM, is not currently in 772 * control of the device. 773 * 774 * This is set between LeaveVT and EnterVT. It needs to be 775 * replaced with a semaphore. It also needs to be 776 * transitioned away from for kernel modesetting. 777 */ 778 int suspended; 779 780 /** Bit 6 swizzling required for X tiling */ 781 uint32_t bit_6_swizzle_x; 782 /** Bit 6 swizzling required for Y tiling */ 783 uint32_t bit_6_swizzle_y; 784 785 /* storage for physical objects */ 786 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 787 788 /* accounting, useful for userland debugging */ 789 size_t object_memory; 790 u32 object_count; 791 }; 792 793 struct i915_gpu_error { 794 /* For hangcheck timer */ 795 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 796 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 797 struct timer_list hangcheck_timer; 798 int hangcheck_count; 799 uint32_t last_acthd[I915_NUM_RINGS]; 800 uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; 801 802 /* For reset and error_state handling. */ 803 spinlock_t lock; 804 /* Protected by the above dev->gpu_error.lock. */ 805 struct drm_i915_error_state *first_error; 806 struct work_struct work; 807 808 unsigned long last_reset; 809 810 /** 811 * State variable and reset counter controlling the reset flow 812 * 813 * Upper bits are for the reset counter. This counter is used by the 814 * wait_seqno code to race-free noticed that a reset event happened and 815 * that it needs to restart the entire ioctl (since most likely the 816 * seqno it waited for won't ever signal anytime soon). 817 * 818 * This is important for lock-free wait paths, where no contended lock 819 * naturally enforces the correct ordering between the bail-out of the 820 * waiter and the gpu reset work code. 821 * 822 * Lowest bit controls the reset state machine: Set means a reset is in 823 * progress. This state will (presuming we don't have any bugs) decay 824 * into either unset (successful reset) or the special WEDGED value (hw 825 * terminally sour). All waiters on the reset_queue will be woken when 826 * that happens. 827 */ 828 atomic_t reset_counter; 829 830 /** 831 * Special values/flags for reset_counter 832 * 833 * Note that the code relies on 834 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG 835 * being true. 836 */ 837 #define I915_RESET_IN_PROGRESS_FLAG 1 838 #define I915_WEDGED 0xffffffff 839 840 /** 841 * Waitqueue to signal when the reset has completed. Used by clients 842 * that wait for dev_priv->mm.wedged to settle. 843 */ 844 wait_queue_head_t reset_queue; 845 846 /* For gpu hang simulation. */ 847 unsigned int stop_rings; 848 }; 849 850 enum modeset_restore { 851 MODESET_ON_LID_OPEN, 852 MODESET_DONE, 853 MODESET_SUSPENDED, 854 }; 855 856 typedef struct drm_i915_private { 857 struct drm_device *dev; 858 struct kmem_cache *slab; 859 860 const struct intel_device_info *info; 861 862 int relative_constants_mode; 863 864 void __iomem *regs; 865 866 struct drm_i915_gt_funcs gt; 867 /** gt_fifo_count and the subsequent register write are synchronized 868 * with dev->struct_mutex. */ 869 unsigned gt_fifo_count; 870 /** forcewake_count is protected by gt_lock */ 871 unsigned forcewake_count; 872 /** gt_lock is also taken in irq contexts. */ 873 spinlock_t gt_lock; 874 875 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 876 877 878 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 879 * controller on different i2c buses. */ 880 struct mutex gmbus_mutex; 881 882 /** 883 * Base address of the gmbus and gpio block. 884 */ 885 uint32_t gpio_mmio_base; 886 887 wait_queue_head_t gmbus_wait_queue; 888 889 struct pci_dev *bridge_dev; 890 struct intel_ring_buffer ring[I915_NUM_RINGS]; 891 uint32_t last_seqno, next_seqno; 892 893 drm_dma_handle_t *status_page_dmah; 894 struct resource mch_res; 895 896 atomic_t irq_received; 897 898 /* protects the irq masks */ 899 spinlock_t irq_lock; 900 901 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 902 struct pm_qos_request pm_qos; 903 904 /* DPIO indirect register protection */ 905 struct mutex dpio_lock; 906 907 /** Cached value of IMR to avoid reads in updating the bitfield */ 908 u32 pipestat[2]; 909 u32 irq_mask; 910 u32 gt_irq_mask; 911 912 u32 hotplug_supported_mask; 913 struct work_struct hotplug_work; 914 bool enable_hotplug_processing; 915 916 int num_pipe; 917 int num_pch_pll; 918 919 unsigned long cfb_size; 920 unsigned int cfb_fb; 921 enum plane cfb_plane; 922 int cfb_y; 923 struct intel_fbc_work *fbc_work; 924 925 struct intel_opregion opregion; 926 927 /* overlay */ 928 struct intel_overlay *overlay; 929 unsigned int sprite_scaling_enabled; 930 931 /* LVDS info */ 932 int backlight_level; /* restore backlight to this value */ 933 bool backlight_enabled; 934 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 935 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 936 937 /* Feature bits from the VBIOS */ 938 unsigned int int_tv_support:1; 939 unsigned int lvds_dither:1; 940 unsigned int lvds_vbt:1; 941 unsigned int int_crt_support:1; 942 unsigned int lvds_use_ssc:1; 943 unsigned int display_clock_mode:1; 944 int lvds_ssc_freq; 945 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 946 struct { 947 int rate; 948 int lanes; 949 int preemphasis; 950 int vswing; 951 952 bool initialized; 953 bool support; 954 int bpp; 955 struct edp_power_seq pps; 956 } edp; 957 bool no_aux_handshake; 958 959 int crt_ddc_pin; 960 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 961 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 962 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 963 964 unsigned int fsb_freq, mem_freq, is_ddr3; 965 966 struct workqueue_struct *wq; 967 968 /* Display functions */ 969 struct drm_i915_display_funcs display; 970 971 /* PCH chipset type */ 972 enum intel_pch pch_type; 973 unsigned short pch_id; 974 975 unsigned long quirks; 976 977 enum modeset_restore modeset_restore; 978 struct mutex modeset_restore_lock; 979 980 struct i915_gtt gtt; 981 982 struct i915_gem_mm mm; 983 984 /* Kernel Modesetting */ 985 986 struct sdvo_device_mapping sdvo_mappings[2]; 987 /* indicate whether the LVDS_BORDER should be enabled or not */ 988 unsigned int lvds_border_bits; 989 /* Panel fitter placement and size for Ironlake+ */ 990 u32 pch_pf_pos, pch_pf_size; 991 992 struct drm_crtc *plane_to_crtc_mapping[3]; 993 struct drm_crtc *pipe_to_crtc_mapping[3]; 994 wait_queue_head_t pending_flip_queue; 995 996 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 997 struct intel_ddi_plls ddi_plls; 998 999 /* Reclocking support */ 1000 bool render_reclock_avail; 1001 bool lvds_downclock_avail; 1002 /* indicates the reduced downclock for LVDS*/ 1003 int lvds_downclock; 1004 u16 orig_clock; 1005 int child_dev_num; 1006 struct child_device_config *child_dev; 1007 1008 bool mchbar_need_disable; 1009 1010 struct intel_l3_parity l3_parity; 1011 1012 /* gen6+ rps state */ 1013 struct intel_gen6_power_mgmt rps; 1014 1015 /* ilk-only ips/rps state. Everything in here is protected by the global 1016 * mchdev_lock in intel_pm.c */ 1017 struct intel_ilk_power_mgmt ips; 1018 1019 enum no_fbc_reason no_fbc_reason; 1020 1021 struct drm_mm_node *compressed_fb; 1022 struct drm_mm_node *compressed_llb; 1023 1024 struct i915_gpu_error gpu_error; 1025 1026 /* list of fbdev register on this device */ 1027 struct intel_fbdev *fbdev; 1028 1029 /* 1030 * The console may be contended at resume, but we don't 1031 * want it to block on it. 1032 */ 1033 struct work_struct console_resume_work; 1034 1035 struct backlight_device *backlight; 1036 1037 struct drm_property *broadcast_rgb_property; 1038 struct drm_property *force_audio_property; 1039 1040 bool hw_contexts_disabled; 1041 uint32_t hw_context_size; 1042 1043 u32 fdi_rx_config; 1044 1045 struct i915_suspend_saved_registers regfile; 1046 1047 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1048 * here! */ 1049 struct i915_dri1_state dri1; 1050 } drm_i915_private_t; 1051 1052 /* Iterate over initialised rings */ 1053 #define for_each_ring(ring__, dev_priv__, i__) \ 1054 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1055 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1056 1057 enum hdmi_force_audio { 1058 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1059 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1060 HDMI_AUDIO_AUTO, /* trust EDID */ 1061 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1062 }; 1063 1064 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) 1065 1066 struct drm_i915_gem_object_ops { 1067 /* Interface between the GEM object and its backing storage. 1068 * get_pages() is called once prior to the use of the associated set 1069 * of pages before to binding them into the GTT, and put_pages() is 1070 * called after we no longer need them. As we expect there to be 1071 * associated cost with migrating pages between the backing storage 1072 * and making them available for the GPU (e.g. clflush), we may hold 1073 * onto the pages after they are no longer referenced by the GPU 1074 * in case they may be used again shortly (for example migrating the 1075 * pages to a different memory domain within the GTT). put_pages() 1076 * will therefore most likely be called when the object itself is 1077 * being released or under memory pressure (where we attempt to 1078 * reap pages for the shrinker). 1079 */ 1080 int (*get_pages)(struct drm_i915_gem_object *); 1081 void (*put_pages)(struct drm_i915_gem_object *); 1082 }; 1083 1084 struct drm_i915_gem_object { 1085 struct drm_gem_object base; 1086 1087 const struct drm_i915_gem_object_ops *ops; 1088 1089 /** Current space allocated to this object in the GTT, if any. */ 1090 struct drm_mm_node *gtt_space; 1091 /** Stolen memory for this object, instead of being backed by shmem. */ 1092 struct drm_mm_node *stolen; 1093 struct list_head gtt_list; 1094 1095 /** This object's place on the active/inactive lists */ 1096 struct list_head ring_list; 1097 struct list_head mm_list; 1098 /** This object's place in the batchbuffer or on the eviction list */ 1099 struct list_head exec_list; 1100 1101 /** 1102 * This is set if the object is on the active lists (has pending 1103 * rendering and so a non-zero seqno), and is not set if it i s on 1104 * inactive (ready to be unbound) list. 1105 */ 1106 unsigned int active:1; 1107 1108 /** 1109 * This is set if the object has been written to since last bound 1110 * to the GTT 1111 */ 1112 unsigned int dirty:1; 1113 1114 /** 1115 * Fence register bits (if any) for this object. Will be set 1116 * as needed when mapped into the GTT. 1117 * Protected by dev->struct_mutex. 1118 */ 1119 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1120 1121 /** 1122 * Advice: are the backing pages purgeable? 1123 */ 1124 unsigned int madv:2; 1125 1126 /** 1127 * Current tiling mode for the object. 1128 */ 1129 unsigned int tiling_mode:2; 1130 /** 1131 * Whether the tiling parameters for the currently associated fence 1132 * register have changed. Note that for the purposes of tracking 1133 * tiling changes we also treat the unfenced register, the register 1134 * slot that the object occupies whilst it executes a fenced 1135 * command (such as BLT on gen2/3), as a "fence". 1136 */ 1137 unsigned int fence_dirty:1; 1138 1139 /** How many users have pinned this object in GTT space. The following 1140 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1141 * (via user_pin_count), execbuffer (objects are not allowed multiple 1142 * times for the same batchbuffer), and the framebuffer code. When 1143 * switching/pageflipping, the framebuffer code has at most two buffers 1144 * pinned per crtc. 1145 * 1146 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1147 * bits with absolutely no headroom. So use 4 bits. */ 1148 unsigned int pin_count:4; 1149 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1150 1151 /** 1152 * Is the object at the current location in the gtt mappable and 1153 * fenceable? Used to avoid costly recalculations. 1154 */ 1155 unsigned int map_and_fenceable:1; 1156 1157 /** 1158 * Whether the current gtt mapping needs to be mappable (and isn't just 1159 * mappable by accident). Track pin and fault separate for a more 1160 * accurate mappable working set. 1161 */ 1162 unsigned int fault_mappable:1; 1163 unsigned int pin_mappable:1; 1164 1165 /* 1166 * Is the GPU currently using a fence to access this buffer, 1167 */ 1168 unsigned int pending_fenced_gpu_access:1; 1169 unsigned int fenced_gpu_access:1; 1170 1171 unsigned int cache_level:2; 1172 1173 unsigned int has_aliasing_ppgtt_mapping:1; 1174 unsigned int has_global_gtt_mapping:1; 1175 unsigned int has_dma_mapping:1; 1176 1177 struct sg_table *pages; 1178 int pages_pin_count; 1179 1180 /* prime dma-buf support */ 1181 void *dma_buf_vmapping; 1182 int vmapping_count; 1183 1184 /** 1185 * Used for performing relocations during execbuffer insertion. 1186 */ 1187 struct hlist_node exec_node; 1188 unsigned long exec_handle; 1189 struct drm_i915_gem_exec_object2 *exec_entry; 1190 1191 /** 1192 * Current offset of the object in GTT space. 1193 * 1194 * This is the same as gtt_space->start 1195 */ 1196 uint32_t gtt_offset; 1197 1198 struct intel_ring_buffer *ring; 1199 1200 /** Breadcrumb of last rendering to the buffer. */ 1201 uint32_t last_read_seqno; 1202 uint32_t last_write_seqno; 1203 /** Breadcrumb of last fenced GPU access to the buffer. */ 1204 uint32_t last_fenced_seqno; 1205 1206 /** Current tiling stride for the object, if it's tiled. */ 1207 uint32_t stride; 1208 1209 /** Record of address bit 17 of each page at last unbind. */ 1210 unsigned long *bit_17; 1211 1212 /** User space pin count and filp owning the pin */ 1213 uint32_t user_pin_count; 1214 struct drm_file *pin_filp; 1215 1216 /** for phy allocated objects */ 1217 struct drm_i915_gem_phys_object *phys_obj; 1218 }; 1219 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1220 1221 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1222 1223 /** 1224 * Request queue structure. 1225 * 1226 * The request queue allows us to note sequence numbers that have been emitted 1227 * and may be associated with active buffers to be retired. 1228 * 1229 * By keeping this list, we can avoid having to do questionable 1230 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1231 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1232 */ 1233 struct drm_i915_gem_request { 1234 /** On Which ring this request was generated */ 1235 struct intel_ring_buffer *ring; 1236 1237 /** GEM sequence number associated with this request. */ 1238 uint32_t seqno; 1239 1240 /** Postion in the ringbuffer of the end of the request */ 1241 u32 tail; 1242 1243 /** Time at which this request was emitted, in jiffies. */ 1244 unsigned long emitted_jiffies; 1245 1246 /** global list entry for this request */ 1247 struct list_head list; 1248 1249 struct drm_i915_file_private *file_priv; 1250 /** file_priv list entry for this request */ 1251 struct list_head client_list; 1252 }; 1253 1254 struct drm_i915_file_private { 1255 struct { 1256 spinlock_t lock; 1257 struct list_head request_list; 1258 } mm; 1259 struct idr context_idr; 1260 }; 1261 1262 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1263 1264 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1265 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1266 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1267 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1268 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1269 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1270 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1271 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1272 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1273 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1274 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1275 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1276 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1277 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1278 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1279 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1280 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1281 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1282 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1283 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1284 (dev)->pci_device == 0x0152 || \ 1285 (dev)->pci_device == 0x015a) 1286 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1287 (dev)->pci_device == 0x0106 || \ 1288 (dev)->pci_device == 0x010A) 1289 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1290 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1291 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1292 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1293 ((dev)->pci_device & 0xFF00) == 0x0A00) 1294 1295 /* 1296 * The genX designation typically refers to the render engine, so render 1297 * capability related checks should use IS_GEN, while display and other checks 1298 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1299 * chips, etc.). 1300 */ 1301 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1302 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1303 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1304 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1305 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1306 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1307 1308 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1309 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1310 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1311 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1312 1313 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1314 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1315 1316 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1317 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1318 1319 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1320 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1321 1322 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1323 * rows, which changed the alignment requirements and fence programming. 1324 */ 1325 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1326 IS_I915GM(dev))) 1327 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1328 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1329 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1330 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1331 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1332 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1333 /* dsparb controlled by hw only */ 1334 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1335 1336 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1337 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1338 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1339 1340 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1341 1342 #define HAS_DDI(dev) (IS_HASWELL(dev)) 1343 1344 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1345 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1346 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1347 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1348 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1349 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1350 1351 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1352 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1353 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1354 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1355 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1356 1357 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1358 1359 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1360 1361 #define GT_FREQUENCY_MULTIPLIER 50 1362 1363 #include "i915_trace.h" 1364 1365 /** 1366 * RC6 is a special power stage which allows the GPU to enter an very 1367 * low-voltage mode when idle, using down to 0V while at this stage. This 1368 * stage is entered automatically when the GPU is idle when RC6 support is 1369 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1370 * 1371 * There are different RC6 modes available in Intel GPU, which differentiate 1372 * among each other with the latency required to enter and leave RC6 and 1373 * voltage consumed by the GPU in different states. 1374 * 1375 * The combination of the following flags define which states GPU is allowed 1376 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1377 * RC6pp is deepest RC6. Their support by hardware varies according to the 1378 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1379 * which brings the most power savings; deeper states save more power, but 1380 * require higher latency to switch to and wake up. 1381 */ 1382 #define INTEL_RC6_ENABLE (1<<0) 1383 #define INTEL_RC6p_ENABLE (1<<1) 1384 #define INTEL_RC6pp_ENABLE (1<<2) 1385 1386 extern struct drm_ioctl_desc i915_ioctls[]; 1387 extern int i915_max_ioctl; 1388 extern unsigned int i915_fbpercrtc __always_unused; 1389 extern int i915_panel_ignore_lid __read_mostly; 1390 extern unsigned int i915_powersave __read_mostly; 1391 extern int i915_semaphores __read_mostly; 1392 extern unsigned int i915_lvds_downclock __read_mostly; 1393 extern int i915_lvds_channel_mode __read_mostly; 1394 extern int i915_panel_use_ssc __read_mostly; 1395 extern int i915_vbt_sdvo_panel_type __read_mostly; 1396 extern int i915_enable_rc6 __read_mostly; 1397 extern int i915_enable_fbc __read_mostly; 1398 extern bool i915_enable_hangcheck __read_mostly; 1399 extern int i915_enable_ppgtt __read_mostly; 1400 extern unsigned int i915_preliminary_hw_support __read_mostly; 1401 1402 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1403 extern int i915_resume(struct drm_device *dev); 1404 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1405 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1406 1407 /* i915_dma.c */ 1408 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1409 extern void i915_kernel_lost_context(struct drm_device * dev); 1410 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1411 extern int i915_driver_unload(struct drm_device *); 1412 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1413 extern void i915_driver_lastclose(struct drm_device * dev); 1414 extern void i915_driver_preclose(struct drm_device *dev, 1415 struct drm_file *file_priv); 1416 extern void i915_driver_postclose(struct drm_device *dev, 1417 struct drm_file *file_priv); 1418 extern int i915_driver_device_is_agp(struct drm_device * dev); 1419 #ifdef CONFIG_COMPAT 1420 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1421 unsigned long arg); 1422 #endif 1423 extern int i915_emit_box(struct drm_device *dev, 1424 struct drm_clip_rect *box, 1425 int DR1, int DR4); 1426 extern int intel_gpu_reset(struct drm_device *dev); 1427 extern int i915_reset(struct drm_device *dev); 1428 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1429 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1430 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1431 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1432 1433 extern void intel_console_resume(struct work_struct *work); 1434 1435 /* i915_irq.c */ 1436 void i915_hangcheck_elapsed(unsigned long data); 1437 void i915_handle_error(struct drm_device *dev, bool wedged); 1438 1439 extern void intel_irq_init(struct drm_device *dev); 1440 extern void intel_hpd_init(struct drm_device *dev); 1441 extern void intel_gt_init(struct drm_device *dev); 1442 extern void intel_gt_reset(struct drm_device *dev); 1443 1444 void i915_error_state_free(struct kref *error_ref); 1445 1446 void 1447 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1448 1449 void 1450 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1451 1452 void intel_enable_asle(struct drm_device *dev); 1453 1454 #ifdef CONFIG_DEBUG_FS 1455 extern void i915_destroy_error_state(struct drm_device *dev); 1456 #else 1457 #define i915_destroy_error_state(x) 1458 #endif 1459 1460 1461 /* i915_gem.c */ 1462 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1463 struct drm_file *file_priv); 1464 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1465 struct drm_file *file_priv); 1466 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1467 struct drm_file *file_priv); 1468 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1469 struct drm_file *file_priv); 1470 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1471 struct drm_file *file_priv); 1472 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1473 struct drm_file *file_priv); 1474 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1475 struct drm_file *file_priv); 1476 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1477 struct drm_file *file_priv); 1478 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1479 struct drm_file *file_priv); 1480 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1481 struct drm_file *file_priv); 1482 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1483 struct drm_file *file_priv); 1484 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1485 struct drm_file *file_priv); 1486 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1487 struct drm_file *file_priv); 1488 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1489 struct drm_file *file); 1490 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1491 struct drm_file *file); 1492 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1493 struct drm_file *file_priv); 1494 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1495 struct drm_file *file_priv); 1496 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1497 struct drm_file *file_priv); 1498 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1499 struct drm_file *file_priv); 1500 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1501 struct drm_file *file_priv); 1502 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1503 struct drm_file *file_priv); 1504 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1505 struct drm_file *file_priv); 1506 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1507 struct drm_file *file_priv); 1508 void i915_gem_load(struct drm_device *dev); 1509 void *i915_gem_object_alloc(struct drm_device *dev); 1510 void i915_gem_object_free(struct drm_i915_gem_object *obj); 1511 int i915_gem_init_object(struct drm_gem_object *obj); 1512 void i915_gem_object_init(struct drm_i915_gem_object *obj, 1513 const struct drm_i915_gem_object_ops *ops); 1514 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1515 size_t size); 1516 void i915_gem_free_object(struct drm_gem_object *obj); 1517 1518 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1519 uint32_t alignment, 1520 bool map_and_fenceable, 1521 bool nonblocking); 1522 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1523 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1524 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 1525 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1526 void i915_gem_lastclose(struct drm_device *dev); 1527 1528 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 1529 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 1530 { 1531 struct scatterlist *sg = obj->pages->sgl; 1532 int nents = obj->pages->nents; 1533 while (nents > SG_MAX_SINGLE_ALLOC) { 1534 if (n < SG_MAX_SINGLE_ALLOC - 1) 1535 break; 1536 1537 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); 1538 n -= SG_MAX_SINGLE_ALLOC - 1; 1539 nents -= SG_MAX_SINGLE_ALLOC - 1; 1540 } 1541 return sg_page(sg+n); 1542 } 1543 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1544 { 1545 BUG_ON(obj->pages == NULL); 1546 obj->pages_pin_count++; 1547 } 1548 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1549 { 1550 BUG_ON(obj->pages_pin_count == 0); 1551 obj->pages_pin_count--; 1552 } 1553 1554 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1555 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1556 struct intel_ring_buffer *to); 1557 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1558 struct intel_ring_buffer *ring); 1559 1560 int i915_gem_dumb_create(struct drm_file *file_priv, 1561 struct drm_device *dev, 1562 struct drm_mode_create_dumb *args); 1563 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1564 uint32_t handle, uint64_t *offset); 1565 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1566 uint32_t handle); 1567 /** 1568 * Returns true if seq1 is later than seq2. 1569 */ 1570 static inline bool 1571 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1572 { 1573 return (int32_t)(seq1 - seq2) >= 0; 1574 } 1575 1576 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1577 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 1578 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1579 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1580 1581 static inline bool 1582 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1583 { 1584 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1585 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1586 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1587 return true; 1588 } else 1589 return false; 1590 } 1591 1592 static inline void 1593 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1594 { 1595 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1596 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1597 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1598 } 1599 } 1600 1601 void i915_gem_retire_requests(struct drm_device *dev); 1602 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1603 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 1604 bool interruptible); 1605 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 1606 { 1607 return unlikely(atomic_read(&error->reset_counter) 1608 & I915_RESET_IN_PROGRESS_FLAG); 1609 } 1610 1611 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 1612 { 1613 return atomic_read(&error->reset_counter) == I915_WEDGED; 1614 } 1615 1616 void i915_gem_reset(struct drm_device *dev); 1617 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1618 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1619 uint32_t read_domains, 1620 uint32_t write_domain); 1621 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1622 int __must_check i915_gem_init(struct drm_device *dev); 1623 int __must_check i915_gem_init_hw(struct drm_device *dev); 1624 void i915_gem_l3_remap(struct drm_device *dev); 1625 void i915_gem_init_swizzling(struct drm_device *dev); 1626 void i915_gem_init_ppgtt(struct drm_device *dev); 1627 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1628 int __must_check i915_gpu_idle(struct drm_device *dev); 1629 int __must_check i915_gem_idle(struct drm_device *dev); 1630 int i915_add_request(struct intel_ring_buffer *ring, 1631 struct drm_file *file, 1632 u32 *seqno); 1633 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1634 uint32_t seqno); 1635 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1636 int __must_check 1637 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1638 bool write); 1639 int __must_check 1640 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1641 int __must_check 1642 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1643 u32 alignment, 1644 struct intel_ring_buffer *pipelined); 1645 int i915_gem_attach_phys_object(struct drm_device *dev, 1646 struct drm_i915_gem_object *obj, 1647 int id, 1648 int align); 1649 void i915_gem_detach_phys_object(struct drm_device *dev, 1650 struct drm_i915_gem_object *obj); 1651 void i915_gem_free_all_phys_object(struct drm_device *dev); 1652 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1653 1654 uint32_t 1655 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 1656 uint32_t 1657 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 1658 int tiling_mode, bool fenced); 1659 1660 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1661 enum i915_cache_level cache_level); 1662 1663 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1664 struct dma_buf *dma_buf); 1665 1666 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1667 struct drm_gem_object *gem_obj, int flags); 1668 1669 /* i915_gem_context.c */ 1670 void i915_gem_context_init(struct drm_device *dev); 1671 void i915_gem_context_fini(struct drm_device *dev); 1672 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1673 int i915_switch_context(struct intel_ring_buffer *ring, 1674 struct drm_file *file, int to_id); 1675 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1676 struct drm_file *file); 1677 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1678 struct drm_file *file); 1679 1680 /* i915_gem_gtt.c */ 1681 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1682 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1683 struct drm_i915_gem_object *obj, 1684 enum i915_cache_level cache_level); 1685 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1686 struct drm_i915_gem_object *obj); 1687 1688 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1689 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1690 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1691 enum i915_cache_level cache_level); 1692 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1693 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1694 void i915_gem_init_global_gtt(struct drm_device *dev); 1695 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 1696 unsigned long mappable_end, unsigned long end); 1697 int i915_gem_gtt_init(struct drm_device *dev); 1698 static inline void i915_gem_chipset_flush(struct drm_device *dev) 1699 { 1700 if (INTEL_INFO(dev)->gen < 6) 1701 intel_gtt_chipset_flush(); 1702 } 1703 1704 1705 /* i915_gem_evict.c */ 1706 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1707 unsigned alignment, 1708 unsigned cache_level, 1709 bool mappable, 1710 bool nonblock); 1711 int i915_gem_evict_everything(struct drm_device *dev); 1712 1713 /* i915_gem_stolen.c */ 1714 int i915_gem_init_stolen(struct drm_device *dev); 1715 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); 1716 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 1717 void i915_gem_cleanup_stolen(struct drm_device *dev); 1718 struct drm_i915_gem_object * 1719 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 1720 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 1721 1722 /* i915_gem_tiling.c */ 1723 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1724 { 1725 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 1726 1727 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1728 obj->tiling_mode != I915_TILING_NONE; 1729 } 1730 1731 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1732 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1733 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1734 1735 /* i915_gem_debug.c */ 1736 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1737 const char *where, uint32_t mark); 1738 #if WATCH_LISTS 1739 int i915_verify_lists(struct drm_device *dev); 1740 #else 1741 #define i915_verify_lists(dev) 0 1742 #endif 1743 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1744 int handle); 1745 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1746 const char *where, uint32_t mark); 1747 1748 /* i915_debugfs.c */ 1749 int i915_debugfs_init(struct drm_minor *minor); 1750 void i915_debugfs_cleanup(struct drm_minor *minor); 1751 1752 /* i915_suspend.c */ 1753 extern int i915_save_state(struct drm_device *dev); 1754 extern int i915_restore_state(struct drm_device *dev); 1755 1756 /* i915_ums.c */ 1757 void i915_save_display_reg(struct drm_device *dev); 1758 void i915_restore_display_reg(struct drm_device *dev); 1759 1760 /* i915_sysfs.c */ 1761 void i915_setup_sysfs(struct drm_device *dev_priv); 1762 void i915_teardown_sysfs(struct drm_device *dev_priv); 1763 1764 /* intel_i2c.c */ 1765 extern int intel_setup_gmbus(struct drm_device *dev); 1766 extern void intel_teardown_gmbus(struct drm_device *dev); 1767 extern inline bool intel_gmbus_is_port_valid(unsigned port) 1768 { 1769 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1770 } 1771 1772 extern struct i2c_adapter *intel_gmbus_get_adapter( 1773 struct drm_i915_private *dev_priv, unsigned port); 1774 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1775 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1776 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1777 { 1778 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1779 } 1780 extern void intel_i2c_reset(struct drm_device *dev); 1781 1782 /* intel_opregion.c */ 1783 extern int intel_opregion_setup(struct drm_device *dev); 1784 #ifdef CONFIG_ACPI 1785 extern void intel_opregion_init(struct drm_device *dev); 1786 extern void intel_opregion_fini(struct drm_device *dev); 1787 extern void intel_opregion_asle_intr(struct drm_device *dev); 1788 extern void intel_opregion_gse_intr(struct drm_device *dev); 1789 extern void intel_opregion_enable_asle(struct drm_device *dev); 1790 #else 1791 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1792 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1793 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1794 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1795 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1796 #endif 1797 1798 /* intel_acpi.c */ 1799 #ifdef CONFIG_ACPI 1800 extern void intel_register_dsm_handler(void); 1801 extern void intel_unregister_dsm_handler(void); 1802 #else 1803 static inline void intel_register_dsm_handler(void) { return; } 1804 static inline void intel_unregister_dsm_handler(void) { return; } 1805 #endif /* CONFIG_ACPI */ 1806 1807 /* modesetting */ 1808 extern void intel_modeset_init_hw(struct drm_device *dev); 1809 extern void intel_modeset_init(struct drm_device *dev); 1810 extern void intel_modeset_gem_init(struct drm_device *dev); 1811 extern void intel_modeset_cleanup(struct drm_device *dev); 1812 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1813 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 1814 bool force_restore); 1815 extern void i915_redisable_vga(struct drm_device *dev); 1816 extern bool intel_fbc_enabled(struct drm_device *dev); 1817 extern void intel_disable_fbc(struct drm_device *dev); 1818 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1819 extern void intel_init_pch_refclk(struct drm_device *dev); 1820 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1821 extern void intel_detect_pch(struct drm_device *dev); 1822 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1823 extern int intel_enable_rc6(const struct drm_device *dev); 1824 1825 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1826 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1827 struct drm_file *file); 1828 1829 /* overlay */ 1830 #ifdef CONFIG_DEBUG_FS 1831 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1832 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1833 1834 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1835 extern void intel_display_print_error_state(struct seq_file *m, 1836 struct drm_device *dev, 1837 struct intel_display_error_state *error); 1838 #endif 1839 1840 /* On SNB platform, before reading ring registers forcewake bit 1841 * must be set to prevent GT core from power down and stale values being 1842 * returned. 1843 */ 1844 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1845 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1846 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1847 1848 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1849 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1850 1851 #define __i915_read(x, y) \ 1852 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1853 1854 __i915_read(8, b) 1855 __i915_read(16, w) 1856 __i915_read(32, l) 1857 __i915_read(64, q) 1858 #undef __i915_read 1859 1860 #define __i915_write(x, y) \ 1861 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1862 1863 __i915_write(8, b) 1864 __i915_write(16, w) 1865 __i915_write(32, l) 1866 __i915_write(64, q) 1867 #undef __i915_write 1868 1869 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1870 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1871 1872 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1873 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1874 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1875 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1876 1877 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1878 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1879 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1880 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1881 1882 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1883 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1884 1885 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1886 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1887 1888 /* "Broadcast RGB" property */ 1889 #define INTEL_BROADCAST_RGB_AUTO 0 1890 #define INTEL_BROADCAST_RGB_FULL 1 1891 #define INTEL_BROADCAST_RGB_LIMITED 2 1892 1893 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 1894 { 1895 if (HAS_PCH_SPLIT(dev)) 1896 return CPU_VGACNTRL; 1897 else if (IS_VALLEYVIEW(dev)) 1898 return VLV_VGACNTRL; 1899 else 1900 return VGACNTRL; 1901 } 1902 1903 #endif 1904