1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hashtable.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/pm_qos.h> 44 #include <linux/shmem_fs.h> 45 46 #include <drm/drmP.h> 47 #include <drm/intel-gtt.h> 48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 49 #include <drm/drm_gem.h> 50 #include <drm/drm_auth.h> 51 52 #include "i915_params.h" 53 #include "i915_reg.h" 54 55 #include "intel_bios.h" 56 #include "intel_dpll_mgr.h" 57 #include "intel_guc.h" 58 #include "intel_lrc.h" 59 #include "intel_ringbuffer.h" 60 61 #include "i915_gem.h" 62 #include "i915_gem_gtt.h" 63 #include "i915_gem_render_state.h" 64 #include "i915_gem_request.h" 65 66 #include "intel_gvt.h" 67 68 /* General customization: 69 */ 70 71 #define DRIVER_NAME "i915" 72 #define DRIVER_DESC "Intel Graphics" 73 #define DRIVER_DATE "20160919" 74 75 #undef WARN_ON 76 /* Many gcc seem to no see through this and fall over :( */ 77 #if 0 78 #define WARN_ON(x) ({ \ 79 bool __i915_warn_cond = (x); \ 80 if (__builtin_constant_p(__i915_warn_cond)) \ 81 BUILD_BUG_ON(__i915_warn_cond); \ 82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) 83 #else 84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 85 #endif 86 87 #undef WARN_ON_ONCE 88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") 89 90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ 91 (long) (x), __func__); 92 93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 95 * which may not necessarily be a user visible problem. This will either 96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 97 * enable distros and users to tailor their preferred amount of i915 abrt 98 * spam. 99 */ 100 #define I915_STATE_WARN(condition, format...) ({ \ 101 int __ret_warn_on = !!(condition); \ 102 if (unlikely(__ret_warn_on)) \ 103 if (!WARN(i915.verbose_state_checks, format)) \ 104 DRM_ERROR(format); \ 105 unlikely(__ret_warn_on); \ 106 }) 107 108 #define I915_STATE_WARN_ON(x) \ 109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 110 111 bool __i915_inject_load_failure(const char *func, int line); 112 #define i915_inject_load_failure() \ 113 __i915_inject_load_failure(__func__, __LINE__) 114 115 static inline const char *yesno(bool v) 116 { 117 return v ? "yes" : "no"; 118 } 119 120 static inline const char *onoff(bool v) 121 { 122 return v ? "on" : "off"; 123 } 124 125 enum pipe { 126 INVALID_PIPE = -1, 127 PIPE_A = 0, 128 PIPE_B, 129 PIPE_C, 130 _PIPE_EDP, 131 I915_MAX_PIPES = _PIPE_EDP 132 }; 133 #define pipe_name(p) ((p) + 'A') 134 135 enum transcoder { 136 TRANSCODER_A = 0, 137 TRANSCODER_B, 138 TRANSCODER_C, 139 TRANSCODER_EDP, 140 TRANSCODER_DSI_A, 141 TRANSCODER_DSI_C, 142 I915_MAX_TRANSCODERS 143 }; 144 145 static inline const char *transcoder_name(enum transcoder transcoder) 146 { 147 switch (transcoder) { 148 case TRANSCODER_A: 149 return "A"; 150 case TRANSCODER_B: 151 return "B"; 152 case TRANSCODER_C: 153 return "C"; 154 case TRANSCODER_EDP: 155 return "EDP"; 156 case TRANSCODER_DSI_A: 157 return "DSI A"; 158 case TRANSCODER_DSI_C: 159 return "DSI C"; 160 default: 161 return "<invalid>"; 162 } 163 } 164 165 static inline bool transcoder_is_dsi(enum transcoder transcoder) 166 { 167 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 168 } 169 170 /* 171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 172 * number of planes per CRTC. Not all platforms really have this many planes, 173 * which means some arrays of size I915_MAX_PLANES may have unused entries 174 * between the topmost sprite plane and the cursor plane. 175 */ 176 enum plane { 177 PLANE_A = 0, 178 PLANE_B, 179 PLANE_C, 180 PLANE_CURSOR, 181 I915_MAX_PLANES, 182 }; 183 #define plane_name(p) ((p) + 'A') 184 185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 186 187 enum port { 188 PORT_A = 0, 189 PORT_B, 190 PORT_C, 191 PORT_D, 192 PORT_E, 193 I915_MAX_PORTS 194 }; 195 #define port_name(p) ((p) + 'A') 196 197 #define I915_NUM_PHYS_VLV 2 198 199 enum dpio_channel { 200 DPIO_CH0, 201 DPIO_CH1 202 }; 203 204 enum dpio_phy { 205 DPIO_PHY0, 206 DPIO_PHY1 207 }; 208 209 enum intel_display_power_domain { 210 POWER_DOMAIN_PIPE_A, 211 POWER_DOMAIN_PIPE_B, 212 POWER_DOMAIN_PIPE_C, 213 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 214 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 215 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 216 POWER_DOMAIN_TRANSCODER_A, 217 POWER_DOMAIN_TRANSCODER_B, 218 POWER_DOMAIN_TRANSCODER_C, 219 POWER_DOMAIN_TRANSCODER_EDP, 220 POWER_DOMAIN_TRANSCODER_DSI_A, 221 POWER_DOMAIN_TRANSCODER_DSI_C, 222 POWER_DOMAIN_PORT_DDI_A_LANES, 223 POWER_DOMAIN_PORT_DDI_B_LANES, 224 POWER_DOMAIN_PORT_DDI_C_LANES, 225 POWER_DOMAIN_PORT_DDI_D_LANES, 226 POWER_DOMAIN_PORT_DDI_E_LANES, 227 POWER_DOMAIN_PORT_DSI, 228 POWER_DOMAIN_PORT_CRT, 229 POWER_DOMAIN_PORT_OTHER, 230 POWER_DOMAIN_VGA, 231 POWER_DOMAIN_AUDIO, 232 POWER_DOMAIN_PLLS, 233 POWER_DOMAIN_AUX_A, 234 POWER_DOMAIN_AUX_B, 235 POWER_DOMAIN_AUX_C, 236 POWER_DOMAIN_AUX_D, 237 POWER_DOMAIN_GMBUS, 238 POWER_DOMAIN_MODESET, 239 POWER_DOMAIN_INIT, 240 241 POWER_DOMAIN_NUM, 242 }; 243 244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 247 #define POWER_DOMAIN_TRANSCODER(tran) \ 248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 249 (tran) + POWER_DOMAIN_TRANSCODER_A) 250 251 enum hpd_pin { 252 HPD_NONE = 0, 253 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 254 HPD_CRT, 255 HPD_SDVO_B, 256 HPD_SDVO_C, 257 HPD_PORT_A, 258 HPD_PORT_B, 259 HPD_PORT_C, 260 HPD_PORT_D, 261 HPD_PORT_E, 262 HPD_NUM_PINS 263 }; 264 265 #define for_each_hpd_pin(__pin) \ 266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 267 268 struct i915_hotplug { 269 struct work_struct hotplug_work; 270 271 struct { 272 unsigned long last_jiffies; 273 int count; 274 enum { 275 HPD_ENABLED = 0, 276 HPD_DISABLED = 1, 277 HPD_MARK_DISABLED = 2 278 } state; 279 } stats[HPD_NUM_PINS]; 280 u32 event_bits; 281 struct delayed_work reenable_work; 282 283 struct intel_digital_port *irq_port[I915_MAX_PORTS]; 284 u32 long_port_mask; 285 u32 short_port_mask; 286 struct work_struct dig_port_work; 287 288 struct work_struct poll_init_work; 289 bool poll_enabled; 290 291 /* 292 * if we get a HPD irq from DP and a HPD irq from non-DP 293 * the non-DP HPD could block the workqueue on a mode config 294 * mutex getting, that userspace may have taken. However 295 * userspace is waiting on the DP workqueue to run which is 296 * blocked behind the non-DP one. 297 */ 298 struct workqueue_struct *dp_wq; 299 }; 300 301 #define I915_GEM_GPU_DOMAINS \ 302 (I915_GEM_DOMAIN_RENDER | \ 303 I915_GEM_DOMAIN_SAMPLER | \ 304 I915_GEM_DOMAIN_COMMAND | \ 305 I915_GEM_DOMAIN_INSTRUCTION | \ 306 I915_GEM_DOMAIN_VERTEX) 307 308 #define for_each_pipe(__dev_priv, __p) \ 309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ 312 for_each_if ((__mask) & (1 << (__p))) 313 #define for_each_plane(__dev_priv, __pipe, __p) \ 314 for ((__p) = 0; \ 315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 316 (__p)++) 317 #define for_each_sprite(__dev_priv, __p, __s) \ 318 for ((__s) = 0; \ 319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ 320 (__s)++) 321 322 #define for_each_port_masked(__port, __ports_mask) \ 323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ 324 for_each_if ((__ports_mask) & (1 << (__port))) 325 326 #define for_each_crtc(dev, crtc) \ 327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 328 329 #define for_each_intel_plane(dev, intel_plane) \ 330 list_for_each_entry(intel_plane, \ 331 &(dev)->mode_config.plane_list, \ 332 base.head) 333 334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 335 list_for_each_entry(intel_plane, \ 336 &(dev)->mode_config.plane_list, \ 337 base.head) \ 338 for_each_if ((plane_mask) & \ 339 (1 << drm_plane_index(&intel_plane->base))) 340 341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 342 list_for_each_entry(intel_plane, \ 343 &(dev)->mode_config.plane_list, \ 344 base.head) \ 345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) 346 347 #define for_each_intel_crtc(dev, intel_crtc) \ 348 list_for_each_entry(intel_crtc, \ 349 &(dev)->mode_config.crtc_list, \ 350 base.head) 351 352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 353 list_for_each_entry(intel_crtc, \ 354 &(dev)->mode_config.crtc_list, \ 355 base.head) \ 356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) 357 358 #define for_each_intel_encoder(dev, intel_encoder) \ 359 list_for_each_entry(intel_encoder, \ 360 &(dev)->mode_config.encoder_list, \ 361 base.head) 362 363 #define for_each_intel_connector(dev, intel_connector) \ 364 list_for_each_entry(intel_connector, \ 365 &(dev)->mode_config.connector_list, \ 366 base.head) 367 368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 370 for_each_if ((intel_encoder)->base.crtc == (__crtc)) 371 372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 374 for_each_if ((intel_connector)->base.encoder == (__encoder)) 375 376 #define for_each_power_domain(domain, mask) \ 377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 378 for_each_if ((1 << (domain)) & (mask)) 379 380 struct drm_i915_private; 381 struct i915_mm_struct; 382 struct i915_mmu_object; 383 384 struct drm_i915_file_private { 385 struct drm_i915_private *dev_priv; 386 struct drm_file *file; 387 388 struct { 389 spinlock_t lock; 390 struct list_head request_list; 391 /* 20ms is a fairly arbitrary limit (greater than the average frame time) 392 * chosen to prevent the CPU getting more than a frame ahead of the GPU 393 * (when using lax throttling for the frontbuffer). We also use it to 394 * offer free GPU waitboosts for severely congested workloads. 395 */ 396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) 397 } mm; 398 struct idr context_idr; 399 400 struct intel_rps_client { 401 struct list_head link; 402 unsigned boosts; 403 } rps; 404 405 unsigned int bsd_engine; 406 }; 407 408 /* Used by dp and fdi links */ 409 struct intel_link_m_n { 410 uint32_t tu; 411 uint32_t gmch_m; 412 uint32_t gmch_n; 413 uint32_t link_m; 414 uint32_t link_n; 415 }; 416 417 void intel_link_compute_m_n(int bpp, int nlanes, 418 int pixel_clock, int link_clock, 419 struct intel_link_m_n *m_n); 420 421 /* Interface history: 422 * 423 * 1.1: Original. 424 * 1.2: Add Power Management 425 * 1.3: Add vblank support 426 * 1.4: Fix cmdbuffer path, add heap destroy 427 * 1.5: Add vblank pipe configuration 428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 429 * - Support vertical blank on secondary display pipe 430 */ 431 #define DRIVER_MAJOR 1 432 #define DRIVER_MINOR 6 433 #define DRIVER_PATCHLEVEL 0 434 435 struct opregion_header; 436 struct opregion_acpi; 437 struct opregion_swsci; 438 struct opregion_asle; 439 440 struct intel_opregion { 441 struct opregion_header *header; 442 struct opregion_acpi *acpi; 443 struct opregion_swsci *swsci; 444 u32 swsci_gbda_sub_functions; 445 u32 swsci_sbcb_sub_functions; 446 struct opregion_asle *asle; 447 void *rvda; 448 const void *vbt; 449 u32 vbt_size; 450 u32 *lid_state; 451 struct work_struct asle_work; 452 }; 453 #define OPREGION_SIZE (8*1024) 454 455 struct intel_overlay; 456 struct intel_overlay_error_state; 457 458 struct drm_i915_fence_reg { 459 struct list_head link; 460 struct drm_i915_private *i915; 461 struct i915_vma *vma; 462 int pin_count; 463 int id; 464 /** 465 * Whether the tiling parameters for the currently 466 * associated fence register have changed. Note that 467 * for the purposes of tracking tiling changes we also 468 * treat the unfenced register, the register slot that 469 * the object occupies whilst it executes a fenced 470 * command (such as BLT on gen2/3), as a "fence". 471 */ 472 bool dirty; 473 }; 474 475 struct sdvo_device_mapping { 476 u8 initialized; 477 u8 dvo_port; 478 u8 slave_addr; 479 u8 dvo_wiring; 480 u8 i2c_pin; 481 u8 ddc_pin; 482 }; 483 484 struct intel_connector; 485 struct intel_encoder; 486 struct intel_crtc_state; 487 struct intel_initial_plane_config; 488 struct intel_crtc; 489 struct intel_limit; 490 struct dpll; 491 492 struct drm_i915_display_funcs { 493 int (*get_display_clock_speed)(struct drm_device *dev); 494 int (*get_fifo_size)(struct drm_device *dev, int plane); 495 int (*compute_pipe_wm)(struct intel_crtc_state *cstate); 496 int (*compute_intermediate_wm)(struct drm_device *dev, 497 struct intel_crtc *intel_crtc, 498 struct intel_crtc_state *newstate); 499 void (*initial_watermarks)(struct intel_crtc_state *cstate); 500 void (*optimize_watermarks)(struct intel_crtc_state *cstate); 501 int (*compute_global_watermarks)(struct drm_atomic_state *state); 502 void (*update_wm)(struct drm_crtc *crtc); 503 int (*modeset_calc_cdclk)(struct drm_atomic_state *state); 504 void (*modeset_commit_cdclk)(struct drm_atomic_state *state); 505 /* Returns the active state of the crtc, and if the crtc is active, 506 * fills out the pipe-config with the hw state. */ 507 bool (*get_pipe_config)(struct intel_crtc *, 508 struct intel_crtc_state *); 509 void (*get_initial_plane_config)(struct intel_crtc *, 510 struct intel_initial_plane_config *); 511 int (*crtc_compute_clock)(struct intel_crtc *crtc, 512 struct intel_crtc_state *crtc_state); 513 void (*crtc_enable)(struct intel_crtc_state *pipe_config, 514 struct drm_atomic_state *old_state); 515 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, 516 struct drm_atomic_state *old_state); 517 void (*update_crtcs)(struct drm_atomic_state *state, 518 unsigned int *crtc_vblank_mask); 519 void (*audio_codec_enable)(struct drm_connector *connector, 520 struct intel_encoder *encoder, 521 const struct drm_display_mode *adjusted_mode); 522 void (*audio_codec_disable)(struct intel_encoder *encoder); 523 void (*fdi_link_train)(struct drm_crtc *crtc); 524 void (*init_clock_gating)(struct drm_device *dev); 525 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 526 struct drm_framebuffer *fb, 527 struct drm_i915_gem_object *obj, 528 struct drm_i915_gem_request *req, 529 uint32_t flags); 530 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 531 /* clock updates for mode set */ 532 /* cursor updates */ 533 /* render clock increase/decrease */ 534 /* display clock increase/decrease */ 535 /* pll clock increase/decrease */ 536 537 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); 538 void (*load_luts)(struct drm_crtc_state *crtc_state); 539 }; 540 541 enum forcewake_domain_id { 542 FW_DOMAIN_ID_RENDER = 0, 543 FW_DOMAIN_ID_BLITTER, 544 FW_DOMAIN_ID_MEDIA, 545 546 FW_DOMAIN_ID_COUNT 547 }; 548 549 enum forcewake_domains { 550 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), 551 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), 552 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), 553 FORCEWAKE_ALL = (FORCEWAKE_RENDER | 554 FORCEWAKE_BLITTER | 555 FORCEWAKE_MEDIA) 556 }; 557 558 #define FW_REG_READ (1) 559 #define FW_REG_WRITE (2) 560 561 enum forcewake_domains 562 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, 563 i915_reg_t reg, unsigned int op); 564 565 struct intel_uncore_funcs { 566 void (*force_wake_get)(struct drm_i915_private *dev_priv, 567 enum forcewake_domains domains); 568 void (*force_wake_put)(struct drm_i915_private *dev_priv, 569 enum forcewake_domains domains); 570 571 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); 572 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); 573 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); 574 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); 575 576 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, 577 uint8_t val, bool trace); 578 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, 579 uint16_t val, bool trace); 580 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, 581 uint32_t val, bool trace); 582 }; 583 584 struct intel_uncore { 585 spinlock_t lock; /** lock is also taken in irq contexts. */ 586 587 struct intel_uncore_funcs funcs; 588 589 unsigned fifo_count; 590 enum forcewake_domains fw_domains; 591 592 struct intel_uncore_forcewake_domain { 593 struct drm_i915_private *i915; 594 enum forcewake_domain_id id; 595 enum forcewake_domains mask; 596 unsigned wake_count; 597 struct hrtimer timer; 598 i915_reg_t reg_set; 599 u32 val_set; 600 u32 val_clear; 601 i915_reg_t reg_ack; 602 i915_reg_t reg_post; 603 u32 val_reset; 604 } fw_domain[FW_DOMAIN_ID_COUNT]; 605 606 int unclaimed_mmio_check; 607 }; 608 609 /* Iterate over initialised fw domains */ 610 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ 611 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ 612 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ 613 (domain__)++) \ 614 for_each_if ((mask__) & (domain__)->mask) 615 616 #define for_each_fw_domain(domain__, dev_priv__) \ 617 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) 618 619 #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) 620 #define CSR_VERSION_MAJOR(version) ((version) >> 16) 621 #define CSR_VERSION_MINOR(version) ((version) & 0xffff) 622 623 struct intel_csr { 624 struct work_struct work; 625 const char *fw_path; 626 uint32_t *dmc_payload; 627 uint32_t dmc_fw_size; 628 uint32_t version; 629 uint32_t mmio_count; 630 i915_reg_t mmioaddr[8]; 631 uint32_t mmiodata[8]; 632 uint32_t dc_state; 633 uint32_t allowed_dc_mask; 634 }; 635 636 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 637 func(is_mobile) sep \ 638 func(is_i85x) sep \ 639 func(is_i915g) sep \ 640 func(is_i945gm) sep \ 641 func(is_g33) sep \ 642 func(hws_needs_physical) sep \ 643 func(is_g4x) sep \ 644 func(is_pineview) sep \ 645 func(is_broadwater) sep \ 646 func(is_crestline) sep \ 647 func(is_ivybridge) sep \ 648 func(is_valleyview) sep \ 649 func(is_cherryview) sep \ 650 func(is_haswell) sep \ 651 func(is_broadwell) sep \ 652 func(is_skylake) sep \ 653 func(is_broxton) sep \ 654 func(is_kabylake) sep \ 655 func(is_preliminary) sep \ 656 func(has_fbc) sep \ 657 func(has_psr) sep \ 658 func(has_runtime_pm) sep \ 659 func(has_csr) sep \ 660 func(has_resource_streamer) sep \ 661 func(has_rc6) sep \ 662 func(has_rc6p) sep \ 663 func(has_dp_mst) sep \ 664 func(has_gmbus_irq) sep \ 665 func(has_hw_contexts) sep \ 666 func(has_logical_ring_contexts) sep \ 667 func(has_l3_dpf) sep \ 668 func(has_gmch_display) sep \ 669 func(has_guc) sep \ 670 func(has_pipe_cxsr) sep \ 671 func(has_hotplug) sep \ 672 func(cursor_needs_physical) sep \ 673 func(has_overlay) sep \ 674 func(overlay_needs_physical) sep \ 675 func(supports_tv) sep \ 676 func(has_llc) sep \ 677 func(has_snoop) sep \ 678 func(has_ddi) sep \ 679 func(has_fpga_dbg) sep \ 680 func(has_pooled_eu) 681 682 #define DEFINE_FLAG(name) u8 name:1 683 #define SEP_SEMICOLON ; 684 685 struct sseu_dev_info { 686 u8 slice_mask; 687 u8 subslice_mask; 688 u8 eu_total; 689 u8 eu_per_subslice; 690 u8 min_eu_in_pool; 691 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 692 u8 subslice_7eu[3]; 693 u8 has_slice_pg:1; 694 u8 has_subslice_pg:1; 695 u8 has_eu_pg:1; 696 }; 697 698 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) 699 { 700 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); 701 } 702 703 struct intel_device_info { 704 u32 display_mmio_offset; 705 u16 device_id; 706 u8 num_pipes; 707 u8 num_sprites[I915_MAX_PIPES]; 708 u8 gen; 709 u16 gen_mask; 710 u8 ring_mask; /* Rings supported by the HW */ 711 u8 num_rings; 712 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 713 u16 ddb_size; /* in blocks */ 714 /* Register offsets for the various display pipes and transcoders */ 715 int pipe_offsets[I915_MAX_TRANSCODERS]; 716 int trans_offsets[I915_MAX_TRANSCODERS]; 717 int palette_offsets[I915_MAX_PIPES]; 718 int cursor_offsets[I915_MAX_PIPES]; 719 720 /* Slice/subslice/EU info */ 721 struct sseu_dev_info sseu; 722 723 struct color_luts { 724 u16 degamma_lut_size; 725 u16 gamma_lut_size; 726 } color; 727 }; 728 729 #undef DEFINE_FLAG 730 #undef SEP_SEMICOLON 731 732 struct intel_display_error_state; 733 734 struct drm_i915_error_state { 735 struct kref ref; 736 struct timeval time; 737 738 char error_msg[128]; 739 bool simulated; 740 int iommu; 741 u32 reset_count; 742 u32 suspend_count; 743 struct intel_device_info device_info; 744 745 /* Generic register state */ 746 u32 eir; 747 u32 pgtbl_er; 748 u32 ier; 749 u32 gtier[4]; 750 u32 ccid; 751 u32 derrmr; 752 u32 forcewake; 753 u32 error; /* gen6+ */ 754 u32 err_int; /* gen7 */ 755 u32 fault_data0; /* gen8, gen9 */ 756 u32 fault_data1; /* gen8, gen9 */ 757 u32 done_reg; 758 u32 gac_eco; 759 u32 gam_ecochk; 760 u32 gab_ctl; 761 u32 gfx_mode; 762 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 763 u64 fence[I915_MAX_NUM_FENCES]; 764 struct intel_overlay_error_state *overlay; 765 struct intel_display_error_state *display; 766 struct drm_i915_error_object *semaphore; 767 768 struct drm_i915_error_engine { 769 int engine_id; 770 /* Software tracked state */ 771 bool waiting; 772 int num_waiters; 773 int hangcheck_score; 774 enum intel_engine_hangcheck_action hangcheck_action; 775 struct i915_address_space *vm; 776 int num_requests; 777 778 /* our own tracking of ring head and tail */ 779 u32 cpu_ring_head; 780 u32 cpu_ring_tail; 781 782 u32 last_seqno; 783 u32 semaphore_seqno[I915_NUM_ENGINES - 1]; 784 785 /* Register state */ 786 u32 start; 787 u32 tail; 788 u32 head; 789 u32 ctl; 790 u32 mode; 791 u32 hws; 792 u32 ipeir; 793 u32 ipehr; 794 u32 instdone; 795 u32 bbstate; 796 u32 instpm; 797 u32 instps; 798 u32 seqno; 799 u64 bbaddr; 800 u64 acthd; 801 u32 fault_reg; 802 u64 faddr; 803 u32 rc_psmi; /* sleep state */ 804 u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; 805 806 struct drm_i915_error_object { 807 int page_count; 808 u64 gtt_offset; 809 u64 gtt_size; 810 u32 *pages[0]; 811 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 812 813 struct drm_i915_error_object *wa_ctx; 814 815 struct drm_i915_error_request { 816 long jiffies; 817 pid_t pid; 818 u32 seqno; 819 u32 head; 820 u32 tail; 821 } *requests; 822 823 struct drm_i915_error_waiter { 824 char comm[TASK_COMM_LEN]; 825 pid_t pid; 826 u32 seqno; 827 } *waiters; 828 829 struct { 830 u32 gfx_mode; 831 union { 832 u64 pdp[4]; 833 u32 pp_dir_base; 834 }; 835 } vm_info; 836 837 pid_t pid; 838 char comm[TASK_COMM_LEN]; 839 } engine[I915_NUM_ENGINES]; 840 841 struct drm_i915_error_buffer { 842 u32 size; 843 u32 name; 844 u32 rseqno[I915_NUM_ENGINES], wseqno; 845 u64 gtt_offset; 846 u32 read_domains; 847 u32 write_domain; 848 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 849 u32 tiling:2; 850 u32 dirty:1; 851 u32 purgeable:1; 852 u32 userptr:1; 853 s32 engine:4; 854 u32 cache_level:3; 855 } *active_bo[I915_NUM_ENGINES], *pinned_bo; 856 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; 857 struct i915_address_space *active_vm[I915_NUM_ENGINES]; 858 }; 859 860 enum i915_cache_level { 861 I915_CACHE_NONE = 0, 862 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 863 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 864 caches, eg sampler/render caches, and the 865 large Last-Level-Cache. LLC is coherent with 866 the CPU, but L3 is only visible to the GPU. */ 867 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 868 }; 869 870 struct i915_ctx_hang_stats { 871 /* This context had batch pending when hang was declared */ 872 unsigned batch_pending; 873 874 /* This context had batch active when hang was declared */ 875 unsigned batch_active; 876 877 /* Time when this context was last blamed for a GPU reset */ 878 unsigned long guilty_ts; 879 880 /* If the contexts causes a second GPU hang within this time, 881 * it is permanently banned from submitting any more work. 882 */ 883 unsigned long ban_period_seconds; 884 885 /* This context is banned to submit more work */ 886 bool banned; 887 }; 888 889 /* This must match up with the value previously used for execbuf2.rsvd1. */ 890 #define DEFAULT_CONTEXT_HANDLE 0 891 892 /** 893 * struct i915_gem_context - as the name implies, represents a context. 894 * @ref: reference count. 895 * @user_handle: userspace tracking identity for this context. 896 * @remap_slice: l3 row remapping information. 897 * @flags: context specific flags: 898 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. 899 * @file_priv: filp associated with this context (NULL for global default 900 * context). 901 * @hang_stats: information about the role of this context in possible GPU 902 * hangs. 903 * @ppgtt: virtual memory space used by this context. 904 * @legacy_hw_ctx: render context backing object and whether it is correctly 905 * initialized (legacy ring submission mechanism only). 906 * @link: link in the global list of contexts. 907 * 908 * Contexts are memory images used by the hardware to store copies of their 909 * internal state. 910 */ 911 struct i915_gem_context { 912 struct kref ref; 913 struct drm_i915_private *i915; 914 struct drm_i915_file_private *file_priv; 915 struct i915_hw_ppgtt *ppgtt; 916 struct pid *pid; 917 918 struct i915_ctx_hang_stats hang_stats; 919 920 unsigned long flags; 921 #define CONTEXT_NO_ZEROMAP BIT(0) 922 #define CONTEXT_NO_ERROR_CAPTURE BIT(1) 923 924 /* Unique identifier for this context, used by the hw for tracking */ 925 unsigned int hw_id; 926 u32 user_handle; 927 928 u32 ggtt_alignment; 929 930 struct intel_context { 931 struct i915_vma *state; 932 struct intel_ring *ring; 933 uint32_t *lrc_reg_state; 934 u64 lrc_desc; 935 int pin_count; 936 bool initialised; 937 } engine[I915_NUM_ENGINES]; 938 u32 ring_size; 939 u32 desc_template; 940 struct atomic_notifier_head status_notifier; 941 bool execlists_force_single_submission; 942 943 struct list_head link; 944 945 u8 remap_slice; 946 bool closed:1; 947 }; 948 949 enum fb_op_origin { 950 ORIGIN_GTT, 951 ORIGIN_CPU, 952 ORIGIN_CS, 953 ORIGIN_FLIP, 954 ORIGIN_DIRTYFB, 955 }; 956 957 struct intel_fbc { 958 /* This is always the inner lock when overlapping with struct_mutex and 959 * it's the outer lock when overlapping with stolen_lock. */ 960 struct mutex lock; 961 unsigned threshold; 962 unsigned int possible_framebuffer_bits; 963 unsigned int busy_bits; 964 unsigned int visible_pipes_mask; 965 struct intel_crtc *crtc; 966 967 struct drm_mm_node compressed_fb; 968 struct drm_mm_node *compressed_llb; 969 970 bool false_color; 971 972 bool enabled; 973 bool active; 974 975 struct intel_fbc_state_cache { 976 struct { 977 unsigned int mode_flags; 978 uint32_t hsw_bdw_pixel_rate; 979 } crtc; 980 981 struct { 982 unsigned int rotation; 983 int src_w; 984 int src_h; 985 bool visible; 986 } plane; 987 988 struct { 989 u64 ilk_ggtt_offset; 990 uint32_t pixel_format; 991 unsigned int stride; 992 int fence_reg; 993 unsigned int tiling_mode; 994 } fb; 995 } state_cache; 996 997 struct intel_fbc_reg_params { 998 struct { 999 enum pipe pipe; 1000 enum plane plane; 1001 unsigned int fence_y_offset; 1002 } crtc; 1003 1004 struct { 1005 u64 ggtt_offset; 1006 uint32_t pixel_format; 1007 unsigned int stride; 1008 int fence_reg; 1009 } fb; 1010 1011 int cfb_size; 1012 } params; 1013 1014 struct intel_fbc_work { 1015 bool scheduled; 1016 u32 scheduled_vblank; 1017 struct work_struct work; 1018 } work; 1019 1020 const char *no_fbc_reason; 1021 }; 1022 1023 /** 1024 * HIGH_RR is the highest eDP panel refresh rate read from EDID 1025 * LOW_RR is the lowest eDP panel refresh rate found from EDID 1026 * parsing for same resolution. 1027 */ 1028 enum drrs_refresh_rate_type { 1029 DRRS_HIGH_RR, 1030 DRRS_LOW_RR, 1031 DRRS_MAX_RR, /* RR count */ 1032 }; 1033 1034 enum drrs_support_type { 1035 DRRS_NOT_SUPPORTED = 0, 1036 STATIC_DRRS_SUPPORT = 1, 1037 SEAMLESS_DRRS_SUPPORT = 2 1038 }; 1039 1040 struct intel_dp; 1041 struct i915_drrs { 1042 struct mutex mutex; 1043 struct delayed_work work; 1044 struct intel_dp *dp; 1045 unsigned busy_frontbuffer_bits; 1046 enum drrs_refresh_rate_type refresh_rate_type; 1047 enum drrs_support_type type; 1048 }; 1049 1050 struct i915_psr { 1051 struct mutex lock; 1052 bool sink_support; 1053 bool source_ok; 1054 struct intel_dp *enabled; 1055 bool active; 1056 struct delayed_work work; 1057 unsigned busy_frontbuffer_bits; 1058 bool psr2_support; 1059 bool aux_frame_sync; 1060 bool link_standby; 1061 }; 1062 1063 enum intel_pch { 1064 PCH_NONE = 0, /* No PCH present */ 1065 PCH_IBX, /* Ibexpeak PCH */ 1066 PCH_CPT, /* Cougarpoint PCH */ 1067 PCH_LPT, /* Lynxpoint PCH */ 1068 PCH_SPT, /* Sunrisepoint PCH */ 1069 PCH_KBP, /* Kabypoint PCH */ 1070 PCH_NOP, 1071 }; 1072 1073 enum intel_sbi_destination { 1074 SBI_ICLK, 1075 SBI_MPHY, 1076 }; 1077 1078 #define QUIRK_PIPEA_FORCE (1<<0) 1079 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 1080 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 1081 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 1082 #define QUIRK_PIPEB_FORCE (1<<4) 1083 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 1084 1085 struct intel_fbdev; 1086 struct intel_fbc_work; 1087 1088 struct intel_gmbus { 1089 struct i2c_adapter adapter; 1090 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 1091 u32 force_bit; 1092 u32 reg0; 1093 i915_reg_t gpio_reg; 1094 struct i2c_algo_bit_data bit_algo; 1095 struct drm_i915_private *dev_priv; 1096 }; 1097 1098 struct i915_suspend_saved_registers { 1099 u32 saveDSPARB; 1100 u32 saveFBC_CONTROL; 1101 u32 saveCACHE_MODE_0; 1102 u32 saveMI_ARB_STATE; 1103 u32 saveSWF0[16]; 1104 u32 saveSWF1[16]; 1105 u32 saveSWF3[3]; 1106 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 1107 u32 savePCH_PORT_HOTPLUG; 1108 u16 saveGCDGMBUS; 1109 }; 1110 1111 struct vlv_s0ix_state { 1112 /* GAM */ 1113 u32 wr_watermark; 1114 u32 gfx_prio_ctrl; 1115 u32 arb_mode; 1116 u32 gfx_pend_tlb0; 1117 u32 gfx_pend_tlb1; 1118 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 1119 u32 media_max_req_count; 1120 u32 gfx_max_req_count; 1121 u32 render_hwsp; 1122 u32 ecochk; 1123 u32 bsd_hwsp; 1124 u32 blt_hwsp; 1125 u32 tlb_rd_addr; 1126 1127 /* MBC */ 1128 u32 g3dctl; 1129 u32 gsckgctl; 1130 u32 mbctl; 1131 1132 /* GCP */ 1133 u32 ucgctl1; 1134 u32 ucgctl3; 1135 u32 rcgctl1; 1136 u32 rcgctl2; 1137 u32 rstctl; 1138 u32 misccpctl; 1139 1140 /* GPM */ 1141 u32 gfxpause; 1142 u32 rpdeuhwtc; 1143 u32 rpdeuc; 1144 u32 ecobus; 1145 u32 pwrdwnupctl; 1146 u32 rp_down_timeout; 1147 u32 rp_deucsw; 1148 u32 rcubmabdtmr; 1149 u32 rcedata; 1150 u32 spare2gh; 1151 1152 /* Display 1 CZ domain */ 1153 u32 gt_imr; 1154 u32 gt_ier; 1155 u32 pm_imr; 1156 u32 pm_ier; 1157 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 1158 1159 /* GT SA CZ domain */ 1160 u32 tilectl; 1161 u32 gt_fifoctl; 1162 u32 gtlc_wake_ctrl; 1163 u32 gtlc_survive; 1164 u32 pmwgicz; 1165 1166 /* Display 2 CZ domain */ 1167 u32 gu_ctl0; 1168 u32 gu_ctl1; 1169 u32 pcbr; 1170 u32 clock_gate_dis2; 1171 }; 1172 1173 struct intel_rps_ei { 1174 u32 cz_clock; 1175 u32 render_c0; 1176 u32 media_c0; 1177 }; 1178 1179 struct intel_gen6_power_mgmt { 1180 /* 1181 * work, interrupts_enabled and pm_iir are protected by 1182 * dev_priv->irq_lock 1183 */ 1184 struct work_struct work; 1185 bool interrupts_enabled; 1186 u32 pm_iir; 1187 1188 /* PM interrupt bits that should never be masked */ 1189 u32 pm_intr_keep; 1190 1191 /* Frequencies are stored in potentially platform dependent multiples. 1192 * In other words, *_freq needs to be multiplied by X to be interesting. 1193 * Soft limits are those which are used for the dynamic reclocking done 1194 * by the driver (raise frequencies under heavy loads, and lower for 1195 * lighter loads). Hard limits are those imposed by the hardware. 1196 * 1197 * A distinction is made for overclocking, which is never enabled by 1198 * default, and is considered to be above the hard limit if it's 1199 * possible at all. 1200 */ 1201 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 1202 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 1203 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 1204 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 1205 u8 min_freq; /* AKA RPn. Minimum frequency */ 1206 u8 boost_freq; /* Frequency to request when wait boosting */ 1207 u8 idle_freq; /* Frequency to request when we are idle */ 1208 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 1209 u8 rp1_freq; /* "less than" RP0 power/freqency */ 1210 u8 rp0_freq; /* Non-overclocked max frequency. */ 1211 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ 1212 1213 u8 up_threshold; /* Current %busy required to uplock */ 1214 u8 down_threshold; /* Current %busy required to downclock */ 1215 1216 int last_adj; 1217 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 1218 1219 spinlock_t client_lock; 1220 struct list_head clients; 1221 bool client_boost; 1222 1223 bool enabled; 1224 struct delayed_work autoenable_work; 1225 unsigned boosts; 1226 1227 /* manual wa residency calculations */ 1228 struct intel_rps_ei up_ei, down_ei; 1229 1230 /* 1231 * Protects RPS/RC6 register access and PCU communication. 1232 * Must be taken after struct_mutex if nested. Note that 1233 * this lock may be held for long periods of time when 1234 * talking to hw - so only take it when talking to hw! 1235 */ 1236 struct mutex hw_lock; 1237 }; 1238 1239 /* defined intel_pm.c */ 1240 extern spinlock_t mchdev_lock; 1241 1242 struct intel_ilk_power_mgmt { 1243 u8 cur_delay; 1244 u8 min_delay; 1245 u8 max_delay; 1246 u8 fmax; 1247 u8 fstart; 1248 1249 u64 last_count1; 1250 unsigned long last_time1; 1251 unsigned long chipset_power; 1252 u64 last_count2; 1253 u64 last_time2; 1254 unsigned long gfx_power; 1255 u8 corr; 1256 1257 int c_m; 1258 int r_t; 1259 }; 1260 1261 struct drm_i915_private; 1262 struct i915_power_well; 1263 1264 struct i915_power_well_ops { 1265 /* 1266 * Synchronize the well's hw state to match the current sw state, for 1267 * example enable/disable it based on the current refcount. Called 1268 * during driver init and resume time, possibly after first calling 1269 * the enable/disable handlers. 1270 */ 1271 void (*sync_hw)(struct drm_i915_private *dev_priv, 1272 struct i915_power_well *power_well); 1273 /* 1274 * Enable the well and resources that depend on it (for example 1275 * interrupts located on the well). Called after the 0->1 refcount 1276 * transition. 1277 */ 1278 void (*enable)(struct drm_i915_private *dev_priv, 1279 struct i915_power_well *power_well); 1280 /* 1281 * Disable the well and resources that depend on it. Called after 1282 * the 1->0 refcount transition. 1283 */ 1284 void (*disable)(struct drm_i915_private *dev_priv, 1285 struct i915_power_well *power_well); 1286 /* Returns the hw enabled state. */ 1287 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1288 struct i915_power_well *power_well); 1289 }; 1290 1291 /* Power well structure for haswell */ 1292 struct i915_power_well { 1293 const char *name; 1294 bool always_on; 1295 /* power well enable/disable usage count */ 1296 int count; 1297 /* cached hw enabled state */ 1298 bool hw_enabled; 1299 unsigned long domains; 1300 unsigned long data; 1301 const struct i915_power_well_ops *ops; 1302 }; 1303 1304 struct i915_power_domains { 1305 /* 1306 * Power wells needed for initialization at driver init and suspend 1307 * time are on. They are kept on until after the first modeset. 1308 */ 1309 bool init_power_on; 1310 bool initializing; 1311 int power_well_count; 1312 1313 struct mutex lock; 1314 int domain_use_count[POWER_DOMAIN_NUM]; 1315 struct i915_power_well *power_wells; 1316 }; 1317 1318 #define MAX_L3_SLICES 2 1319 struct intel_l3_parity { 1320 u32 *remap_info[MAX_L3_SLICES]; 1321 struct work_struct error_work; 1322 int which_slice; 1323 }; 1324 1325 struct i915_gem_mm { 1326 /** Memory allocator for GTT stolen memory */ 1327 struct drm_mm stolen; 1328 /** Protects the usage of the GTT stolen memory allocator. This is 1329 * always the inner lock when overlapping with struct_mutex. */ 1330 struct mutex stolen_lock; 1331 1332 /** List of all objects in gtt_space. Used to restore gtt 1333 * mappings on resume */ 1334 struct list_head bound_list; 1335 /** 1336 * List of objects which are not bound to the GTT (thus 1337 * are idle and not used by the GPU) but still have 1338 * (presumably uncached) pages still attached. 1339 */ 1340 struct list_head unbound_list; 1341 1342 /** Usable portion of the GTT for GEM */ 1343 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1344 1345 /** PPGTT used for aliasing the PPGTT with the GTT */ 1346 struct i915_hw_ppgtt *aliasing_ppgtt; 1347 1348 struct notifier_block oom_notifier; 1349 struct notifier_block vmap_notifier; 1350 struct shrinker shrinker; 1351 1352 /** LRU list of objects with fence regs on them. */ 1353 struct list_head fence_list; 1354 1355 /** 1356 * Are we in a non-interruptible section of code like 1357 * modesetting? 1358 */ 1359 bool interruptible; 1360 1361 /* the indicator for dispatch video commands on two BSD rings */ 1362 atomic_t bsd_engine_dispatch_index; 1363 1364 /** Bit 6 swizzling required for X tiling */ 1365 uint32_t bit_6_swizzle_x; 1366 /** Bit 6 swizzling required for Y tiling */ 1367 uint32_t bit_6_swizzle_y; 1368 1369 /* accounting, useful for userland debugging */ 1370 spinlock_t object_stat_lock; 1371 size_t object_memory; 1372 u32 object_count; 1373 }; 1374 1375 struct drm_i915_error_state_buf { 1376 struct drm_i915_private *i915; 1377 unsigned bytes; 1378 unsigned size; 1379 int err; 1380 u8 *buf; 1381 loff_t start; 1382 loff_t pos; 1383 }; 1384 1385 struct i915_error_state_file_priv { 1386 struct drm_device *dev; 1387 struct drm_i915_error_state *error; 1388 }; 1389 1390 struct i915_gpu_error { 1391 /* For hangcheck timer */ 1392 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1393 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1394 /* Hang gpu twice in this window and your context gets banned */ 1395 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1396 1397 struct delayed_work hangcheck_work; 1398 1399 /* For reset and error_state handling. */ 1400 spinlock_t lock; 1401 /* Protected by the above dev->gpu_error.lock. */ 1402 struct drm_i915_error_state *first_error; 1403 1404 unsigned long missed_irq_rings; 1405 1406 /** 1407 * State variable controlling the reset flow and count 1408 * 1409 * This is a counter which gets incremented when reset is triggered, 1410 * 1411 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set 1412 * meaning that any waiters holding onto the struct_mutex should 1413 * relinquish the lock immediately in order for the reset to start. 1414 * 1415 * If reset is not completed succesfully, the I915_WEDGE bit is 1416 * set meaning that hardware is terminally sour and there is no 1417 * recovery. All waiters on the reset_queue will be woken when 1418 * that happens. 1419 * 1420 * This counter is used by the wait_seqno code to notice that reset 1421 * event happened and it needs to restart the entire ioctl (since most 1422 * likely the seqno it waited for won't ever signal anytime soon). 1423 * 1424 * This is important for lock-free wait paths, where no contended lock 1425 * naturally enforces the correct ordering between the bail-out of the 1426 * waiter and the gpu reset work code. 1427 */ 1428 unsigned long reset_count; 1429 1430 unsigned long flags; 1431 #define I915_RESET_IN_PROGRESS 0 1432 #define I915_WEDGED (BITS_PER_LONG - 1) 1433 1434 /** 1435 * Waitqueue to signal when a hang is detected. Used to for waiters 1436 * to release the struct_mutex for the reset to procede. 1437 */ 1438 wait_queue_head_t wait_queue; 1439 1440 /** 1441 * Waitqueue to signal when the reset has completed. Used by clients 1442 * that wait for dev_priv->mm.wedged to settle. 1443 */ 1444 wait_queue_head_t reset_queue; 1445 1446 /* For missed irq/seqno simulation. */ 1447 unsigned long test_irq_rings; 1448 }; 1449 1450 enum modeset_restore { 1451 MODESET_ON_LID_OPEN, 1452 MODESET_DONE, 1453 MODESET_SUSPENDED, 1454 }; 1455 1456 #define DP_AUX_A 0x40 1457 #define DP_AUX_B 0x10 1458 #define DP_AUX_C 0x20 1459 #define DP_AUX_D 0x30 1460 1461 #define DDC_PIN_B 0x05 1462 #define DDC_PIN_C 0x04 1463 #define DDC_PIN_D 0x06 1464 1465 struct ddi_vbt_port_info { 1466 /* 1467 * This is an index in the HDMI/DVI DDI buffer translation table. 1468 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1469 * populate this field. 1470 */ 1471 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1472 uint8_t hdmi_level_shift; 1473 1474 uint8_t supports_dvi:1; 1475 uint8_t supports_hdmi:1; 1476 uint8_t supports_dp:1; 1477 1478 uint8_t alternate_aux_channel; 1479 uint8_t alternate_ddc_pin; 1480 1481 uint8_t dp_boost_level; 1482 uint8_t hdmi_boost_level; 1483 }; 1484 1485 enum psr_lines_to_wait { 1486 PSR_0_LINES_TO_WAIT = 0, 1487 PSR_1_LINE_TO_WAIT, 1488 PSR_4_LINES_TO_WAIT, 1489 PSR_8_LINES_TO_WAIT 1490 }; 1491 1492 struct intel_vbt_data { 1493 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1494 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1495 1496 /* Feature bits */ 1497 unsigned int int_tv_support:1; 1498 unsigned int lvds_dither:1; 1499 unsigned int lvds_vbt:1; 1500 unsigned int int_crt_support:1; 1501 unsigned int lvds_use_ssc:1; 1502 unsigned int display_clock_mode:1; 1503 unsigned int fdi_rx_polarity_inverted:1; 1504 unsigned int panel_type:4; 1505 int lvds_ssc_freq; 1506 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1507 1508 enum drrs_support_type drrs_type; 1509 1510 struct { 1511 int rate; 1512 int lanes; 1513 int preemphasis; 1514 int vswing; 1515 bool low_vswing; 1516 bool initialized; 1517 bool support; 1518 int bpp; 1519 struct edp_power_seq pps; 1520 } edp; 1521 1522 struct { 1523 bool full_link; 1524 bool require_aux_wakeup; 1525 int idle_frames; 1526 enum psr_lines_to_wait lines_to_wait; 1527 int tp1_wakeup_time; 1528 int tp2_tp3_wakeup_time; 1529 } psr; 1530 1531 struct { 1532 u16 pwm_freq_hz; 1533 bool present; 1534 bool active_low_pwm; 1535 u8 min_brightness; /* min_brightness/255 of max */ 1536 enum intel_backlight_type type; 1537 } backlight; 1538 1539 /* MIPI DSI */ 1540 struct { 1541 u16 panel_id; 1542 struct mipi_config *config; 1543 struct mipi_pps_data *pps; 1544 u8 seq_version; 1545 u32 size; 1546 u8 *data; 1547 const u8 *sequence[MIPI_SEQ_MAX]; 1548 } dsi; 1549 1550 int crt_ddc_pin; 1551 1552 int child_dev_num; 1553 union child_device_config *child_dev; 1554 1555 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1556 struct sdvo_device_mapping sdvo_mappings[2]; 1557 }; 1558 1559 enum intel_ddb_partitioning { 1560 INTEL_DDB_PART_1_2, 1561 INTEL_DDB_PART_5_6, /* IVB+ */ 1562 }; 1563 1564 struct intel_wm_level { 1565 bool enable; 1566 uint32_t pri_val; 1567 uint32_t spr_val; 1568 uint32_t cur_val; 1569 uint32_t fbc_val; 1570 }; 1571 1572 struct ilk_wm_values { 1573 uint32_t wm_pipe[3]; 1574 uint32_t wm_lp[3]; 1575 uint32_t wm_lp_spr[3]; 1576 uint32_t wm_linetime[3]; 1577 bool enable_fbc_wm; 1578 enum intel_ddb_partitioning partitioning; 1579 }; 1580 1581 struct vlv_pipe_wm { 1582 uint16_t primary; 1583 uint16_t sprite[2]; 1584 uint8_t cursor; 1585 }; 1586 1587 struct vlv_sr_wm { 1588 uint16_t plane; 1589 uint8_t cursor; 1590 }; 1591 1592 struct vlv_wm_values { 1593 struct vlv_pipe_wm pipe[3]; 1594 struct vlv_sr_wm sr; 1595 struct { 1596 uint8_t cursor; 1597 uint8_t sprite[2]; 1598 uint8_t primary; 1599 } ddl[3]; 1600 uint8_t level; 1601 bool cxsr; 1602 }; 1603 1604 struct skl_ddb_entry { 1605 uint16_t start, end; /* in number of blocks, 'end' is exclusive */ 1606 }; 1607 1608 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) 1609 { 1610 return entry->end - entry->start; 1611 } 1612 1613 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 1614 const struct skl_ddb_entry *e2) 1615 { 1616 if (e1->start == e2->start && e1->end == e2->end) 1617 return true; 1618 1619 return false; 1620 } 1621 1622 struct skl_ddb_allocation { 1623 struct skl_ddb_entry pipe[I915_MAX_PIPES]; 1624 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ 1625 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; 1626 }; 1627 1628 struct skl_wm_values { 1629 unsigned dirty_pipes; 1630 struct skl_ddb_allocation ddb; 1631 uint32_t wm_linetime[I915_MAX_PIPES]; 1632 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; 1633 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; 1634 }; 1635 1636 struct skl_wm_level { 1637 bool plane_en[I915_MAX_PLANES]; 1638 uint16_t plane_res_b[I915_MAX_PLANES]; 1639 uint8_t plane_res_l[I915_MAX_PLANES]; 1640 }; 1641 1642 /* 1643 * This struct helps tracking the state needed for runtime PM, which puts the 1644 * device in PCI D3 state. Notice that when this happens, nothing on the 1645 * graphics device works, even register access, so we don't get interrupts nor 1646 * anything else. 1647 * 1648 * Every piece of our code that needs to actually touch the hardware needs to 1649 * either call intel_runtime_pm_get or call intel_display_power_get with the 1650 * appropriate power domain. 1651 * 1652 * Our driver uses the autosuspend delay feature, which means we'll only really 1653 * suspend if we stay with zero refcount for a certain amount of time. The 1654 * default value is currently very conservative (see intel_runtime_pm_enable), but 1655 * it can be changed with the standard runtime PM files from sysfs. 1656 * 1657 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1658 * goes back to false exactly before we reenable the IRQs. We use this variable 1659 * to check if someone is trying to enable/disable IRQs while they're supposed 1660 * to be disabled. This shouldn't happen and we'll print some error messages in 1661 * case it happens. 1662 * 1663 * For more, read the Documentation/power/runtime_pm.txt. 1664 */ 1665 struct i915_runtime_pm { 1666 atomic_t wakeref_count; 1667 atomic_t atomic_seq; 1668 bool suspended; 1669 bool irqs_enabled; 1670 }; 1671 1672 enum intel_pipe_crc_source { 1673 INTEL_PIPE_CRC_SOURCE_NONE, 1674 INTEL_PIPE_CRC_SOURCE_PLANE1, 1675 INTEL_PIPE_CRC_SOURCE_PLANE2, 1676 INTEL_PIPE_CRC_SOURCE_PF, 1677 INTEL_PIPE_CRC_SOURCE_PIPE, 1678 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1679 INTEL_PIPE_CRC_SOURCE_TV, 1680 INTEL_PIPE_CRC_SOURCE_DP_B, 1681 INTEL_PIPE_CRC_SOURCE_DP_C, 1682 INTEL_PIPE_CRC_SOURCE_DP_D, 1683 INTEL_PIPE_CRC_SOURCE_AUTO, 1684 INTEL_PIPE_CRC_SOURCE_MAX, 1685 }; 1686 1687 struct intel_pipe_crc_entry { 1688 uint32_t frame; 1689 uint32_t crc[5]; 1690 }; 1691 1692 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1693 struct intel_pipe_crc { 1694 spinlock_t lock; 1695 bool opened; /* exclusive access to the result file */ 1696 struct intel_pipe_crc_entry *entries; 1697 enum intel_pipe_crc_source source; 1698 int head, tail; 1699 wait_queue_head_t wq; 1700 }; 1701 1702 struct i915_frontbuffer_tracking { 1703 spinlock_t lock; 1704 1705 /* 1706 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1707 * scheduled flips. 1708 */ 1709 unsigned busy_bits; 1710 unsigned flip_bits; 1711 }; 1712 1713 struct i915_wa_reg { 1714 i915_reg_t addr; 1715 u32 value; 1716 /* bitmask representing WA bits */ 1717 u32 mask; 1718 }; 1719 1720 /* 1721 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only 1722 * allowing it for RCS as we don't foresee any requirement of having 1723 * a whitelist for other engines. When it is really required for 1724 * other engines then the limit need to be increased. 1725 */ 1726 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) 1727 1728 struct i915_workarounds { 1729 struct i915_wa_reg reg[I915_MAX_WA_REGS]; 1730 u32 count; 1731 u32 hw_whitelist_count[I915_NUM_ENGINES]; 1732 }; 1733 1734 struct i915_virtual_gpu { 1735 bool active; 1736 }; 1737 1738 /* used in computing the new watermarks state */ 1739 struct intel_wm_config { 1740 unsigned int num_pipes_active; 1741 bool sprites_enabled; 1742 bool sprites_scaled; 1743 }; 1744 1745 struct drm_i915_private { 1746 struct drm_device drm; 1747 1748 struct kmem_cache *objects; 1749 struct kmem_cache *vmas; 1750 struct kmem_cache *requests; 1751 1752 const struct intel_device_info info; 1753 1754 int relative_constants_mode; 1755 1756 void __iomem *regs; 1757 1758 struct intel_uncore uncore; 1759 1760 struct i915_virtual_gpu vgpu; 1761 1762 struct intel_gvt gvt; 1763 1764 struct intel_guc guc; 1765 1766 struct intel_csr csr; 1767 1768 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 1769 1770 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1771 * controller on different i2c buses. */ 1772 struct mutex gmbus_mutex; 1773 1774 /** 1775 * Base address of the gmbus and gpio block. 1776 */ 1777 uint32_t gpio_mmio_base; 1778 1779 /* MMIO base address for MIPI regs */ 1780 uint32_t mipi_mmio_base; 1781 1782 uint32_t psr_mmio_base; 1783 1784 uint32_t pps_mmio_base; 1785 1786 wait_queue_head_t gmbus_wait_queue; 1787 1788 struct pci_dev *bridge_dev; 1789 struct i915_gem_context *kernel_context; 1790 struct intel_engine_cs engine[I915_NUM_ENGINES]; 1791 struct i915_vma *semaphore; 1792 u32 next_seqno; 1793 1794 struct drm_dma_handle *status_page_dmah; 1795 struct resource mch_res; 1796 1797 /* protects the irq masks */ 1798 spinlock_t irq_lock; 1799 1800 /* protects the mmio flip data */ 1801 spinlock_t mmio_flip_lock; 1802 1803 bool display_irqs_enabled; 1804 1805 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1806 struct pm_qos_request pm_qos; 1807 1808 /* Sideband mailbox protection */ 1809 struct mutex sb_lock; 1810 1811 /** Cached value of IMR to avoid reads in updating the bitfield */ 1812 union { 1813 u32 irq_mask; 1814 u32 de_irq_mask[I915_MAX_PIPES]; 1815 }; 1816 u32 gt_irq_mask; 1817 u32 pm_irq_mask; 1818 u32 pm_rps_events; 1819 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1820 1821 struct i915_hotplug hotplug; 1822 struct intel_fbc fbc; 1823 struct i915_drrs drrs; 1824 struct intel_opregion opregion; 1825 struct intel_vbt_data vbt; 1826 1827 bool preserve_bios_swizzle; 1828 1829 /* overlay */ 1830 struct intel_overlay *overlay; 1831 1832 /* backlight registers and fields in struct intel_panel */ 1833 struct mutex backlight_lock; 1834 1835 /* LVDS info */ 1836 bool no_aux_handshake; 1837 1838 /* protects panel power sequencer state */ 1839 struct mutex pps_mutex; 1840 1841 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1842 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1843 1844 unsigned int fsb_freq, mem_freq, is_ddr3; 1845 unsigned int skl_preferred_vco_freq; 1846 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; 1847 unsigned int max_dotclk_freq; 1848 unsigned int rawclk_freq; 1849 unsigned int hpll_freq; 1850 unsigned int czclk_freq; 1851 1852 struct { 1853 unsigned int vco, ref; 1854 } cdclk_pll; 1855 1856 /** 1857 * wq - Driver workqueue for GEM. 1858 * 1859 * NOTE: Work items scheduled here are not allowed to grab any modeset 1860 * locks, for otherwise the flushing done in the pageflip code will 1861 * result in deadlocks. 1862 */ 1863 struct workqueue_struct *wq; 1864 1865 /* Display functions */ 1866 struct drm_i915_display_funcs display; 1867 1868 /* PCH chipset type */ 1869 enum intel_pch pch_type; 1870 unsigned short pch_id; 1871 1872 unsigned long quirks; 1873 1874 enum modeset_restore modeset_restore; 1875 struct mutex modeset_restore_lock; 1876 struct drm_atomic_state *modeset_restore_state; 1877 struct drm_modeset_acquire_ctx reset_ctx; 1878 1879 struct list_head vm_list; /* Global list of all address spaces */ 1880 struct i915_ggtt ggtt; /* VM representing the global address space */ 1881 1882 struct i915_gem_mm mm; 1883 DECLARE_HASHTABLE(mm_structs, 7); 1884 struct mutex mm_lock; 1885 1886 /* The hw wants to have a stable context identifier for the lifetime 1887 * of the context (for OA, PASID, faults, etc). This is limited 1888 * in execlists to 21 bits. 1889 */ 1890 struct ida context_hw_ida; 1891 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 1892 1893 /* Kernel Modesetting */ 1894 1895 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1896 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1897 wait_queue_head_t pending_flip_queue; 1898 1899 #ifdef CONFIG_DEBUG_FS 1900 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1901 #endif 1902 1903 /* dpll and cdclk state is protected by connection_mutex */ 1904 int num_shared_dpll; 1905 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1906 const struct intel_dpll_mgr *dpll_mgr; 1907 1908 /* 1909 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1910 * Must be global rather than per dpll, because on some platforms 1911 * plls share registers. 1912 */ 1913 struct mutex dpll_lock; 1914 1915 unsigned int active_crtcs; 1916 unsigned int min_pixclk[I915_MAX_PIPES]; 1917 1918 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1919 1920 struct i915_workarounds workarounds; 1921 1922 struct i915_frontbuffer_tracking fb_tracking; 1923 1924 u16 orig_clock; 1925 1926 bool mchbar_need_disable; 1927 1928 struct intel_l3_parity l3_parity; 1929 1930 /* Cannot be determined by PCIID. You must always read a register. */ 1931 u32 edram_cap; 1932 1933 /* gen6+ rps state */ 1934 struct intel_gen6_power_mgmt rps; 1935 1936 /* ilk-only ips/rps state. Everything in here is protected by the global 1937 * mchdev_lock in intel_pm.c */ 1938 struct intel_ilk_power_mgmt ips; 1939 1940 struct i915_power_domains power_domains; 1941 1942 struct i915_psr psr; 1943 1944 struct i915_gpu_error gpu_error; 1945 1946 struct drm_i915_gem_object *vlv_pctx; 1947 1948 #ifdef CONFIG_DRM_FBDEV_EMULATION 1949 /* list of fbdev register on this device */ 1950 struct intel_fbdev *fbdev; 1951 struct work_struct fbdev_suspend_work; 1952 #endif 1953 1954 struct drm_property *broadcast_rgb_property; 1955 struct drm_property *force_audio_property; 1956 1957 /* hda/i915 audio component */ 1958 struct i915_audio_component *audio_component; 1959 bool audio_component_registered; 1960 /** 1961 * av_mutex - mutex for audio/video sync 1962 * 1963 */ 1964 struct mutex av_mutex; 1965 1966 uint32_t hw_context_size; 1967 struct list_head context_list; 1968 1969 u32 fdi_rx_config; 1970 1971 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1972 u32 chv_phy_control; 1973 /* 1974 * Shadows for CHV DPLL_MD regs to keep the state 1975 * checker somewhat working in the presence hardware 1976 * crappiness (can't read out DPLL_MD for pipes B & C). 1977 */ 1978 u32 chv_dpll_md[I915_MAX_PIPES]; 1979 u32 bxt_phy_grc; 1980 1981 u32 suspend_count; 1982 bool suspended_to_idle; 1983 struct i915_suspend_saved_registers regfile; 1984 struct vlv_s0ix_state vlv_s0ix_state; 1985 1986 enum { 1987 I915_SAGV_UNKNOWN = 0, 1988 I915_SAGV_DISABLED, 1989 I915_SAGV_ENABLED, 1990 I915_SAGV_NOT_CONTROLLED 1991 } sagv_status; 1992 1993 struct { 1994 /* 1995 * Raw watermark latency values: 1996 * in 0.1us units for WM0, 1997 * in 0.5us units for WM1+. 1998 */ 1999 /* primary */ 2000 uint16_t pri_latency[5]; 2001 /* sprite */ 2002 uint16_t spr_latency[5]; 2003 /* cursor */ 2004 uint16_t cur_latency[5]; 2005 /* 2006 * Raw watermark memory latency values 2007 * for SKL for all 8 levels 2008 * in 1us units. 2009 */ 2010 uint16_t skl_latency[8]; 2011 2012 /* 2013 * The skl_wm_values structure is a bit too big for stack 2014 * allocation, so we keep the staging struct where we store 2015 * intermediate results here instead. 2016 */ 2017 struct skl_wm_values skl_results; 2018 2019 /* current hardware state */ 2020 union { 2021 struct ilk_wm_values hw; 2022 struct skl_wm_values skl_hw; 2023 struct vlv_wm_values vlv; 2024 }; 2025 2026 uint8_t max_level; 2027 2028 /* 2029 * Should be held around atomic WM register writing; also 2030 * protects * intel_crtc->wm.active and 2031 * cstate->wm.need_postvbl_update. 2032 */ 2033 struct mutex wm_mutex; 2034 2035 /* 2036 * Set during HW readout of watermarks/DDB. Some platforms 2037 * need to know when we're still using BIOS-provided values 2038 * (which we don't fully trust). 2039 */ 2040 bool distrust_bios_wm; 2041 } wm; 2042 2043 struct i915_runtime_pm pm; 2044 2045 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 2046 struct { 2047 void (*resume)(struct drm_i915_private *); 2048 void (*cleanup_engine)(struct intel_engine_cs *engine); 2049 2050 /** 2051 * Is the GPU currently considered idle, or busy executing 2052 * userspace requests? Whilst idle, we allow runtime power 2053 * management to power down the hardware and display clocks. 2054 * In order to reduce the effect on performance, there 2055 * is a slight delay before we do so. 2056 */ 2057 unsigned int active_engines; 2058 bool awake; 2059 2060 /** 2061 * We leave the user IRQ off as much as possible, 2062 * but this means that requests will finish and never 2063 * be retired once the system goes idle. Set a timer to 2064 * fire periodically while the ring is running. When it 2065 * fires, go retire requests. 2066 */ 2067 struct delayed_work retire_work; 2068 2069 /** 2070 * When we detect an idle GPU, we want to turn on 2071 * powersaving features. So once we see that there 2072 * are no more requests outstanding and no more 2073 * arrive within a small period of time, we fire 2074 * off the idle_work. 2075 */ 2076 struct delayed_work idle_work; 2077 } gt; 2078 2079 /* perform PHY state sanity checks? */ 2080 bool chv_phy_assert[2]; 2081 2082 struct intel_encoder *dig_port_map[I915_MAX_PORTS]; 2083 2084 /* 2085 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 2086 * will be rejected. Instead look for a better place. 2087 */ 2088 }; 2089 2090 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 2091 { 2092 return container_of(dev, struct drm_i915_private, drm); 2093 } 2094 2095 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 2096 { 2097 return to_i915(dev_get_drvdata(kdev)); 2098 } 2099 2100 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) 2101 { 2102 return container_of(guc, struct drm_i915_private, guc); 2103 } 2104 2105 /* Simple iterator over all initialised engines */ 2106 #define for_each_engine(engine__, dev_priv__) \ 2107 for ((engine__) = &(dev_priv__)->engine[0]; \ 2108 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ 2109 (engine__)++) \ 2110 for_each_if (intel_engine_initialized(engine__)) 2111 2112 /* Iterator with engine_id */ 2113 #define for_each_engine_id(engine__, dev_priv__, id__) \ 2114 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ 2115 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ 2116 (engine__)++) \ 2117 for_each_if (((id__) = (engine__)->id, \ 2118 intel_engine_initialized(engine__))) 2119 2120 #define __mask_next_bit(mask) ({ \ 2121 int __idx = ffs(mask) - 1; \ 2122 mask &= ~BIT(__idx); \ 2123 __idx; \ 2124 }) 2125 2126 /* Iterator over subset of engines selected by mask */ 2127 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ 2128 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ 2129 tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) 2130 2131 enum hdmi_force_audio { 2132 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 2133 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 2134 HDMI_AUDIO_AUTO, /* trust EDID */ 2135 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 2136 }; 2137 2138 #define I915_GTT_OFFSET_NONE ((u32)-1) 2139 2140 struct drm_i915_gem_object_ops { 2141 unsigned int flags; 2142 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 2143 2144 /* Interface between the GEM object and its backing storage. 2145 * get_pages() is called once prior to the use of the associated set 2146 * of pages before to binding them into the GTT, and put_pages() is 2147 * called after we no longer need them. As we expect there to be 2148 * associated cost with migrating pages between the backing storage 2149 * and making them available for the GPU (e.g. clflush), we may hold 2150 * onto the pages after they are no longer referenced by the GPU 2151 * in case they may be used again shortly (for example migrating the 2152 * pages to a different memory domain within the GTT). put_pages() 2153 * will therefore most likely be called when the object itself is 2154 * being released or under memory pressure (where we attempt to 2155 * reap pages for the shrinker). 2156 */ 2157 int (*get_pages)(struct drm_i915_gem_object *); 2158 void (*put_pages)(struct drm_i915_gem_object *); 2159 2160 int (*dmabuf_export)(struct drm_i915_gem_object *); 2161 void (*release)(struct drm_i915_gem_object *); 2162 }; 2163 2164 /* 2165 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 2166 * considered to be the frontbuffer for the given plane interface-wise. This 2167 * doesn't mean that the hw necessarily already scans it out, but that any 2168 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 2169 * 2170 * We have one bit per pipe and per scanout plane type. 2171 */ 2172 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 2173 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 2174 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 2175 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 2176 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 2177 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 2178 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ 2179 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 2180 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 2181 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 2182 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 2183 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 2184 2185 struct drm_i915_gem_object { 2186 struct drm_gem_object base; 2187 2188 const struct drm_i915_gem_object_ops *ops; 2189 2190 /** List of VMAs backed by this object */ 2191 struct list_head vma_list; 2192 2193 /** Stolen memory for this object, instead of being backed by shmem. */ 2194 struct drm_mm_node *stolen; 2195 struct list_head global_list; 2196 2197 /** Used in execbuf to temporarily hold a ref */ 2198 struct list_head obj_exec_link; 2199 2200 struct list_head batch_pool_link; 2201 2202 unsigned long flags; 2203 /** 2204 * This is set if the object is on the active lists (has pending 2205 * rendering and so a non-zero seqno), and is not set if it i s on 2206 * inactive (ready to be unbound) list. 2207 */ 2208 #define I915_BO_ACTIVE_SHIFT 0 2209 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1) 2210 #define __I915_BO_ACTIVE(bo) \ 2211 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK) 2212 2213 /** 2214 * This is set if the object has been written to since last bound 2215 * to the GTT 2216 */ 2217 unsigned int dirty:1; 2218 2219 /** 2220 * Advice: are the backing pages purgeable? 2221 */ 2222 unsigned int madv:2; 2223 2224 /** 2225 * Whether the current gtt mapping needs to be mappable (and isn't just 2226 * mappable by accident). Track pin and fault separate for a more 2227 * accurate mappable working set. 2228 */ 2229 unsigned int fault_mappable:1; 2230 2231 /* 2232 * Is the object to be mapped as read-only to the GPU 2233 * Only honoured if hardware has relevant pte bit 2234 */ 2235 unsigned long gt_ro:1; 2236 unsigned int cache_level:3; 2237 unsigned int cache_dirty:1; 2238 2239 atomic_t frontbuffer_bits; 2240 unsigned int frontbuffer_ggtt_origin; /* write once */ 2241 2242 /** Current tiling stride for the object, if it's tiled. */ 2243 unsigned int tiling_and_stride; 2244 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */ 2245 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1) 2246 #define STRIDE_MASK (~TILING_MASK) 2247 2248 /** Count of VMA actually bound by this object */ 2249 unsigned int bind_count; 2250 unsigned int pin_display; 2251 2252 struct sg_table *pages; 2253 int pages_pin_count; 2254 struct get_page { 2255 struct scatterlist *sg; 2256 int last; 2257 } get_page; 2258 void *mapping; 2259 2260 /** Breadcrumb of last rendering to the buffer. 2261 * There can only be one writer, but we allow for multiple readers. 2262 * If there is a writer that necessarily implies that all other 2263 * read requests are complete - but we may only be lazily clearing 2264 * the read requests. A read request is naturally the most recent 2265 * request on a ring, so we may have two different write and read 2266 * requests on one ring where the write request is older than the 2267 * read request. This allows for the CPU to read from an active 2268 * buffer by only waiting for the write to complete. 2269 */ 2270 struct i915_gem_active last_read[I915_NUM_ENGINES]; 2271 struct i915_gem_active last_write; 2272 2273 /** References from framebuffers, locks out tiling changes. */ 2274 unsigned long framebuffer_references; 2275 2276 /** Record of address bit 17 of each page at last unbind. */ 2277 unsigned long *bit_17; 2278 2279 struct i915_gem_userptr { 2280 uintptr_t ptr; 2281 unsigned read_only :1; 2282 unsigned workers :4; 2283 #define I915_GEM_USERPTR_MAX_WORKERS 15 2284 2285 struct i915_mm_struct *mm; 2286 struct i915_mmu_object *mmu_object; 2287 struct work_struct *work; 2288 } userptr; 2289 2290 /** for phys allocated objects */ 2291 struct drm_dma_handle *phys_handle; 2292 }; 2293 2294 static inline struct drm_i915_gem_object * 2295 to_intel_bo(struct drm_gem_object *gem) 2296 { 2297 /* Assert that to_intel_bo(NULL) == NULL */ 2298 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); 2299 2300 return container_of(gem, struct drm_i915_gem_object, base); 2301 } 2302 2303 static inline struct drm_i915_gem_object * 2304 i915_gem_object_lookup(struct drm_file *file, u32 handle) 2305 { 2306 return to_intel_bo(drm_gem_object_lookup(file, handle)); 2307 } 2308 2309 __deprecated 2310 extern struct drm_gem_object * 2311 drm_gem_object_lookup(struct drm_file *file, u32 handle); 2312 2313 __attribute__((nonnull)) 2314 static inline struct drm_i915_gem_object * 2315 i915_gem_object_get(struct drm_i915_gem_object *obj) 2316 { 2317 drm_gem_object_reference(&obj->base); 2318 return obj; 2319 } 2320 2321 __deprecated 2322 extern void drm_gem_object_reference(struct drm_gem_object *); 2323 2324 __attribute__((nonnull)) 2325 static inline void 2326 i915_gem_object_put(struct drm_i915_gem_object *obj) 2327 { 2328 drm_gem_object_unreference(&obj->base); 2329 } 2330 2331 __deprecated 2332 extern void drm_gem_object_unreference(struct drm_gem_object *); 2333 2334 __attribute__((nonnull)) 2335 static inline void 2336 i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj) 2337 { 2338 drm_gem_object_unreference_unlocked(&obj->base); 2339 } 2340 2341 __deprecated 2342 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); 2343 2344 static inline bool 2345 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) 2346 { 2347 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; 2348 } 2349 2350 static inline unsigned long 2351 i915_gem_object_get_active(const struct drm_i915_gem_object *obj) 2352 { 2353 return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK; 2354 } 2355 2356 static inline bool 2357 i915_gem_object_is_active(const struct drm_i915_gem_object *obj) 2358 { 2359 return i915_gem_object_get_active(obj); 2360 } 2361 2362 static inline void 2363 i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine) 2364 { 2365 obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT); 2366 } 2367 2368 static inline void 2369 i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine) 2370 { 2371 obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT); 2372 } 2373 2374 static inline bool 2375 i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj, 2376 int engine) 2377 { 2378 return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT); 2379 } 2380 2381 static inline unsigned int 2382 i915_gem_object_get_tiling(struct drm_i915_gem_object *obj) 2383 { 2384 return obj->tiling_and_stride & TILING_MASK; 2385 } 2386 2387 static inline bool 2388 i915_gem_object_is_tiled(struct drm_i915_gem_object *obj) 2389 { 2390 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE; 2391 } 2392 2393 static inline unsigned int 2394 i915_gem_object_get_stride(struct drm_i915_gem_object *obj) 2395 { 2396 return obj->tiling_and_stride & STRIDE_MASK; 2397 } 2398 2399 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) 2400 { 2401 i915_gem_object_get(vma->obj); 2402 return vma; 2403 } 2404 2405 static inline void i915_vma_put(struct i915_vma *vma) 2406 { 2407 lockdep_assert_held(&vma->vm->dev->struct_mutex); 2408 i915_gem_object_put(vma->obj); 2409 } 2410 2411 /* 2412 * Optimised SGL iterator for GEM objects 2413 */ 2414 static __always_inline struct sgt_iter { 2415 struct scatterlist *sgp; 2416 union { 2417 unsigned long pfn; 2418 dma_addr_t dma; 2419 }; 2420 unsigned int curr; 2421 unsigned int max; 2422 } __sgt_iter(struct scatterlist *sgl, bool dma) { 2423 struct sgt_iter s = { .sgp = sgl }; 2424 2425 if (s.sgp) { 2426 s.max = s.curr = s.sgp->offset; 2427 s.max += s.sgp->length; 2428 if (dma) 2429 s.dma = sg_dma_address(s.sgp); 2430 else 2431 s.pfn = page_to_pfn(sg_page(s.sgp)); 2432 } 2433 2434 return s; 2435 } 2436 2437 /** 2438 * __sg_next - return the next scatterlist entry in a list 2439 * @sg: The current sg entry 2440 * 2441 * Description: 2442 * If the entry is the last, return NULL; otherwise, step to the next 2443 * element in the array (@sg@+1). If that's a chain pointer, follow it; 2444 * otherwise just return the pointer to the current element. 2445 **/ 2446 static inline struct scatterlist *__sg_next(struct scatterlist *sg) 2447 { 2448 #ifdef CONFIG_DEBUG_SG 2449 BUG_ON(sg->sg_magic != SG_MAGIC); 2450 #endif 2451 return sg_is_last(sg) ? NULL : 2452 likely(!sg_is_chain(++sg)) ? sg : 2453 sg_chain_ptr(sg); 2454 } 2455 2456 /** 2457 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table 2458 * @__dmap: DMA address (output) 2459 * @__iter: 'struct sgt_iter' (iterator state, internal) 2460 * @__sgt: sg_table to iterate over (input) 2461 */ 2462 #define for_each_sgt_dma(__dmap, __iter, __sgt) \ 2463 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ 2464 ((__dmap) = (__iter).dma + (__iter).curr); \ 2465 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ 2466 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) 2467 2468 /** 2469 * for_each_sgt_page - iterate over the pages of the given sg_table 2470 * @__pp: page pointer (output) 2471 * @__iter: 'struct sgt_iter' (iterator state, internal) 2472 * @__sgt: sg_table to iterate over (input) 2473 */ 2474 #define for_each_sgt_page(__pp, __iter, __sgt) \ 2475 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ 2476 ((__pp) = (__iter).pfn == 0 ? NULL : \ 2477 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ 2478 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ 2479 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) 2480 2481 /* 2482 * A command that requires special handling by the command parser. 2483 */ 2484 struct drm_i915_cmd_descriptor { 2485 /* 2486 * Flags describing how the command parser processes the command. 2487 * 2488 * CMD_DESC_FIXED: The command has a fixed length if this is set, 2489 * a length mask if not set 2490 * CMD_DESC_SKIP: The command is allowed but does not follow the 2491 * standard length encoding for the opcode range in 2492 * which it falls 2493 * CMD_DESC_REJECT: The command is never allowed 2494 * CMD_DESC_REGISTER: The command should be checked against the 2495 * register whitelist for the appropriate ring 2496 * CMD_DESC_MASTER: The command is allowed if the submitting process 2497 * is the DRM master 2498 */ 2499 u32 flags; 2500 #define CMD_DESC_FIXED (1<<0) 2501 #define CMD_DESC_SKIP (1<<1) 2502 #define CMD_DESC_REJECT (1<<2) 2503 #define CMD_DESC_REGISTER (1<<3) 2504 #define CMD_DESC_BITMASK (1<<4) 2505 #define CMD_DESC_MASTER (1<<5) 2506 2507 /* 2508 * The command's unique identification bits and the bitmask to get them. 2509 * This isn't strictly the opcode field as defined in the spec and may 2510 * also include type, subtype, and/or subop fields. 2511 */ 2512 struct { 2513 u32 value; 2514 u32 mask; 2515 } cmd; 2516 2517 /* 2518 * The command's length. The command is either fixed length (i.e. does 2519 * not include a length field) or has a length field mask. The flag 2520 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 2521 * a length mask. All command entries in a command table must include 2522 * length information. 2523 */ 2524 union { 2525 u32 fixed; 2526 u32 mask; 2527 } length; 2528 2529 /* 2530 * Describes where to find a register address in the command to check 2531 * against the ring's register whitelist. Only valid if flags has the 2532 * CMD_DESC_REGISTER bit set. 2533 * 2534 * A non-zero step value implies that the command may access multiple 2535 * registers in sequence (e.g. LRI), in that case step gives the 2536 * distance in dwords between individual offset fields. 2537 */ 2538 struct { 2539 u32 offset; 2540 u32 mask; 2541 u32 step; 2542 } reg; 2543 2544 #define MAX_CMD_DESC_BITMASKS 3 2545 /* 2546 * Describes command checks where a particular dword is masked and 2547 * compared against an expected value. If the command does not match 2548 * the expected value, the parser rejects it. Only valid if flags has 2549 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2550 * are valid. 2551 * 2552 * If the check specifies a non-zero condition_mask then the parser 2553 * only performs the check when the bits specified by condition_mask 2554 * are non-zero. 2555 */ 2556 struct { 2557 u32 offset; 2558 u32 mask; 2559 u32 expected; 2560 u32 condition_offset; 2561 u32 condition_mask; 2562 } bits[MAX_CMD_DESC_BITMASKS]; 2563 }; 2564 2565 /* 2566 * A table of commands requiring special handling by the command parser. 2567 * 2568 * Each engine has an array of tables. Each table consists of an array of 2569 * command descriptors, which must be sorted with command opcodes in 2570 * ascending order. 2571 */ 2572 struct drm_i915_cmd_table { 2573 const struct drm_i915_cmd_descriptor *table; 2574 int count; 2575 }; 2576 2577 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2578 #define __I915__(p) ({ \ 2579 struct drm_i915_private *__p; \ 2580 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2581 __p = (struct drm_i915_private *)p; \ 2582 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2583 __p = to_i915((struct drm_device *)p); \ 2584 else \ 2585 BUILD_BUG(); \ 2586 __p; \ 2587 }) 2588 #define INTEL_INFO(p) (&__I915__(p)->info) 2589 #define INTEL_GEN(p) (INTEL_INFO(p)->gen) 2590 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2591 2592 #define REVID_FOREVER 0xff 2593 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) 2594 2595 #define GEN_FOREVER (0) 2596 /* 2597 * Returns true if Gen is in inclusive range [Start, End]. 2598 * 2599 * Use GEN_FOREVER for unbound start and or end. 2600 */ 2601 #define IS_GEN(p, s, e) ({ \ 2602 unsigned int __s = (s), __e = (e); \ 2603 BUILD_BUG_ON(!__builtin_constant_p(s)); \ 2604 BUILD_BUG_ON(!__builtin_constant_p(e)); \ 2605 if ((__s) != GEN_FOREVER) \ 2606 __s = (s) - 1; \ 2607 if ((__e) == GEN_FOREVER) \ 2608 __e = BITS_PER_LONG - 1; \ 2609 else \ 2610 __e = (e) - 1; \ 2611 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \ 2612 }) 2613 2614 /* 2615 * Return true if revision is in range [since,until] inclusive. 2616 * 2617 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 2618 */ 2619 #define IS_REVID(p, since, until) \ 2620 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 2621 2622 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2623 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2624 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2625 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2626 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2627 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2628 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2629 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2630 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2631 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2632 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2633 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2634 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2635 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2636 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2637 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2638 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2639 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2640 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2641 INTEL_DEVID(dev) == 0x0152 || \ 2642 INTEL_DEVID(dev) == 0x015a) 2643 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2644 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) 2645 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2646 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell) 2647 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) 2648 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) 2649 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) 2650 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2651 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2652 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2653 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2654 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2655 (INTEL_DEVID(dev) & 0xf) == 0xb || \ 2656 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2657 /* ULX machines are also considered ULT. */ 2658 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ 2659 (INTEL_DEVID(dev) & 0xf) == 0xe) 2660 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2661 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2662 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2663 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2664 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2665 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2666 /* ULX machines are also considered ULT. */ 2667 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2668 INTEL_DEVID(dev) == 0x0A1E) 2669 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ 2670 INTEL_DEVID(dev) == 0x1913 || \ 2671 INTEL_DEVID(dev) == 0x1916 || \ 2672 INTEL_DEVID(dev) == 0x1921 || \ 2673 INTEL_DEVID(dev) == 0x1926) 2674 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ 2675 INTEL_DEVID(dev) == 0x1915 || \ 2676 INTEL_DEVID(dev) == 0x191E) 2677 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ 2678 INTEL_DEVID(dev) == 0x5913 || \ 2679 INTEL_DEVID(dev) == 0x5916 || \ 2680 INTEL_DEVID(dev) == 0x5921 || \ 2681 INTEL_DEVID(dev) == 0x5926) 2682 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ 2683 INTEL_DEVID(dev) == 0x5915 || \ 2684 INTEL_DEVID(dev) == 0x591E) 2685 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ 2686 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2687 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ 2688 (INTEL_DEVID(dev) & 0x00F0) == 0x0030) 2689 2690 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2691 2692 #define SKL_REVID_A0 0x0 2693 #define SKL_REVID_B0 0x1 2694 #define SKL_REVID_C0 0x2 2695 #define SKL_REVID_D0 0x3 2696 #define SKL_REVID_E0 0x4 2697 #define SKL_REVID_F0 0x5 2698 #define SKL_REVID_G0 0x6 2699 #define SKL_REVID_H0 0x7 2700 2701 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 2702 2703 #define BXT_REVID_A0 0x0 2704 #define BXT_REVID_A1 0x1 2705 #define BXT_REVID_B0 0x3 2706 #define BXT_REVID_C0 0x9 2707 2708 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) 2709 2710 #define KBL_REVID_A0 0x0 2711 #define KBL_REVID_B0 0x1 2712 #define KBL_REVID_C0 0x2 2713 #define KBL_REVID_D0 0x3 2714 #define KBL_REVID_E0 0x4 2715 2716 #define IS_KBL_REVID(p, since, until) \ 2717 (IS_KABYLAKE(p) && IS_REVID(p, since, until)) 2718 2719 /* 2720 * The genX designation typically refers to the render engine, so render 2721 * capability related checks should use IS_GEN, while display and other checks 2722 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2723 * chips, etc.). 2724 */ 2725 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) 2726 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) 2727 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) 2728 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) 2729 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) 2730 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) 2731 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) 2732 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) 2733 2734 #define ENGINE_MASK(id) BIT(id) 2735 #define RENDER_RING ENGINE_MASK(RCS) 2736 #define BSD_RING ENGINE_MASK(VCS) 2737 #define BLT_RING ENGINE_MASK(BCS) 2738 #define VEBOX_RING ENGINE_MASK(VECS) 2739 #define BSD2_RING ENGINE_MASK(VCS2) 2740 #define ALL_ENGINES (~0) 2741 2742 #define HAS_ENGINE(dev_priv, id) \ 2743 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) 2744 2745 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) 2746 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) 2747 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) 2748 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) 2749 2750 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2751 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) 2752 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) 2753 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2754 HAS_EDRAM(dev)) 2755 #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical) 2756 2757 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts) 2758 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts) 2759 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2760 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) 2761 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) 2762 2763 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2764 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2765 2766 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2767 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2768 2769 /* WaRsDisableCoarsePowerGating:skl,bxt */ 2770 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 2771 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ 2772 IS_SKL_GT3(dev_priv) || \ 2773 IS_SKL_GT4(dev_priv)) 2774 2775 /* 2776 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2777 * even when in MSI mode. This results in spurious interrupt warnings if the 2778 * legacy irq no. is shared with another device. The kernel then disables that 2779 * interrupt source and so prevents the other device from working properly. 2780 */ 2781 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2782 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq) 2783 2784 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2785 * rows, which changed the alignment requirements and fence programming. 2786 */ 2787 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2788 IS_I915GM(dev))) 2789 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2790 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2791 2792 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2793 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2794 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2795 2796 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) 2797 2798 #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst) 2799 2800 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2801 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2802 #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) 2803 #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm) 2804 #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) 2805 #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p) 2806 2807 #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr) 2808 2809 /* 2810 * For now, anything with a GuC requires uCode loading, and then supports 2811 * command submission once loaded. But these are logically independent 2812 * properties, so we have separate macros to test them. 2813 */ 2814 #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc) 2815 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) 2816 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) 2817 2818 #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer) 2819 2820 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) 2821 2822 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2823 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2824 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2825 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2826 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2827 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2828 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 2829 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 2830 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 2831 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 2832 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 2833 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ 2834 2835 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) 2836 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP) 2837 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) 2838 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2839 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 2840 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) 2841 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2842 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2843 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2844 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2845 2846 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display) 2847 2848 /* DPF == dynamic parity feature */ 2849 #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) 2850 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2851 2852 #define GT_FREQUENCY_MULTIPLIER 50 2853 #define GEN9_FREQ_SCALER 3 2854 2855 #include "i915_trace.h" 2856 2857 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 2858 { 2859 #ifdef CONFIG_INTEL_IOMMU 2860 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) 2861 return true; 2862 #endif 2863 return false; 2864 } 2865 2866 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); 2867 extern int i915_resume_switcheroo(struct drm_device *dev); 2868 2869 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, 2870 int enable_ppgtt); 2871 2872 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); 2873 2874 /* i915_drv.c */ 2875 void __printf(3, 4) 2876 __i915_printk(struct drm_i915_private *dev_priv, const char *level, 2877 const char *fmt, ...); 2878 2879 #define i915_report_error(dev_priv, fmt, ...) \ 2880 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) 2881 2882 #ifdef CONFIG_COMPAT 2883 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2884 unsigned long arg); 2885 #endif 2886 extern const struct dev_pm_ops i915_pm_ops; 2887 2888 extern int i915_driver_load(struct pci_dev *pdev, 2889 const struct pci_device_id *ent); 2890 extern void i915_driver_unload(struct drm_device *dev); 2891 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); 2892 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); 2893 extern void i915_reset(struct drm_i915_private *dev_priv); 2894 extern int intel_guc_reset(struct drm_i915_private *dev_priv); 2895 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); 2896 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2897 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2898 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2899 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2900 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2901 2902 /* intel_hotplug.c */ 2903 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, 2904 u32 pin_mask, u32 long_mask); 2905 void intel_hpd_init(struct drm_i915_private *dev_priv); 2906 void intel_hpd_init_work(struct drm_i915_private *dev_priv); 2907 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2908 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); 2909 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); 2910 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); 2911 2912 /* i915_irq.c */ 2913 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) 2914 { 2915 unsigned long delay; 2916 2917 if (unlikely(!i915.enable_hangcheck)) 2918 return; 2919 2920 /* Don't continually defer the hangcheck so that it is always run at 2921 * least once after work has been scheduled on any ring. Otherwise, 2922 * we will ignore a hung ring if a second ring is kept busy. 2923 */ 2924 2925 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); 2926 queue_delayed_work(system_long_wq, 2927 &dev_priv->gpu_error.hangcheck_work, delay); 2928 } 2929 2930 __printf(3, 4) 2931 void i915_handle_error(struct drm_i915_private *dev_priv, 2932 u32 engine_mask, 2933 const char *fmt, ...); 2934 2935 extern void intel_irq_init(struct drm_i915_private *dev_priv); 2936 int intel_irq_install(struct drm_i915_private *dev_priv); 2937 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 2938 2939 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); 2940 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, 2941 bool restore_forcewake); 2942 extern void intel_uncore_init(struct drm_i915_private *dev_priv); 2943 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); 2944 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); 2945 extern void intel_uncore_fini(struct drm_i915_private *dev_priv); 2946 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, 2947 bool restore); 2948 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); 2949 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 2950 enum forcewake_domains domains); 2951 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 2952 enum forcewake_domains domains); 2953 /* Like above but the caller must manage the uncore.lock itself. 2954 * Must be used with I915_READ_FW and friends. 2955 */ 2956 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, 2957 enum forcewake_domains domains); 2958 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, 2959 enum forcewake_domains domains); 2960 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); 2961 2962 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); 2963 2964 int intel_wait_for_register(struct drm_i915_private *dev_priv, 2965 i915_reg_t reg, 2966 const u32 mask, 2967 const u32 value, 2968 const unsigned long timeout_ms); 2969 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, 2970 i915_reg_t reg, 2971 const u32 mask, 2972 const u32 value, 2973 const unsigned long timeout_ms); 2974 2975 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 2976 { 2977 return dev_priv->gvt.initialized; 2978 } 2979 2980 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 2981 { 2982 return dev_priv->vgpu.active; 2983 } 2984 2985 void 2986 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2987 u32 status_mask); 2988 2989 void 2990 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2991 u32 status_mask); 2992 2993 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2994 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2995 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 2996 uint32_t mask, 2997 uint32_t bits); 2998 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 2999 uint32_t interrupt_mask, 3000 uint32_t enabled_irq_mask); 3001 static inline void 3002 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) 3003 { 3004 ilk_update_display_irq(dev_priv, bits, bits); 3005 } 3006 static inline void 3007 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) 3008 { 3009 ilk_update_display_irq(dev_priv, bits, 0); 3010 } 3011 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 3012 enum pipe pipe, 3013 uint32_t interrupt_mask, 3014 uint32_t enabled_irq_mask); 3015 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, 3016 enum pipe pipe, uint32_t bits) 3017 { 3018 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); 3019 } 3020 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, 3021 enum pipe pipe, uint32_t bits) 3022 { 3023 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); 3024 } 3025 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 3026 uint32_t interrupt_mask, 3027 uint32_t enabled_irq_mask); 3028 static inline void 3029 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) 3030 { 3031 ibx_display_interrupt_update(dev_priv, bits, bits); 3032 } 3033 static inline void 3034 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) 3035 { 3036 ibx_display_interrupt_update(dev_priv, bits, 0); 3037 } 3038 3039 /* i915_gem.c */ 3040 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 3041 struct drm_file *file_priv); 3042 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 3043 struct drm_file *file_priv); 3044 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 3045 struct drm_file *file_priv); 3046 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 3047 struct drm_file *file_priv); 3048 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 3049 struct drm_file *file_priv); 3050 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 3051 struct drm_file *file_priv); 3052 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 3053 struct drm_file *file_priv); 3054 int i915_gem_execbuffer(struct drm_device *dev, void *data, 3055 struct drm_file *file_priv); 3056 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 3057 struct drm_file *file_priv); 3058 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 3059 struct drm_file *file_priv); 3060 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 3061 struct drm_file *file); 3062 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 3063 struct drm_file *file); 3064 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 3065 struct drm_file *file_priv); 3066 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 3067 struct drm_file *file_priv); 3068 int i915_gem_set_tiling(struct drm_device *dev, void *data, 3069 struct drm_file *file_priv); 3070 int i915_gem_get_tiling(struct drm_device *dev, void *data, 3071 struct drm_file *file_priv); 3072 void i915_gem_init_userptr(struct drm_i915_private *dev_priv); 3073 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 3074 struct drm_file *file); 3075 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 3076 struct drm_file *file_priv); 3077 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 3078 struct drm_file *file_priv); 3079 void i915_gem_load_init(struct drm_device *dev); 3080 void i915_gem_load_cleanup(struct drm_device *dev); 3081 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); 3082 int i915_gem_freeze(struct drm_i915_private *dev_priv); 3083 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 3084 3085 void *i915_gem_object_alloc(struct drm_device *dev); 3086 void i915_gem_object_free(struct drm_i915_gem_object *obj); 3087 void i915_gem_object_init(struct drm_i915_gem_object *obj, 3088 const struct drm_i915_gem_object_ops *ops); 3089 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, 3090 size_t size); 3091 struct drm_i915_gem_object *i915_gem_object_create_from_data( 3092 struct drm_device *dev, const void *data, size_t size); 3093 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); 3094 void i915_gem_free_object(struct drm_gem_object *obj); 3095 3096 struct i915_vma * __must_check 3097 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 3098 const struct i915_ggtt_view *view, 3099 u64 size, 3100 u64 alignment, 3101 u64 flags); 3102 3103 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 3104 u32 flags); 3105 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); 3106 int __must_check i915_vma_unbind(struct i915_vma *vma); 3107 void i915_vma_close(struct i915_vma *vma); 3108 void i915_vma_destroy(struct i915_vma *vma); 3109 3110 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 3111 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 3112 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 3113 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 3114 3115 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 3116 3117 static inline int __sg_page_count(struct scatterlist *sg) 3118 { 3119 return sg->length >> PAGE_SHIFT; 3120 } 3121 3122 struct page * 3123 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); 3124 3125 static inline dma_addr_t 3126 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n) 3127 { 3128 if (n < obj->get_page.last) { 3129 obj->get_page.sg = obj->pages->sgl; 3130 obj->get_page.last = 0; 3131 } 3132 3133 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { 3134 obj->get_page.last += __sg_page_count(obj->get_page.sg++); 3135 if (unlikely(sg_is_chain(obj->get_page.sg))) 3136 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); 3137 } 3138 3139 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT); 3140 } 3141 3142 static inline struct page * 3143 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 3144 { 3145 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) 3146 return NULL; 3147 3148 if (n < obj->get_page.last) { 3149 obj->get_page.sg = obj->pages->sgl; 3150 obj->get_page.last = 0; 3151 } 3152 3153 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { 3154 obj->get_page.last += __sg_page_count(obj->get_page.sg++); 3155 if (unlikely(sg_is_chain(obj->get_page.sg))) 3156 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); 3157 } 3158 3159 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); 3160 } 3161 3162 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 3163 { 3164 BUG_ON(obj->pages == NULL); 3165 obj->pages_pin_count++; 3166 } 3167 3168 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 3169 { 3170 BUG_ON(obj->pages_pin_count == 0); 3171 obj->pages_pin_count--; 3172 } 3173 3174 enum i915_map_type { 3175 I915_MAP_WB = 0, 3176 I915_MAP_WC, 3177 }; 3178 3179 /** 3180 * i915_gem_object_pin_map - return a contiguous mapping of the entire object 3181 * @obj - the object to map into kernel address space 3182 * @type - the type of mapping, used to select pgprot_t 3183 * 3184 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's 3185 * pages and then returns a contiguous mapping of the backing storage into 3186 * the kernel address space. Based on the @type of mapping, the PTE will be 3187 * set to either WriteBack or WriteCombine (via pgprot_t). 3188 * 3189 * The caller must hold the struct_mutex, and is responsible for calling 3190 * i915_gem_object_unpin_map() when the mapping is no longer required. 3191 * 3192 * Returns the pointer through which to access the mapped object, or an 3193 * ERR_PTR() on error. 3194 */ 3195 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, 3196 enum i915_map_type type); 3197 3198 /** 3199 * i915_gem_object_unpin_map - releases an earlier mapping 3200 * @obj - the object to unmap 3201 * 3202 * After pinning the object and mapping its pages, once you are finished 3203 * with your access, call i915_gem_object_unpin_map() to release the pin 3204 * upon the mapping. Once the pin count reaches zero, that mapping may be 3205 * removed. 3206 * 3207 * The caller must hold the struct_mutex. 3208 */ 3209 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) 3210 { 3211 lockdep_assert_held(&obj->base.dev->struct_mutex); 3212 i915_gem_object_unpin_pages(obj); 3213 } 3214 3215 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 3216 unsigned int *needs_clflush); 3217 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, 3218 unsigned int *needs_clflush); 3219 #define CLFLUSH_BEFORE 0x1 3220 #define CLFLUSH_AFTER 0x2 3221 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) 3222 3223 static inline void 3224 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) 3225 { 3226 i915_gem_object_unpin_pages(obj); 3227 } 3228 3229 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 3230 void i915_vma_move_to_active(struct i915_vma *vma, 3231 struct drm_i915_gem_request *req, 3232 unsigned int flags); 3233 int i915_gem_dumb_create(struct drm_file *file_priv, 3234 struct drm_device *dev, 3235 struct drm_mode_create_dumb *args); 3236 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 3237 uint32_t handle, uint64_t *offset); 3238 int i915_gem_mmap_gtt_version(void); 3239 3240 void i915_gem_track_fb(struct drm_i915_gem_object *old, 3241 struct drm_i915_gem_object *new, 3242 unsigned frontbuffer_bits); 3243 3244 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 3245 3246 struct drm_i915_gem_request * 3247 i915_gem_find_active_request(struct intel_engine_cs *engine); 3248 3249 void i915_gem_retire_requests(struct drm_i915_private *dev_priv); 3250 3251 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 3252 { 3253 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags)); 3254 } 3255 3256 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 3257 { 3258 return unlikely(test_bit(I915_WEDGED, &error->flags)); 3259 } 3260 3261 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) 3262 { 3263 return i915_reset_in_progress(error) | i915_terminally_wedged(error); 3264 } 3265 3266 static inline u32 i915_reset_count(struct i915_gpu_error *error) 3267 { 3268 return READ_ONCE(error->reset_count); 3269 } 3270 3271 void i915_gem_reset(struct drm_i915_private *dev_priv); 3272 void i915_gem_set_wedged(struct drm_i915_private *dev_priv); 3273 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 3274 int __must_check i915_gem_init(struct drm_device *dev); 3275 int __must_check i915_gem_init_hw(struct drm_device *dev); 3276 void i915_gem_init_swizzling(struct drm_device *dev); 3277 void i915_gem_cleanup_engines(struct drm_device *dev); 3278 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, 3279 unsigned int flags); 3280 int __must_check i915_gem_suspend(struct drm_device *dev); 3281 void i915_gem_resume(struct drm_device *dev); 3282 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 3283 int __must_check 3284 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 3285 bool readonly); 3286 int __must_check 3287 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 3288 bool write); 3289 int __must_check 3290 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 3291 struct i915_vma * __must_check 3292 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 3293 u32 alignment, 3294 const struct i915_ggtt_view *view); 3295 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); 3296 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 3297 int align); 3298 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 3299 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 3300 3301 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size, 3302 int tiling_mode); 3303 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, 3304 int tiling_mode, bool fenced); 3305 3306 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 3307 enum i915_cache_level cache_level); 3308 3309 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 3310 struct dma_buf *dma_buf); 3311 3312 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 3313 struct drm_gem_object *gem_obj, int flags); 3314 3315 struct i915_vma * 3316 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 3317 struct i915_address_space *vm, 3318 const struct i915_ggtt_view *view); 3319 3320 struct i915_vma * 3321 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 3322 struct i915_address_space *vm, 3323 const struct i915_ggtt_view *view); 3324 3325 static inline struct i915_hw_ppgtt * 3326 i915_vm_to_ppgtt(struct i915_address_space *vm) 3327 { 3328 return container_of(vm, struct i915_hw_ppgtt, base); 3329 } 3330 3331 static inline struct i915_vma * 3332 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj, 3333 const struct i915_ggtt_view *view) 3334 { 3335 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view); 3336 } 3337 3338 static inline unsigned long 3339 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o, 3340 const struct i915_ggtt_view *view) 3341 { 3342 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view)); 3343 } 3344 3345 /* i915_gem_fence.c */ 3346 int __must_check i915_vma_get_fence(struct i915_vma *vma); 3347 int __must_check i915_vma_put_fence(struct i915_vma *vma); 3348 3349 /** 3350 * i915_vma_pin_fence - pin fencing state 3351 * @vma: vma to pin fencing for 3352 * 3353 * This pins the fencing state (whether tiled or untiled) to make sure the 3354 * vma (and its object) is ready to be used as a scanout target. Fencing 3355 * status must be synchronize first by calling i915_vma_get_fence(): 3356 * 3357 * The resulting fence pin reference must be released again with 3358 * i915_vma_unpin_fence(). 3359 * 3360 * Returns: 3361 * 3362 * True if the vma has a fence, false otherwise. 3363 */ 3364 static inline bool 3365 i915_vma_pin_fence(struct i915_vma *vma) 3366 { 3367 if (vma->fence) { 3368 vma->fence->pin_count++; 3369 return true; 3370 } else 3371 return false; 3372 } 3373 3374 /** 3375 * i915_vma_unpin_fence - unpin fencing state 3376 * @vma: vma to unpin fencing for 3377 * 3378 * This releases the fence pin reference acquired through 3379 * i915_vma_pin_fence. It will handle both objects with and without an 3380 * attached fence correctly, callers do not need to distinguish this. 3381 */ 3382 static inline void 3383 i915_vma_unpin_fence(struct i915_vma *vma) 3384 { 3385 if (vma->fence) { 3386 GEM_BUG_ON(vma->fence->pin_count <= 0); 3387 vma->fence->pin_count--; 3388 } 3389 } 3390 3391 void i915_gem_restore_fences(struct drm_device *dev); 3392 3393 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 3394 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 3395 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 3396 3397 /* i915_gem_context.c */ 3398 int __must_check i915_gem_context_init(struct drm_device *dev); 3399 void i915_gem_context_lost(struct drm_i915_private *dev_priv); 3400 void i915_gem_context_fini(struct drm_device *dev); 3401 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 3402 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 3403 int i915_switch_context(struct drm_i915_gem_request *req); 3404 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv); 3405 void i915_gem_context_free(struct kref *ctx_ref); 3406 struct drm_i915_gem_object * 3407 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); 3408 struct i915_gem_context * 3409 i915_gem_context_create_gvt(struct drm_device *dev); 3410 3411 static inline struct i915_gem_context * 3412 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 3413 { 3414 struct i915_gem_context *ctx; 3415 3416 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); 3417 3418 ctx = idr_find(&file_priv->context_idr, id); 3419 if (!ctx) 3420 return ERR_PTR(-ENOENT); 3421 3422 return ctx; 3423 } 3424 3425 static inline struct i915_gem_context * 3426 i915_gem_context_get(struct i915_gem_context *ctx) 3427 { 3428 kref_get(&ctx->ref); 3429 return ctx; 3430 } 3431 3432 static inline void i915_gem_context_put(struct i915_gem_context *ctx) 3433 { 3434 lockdep_assert_held(&ctx->i915->drm.struct_mutex); 3435 kref_put(&ctx->ref, i915_gem_context_free); 3436 } 3437 3438 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) 3439 { 3440 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 3441 } 3442 3443 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 3444 struct drm_file *file); 3445 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 3446 struct drm_file *file); 3447 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 3448 struct drm_file *file_priv); 3449 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 3450 struct drm_file *file_priv); 3451 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, 3452 struct drm_file *file); 3453 3454 /* i915_gem_evict.c */ 3455 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 3456 u64 min_size, u64 alignment, 3457 unsigned cache_level, 3458 u64 start, u64 end, 3459 unsigned flags); 3460 int __must_check i915_gem_evict_for_vma(struct i915_vma *target); 3461 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 3462 3463 /* belongs in i915_gem_gtt.h */ 3464 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) 3465 { 3466 wmb(); 3467 if (INTEL_GEN(dev_priv) < 6) 3468 intel_gtt_chipset_flush(); 3469 } 3470 3471 /* i915_gem_stolen.c */ 3472 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, 3473 struct drm_mm_node *node, u64 size, 3474 unsigned alignment); 3475 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, 3476 struct drm_mm_node *node, u64 size, 3477 unsigned alignment, u64 start, 3478 u64 end); 3479 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, 3480 struct drm_mm_node *node); 3481 int i915_gem_init_stolen(struct drm_device *dev); 3482 void i915_gem_cleanup_stolen(struct drm_device *dev); 3483 struct drm_i915_gem_object * 3484 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 3485 struct drm_i915_gem_object * 3486 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 3487 u32 stolen_offset, 3488 u32 gtt_offset, 3489 u32 size); 3490 3491 /* i915_gem_shrinker.c */ 3492 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 3493 unsigned long target, 3494 unsigned flags); 3495 #define I915_SHRINK_PURGEABLE 0x1 3496 #define I915_SHRINK_UNBOUND 0x2 3497 #define I915_SHRINK_BOUND 0x4 3498 #define I915_SHRINK_ACTIVE 0x8 3499 #define I915_SHRINK_VMAPS 0x10 3500 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); 3501 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); 3502 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); 3503 3504 3505 /* i915_gem_tiling.c */ 3506 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 3507 { 3508 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 3509 3510 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 3511 i915_gem_object_is_tiled(obj); 3512 } 3513 3514 /* i915_debugfs.c */ 3515 #ifdef CONFIG_DEBUG_FS 3516 int i915_debugfs_register(struct drm_i915_private *dev_priv); 3517 void i915_debugfs_unregister(struct drm_i915_private *dev_priv); 3518 int i915_debugfs_connector_add(struct drm_connector *connector); 3519 void intel_display_crc_init(struct drm_i915_private *dev_priv); 3520 #else 3521 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} 3522 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} 3523 static inline int i915_debugfs_connector_add(struct drm_connector *connector) 3524 { return 0; } 3525 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} 3526 #endif 3527 3528 /* i915_gpu_error.c */ 3529 __printf(2, 3) 3530 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 3531 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 3532 const struct i915_error_state_file_priv *error); 3533 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 3534 struct drm_i915_private *i915, 3535 size_t count, loff_t pos); 3536 static inline void i915_error_state_buf_release( 3537 struct drm_i915_error_state_buf *eb) 3538 { 3539 kfree(eb->buf); 3540 } 3541 void i915_capture_error_state(struct drm_i915_private *dev_priv, 3542 u32 engine_mask, 3543 const char *error_msg); 3544 void i915_error_state_get(struct drm_device *dev, 3545 struct i915_error_state_file_priv *error_priv); 3546 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 3547 void i915_destroy_error_state(struct drm_device *dev); 3548 3549 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone); 3550 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 3551 3552 /* i915_cmd_parser.c */ 3553 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 3554 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 3555 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 3556 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine); 3557 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 3558 struct drm_i915_gem_object *batch_obj, 3559 struct drm_i915_gem_object *shadow_batch_obj, 3560 u32 batch_start_offset, 3561 u32 batch_len, 3562 bool is_master); 3563 3564 /* i915_suspend.c */ 3565 extern int i915_save_state(struct drm_device *dev); 3566 extern int i915_restore_state(struct drm_device *dev); 3567 3568 /* i915_sysfs.c */ 3569 void i915_setup_sysfs(struct drm_i915_private *dev_priv); 3570 void i915_teardown_sysfs(struct drm_i915_private *dev_priv); 3571 3572 /* intel_i2c.c */ 3573 extern int intel_setup_gmbus(struct drm_device *dev); 3574 extern void intel_teardown_gmbus(struct drm_device *dev); 3575 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 3576 unsigned int pin); 3577 3578 extern struct i2c_adapter * 3579 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); 3580 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 3581 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 3582 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 3583 { 3584 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 3585 } 3586 extern void intel_i2c_reset(struct drm_device *dev); 3587 3588 /* intel_bios.c */ 3589 int intel_bios_init(struct drm_i915_private *dev_priv); 3590 bool intel_bios_is_valid_vbt(const void *buf, size_t size); 3591 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); 3592 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); 3593 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); 3594 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); 3595 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); 3596 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); 3597 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, 3598 enum port port); 3599 3600 /* intel_opregion.c */ 3601 #ifdef CONFIG_ACPI 3602 extern int intel_opregion_setup(struct drm_i915_private *dev_priv); 3603 extern void intel_opregion_register(struct drm_i915_private *dev_priv); 3604 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); 3605 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); 3606 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 3607 bool enable); 3608 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, 3609 pci_power_t state); 3610 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); 3611 #else 3612 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } 3613 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } 3614 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } 3615 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) 3616 { 3617 } 3618 static inline int 3619 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 3620 { 3621 return 0; 3622 } 3623 static inline int 3624 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) 3625 { 3626 return 0; 3627 } 3628 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) 3629 { 3630 return -ENODEV; 3631 } 3632 #endif 3633 3634 /* intel_acpi.c */ 3635 #ifdef CONFIG_ACPI 3636 extern void intel_register_dsm_handler(void); 3637 extern void intel_unregister_dsm_handler(void); 3638 #else 3639 static inline void intel_register_dsm_handler(void) { return; } 3640 static inline void intel_unregister_dsm_handler(void) { return; } 3641 #endif /* CONFIG_ACPI */ 3642 3643 /* intel_device_info.c */ 3644 static inline struct intel_device_info * 3645 mkwrite_device_info(struct drm_i915_private *dev_priv) 3646 { 3647 return (struct intel_device_info *)&dev_priv->info; 3648 } 3649 3650 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 3651 void intel_device_info_dump(struct drm_i915_private *dev_priv); 3652 3653 /* modesetting */ 3654 extern void intel_modeset_init_hw(struct drm_device *dev); 3655 extern void intel_modeset_init(struct drm_device *dev); 3656 extern void intel_modeset_gem_init(struct drm_device *dev); 3657 extern void intel_modeset_cleanup(struct drm_device *dev); 3658 extern int intel_connector_register(struct drm_connector *); 3659 extern void intel_connector_unregister(struct drm_connector *); 3660 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 3661 extern void intel_display_resume(struct drm_device *dev); 3662 extern void i915_redisable_vga(struct drm_device *dev); 3663 extern void i915_redisable_vga_power_on(struct drm_device *dev); 3664 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); 3665 extern void intel_init_pch_refclk(struct drm_device *dev); 3666 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); 3667 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 3668 bool enable); 3669 3670 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 3671 struct drm_file *file); 3672 3673 /* overlay */ 3674 extern struct intel_overlay_error_state * 3675 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); 3676 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 3677 struct intel_overlay_error_state *error); 3678 3679 extern struct intel_display_error_state * 3680 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 3681 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 3682 struct drm_device *dev, 3683 struct intel_display_error_state *error); 3684 3685 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3686 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 3687 3688 /* intel_sideband.c */ 3689 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); 3690 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); 3691 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 3692 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); 3693 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); 3694 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 3695 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3696 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 3697 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3698 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 3699 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3700 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 3701 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 3702 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 3703 enum intel_sbi_destination destination); 3704 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 3705 enum intel_sbi_destination destination); 3706 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 3707 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3708 3709 /* intel_dpio_phy.c */ 3710 void chv_set_phy_signal_level(struct intel_encoder *encoder, 3711 u32 deemph_reg_value, u32 margin_reg_value, 3712 bool uniq_trans_scale); 3713 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 3714 bool reset); 3715 void chv_phy_pre_pll_enable(struct intel_encoder *encoder); 3716 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); 3717 void chv_phy_release_cl2_override(struct intel_encoder *encoder); 3718 void chv_phy_post_pll_disable(struct intel_encoder *encoder); 3719 3720 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 3721 u32 demph_reg_value, u32 preemph_reg_value, 3722 u32 uniqtranscale_reg_value, u32 tx3_demph); 3723 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); 3724 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); 3725 void vlv_phy_reset_lanes(struct intel_encoder *encoder); 3726 3727 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); 3728 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 3729 3730 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 3731 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 3732 3733 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 3734 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 3735 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 3736 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 3737 3738 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 3739 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 3740 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 3741 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 3742 3743 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 3744 * will be implemented using 2 32-bit writes in an arbitrary order with 3745 * an arbitrary delay between them. This can cause the hardware to 3746 * act upon the intermediate value, possibly leading to corruption and 3747 * machine death. For this reason we do not support I915_WRITE64, or 3748 * dev_priv->uncore.funcs.mmio_writeq. 3749 * 3750 * When reading a 64-bit value as two 32-bit values, the delay may cause 3751 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that 3752 * occasionally a 64-bit register does not actualy support a full readq 3753 * and must be read using two 32-bit reads. 3754 * 3755 * You have been warned. 3756 */ 3757 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 3758 3759 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 3760 u32 upper, lower, old_upper, loop = 0; \ 3761 upper = I915_READ(upper_reg); \ 3762 do { \ 3763 old_upper = upper; \ 3764 lower = I915_READ(lower_reg); \ 3765 upper = I915_READ(upper_reg); \ 3766 } while (upper != old_upper && loop++ < 2); \ 3767 (u64)upper << 32 | lower; }) 3768 3769 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 3770 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 3771 3772 #define __raw_read(x, s) \ 3773 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ 3774 i915_reg_t reg) \ 3775 { \ 3776 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ 3777 } 3778 3779 #define __raw_write(x, s) \ 3780 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ 3781 i915_reg_t reg, uint##x##_t val) \ 3782 { \ 3783 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ 3784 } 3785 __raw_read(8, b) 3786 __raw_read(16, w) 3787 __raw_read(32, l) 3788 __raw_read(64, q) 3789 3790 __raw_write(8, b) 3791 __raw_write(16, w) 3792 __raw_write(32, l) 3793 __raw_write(64, q) 3794 3795 #undef __raw_read 3796 #undef __raw_write 3797 3798 /* These are untraced mmio-accessors that are only valid to be used inside 3799 * critical sections inside IRQ handlers where forcewake is explicitly 3800 * controlled. 3801 * Think twice, and think again, before using these. 3802 * Note: Should only be used between intel_uncore_forcewake_irqlock() and 3803 * intel_uncore_forcewake_irqunlock(). 3804 */ 3805 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) 3806 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) 3807 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) 3808 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) 3809 3810 /* "Broadcast RGB" property */ 3811 #define INTEL_BROADCAST_RGB_AUTO 0 3812 #define INTEL_BROADCAST_RGB_FULL 1 3813 #define INTEL_BROADCAST_RGB_LIMITED 2 3814 3815 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) 3816 { 3817 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 3818 return VLV_VGACNTRL; 3819 else if (INTEL_INFO(dev)->gen >= 5) 3820 return CPU_VGACNTRL; 3821 else 3822 return VGACNTRL; 3823 } 3824 3825 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 3826 { 3827 unsigned long j = msecs_to_jiffies(m); 3828 3829 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3830 } 3831 3832 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 3833 { 3834 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 3835 } 3836 3837 static inline unsigned long 3838 timespec_to_jiffies_timeout(const struct timespec *value) 3839 { 3840 unsigned long j = timespec_to_jiffies(value); 3841 3842 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3843 } 3844 3845 /* 3846 * If you need to wait X milliseconds between events A and B, but event B 3847 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 3848 * when event A happened, then just before event B you call this function and 3849 * pass the timestamp as the first argument, and X as the second argument. 3850 */ 3851 static inline void 3852 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 3853 { 3854 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 3855 3856 /* 3857 * Don't re-read the value of "jiffies" every time since it may change 3858 * behind our back and break the math. 3859 */ 3860 tmp_jiffies = jiffies; 3861 target_jiffies = timestamp_jiffies + 3862 msecs_to_jiffies_timeout(to_wait_ms); 3863 3864 if (time_after(target_jiffies, tmp_jiffies)) { 3865 remaining_jiffies = target_jiffies - tmp_jiffies; 3866 while (remaining_jiffies) 3867 remaining_jiffies = 3868 schedule_timeout_uninterruptible(remaining_jiffies); 3869 } 3870 } 3871 3872 static inline bool 3873 __i915_request_irq_complete(struct drm_i915_gem_request *req) 3874 { 3875 struct intel_engine_cs *engine = req->engine; 3876 3877 /* Before we do the heavier coherent read of the seqno, 3878 * check the value (hopefully) in the CPU cacheline. 3879 */ 3880 if (i915_gem_request_completed(req)) 3881 return true; 3882 3883 /* Ensure our read of the seqno is coherent so that we 3884 * do not "miss an interrupt" (i.e. if this is the last 3885 * request and the seqno write from the GPU is not visible 3886 * by the time the interrupt fires, we will see that the 3887 * request is incomplete and go back to sleep awaiting 3888 * another interrupt that will never come.) 3889 * 3890 * Strictly, we only need to do this once after an interrupt, 3891 * but it is easier and safer to do it every time the waiter 3892 * is woken. 3893 */ 3894 if (engine->irq_seqno_barrier && 3895 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current && 3896 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { 3897 struct task_struct *tsk; 3898 3899 /* The ordering of irq_posted versus applying the barrier 3900 * is crucial. The clearing of the current irq_posted must 3901 * be visible before we perform the barrier operation, 3902 * such that if a subsequent interrupt arrives, irq_posted 3903 * is reasserted and our task rewoken (which causes us to 3904 * do another __i915_request_irq_complete() immediately 3905 * and reapply the barrier). Conversely, if the clear 3906 * occurs after the barrier, then an interrupt that arrived 3907 * whilst we waited on the barrier would not trigger a 3908 * barrier on the next pass, and the read may not see the 3909 * seqno update. 3910 */ 3911 engine->irq_seqno_barrier(engine); 3912 3913 /* If we consume the irq, but we are no longer the bottom-half, 3914 * the real bottom-half may not have serialised their own 3915 * seqno check with the irq-barrier (i.e. may have inspected 3916 * the seqno before we believe it coherent since they see 3917 * irq_posted == false but we are still running). 3918 */ 3919 rcu_read_lock(); 3920 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh); 3921 if (tsk && tsk != current) 3922 /* Note that if the bottom-half is changed as we 3923 * are sending the wake-up, the new bottom-half will 3924 * be woken by whomever made the change. We only have 3925 * to worry about when we steal the irq-posted for 3926 * ourself. 3927 */ 3928 wake_up_process(tsk); 3929 rcu_read_unlock(); 3930 3931 if (i915_gem_request_completed(req)) 3932 return true; 3933 } 3934 3935 return false; 3936 } 3937 3938 void i915_memcpy_init_early(struct drm_i915_private *dev_priv); 3939 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); 3940 3941 /* i915_mm.c */ 3942 int remap_io_mapping(struct vm_area_struct *vma, 3943 unsigned long addr, unsigned long pfn, unsigned long size, 3944 struct io_mapping *iomap); 3945 3946 #define ptr_mask_bits(ptr) ({ \ 3947 unsigned long __v = (unsigned long)(ptr); \ 3948 (typeof(ptr))(__v & PAGE_MASK); \ 3949 }) 3950 3951 #define ptr_unpack_bits(ptr, bits) ({ \ 3952 unsigned long __v = (unsigned long)(ptr); \ 3953 (bits) = __v & ~PAGE_MASK; \ 3954 (typeof(ptr))(__v & PAGE_MASK); \ 3955 }) 3956 3957 #define ptr_pack_bits(ptr, bits) \ 3958 ((typeof(ptr))((unsigned long)(ptr) | (bits))) 3959 3960 #define fetch_and_zero(ptr) ({ \ 3961 typeof(*ptr) __T = *(ptr); \ 3962 *(ptr) = (typeof(*ptr))0; \ 3963 __T; \ 3964 }) 3965 3966 #endif 3967