1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <drm/intel-gtt.h> 42 #include <linux/backlight.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/pm_qos.h> 46 47 /* General customization: 48 */ 49 50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 51 52 #define DRIVER_NAME "i915" 53 #define DRIVER_DESC "Intel Graphics" 54 #define DRIVER_DATE "20080730" 55 56 enum pipe { 57 PIPE_A = 0, 58 PIPE_B, 59 PIPE_C, 60 I915_MAX_PIPES 61 }; 62 #define pipe_name(p) ((p) + 'A') 63 64 enum transcoder { 65 TRANSCODER_A = 0, 66 TRANSCODER_B, 67 TRANSCODER_C, 68 TRANSCODER_EDP = 0xF, 69 }; 70 #define transcoder_name(t) ((t) + 'A') 71 72 enum plane { 73 PLANE_A = 0, 74 PLANE_B, 75 PLANE_C, 76 }; 77 #define plane_name(p) ((p) + 'A') 78 79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') 80 81 enum port { 82 PORT_A = 0, 83 PORT_B, 84 PORT_C, 85 PORT_D, 86 PORT_E, 87 I915_MAX_PORTS 88 }; 89 #define port_name(p) ((p) + 'A') 90 91 enum intel_display_power_domain { 92 POWER_DOMAIN_PIPE_A, 93 POWER_DOMAIN_PIPE_B, 94 POWER_DOMAIN_PIPE_C, 95 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 96 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 97 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 98 POWER_DOMAIN_TRANSCODER_A, 99 POWER_DOMAIN_TRANSCODER_B, 100 POWER_DOMAIN_TRANSCODER_C, 101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF, 102 }; 103 104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A) 108 109 enum hpd_pin { 110 HPD_NONE = 0, 111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 113 HPD_CRT, 114 HPD_SDVO_B, 115 HPD_SDVO_C, 116 HPD_PORT_B, 117 HPD_PORT_C, 118 HPD_PORT_D, 119 HPD_NUM_PINS 120 }; 121 122 #define I915_GEM_GPU_DOMAINS \ 123 (I915_GEM_DOMAIN_RENDER | \ 124 I915_GEM_DOMAIN_SAMPLER | \ 125 I915_GEM_DOMAIN_COMMAND | \ 126 I915_GEM_DOMAIN_INSTRUCTION | \ 127 I915_GEM_DOMAIN_VERTEX) 128 129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 130 131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 133 if ((intel_encoder)->base.crtc == (__crtc)) 134 135 struct drm_i915_private; 136 137 enum intel_dpll_id { 138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 139 /* real shared dpll ids must be >= 0 */ 140 DPLL_ID_PCH_PLL_A, 141 DPLL_ID_PCH_PLL_B, 142 }; 143 #define I915_NUM_PLLS 2 144 145 struct intel_dpll_hw_state { 146 uint32_t dpll; 147 uint32_t fp0; 148 uint32_t fp1; 149 }; 150 151 struct intel_shared_dpll { 152 int refcount; /* count of number of CRTCs sharing this PLL */ 153 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 154 bool on; /* is the PLL actually active? Disabled during modeset */ 155 const char *name; 156 /* should match the index in the dev_priv->shared_dplls array */ 157 enum intel_dpll_id id; 158 struct intel_dpll_hw_state hw_state; 159 void (*enable)(struct drm_i915_private *dev_priv, 160 struct intel_shared_dpll *pll); 161 void (*disable)(struct drm_i915_private *dev_priv, 162 struct intel_shared_dpll *pll); 163 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 164 struct intel_shared_dpll *pll, 165 struct intel_dpll_hw_state *hw_state); 166 }; 167 168 /* Used by dp and fdi links */ 169 struct intel_link_m_n { 170 uint32_t tu; 171 uint32_t gmch_m; 172 uint32_t gmch_n; 173 uint32_t link_m; 174 uint32_t link_n; 175 }; 176 177 void intel_link_compute_m_n(int bpp, int nlanes, 178 int pixel_clock, int link_clock, 179 struct intel_link_m_n *m_n); 180 181 struct intel_ddi_plls { 182 int spll_refcount; 183 int wrpll1_refcount; 184 int wrpll2_refcount; 185 }; 186 187 /* Interface history: 188 * 189 * 1.1: Original. 190 * 1.2: Add Power Management 191 * 1.3: Add vblank support 192 * 1.4: Fix cmdbuffer path, add heap destroy 193 * 1.5: Add vblank pipe configuration 194 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 195 * - Support vertical blank on secondary display pipe 196 */ 197 #define DRIVER_MAJOR 1 198 #define DRIVER_MINOR 6 199 #define DRIVER_PATCHLEVEL 0 200 201 #define WATCH_COHERENCY 0 202 #define WATCH_LISTS 0 203 #define WATCH_GTT 0 204 205 #define I915_GEM_PHYS_CURSOR_0 1 206 #define I915_GEM_PHYS_CURSOR_1 2 207 #define I915_GEM_PHYS_OVERLAY_REGS 3 208 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 209 210 struct drm_i915_gem_phys_object { 211 int id; 212 struct page **page_list; 213 drm_dma_handle_t *handle; 214 struct drm_i915_gem_object *cur_obj; 215 }; 216 217 struct opregion_header; 218 struct opregion_acpi; 219 struct opregion_swsci; 220 struct opregion_asle; 221 222 struct intel_opregion { 223 struct opregion_header __iomem *header; 224 struct opregion_acpi __iomem *acpi; 225 struct opregion_swsci __iomem *swsci; 226 struct opregion_asle __iomem *asle; 227 void __iomem *vbt; 228 u32 __iomem *lid_state; 229 }; 230 #define OPREGION_SIZE (8*1024) 231 232 struct intel_overlay; 233 struct intel_overlay_error_state; 234 235 struct drm_i915_master_private { 236 drm_local_map_t *sarea; 237 struct _drm_i915_sarea *sarea_priv; 238 }; 239 #define I915_FENCE_REG_NONE -1 240 #define I915_MAX_NUM_FENCES 32 241 /* 32 fences + sign bit for FENCE_REG_NONE */ 242 #define I915_MAX_NUM_FENCE_BITS 6 243 244 struct drm_i915_fence_reg { 245 struct list_head lru_list; 246 struct drm_i915_gem_object *obj; 247 int pin_count; 248 }; 249 250 struct sdvo_device_mapping { 251 u8 initialized; 252 u8 dvo_port; 253 u8 slave_addr; 254 u8 dvo_wiring; 255 u8 i2c_pin; 256 u8 ddc_pin; 257 }; 258 259 struct intel_display_error_state; 260 261 struct drm_i915_error_state { 262 struct kref ref; 263 u32 eir; 264 u32 pgtbl_er; 265 u32 ier; 266 u32 ccid; 267 u32 derrmr; 268 u32 forcewake; 269 bool waiting[I915_NUM_RINGS]; 270 u32 pipestat[I915_MAX_PIPES]; 271 u32 tail[I915_NUM_RINGS]; 272 u32 head[I915_NUM_RINGS]; 273 u32 ctl[I915_NUM_RINGS]; 274 u32 ipeir[I915_NUM_RINGS]; 275 u32 ipehr[I915_NUM_RINGS]; 276 u32 instdone[I915_NUM_RINGS]; 277 u32 acthd[I915_NUM_RINGS]; 278 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 279 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 280 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 281 /* our own tracking of ring head and tail */ 282 u32 cpu_ring_head[I915_NUM_RINGS]; 283 u32 cpu_ring_tail[I915_NUM_RINGS]; 284 u32 error; /* gen6+ */ 285 u32 err_int; /* gen7 */ 286 u32 instpm[I915_NUM_RINGS]; 287 u32 instps[I915_NUM_RINGS]; 288 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 289 u32 seqno[I915_NUM_RINGS]; 290 u64 bbaddr; 291 u32 fault_reg[I915_NUM_RINGS]; 292 u32 done_reg; 293 u32 faddr[I915_NUM_RINGS]; 294 u64 fence[I915_MAX_NUM_FENCES]; 295 struct timeval time; 296 struct drm_i915_error_ring { 297 struct drm_i915_error_object { 298 int page_count; 299 u32 gtt_offset; 300 u32 *pages[0]; 301 } *ringbuffer, *batchbuffer, *ctx; 302 struct drm_i915_error_request { 303 long jiffies; 304 u32 seqno; 305 u32 tail; 306 } *requests; 307 int num_requests; 308 } ring[I915_NUM_RINGS]; 309 struct drm_i915_error_buffer { 310 u32 size; 311 u32 name; 312 u32 rseqno, wseqno; 313 u32 gtt_offset; 314 u32 read_domains; 315 u32 write_domain; 316 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 317 s32 pinned:2; 318 u32 tiling:2; 319 u32 dirty:1; 320 u32 purgeable:1; 321 s32 ring:4; 322 u32 cache_level:2; 323 } *active_bo, *pinned_bo; 324 u32 active_bo_count, pinned_bo_count; 325 struct intel_overlay_error_state *overlay; 326 struct intel_display_error_state *display; 327 }; 328 329 struct intel_crtc_config; 330 struct intel_crtc; 331 struct intel_limit; 332 struct dpll; 333 334 struct drm_i915_display_funcs { 335 bool (*fbc_enabled)(struct drm_device *dev); 336 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 337 void (*disable_fbc)(struct drm_device *dev); 338 int (*get_display_clock_speed)(struct drm_device *dev); 339 int (*get_fifo_size)(struct drm_device *dev, int plane); 340 /** 341 * find_dpll() - Find the best values for the PLL 342 * @limit: limits for the PLL 343 * @crtc: current CRTC 344 * @target: target frequency in kHz 345 * @refclk: reference clock frequency in kHz 346 * @match_clock: if provided, @best_clock P divider must 347 * match the P divider from @match_clock 348 * used for LVDS downclocking 349 * @best_clock: best PLL values found 350 * 351 * Returns true on success, false on failure. 352 */ 353 bool (*find_dpll)(const struct intel_limit *limit, 354 struct drm_crtc *crtc, 355 int target, int refclk, 356 struct dpll *match_clock, 357 struct dpll *best_clock); 358 void (*update_wm)(struct drm_device *dev); 359 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 360 uint32_t sprite_width, int pixel_size, 361 bool enable); 362 void (*modeset_global_resources)(struct drm_device *dev); 363 /* Returns the active state of the crtc, and if the crtc is active, 364 * fills out the pipe-config with the hw state. */ 365 bool (*get_pipe_config)(struct intel_crtc *, 366 struct intel_crtc_config *); 367 int (*crtc_mode_set)(struct drm_crtc *crtc, 368 int x, int y, 369 struct drm_framebuffer *old_fb); 370 void (*crtc_enable)(struct drm_crtc *crtc); 371 void (*crtc_disable)(struct drm_crtc *crtc); 372 void (*off)(struct drm_crtc *crtc); 373 void (*write_eld)(struct drm_connector *connector, 374 struct drm_crtc *crtc); 375 void (*fdi_link_train)(struct drm_crtc *crtc); 376 void (*init_clock_gating)(struct drm_device *dev); 377 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 378 struct drm_framebuffer *fb, 379 struct drm_i915_gem_object *obj); 380 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 381 int x, int y); 382 void (*hpd_irq_setup)(struct drm_device *dev); 383 /* clock updates for mode set */ 384 /* cursor updates */ 385 /* render clock increase/decrease */ 386 /* display clock increase/decrease */ 387 /* pll clock increase/decrease */ 388 }; 389 390 struct drm_i915_gt_funcs { 391 void (*force_wake_get)(struct drm_i915_private *dev_priv); 392 void (*force_wake_put)(struct drm_i915_private *dev_priv); 393 }; 394 395 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 396 func(is_mobile) sep \ 397 func(is_i85x) sep \ 398 func(is_i915g) sep \ 399 func(is_i945gm) sep \ 400 func(is_g33) sep \ 401 func(need_gfx_hws) sep \ 402 func(is_g4x) sep \ 403 func(is_pineview) sep \ 404 func(is_broadwater) sep \ 405 func(is_crestline) sep \ 406 func(is_ivybridge) sep \ 407 func(is_valleyview) sep \ 408 func(is_haswell) sep \ 409 func(has_force_wake) sep \ 410 func(has_fbc) sep \ 411 func(has_pipe_cxsr) sep \ 412 func(has_hotplug) sep \ 413 func(cursor_needs_physical) sep \ 414 func(has_overlay) sep \ 415 func(overlay_needs_physical) sep \ 416 func(supports_tv) sep \ 417 func(has_bsd_ring) sep \ 418 func(has_blt_ring) sep \ 419 func(has_vebox_ring) sep \ 420 func(has_llc) sep \ 421 func(has_ddi) sep \ 422 func(has_fpga_dbg) 423 424 #define DEFINE_FLAG(name) u8 name:1 425 #define SEP_SEMICOLON ; 426 427 struct intel_device_info { 428 u32 display_mmio_offset; 429 u8 num_pipes:3; 430 u8 gen; 431 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 432 }; 433 434 #undef DEFINE_FLAG 435 #undef SEP_SEMICOLON 436 437 enum i915_cache_level { 438 I915_CACHE_NONE = 0, 439 I915_CACHE_LLC, 440 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ 441 }; 442 443 typedef uint32_t gen6_gtt_pte_t; 444 445 /* The Graphics Translation Table is the way in which GEN hardware translates a 446 * Graphics Virtual Address into a Physical Address. In addition to the normal 447 * collateral associated with any va->pa translations GEN hardware also has a 448 * portion of the GTT which can be mapped by the CPU and remain both coherent 449 * and correct (in cases like swizzling). That region is referred to as GMADR in 450 * the spec. 451 */ 452 struct i915_gtt { 453 unsigned long start; /* Start offset of used GTT */ 454 size_t total; /* Total size GTT can map */ 455 size_t stolen_size; /* Total size of stolen memory */ 456 457 unsigned long mappable_end; /* End offset that we can CPU map */ 458 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 459 phys_addr_t mappable_base; /* PA of our GMADR */ 460 461 /** "Graphics Stolen Memory" holds the global PTEs */ 462 void __iomem *gsm; 463 464 bool do_idle_maps; 465 dma_addr_t scratch_page_dma; 466 struct page *scratch_page; 467 468 /* global gtt ops */ 469 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 470 size_t *stolen, phys_addr_t *mappable_base, 471 unsigned long *mappable_end); 472 void (*gtt_remove)(struct drm_device *dev); 473 void (*gtt_clear_range)(struct drm_device *dev, 474 unsigned int first_entry, 475 unsigned int num_entries); 476 void (*gtt_insert_entries)(struct drm_device *dev, 477 struct sg_table *st, 478 unsigned int pg_start, 479 enum i915_cache_level cache_level); 480 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, 481 dma_addr_t addr, 482 enum i915_cache_level level); 483 }; 484 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) 485 486 #define I915_PPGTT_PD_ENTRIES 512 487 #define I915_PPGTT_PT_ENTRIES 1024 488 struct i915_hw_ppgtt { 489 struct drm_device *dev; 490 unsigned num_pd_entries; 491 struct page **pt_pages; 492 uint32_t pd_offset; 493 dma_addr_t *pt_dma_addr; 494 dma_addr_t scratch_page_dma_addr; 495 496 /* pte functions, mirroring the interface of the global gtt. */ 497 void (*clear_range)(struct i915_hw_ppgtt *ppgtt, 498 unsigned int first_entry, 499 unsigned int num_entries); 500 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, 501 struct sg_table *st, 502 unsigned int pg_start, 503 enum i915_cache_level cache_level); 504 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, 505 dma_addr_t addr, 506 enum i915_cache_level level); 507 int (*enable)(struct drm_device *dev); 508 void (*cleanup)(struct i915_hw_ppgtt *ppgtt); 509 }; 510 511 struct i915_ctx_hang_stats { 512 /* This context had batch pending when hang was declared */ 513 unsigned batch_pending; 514 515 /* This context had batch active when hang was declared */ 516 unsigned batch_active; 517 }; 518 519 /* This must match up with the value previously used for execbuf2.rsvd1. */ 520 #define DEFAULT_CONTEXT_ID 0 521 struct i915_hw_context { 522 struct kref ref; 523 int id; 524 bool is_initialized; 525 struct drm_i915_file_private *file_priv; 526 struct intel_ring_buffer *ring; 527 struct drm_i915_gem_object *obj; 528 struct i915_ctx_hang_stats hang_stats; 529 }; 530 531 enum no_fbc_reason { 532 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 533 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 534 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 535 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 536 FBC_BAD_PLANE, /* fbc not supported on plane */ 537 FBC_NOT_TILED, /* buffer not tiled */ 538 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 539 FBC_MODULE_PARAM, 540 }; 541 542 enum intel_pch { 543 PCH_NONE = 0, /* No PCH present */ 544 PCH_IBX, /* Ibexpeak PCH */ 545 PCH_CPT, /* Cougarpoint PCH */ 546 PCH_LPT, /* Lynxpoint PCH */ 547 PCH_NOP, 548 }; 549 550 enum intel_sbi_destination { 551 SBI_ICLK, 552 SBI_MPHY, 553 }; 554 555 #define QUIRK_PIPEA_FORCE (1<<0) 556 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 557 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 558 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) 559 560 struct intel_fbdev; 561 struct intel_fbc_work; 562 563 struct intel_gmbus { 564 struct i2c_adapter adapter; 565 u32 force_bit; 566 u32 reg0; 567 u32 gpio_reg; 568 struct i2c_algo_bit_data bit_algo; 569 struct drm_i915_private *dev_priv; 570 }; 571 572 struct i915_suspend_saved_registers { 573 u8 saveLBB; 574 u32 saveDSPACNTR; 575 u32 saveDSPBCNTR; 576 u32 saveDSPARB; 577 u32 savePIPEACONF; 578 u32 savePIPEBCONF; 579 u32 savePIPEASRC; 580 u32 savePIPEBSRC; 581 u32 saveFPA0; 582 u32 saveFPA1; 583 u32 saveDPLL_A; 584 u32 saveDPLL_A_MD; 585 u32 saveHTOTAL_A; 586 u32 saveHBLANK_A; 587 u32 saveHSYNC_A; 588 u32 saveVTOTAL_A; 589 u32 saveVBLANK_A; 590 u32 saveVSYNC_A; 591 u32 saveBCLRPAT_A; 592 u32 saveTRANSACONF; 593 u32 saveTRANS_HTOTAL_A; 594 u32 saveTRANS_HBLANK_A; 595 u32 saveTRANS_HSYNC_A; 596 u32 saveTRANS_VTOTAL_A; 597 u32 saveTRANS_VBLANK_A; 598 u32 saveTRANS_VSYNC_A; 599 u32 savePIPEASTAT; 600 u32 saveDSPASTRIDE; 601 u32 saveDSPASIZE; 602 u32 saveDSPAPOS; 603 u32 saveDSPAADDR; 604 u32 saveDSPASURF; 605 u32 saveDSPATILEOFF; 606 u32 savePFIT_PGM_RATIOS; 607 u32 saveBLC_HIST_CTL; 608 u32 saveBLC_PWM_CTL; 609 u32 saveBLC_PWM_CTL2; 610 u32 saveBLC_CPU_PWM_CTL; 611 u32 saveBLC_CPU_PWM_CTL2; 612 u32 saveFPB0; 613 u32 saveFPB1; 614 u32 saveDPLL_B; 615 u32 saveDPLL_B_MD; 616 u32 saveHTOTAL_B; 617 u32 saveHBLANK_B; 618 u32 saveHSYNC_B; 619 u32 saveVTOTAL_B; 620 u32 saveVBLANK_B; 621 u32 saveVSYNC_B; 622 u32 saveBCLRPAT_B; 623 u32 saveTRANSBCONF; 624 u32 saveTRANS_HTOTAL_B; 625 u32 saveTRANS_HBLANK_B; 626 u32 saveTRANS_HSYNC_B; 627 u32 saveTRANS_VTOTAL_B; 628 u32 saveTRANS_VBLANK_B; 629 u32 saveTRANS_VSYNC_B; 630 u32 savePIPEBSTAT; 631 u32 saveDSPBSTRIDE; 632 u32 saveDSPBSIZE; 633 u32 saveDSPBPOS; 634 u32 saveDSPBADDR; 635 u32 saveDSPBSURF; 636 u32 saveDSPBTILEOFF; 637 u32 saveVGA0; 638 u32 saveVGA1; 639 u32 saveVGA_PD; 640 u32 saveVGACNTRL; 641 u32 saveADPA; 642 u32 saveLVDS; 643 u32 savePP_ON_DELAYS; 644 u32 savePP_OFF_DELAYS; 645 u32 saveDVOA; 646 u32 saveDVOB; 647 u32 saveDVOC; 648 u32 savePP_ON; 649 u32 savePP_OFF; 650 u32 savePP_CONTROL; 651 u32 savePP_DIVISOR; 652 u32 savePFIT_CONTROL; 653 u32 save_palette_a[256]; 654 u32 save_palette_b[256]; 655 u32 saveDPFC_CB_BASE; 656 u32 saveFBC_CFB_BASE; 657 u32 saveFBC_LL_BASE; 658 u32 saveFBC_CONTROL; 659 u32 saveFBC_CONTROL2; 660 u32 saveIER; 661 u32 saveIIR; 662 u32 saveIMR; 663 u32 saveDEIER; 664 u32 saveDEIMR; 665 u32 saveGTIER; 666 u32 saveGTIMR; 667 u32 saveFDI_RXA_IMR; 668 u32 saveFDI_RXB_IMR; 669 u32 saveCACHE_MODE_0; 670 u32 saveMI_ARB_STATE; 671 u32 saveSWF0[16]; 672 u32 saveSWF1[16]; 673 u32 saveSWF2[3]; 674 u8 saveMSR; 675 u8 saveSR[8]; 676 u8 saveGR[25]; 677 u8 saveAR_INDEX; 678 u8 saveAR[21]; 679 u8 saveDACMASK; 680 u8 saveCR[37]; 681 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 682 u32 saveCURACNTR; 683 u32 saveCURAPOS; 684 u32 saveCURABASE; 685 u32 saveCURBCNTR; 686 u32 saveCURBPOS; 687 u32 saveCURBBASE; 688 u32 saveCURSIZE; 689 u32 saveDP_B; 690 u32 saveDP_C; 691 u32 saveDP_D; 692 u32 savePIPEA_GMCH_DATA_M; 693 u32 savePIPEB_GMCH_DATA_M; 694 u32 savePIPEA_GMCH_DATA_N; 695 u32 savePIPEB_GMCH_DATA_N; 696 u32 savePIPEA_DP_LINK_M; 697 u32 savePIPEB_DP_LINK_M; 698 u32 savePIPEA_DP_LINK_N; 699 u32 savePIPEB_DP_LINK_N; 700 u32 saveFDI_RXA_CTL; 701 u32 saveFDI_TXA_CTL; 702 u32 saveFDI_RXB_CTL; 703 u32 saveFDI_TXB_CTL; 704 u32 savePFA_CTL_1; 705 u32 savePFB_CTL_1; 706 u32 savePFA_WIN_SZ; 707 u32 savePFB_WIN_SZ; 708 u32 savePFA_WIN_POS; 709 u32 savePFB_WIN_POS; 710 u32 savePCH_DREF_CONTROL; 711 u32 saveDISP_ARB_CTL; 712 u32 savePIPEA_DATA_M1; 713 u32 savePIPEA_DATA_N1; 714 u32 savePIPEA_LINK_M1; 715 u32 savePIPEA_LINK_N1; 716 u32 savePIPEB_DATA_M1; 717 u32 savePIPEB_DATA_N1; 718 u32 savePIPEB_LINK_M1; 719 u32 savePIPEB_LINK_N1; 720 u32 saveMCHBAR_RENDER_STANDBY; 721 u32 savePCH_PORT_HOTPLUG; 722 }; 723 724 struct intel_gen6_power_mgmt { 725 struct work_struct work; 726 struct delayed_work vlv_work; 727 u32 pm_iir; 728 /* lock - irqsave spinlock that protectects the work_struct and 729 * pm_iir. */ 730 spinlock_t lock; 731 732 /* The below variables an all the rps hw state are protected by 733 * dev->struct mutext. */ 734 u8 cur_delay; 735 u8 min_delay; 736 u8 max_delay; 737 u8 rpe_delay; 738 u8 hw_max; 739 740 struct delayed_work delayed_resume_work; 741 742 /* 743 * Protects RPS/RC6 register access and PCU communication. 744 * Must be taken after struct_mutex if nested. 745 */ 746 struct mutex hw_lock; 747 }; 748 749 /* defined intel_pm.c */ 750 extern spinlock_t mchdev_lock; 751 752 struct intel_ilk_power_mgmt { 753 u8 cur_delay; 754 u8 min_delay; 755 u8 max_delay; 756 u8 fmax; 757 u8 fstart; 758 759 u64 last_count1; 760 unsigned long last_time1; 761 unsigned long chipset_power; 762 u64 last_count2; 763 struct timespec last_time2; 764 unsigned long gfx_power; 765 u8 corr; 766 767 int c_m; 768 int r_t; 769 770 struct drm_i915_gem_object *pwrctx; 771 struct drm_i915_gem_object *renderctx; 772 }; 773 774 /* Power well structure for haswell */ 775 struct i915_power_well { 776 struct drm_device *device; 777 spinlock_t lock; 778 /* power well enable/disable usage count */ 779 int count; 780 int i915_request; 781 }; 782 783 struct i915_dri1_state { 784 unsigned allow_batchbuffer : 1; 785 u32 __iomem *gfx_hws_cpu_addr; 786 787 unsigned int cpp; 788 int back_offset; 789 int front_offset; 790 int current_page; 791 int page_flipping; 792 793 uint32_t counter; 794 }; 795 796 struct intel_l3_parity { 797 u32 *remap_info; 798 struct work_struct error_work; 799 }; 800 801 struct i915_gem_mm { 802 /** Memory allocator for GTT stolen memory */ 803 struct drm_mm stolen; 804 /** Memory allocator for GTT */ 805 struct drm_mm gtt_space; 806 /** List of all objects in gtt_space. Used to restore gtt 807 * mappings on resume */ 808 struct list_head bound_list; 809 /** 810 * List of objects which are not bound to the GTT (thus 811 * are idle and not used by the GPU) but still have 812 * (presumably uncached) pages still attached. 813 */ 814 struct list_head unbound_list; 815 816 /** Usable portion of the GTT for GEM */ 817 unsigned long stolen_base; /* limited to low memory (32-bit) */ 818 819 int gtt_mtrr; 820 821 /** PPGTT used for aliasing the PPGTT with the GTT */ 822 struct i915_hw_ppgtt *aliasing_ppgtt; 823 824 struct shrinker inactive_shrinker; 825 bool shrinker_no_lock_stealing; 826 827 /** 828 * List of objects currently involved in rendering. 829 * 830 * Includes buffers having the contents of their GPU caches 831 * flushed, not necessarily primitives. last_rendering_seqno 832 * represents when the rendering involved will be completed. 833 * 834 * A reference is held on the buffer while on this list. 835 */ 836 struct list_head active_list; 837 838 /** 839 * LRU list of objects which are not in the ringbuffer and 840 * are ready to unbind, but are still in the GTT. 841 * 842 * last_rendering_seqno is 0 while an object is in this list. 843 * 844 * A reference is not held on the buffer while on this list, 845 * as merely being GTT-bound shouldn't prevent its being 846 * freed, and we'll pull it off the list in the free path. 847 */ 848 struct list_head inactive_list; 849 850 /** LRU list of objects with fence regs on them. */ 851 struct list_head fence_list; 852 853 /** 854 * We leave the user IRQ off as much as possible, 855 * but this means that requests will finish and never 856 * be retired once the system goes idle. Set a timer to 857 * fire periodically while the ring is running. When it 858 * fires, go retire requests. 859 */ 860 struct delayed_work retire_work; 861 862 /** 863 * Are we in a non-interruptible section of code like 864 * modesetting? 865 */ 866 bool interruptible; 867 868 /** 869 * Flag if the X Server, and thus DRM, is not currently in 870 * control of the device. 871 * 872 * This is set between LeaveVT and EnterVT. It needs to be 873 * replaced with a semaphore. It also needs to be 874 * transitioned away from for kernel modesetting. 875 */ 876 int suspended; 877 878 /** Bit 6 swizzling required for X tiling */ 879 uint32_t bit_6_swizzle_x; 880 /** Bit 6 swizzling required for Y tiling */ 881 uint32_t bit_6_swizzle_y; 882 883 /* storage for physical objects */ 884 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 885 886 /* accounting, useful for userland debugging */ 887 size_t object_memory; 888 u32 object_count; 889 }; 890 891 struct drm_i915_error_state_buf { 892 unsigned bytes; 893 unsigned size; 894 int err; 895 u8 *buf; 896 loff_t start; 897 loff_t pos; 898 }; 899 900 struct i915_gpu_error { 901 /* For hangcheck timer */ 902 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 903 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 904 struct timer_list hangcheck_timer; 905 906 /* For reset and error_state handling. */ 907 spinlock_t lock; 908 /* Protected by the above dev->gpu_error.lock. */ 909 struct drm_i915_error_state *first_error; 910 struct work_struct work; 911 912 unsigned long last_reset; 913 914 /** 915 * State variable and reset counter controlling the reset flow 916 * 917 * Upper bits are for the reset counter. This counter is used by the 918 * wait_seqno code to race-free noticed that a reset event happened and 919 * that it needs to restart the entire ioctl (since most likely the 920 * seqno it waited for won't ever signal anytime soon). 921 * 922 * This is important for lock-free wait paths, where no contended lock 923 * naturally enforces the correct ordering between the bail-out of the 924 * waiter and the gpu reset work code. 925 * 926 * Lowest bit controls the reset state machine: Set means a reset is in 927 * progress. This state will (presuming we don't have any bugs) decay 928 * into either unset (successful reset) or the special WEDGED value (hw 929 * terminally sour). All waiters on the reset_queue will be woken when 930 * that happens. 931 */ 932 atomic_t reset_counter; 933 934 /** 935 * Special values/flags for reset_counter 936 * 937 * Note that the code relies on 938 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG 939 * being true. 940 */ 941 #define I915_RESET_IN_PROGRESS_FLAG 1 942 #define I915_WEDGED 0xffffffff 943 944 /** 945 * Waitqueue to signal when the reset has completed. Used by clients 946 * that wait for dev_priv->mm.wedged to settle. 947 */ 948 wait_queue_head_t reset_queue; 949 950 /* For gpu hang simulation. */ 951 unsigned int stop_rings; 952 }; 953 954 enum modeset_restore { 955 MODESET_ON_LID_OPEN, 956 MODESET_DONE, 957 MODESET_SUSPENDED, 958 }; 959 960 struct intel_vbt_data { 961 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 962 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 963 964 /* Feature bits */ 965 unsigned int int_tv_support:1; 966 unsigned int lvds_dither:1; 967 unsigned int lvds_vbt:1; 968 unsigned int int_crt_support:1; 969 unsigned int lvds_use_ssc:1; 970 unsigned int display_clock_mode:1; 971 unsigned int fdi_rx_polarity_inverted:1; 972 int lvds_ssc_freq; 973 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 974 975 /* eDP */ 976 int edp_rate; 977 int edp_lanes; 978 int edp_preemphasis; 979 int edp_vswing; 980 bool edp_initialized; 981 bool edp_support; 982 int edp_bpp; 983 struct edp_power_seq edp_pps; 984 985 int crt_ddc_pin; 986 987 int child_dev_num; 988 struct child_device_config *child_dev; 989 }; 990 991 typedef struct drm_i915_private { 992 struct drm_device *dev; 993 struct kmem_cache *slab; 994 995 const struct intel_device_info *info; 996 997 int relative_constants_mode; 998 999 void __iomem *regs; 1000 1001 struct drm_i915_gt_funcs gt; 1002 /** gt_fifo_count and the subsequent register write are synchronized 1003 * with dev->struct_mutex. */ 1004 unsigned gt_fifo_count; 1005 /** forcewake_count is protected by gt_lock */ 1006 unsigned forcewake_count; 1007 /** gt_lock is also taken in irq contexts. */ 1008 spinlock_t gt_lock; 1009 1010 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 1011 1012 1013 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1014 * controller on different i2c buses. */ 1015 struct mutex gmbus_mutex; 1016 1017 /** 1018 * Base address of the gmbus and gpio block. 1019 */ 1020 uint32_t gpio_mmio_base; 1021 1022 wait_queue_head_t gmbus_wait_queue; 1023 1024 struct pci_dev *bridge_dev; 1025 struct intel_ring_buffer ring[I915_NUM_RINGS]; 1026 uint32_t last_seqno, next_seqno; 1027 1028 drm_dma_handle_t *status_page_dmah; 1029 struct resource mch_res; 1030 1031 atomic_t irq_received; 1032 1033 /* protects the irq masks */ 1034 spinlock_t irq_lock; 1035 1036 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1037 struct pm_qos_request pm_qos; 1038 1039 /* DPIO indirect register protection */ 1040 struct mutex dpio_lock; 1041 1042 /** Cached value of IMR to avoid reads in updating the bitfield */ 1043 u32 irq_mask; 1044 u32 gt_irq_mask; 1045 1046 struct work_struct hotplug_work; 1047 bool enable_hotplug_processing; 1048 struct { 1049 unsigned long hpd_last_jiffies; 1050 int hpd_cnt; 1051 enum { 1052 HPD_ENABLED = 0, 1053 HPD_DISABLED = 1, 1054 HPD_MARK_DISABLED = 2 1055 } hpd_mark; 1056 } hpd_stats[HPD_NUM_PINS]; 1057 u32 hpd_event_bits; 1058 struct timer_list hotplug_reenable_timer; 1059 1060 int num_plane; 1061 1062 unsigned long cfb_size; 1063 unsigned int cfb_fb; 1064 enum plane cfb_plane; 1065 int cfb_y; 1066 struct intel_fbc_work *fbc_work; 1067 1068 struct intel_opregion opregion; 1069 struct intel_vbt_data vbt; 1070 1071 /* overlay */ 1072 struct intel_overlay *overlay; 1073 unsigned int sprite_scaling_enabled; 1074 1075 /* backlight */ 1076 struct { 1077 int level; 1078 bool enabled; 1079 spinlock_t lock; /* bl registers and the above bl fields */ 1080 struct backlight_device *device; 1081 } backlight; 1082 1083 /* LVDS info */ 1084 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1085 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1086 bool no_aux_handshake; 1087 1088 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1089 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1090 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1091 1092 unsigned int fsb_freq, mem_freq, is_ddr3; 1093 1094 struct workqueue_struct *wq; 1095 1096 /* Display functions */ 1097 struct drm_i915_display_funcs display; 1098 1099 /* PCH chipset type */ 1100 enum intel_pch pch_type; 1101 unsigned short pch_id; 1102 1103 unsigned long quirks; 1104 1105 enum modeset_restore modeset_restore; 1106 struct mutex modeset_restore_lock; 1107 1108 struct i915_gtt gtt; 1109 1110 struct i915_gem_mm mm; 1111 1112 /* Kernel Modesetting */ 1113 1114 struct sdvo_device_mapping sdvo_mappings[2]; 1115 1116 struct drm_crtc *plane_to_crtc_mapping[3]; 1117 struct drm_crtc *pipe_to_crtc_mapping[3]; 1118 wait_queue_head_t pending_flip_queue; 1119 1120 int num_shared_dpll; 1121 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1122 struct intel_ddi_plls ddi_plls; 1123 1124 /* Reclocking support */ 1125 bool render_reclock_avail; 1126 bool lvds_downclock_avail; 1127 /* indicates the reduced downclock for LVDS*/ 1128 int lvds_downclock; 1129 u16 orig_clock; 1130 1131 bool mchbar_need_disable; 1132 1133 struct intel_l3_parity l3_parity; 1134 1135 /* gen6+ rps state */ 1136 struct intel_gen6_power_mgmt rps; 1137 1138 /* ilk-only ips/rps state. Everything in here is protected by the global 1139 * mchdev_lock in intel_pm.c */ 1140 struct intel_ilk_power_mgmt ips; 1141 1142 /* Haswell power well */ 1143 struct i915_power_well power_well; 1144 1145 enum no_fbc_reason no_fbc_reason; 1146 1147 struct drm_mm_node *compressed_fb; 1148 struct drm_mm_node *compressed_llb; 1149 1150 struct i915_gpu_error gpu_error; 1151 1152 struct drm_i915_gem_object *vlv_pctx; 1153 1154 /* list of fbdev register on this device */ 1155 struct intel_fbdev *fbdev; 1156 1157 /* 1158 * The console may be contended at resume, but we don't 1159 * want it to block on it. 1160 */ 1161 struct work_struct console_resume_work; 1162 1163 struct drm_property *broadcast_rgb_property; 1164 struct drm_property *force_audio_property; 1165 1166 bool hw_contexts_disabled; 1167 uint32_t hw_context_size; 1168 1169 u32 fdi_rx_config; 1170 1171 struct i915_suspend_saved_registers regfile; 1172 1173 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1174 * here! */ 1175 struct i915_dri1_state dri1; 1176 } drm_i915_private_t; 1177 1178 /* Iterate over initialised rings */ 1179 #define for_each_ring(ring__, dev_priv__, i__) \ 1180 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1181 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1182 1183 enum hdmi_force_audio { 1184 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1185 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1186 HDMI_AUDIO_AUTO, /* trust EDID */ 1187 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1188 }; 1189 1190 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) 1191 1192 struct drm_i915_gem_object_ops { 1193 /* Interface between the GEM object and its backing storage. 1194 * get_pages() is called once prior to the use of the associated set 1195 * of pages before to binding them into the GTT, and put_pages() is 1196 * called after we no longer need them. As we expect there to be 1197 * associated cost with migrating pages between the backing storage 1198 * and making them available for the GPU (e.g. clflush), we may hold 1199 * onto the pages after they are no longer referenced by the GPU 1200 * in case they may be used again shortly (for example migrating the 1201 * pages to a different memory domain within the GTT). put_pages() 1202 * will therefore most likely be called when the object itself is 1203 * being released or under memory pressure (where we attempt to 1204 * reap pages for the shrinker). 1205 */ 1206 int (*get_pages)(struct drm_i915_gem_object *); 1207 void (*put_pages)(struct drm_i915_gem_object *); 1208 }; 1209 1210 struct drm_i915_gem_object { 1211 struct drm_gem_object base; 1212 1213 const struct drm_i915_gem_object_ops *ops; 1214 1215 /** Current space allocated to this object in the GTT, if any. */ 1216 struct drm_mm_node *gtt_space; 1217 /** Stolen memory for this object, instead of being backed by shmem. */ 1218 struct drm_mm_node *stolen; 1219 struct list_head global_list; 1220 1221 /** This object's place on the active/inactive lists */ 1222 struct list_head ring_list; 1223 struct list_head mm_list; 1224 /** This object's place in the batchbuffer or on the eviction list */ 1225 struct list_head exec_list; 1226 1227 /** 1228 * This is set if the object is on the active lists (has pending 1229 * rendering and so a non-zero seqno), and is not set if it i s on 1230 * inactive (ready to be unbound) list. 1231 */ 1232 unsigned int active:1; 1233 1234 /** 1235 * This is set if the object has been written to since last bound 1236 * to the GTT 1237 */ 1238 unsigned int dirty:1; 1239 1240 /** 1241 * Fence register bits (if any) for this object. Will be set 1242 * as needed when mapped into the GTT. 1243 * Protected by dev->struct_mutex. 1244 */ 1245 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1246 1247 /** 1248 * Advice: are the backing pages purgeable? 1249 */ 1250 unsigned int madv:2; 1251 1252 /** 1253 * Current tiling mode for the object. 1254 */ 1255 unsigned int tiling_mode:2; 1256 /** 1257 * Whether the tiling parameters for the currently associated fence 1258 * register have changed. Note that for the purposes of tracking 1259 * tiling changes we also treat the unfenced register, the register 1260 * slot that the object occupies whilst it executes a fenced 1261 * command (such as BLT on gen2/3), as a "fence". 1262 */ 1263 unsigned int fence_dirty:1; 1264 1265 /** How many users have pinned this object in GTT space. The following 1266 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1267 * (via user_pin_count), execbuffer (objects are not allowed multiple 1268 * times for the same batchbuffer), and the framebuffer code. When 1269 * switching/pageflipping, the framebuffer code has at most two buffers 1270 * pinned per crtc. 1271 * 1272 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1273 * bits with absolutely no headroom. So use 4 bits. */ 1274 unsigned int pin_count:4; 1275 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1276 1277 /** 1278 * Is the object at the current location in the gtt mappable and 1279 * fenceable? Used to avoid costly recalculations. 1280 */ 1281 unsigned int map_and_fenceable:1; 1282 1283 /** 1284 * Whether the current gtt mapping needs to be mappable (and isn't just 1285 * mappable by accident). Track pin and fault separate for a more 1286 * accurate mappable working set. 1287 */ 1288 unsigned int fault_mappable:1; 1289 unsigned int pin_mappable:1; 1290 1291 /* 1292 * Is the GPU currently using a fence to access this buffer, 1293 */ 1294 unsigned int pending_fenced_gpu_access:1; 1295 unsigned int fenced_gpu_access:1; 1296 1297 unsigned int cache_level:2; 1298 1299 unsigned int has_aliasing_ppgtt_mapping:1; 1300 unsigned int has_global_gtt_mapping:1; 1301 unsigned int has_dma_mapping:1; 1302 1303 struct sg_table *pages; 1304 int pages_pin_count; 1305 1306 /* prime dma-buf support */ 1307 void *dma_buf_vmapping; 1308 int vmapping_count; 1309 1310 /** 1311 * Used for performing relocations during execbuffer insertion. 1312 */ 1313 struct hlist_node exec_node; 1314 unsigned long exec_handle; 1315 struct drm_i915_gem_exec_object2 *exec_entry; 1316 1317 /** 1318 * Current offset of the object in GTT space. 1319 * 1320 * This is the same as gtt_space->start 1321 */ 1322 uint32_t gtt_offset; 1323 1324 struct intel_ring_buffer *ring; 1325 1326 /** Breadcrumb of last rendering to the buffer. */ 1327 uint32_t last_read_seqno; 1328 uint32_t last_write_seqno; 1329 /** Breadcrumb of last fenced GPU access to the buffer. */ 1330 uint32_t last_fenced_seqno; 1331 1332 /** Current tiling stride for the object, if it's tiled. */ 1333 uint32_t stride; 1334 1335 /** Record of address bit 17 of each page at last unbind. */ 1336 unsigned long *bit_17; 1337 1338 /** User space pin count and filp owning the pin */ 1339 uint32_t user_pin_count; 1340 struct drm_file *pin_filp; 1341 1342 /** for phy allocated objects */ 1343 struct drm_i915_gem_phys_object *phys_obj; 1344 }; 1345 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1346 1347 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1348 1349 /** 1350 * Request queue structure. 1351 * 1352 * The request queue allows us to note sequence numbers that have been emitted 1353 * and may be associated with active buffers to be retired. 1354 * 1355 * By keeping this list, we can avoid having to do questionable 1356 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1357 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1358 */ 1359 struct drm_i915_gem_request { 1360 /** On Which ring this request was generated */ 1361 struct intel_ring_buffer *ring; 1362 1363 /** GEM sequence number associated with this request. */ 1364 uint32_t seqno; 1365 1366 /** Position in the ringbuffer of the start of the request */ 1367 u32 head; 1368 1369 /** Position in the ringbuffer of the end of the request */ 1370 u32 tail; 1371 1372 /** Context related to this request */ 1373 struct i915_hw_context *ctx; 1374 1375 /** Batch buffer related to this request if any */ 1376 struct drm_i915_gem_object *batch_obj; 1377 1378 /** Time at which this request was emitted, in jiffies. */ 1379 unsigned long emitted_jiffies; 1380 1381 /** global list entry for this request */ 1382 struct list_head list; 1383 1384 struct drm_i915_file_private *file_priv; 1385 /** file_priv list entry for this request */ 1386 struct list_head client_list; 1387 }; 1388 1389 struct drm_i915_file_private { 1390 struct { 1391 spinlock_t lock; 1392 struct list_head request_list; 1393 } mm; 1394 struct idr context_idr; 1395 1396 struct i915_ctx_hang_stats hang_stats; 1397 }; 1398 1399 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1400 1401 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1402 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1403 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1404 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1405 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1406 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1407 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1408 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1409 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1410 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1411 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1412 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1413 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1414 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1415 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1416 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1417 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1418 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1419 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1420 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1421 (dev)->pci_device == 0x0152 || \ 1422 (dev)->pci_device == 0x015a) 1423 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1424 (dev)->pci_device == 0x0106 || \ 1425 (dev)->pci_device == 0x010A) 1426 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1427 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1428 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1429 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1430 ((dev)->pci_device & 0xFF00) == 0x0A00) 1431 1432 /* 1433 * The genX designation typically refers to the render engine, so render 1434 * capability related checks should use IS_GEN, while display and other checks 1435 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1436 * chips, etc.). 1437 */ 1438 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1439 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1440 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1441 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1442 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1443 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1444 1445 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1446 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1447 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring) 1448 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1449 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1450 1451 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1452 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1453 1454 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1455 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1456 1457 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1458 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1459 1460 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1461 * rows, which changed the alignment requirements and fence programming. 1462 */ 1463 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1464 IS_I915GM(dev))) 1465 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1466 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1467 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1468 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1469 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1470 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1471 /* dsparb controlled by hw only */ 1472 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1473 1474 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1475 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1476 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1477 1478 #define HAS_IPS(dev) (IS_ULT(dev)) 1479 1480 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1481 1482 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 1483 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) 1484 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 1485 1486 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1487 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1488 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1489 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1490 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1491 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1492 1493 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1494 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1495 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1496 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1497 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 1498 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1499 1500 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1501 1502 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1503 1504 #define GT_FREQUENCY_MULTIPLIER 50 1505 1506 #include "i915_trace.h" 1507 1508 /** 1509 * RC6 is a special power stage which allows the GPU to enter an very 1510 * low-voltage mode when idle, using down to 0V while at this stage. This 1511 * stage is entered automatically when the GPU is idle when RC6 support is 1512 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1513 * 1514 * There are different RC6 modes available in Intel GPU, which differentiate 1515 * among each other with the latency required to enter and leave RC6 and 1516 * voltage consumed by the GPU in different states. 1517 * 1518 * The combination of the following flags define which states GPU is allowed 1519 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1520 * RC6pp is deepest RC6. Their support by hardware varies according to the 1521 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1522 * which brings the most power savings; deeper states save more power, but 1523 * require higher latency to switch to and wake up. 1524 */ 1525 #define INTEL_RC6_ENABLE (1<<0) 1526 #define INTEL_RC6p_ENABLE (1<<1) 1527 #define INTEL_RC6pp_ENABLE (1<<2) 1528 1529 extern struct drm_ioctl_desc i915_ioctls[]; 1530 extern int i915_max_ioctl; 1531 extern unsigned int i915_fbpercrtc __always_unused; 1532 extern int i915_panel_ignore_lid __read_mostly; 1533 extern unsigned int i915_powersave __read_mostly; 1534 extern int i915_semaphores __read_mostly; 1535 extern unsigned int i915_lvds_downclock __read_mostly; 1536 extern int i915_lvds_channel_mode __read_mostly; 1537 extern int i915_panel_use_ssc __read_mostly; 1538 extern int i915_vbt_sdvo_panel_type __read_mostly; 1539 extern int i915_enable_rc6 __read_mostly; 1540 extern int i915_enable_fbc __read_mostly; 1541 extern bool i915_enable_hangcheck __read_mostly; 1542 extern int i915_enable_ppgtt __read_mostly; 1543 extern unsigned int i915_preliminary_hw_support __read_mostly; 1544 extern int i915_disable_power_well __read_mostly; 1545 extern int i915_enable_ips __read_mostly; 1546 1547 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1548 extern int i915_resume(struct drm_device *dev); 1549 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1550 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1551 1552 /* i915_dma.c */ 1553 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1554 extern void i915_kernel_lost_context(struct drm_device * dev); 1555 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1556 extern int i915_driver_unload(struct drm_device *); 1557 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1558 extern void i915_driver_lastclose(struct drm_device * dev); 1559 extern void i915_driver_preclose(struct drm_device *dev, 1560 struct drm_file *file_priv); 1561 extern void i915_driver_postclose(struct drm_device *dev, 1562 struct drm_file *file_priv); 1563 extern int i915_driver_device_is_agp(struct drm_device * dev); 1564 #ifdef CONFIG_COMPAT 1565 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1566 unsigned long arg); 1567 #endif 1568 extern int i915_emit_box(struct drm_device *dev, 1569 struct drm_clip_rect *box, 1570 int DR1, int DR4); 1571 extern int intel_gpu_reset(struct drm_device *dev); 1572 extern int i915_reset(struct drm_device *dev); 1573 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1574 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1575 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1576 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1577 1578 extern void intel_console_resume(struct work_struct *work); 1579 1580 /* i915_irq.c */ 1581 void i915_hangcheck_elapsed(unsigned long data); 1582 void i915_handle_error(struct drm_device *dev, bool wedged); 1583 1584 extern void intel_irq_init(struct drm_device *dev); 1585 extern void intel_pm_init(struct drm_device *dev); 1586 extern void intel_hpd_init(struct drm_device *dev); 1587 extern void intel_gt_init(struct drm_device *dev); 1588 extern void intel_gt_sanitize(struct drm_device *dev); 1589 1590 void i915_error_state_free(struct kref *error_ref); 1591 1592 void 1593 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1594 1595 void 1596 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1597 1598 #ifdef CONFIG_DEBUG_FS 1599 extern void i915_destroy_error_state(struct drm_device *dev); 1600 #else 1601 #define i915_destroy_error_state(x) 1602 #endif 1603 1604 1605 /* i915_gem.c */ 1606 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1607 struct drm_file *file_priv); 1608 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1609 struct drm_file *file_priv); 1610 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1611 struct drm_file *file_priv); 1612 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1613 struct drm_file *file_priv); 1614 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1615 struct drm_file *file_priv); 1616 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1617 struct drm_file *file_priv); 1618 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1619 struct drm_file *file_priv); 1620 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1621 struct drm_file *file_priv); 1622 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1623 struct drm_file *file_priv); 1624 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1625 struct drm_file *file_priv); 1626 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1627 struct drm_file *file_priv); 1628 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1629 struct drm_file *file_priv); 1630 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1631 struct drm_file *file_priv); 1632 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1633 struct drm_file *file); 1634 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1635 struct drm_file *file); 1636 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1637 struct drm_file *file_priv); 1638 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1639 struct drm_file *file_priv); 1640 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1641 struct drm_file *file_priv); 1642 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1643 struct drm_file *file_priv); 1644 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1645 struct drm_file *file_priv); 1646 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1647 struct drm_file *file_priv); 1648 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1649 struct drm_file *file_priv); 1650 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1651 struct drm_file *file_priv); 1652 void i915_gem_load(struct drm_device *dev); 1653 void *i915_gem_object_alloc(struct drm_device *dev); 1654 void i915_gem_object_free(struct drm_i915_gem_object *obj); 1655 int i915_gem_init_object(struct drm_gem_object *obj); 1656 void i915_gem_object_init(struct drm_i915_gem_object *obj, 1657 const struct drm_i915_gem_object_ops *ops); 1658 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1659 size_t size); 1660 void i915_gem_free_object(struct drm_gem_object *obj); 1661 1662 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1663 uint32_t alignment, 1664 bool map_and_fenceable, 1665 bool nonblocking); 1666 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1667 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1668 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 1669 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1670 void i915_gem_lastclose(struct drm_device *dev); 1671 1672 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 1673 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 1674 { 1675 struct sg_page_iter sg_iter; 1676 1677 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 1678 return sg_page_iter_page(&sg_iter); 1679 1680 return NULL; 1681 } 1682 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1683 { 1684 BUG_ON(obj->pages == NULL); 1685 obj->pages_pin_count++; 1686 } 1687 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1688 { 1689 BUG_ON(obj->pages_pin_count == 0); 1690 obj->pages_pin_count--; 1691 } 1692 1693 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1694 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1695 struct intel_ring_buffer *to); 1696 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1697 struct intel_ring_buffer *ring); 1698 1699 int i915_gem_dumb_create(struct drm_file *file_priv, 1700 struct drm_device *dev, 1701 struct drm_mode_create_dumb *args); 1702 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1703 uint32_t handle, uint64_t *offset); 1704 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1705 uint32_t handle); 1706 /** 1707 * Returns true if seq1 is later than seq2. 1708 */ 1709 static inline bool 1710 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1711 { 1712 return (int32_t)(seq1 - seq2) >= 0; 1713 } 1714 1715 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1716 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 1717 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1718 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1719 1720 static inline bool 1721 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1722 { 1723 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1724 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1725 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1726 return true; 1727 } else 1728 return false; 1729 } 1730 1731 static inline void 1732 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1733 { 1734 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1735 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1736 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); 1737 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1738 } 1739 } 1740 1741 void i915_gem_retire_requests(struct drm_device *dev); 1742 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1743 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 1744 bool interruptible); 1745 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 1746 { 1747 return unlikely(atomic_read(&error->reset_counter) 1748 & I915_RESET_IN_PROGRESS_FLAG); 1749 } 1750 1751 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 1752 { 1753 return atomic_read(&error->reset_counter) == I915_WEDGED; 1754 } 1755 1756 void i915_gem_reset(struct drm_device *dev); 1757 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1758 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1759 uint32_t read_domains, 1760 uint32_t write_domain); 1761 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1762 int __must_check i915_gem_init(struct drm_device *dev); 1763 int __must_check i915_gem_init_hw(struct drm_device *dev); 1764 void i915_gem_l3_remap(struct drm_device *dev); 1765 void i915_gem_init_swizzling(struct drm_device *dev); 1766 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1767 int __must_check i915_gpu_idle(struct drm_device *dev); 1768 int __must_check i915_gem_idle(struct drm_device *dev); 1769 int __i915_add_request(struct intel_ring_buffer *ring, 1770 struct drm_file *file, 1771 struct drm_i915_gem_object *batch_obj, 1772 u32 *seqno); 1773 #define i915_add_request(ring, seqno) \ 1774 __i915_add_request(ring, NULL, NULL, seqno) 1775 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1776 uint32_t seqno); 1777 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1778 int __must_check 1779 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1780 bool write); 1781 int __must_check 1782 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1783 int __must_check 1784 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1785 u32 alignment, 1786 struct intel_ring_buffer *pipelined); 1787 int i915_gem_attach_phys_object(struct drm_device *dev, 1788 struct drm_i915_gem_object *obj, 1789 int id, 1790 int align); 1791 void i915_gem_detach_phys_object(struct drm_device *dev, 1792 struct drm_i915_gem_object *obj); 1793 void i915_gem_free_all_phys_object(struct drm_device *dev); 1794 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1795 1796 uint32_t 1797 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 1798 uint32_t 1799 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 1800 int tiling_mode, bool fenced); 1801 1802 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1803 enum i915_cache_level cache_level); 1804 1805 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1806 struct dma_buf *dma_buf); 1807 1808 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1809 struct drm_gem_object *gem_obj, int flags); 1810 1811 void i915_gem_restore_fences(struct drm_device *dev); 1812 1813 /* i915_gem_context.c */ 1814 void i915_gem_context_init(struct drm_device *dev); 1815 void i915_gem_context_fini(struct drm_device *dev); 1816 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1817 int i915_switch_context(struct intel_ring_buffer *ring, 1818 struct drm_file *file, int to_id); 1819 void i915_gem_context_free(struct kref *ctx_ref); 1820 static inline void i915_gem_context_reference(struct i915_hw_context *ctx) 1821 { 1822 kref_get(&ctx->ref); 1823 } 1824 1825 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) 1826 { 1827 kref_put(&ctx->ref, i915_gem_context_free); 1828 } 1829 1830 struct i915_ctx_hang_stats * __must_check 1831 i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring, 1832 struct drm_file *file, 1833 u32 id); 1834 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1835 struct drm_file *file); 1836 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1837 struct drm_file *file); 1838 1839 /* i915_gem_gtt.c */ 1840 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1841 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1842 struct drm_i915_gem_object *obj, 1843 enum i915_cache_level cache_level); 1844 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1845 struct drm_i915_gem_object *obj); 1846 1847 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1848 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1849 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1850 enum i915_cache_level cache_level); 1851 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1852 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1853 void i915_gem_init_global_gtt(struct drm_device *dev); 1854 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 1855 unsigned long mappable_end, unsigned long end); 1856 int i915_gem_gtt_init(struct drm_device *dev); 1857 static inline void i915_gem_chipset_flush(struct drm_device *dev) 1858 { 1859 if (INTEL_INFO(dev)->gen < 6) 1860 intel_gtt_chipset_flush(); 1861 } 1862 1863 1864 /* i915_gem_evict.c */ 1865 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1866 unsigned alignment, 1867 unsigned cache_level, 1868 bool mappable, 1869 bool nonblock); 1870 int i915_gem_evict_everything(struct drm_device *dev); 1871 1872 /* i915_gem_stolen.c */ 1873 int i915_gem_init_stolen(struct drm_device *dev); 1874 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); 1875 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 1876 void i915_gem_cleanup_stolen(struct drm_device *dev); 1877 struct drm_i915_gem_object * 1878 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 1879 struct drm_i915_gem_object * 1880 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 1881 u32 stolen_offset, 1882 u32 gtt_offset, 1883 u32 size); 1884 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 1885 1886 /* i915_gem_tiling.c */ 1887 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1888 { 1889 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 1890 1891 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1892 obj->tiling_mode != I915_TILING_NONE; 1893 } 1894 1895 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1896 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1897 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1898 1899 /* i915_gem_debug.c */ 1900 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1901 const char *where, uint32_t mark); 1902 #if WATCH_LISTS 1903 int i915_verify_lists(struct drm_device *dev); 1904 #else 1905 #define i915_verify_lists(dev) 0 1906 #endif 1907 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1908 int handle); 1909 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1910 const char *where, uint32_t mark); 1911 1912 /* i915_debugfs.c */ 1913 int i915_debugfs_init(struct drm_minor *minor); 1914 void i915_debugfs_cleanup(struct drm_minor *minor); 1915 __printf(2, 3) 1916 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 1917 1918 /* i915_suspend.c */ 1919 extern int i915_save_state(struct drm_device *dev); 1920 extern int i915_restore_state(struct drm_device *dev); 1921 1922 /* i915_ums.c */ 1923 void i915_save_display_reg(struct drm_device *dev); 1924 void i915_restore_display_reg(struct drm_device *dev); 1925 1926 /* i915_sysfs.c */ 1927 void i915_setup_sysfs(struct drm_device *dev_priv); 1928 void i915_teardown_sysfs(struct drm_device *dev_priv); 1929 1930 /* intel_i2c.c */ 1931 extern int intel_setup_gmbus(struct drm_device *dev); 1932 extern void intel_teardown_gmbus(struct drm_device *dev); 1933 static inline bool intel_gmbus_is_port_valid(unsigned port) 1934 { 1935 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1936 } 1937 1938 extern struct i2c_adapter *intel_gmbus_get_adapter( 1939 struct drm_i915_private *dev_priv, unsigned port); 1940 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1941 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1942 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1943 { 1944 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1945 } 1946 extern void intel_i2c_reset(struct drm_device *dev); 1947 1948 /* intel_opregion.c */ 1949 extern int intel_opregion_setup(struct drm_device *dev); 1950 #ifdef CONFIG_ACPI 1951 extern void intel_opregion_init(struct drm_device *dev); 1952 extern void intel_opregion_fini(struct drm_device *dev); 1953 extern void intel_opregion_asle_intr(struct drm_device *dev); 1954 #else 1955 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1956 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1957 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1958 #endif 1959 1960 /* intel_acpi.c */ 1961 #ifdef CONFIG_ACPI 1962 extern void intel_register_dsm_handler(void); 1963 extern void intel_unregister_dsm_handler(void); 1964 #else 1965 static inline void intel_register_dsm_handler(void) { return; } 1966 static inline void intel_unregister_dsm_handler(void) { return; } 1967 #endif /* CONFIG_ACPI */ 1968 1969 /* modesetting */ 1970 extern void intel_modeset_init_hw(struct drm_device *dev); 1971 extern void intel_modeset_suspend_hw(struct drm_device *dev); 1972 extern void intel_modeset_init(struct drm_device *dev); 1973 extern void intel_modeset_gem_init(struct drm_device *dev); 1974 extern void intel_modeset_cleanup(struct drm_device *dev); 1975 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1976 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 1977 bool force_restore); 1978 extern void i915_redisable_vga(struct drm_device *dev); 1979 extern bool intel_fbc_enabled(struct drm_device *dev); 1980 extern void intel_disable_fbc(struct drm_device *dev); 1981 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1982 extern void intel_init_pch_refclk(struct drm_device *dev); 1983 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1984 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 1985 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); 1986 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); 1987 extern void intel_detect_pch(struct drm_device *dev); 1988 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1989 extern int intel_enable_rc6(const struct drm_device *dev); 1990 1991 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1992 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1993 struct drm_file *file); 1994 1995 /* overlay */ 1996 #ifdef CONFIG_DEBUG_FS 1997 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1998 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 1999 struct intel_overlay_error_state *error); 2000 2001 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2002 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2003 struct drm_device *dev, 2004 struct intel_display_error_state *error); 2005 #endif 2006 2007 /* On SNB platform, before reading ring registers forcewake bit 2008 * must be set to prevent GT core from power down and stale values being 2009 * returned. 2010 */ 2011 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 2012 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 2013 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 2014 2015 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2016 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2017 2018 /* intel_sideband.c */ 2019 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2020 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2021 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2022 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); 2023 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); 2024 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2025 enum intel_sbi_destination destination); 2026 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2027 enum intel_sbi_destination destination); 2028 2029 int vlv_gpu_freq(int ddr_freq, int val); 2030 int vlv_freq_opcode(int ddr_freq, int val); 2031 2032 #define __i915_read(x, y) \ 2033 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 2034 2035 __i915_read(8, b) 2036 __i915_read(16, w) 2037 __i915_read(32, l) 2038 __i915_read(64, q) 2039 #undef __i915_read 2040 2041 #define __i915_write(x, y) \ 2042 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 2043 2044 __i915_write(8, b) 2045 __i915_write(16, w) 2046 __i915_write(32, l) 2047 __i915_write(64, q) 2048 #undef __i915_write 2049 2050 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 2051 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 2052 2053 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 2054 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 2055 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 2056 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 2057 2058 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 2059 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 2060 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 2061 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 2062 2063 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 2064 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 2065 2066 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2067 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2068 2069 /* "Broadcast RGB" property */ 2070 #define INTEL_BROADCAST_RGB_AUTO 0 2071 #define INTEL_BROADCAST_RGB_FULL 1 2072 #define INTEL_BROADCAST_RGB_LIMITED 2 2073 2074 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2075 { 2076 if (HAS_PCH_SPLIT(dev)) 2077 return CPU_VGACNTRL; 2078 else if (IS_VALLEYVIEW(dev)) 2079 return VLV_VGACNTRL; 2080 else 2081 return VGACNTRL; 2082 } 2083 2084 static inline void __user *to_user_ptr(u64 address) 2085 { 2086 return (void __user *)(uintptr_t)address; 2087 } 2088 2089 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2090 { 2091 unsigned long j = msecs_to_jiffies(m); 2092 2093 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2094 } 2095 2096 static inline unsigned long 2097 timespec_to_jiffies_timeout(const struct timespec *value) 2098 { 2099 unsigned long j = timespec_to_jiffies(value); 2100 2101 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2102 } 2103 2104 #endif 2105