1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pm_qos.h> 36 37 #include <drm/ttm/ttm_device.h> 38 39 #include "display/intel_display.h" 40 #include "display/intel_display_core.h" 41 42 #include "gem/i915_gem_context_types.h" 43 #include "gem/i915_gem_lmem.h" 44 #include "gem/i915_gem_shrinker.h" 45 #include "gem/i915_gem_stolen.h" 46 47 #include "gt/intel_engine.h" 48 #include "gt/intel_gt_types.h" 49 #include "gt/intel_region_lmem.h" 50 #include "gt/intel_workarounds.h" 51 #include "gt/uc/intel_uc.h" 52 53 #include "i915_drm_client.h" 54 #include "i915_gem.h" 55 #include "i915_gpu_error.h" 56 #include "i915_params.h" 57 #include "i915_perf_types.h" 58 #include "i915_scheduler.h" 59 #include "i915_utils.h" 60 #include "intel_device_info.h" 61 #include "intel_memory_region.h" 62 #include "intel_pch.h" 63 #include "intel_runtime_pm.h" 64 #include "intel_step.h" 65 #include "intel_uncore.h" 66 #include "intel_wopcm.h" 67 68 struct drm_i915_clock_gating_funcs; 69 struct drm_i915_gem_object; 70 struct drm_i915_private; 71 struct intel_connector; 72 struct intel_dp; 73 struct intel_encoder; 74 struct intel_limit; 75 struct intel_overlay_error_state; 76 struct vlv_s0ix_state; 77 78 #define I915_GEM_GPU_DOMAINS \ 79 (I915_GEM_DOMAIN_RENDER | \ 80 I915_GEM_DOMAIN_SAMPLER | \ 81 I915_GEM_DOMAIN_COMMAND | \ 82 I915_GEM_DOMAIN_INSTRUCTION | \ 83 I915_GEM_DOMAIN_VERTEX) 84 85 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 86 87 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 88 89 struct i915_suspend_saved_registers { 90 u32 saveDSPARB; 91 u32 saveSWF0[16]; 92 u32 saveSWF1[16]; 93 u32 saveSWF3[3]; 94 u16 saveGCDGMBUS; 95 }; 96 97 #define MAX_L3_SLICES 2 98 struct intel_l3_parity { 99 u32 *remap_info[MAX_L3_SLICES]; 100 struct work_struct error_work; 101 int which_slice; 102 }; 103 104 struct i915_gem_mm { 105 /* 106 * Shortcut for the stolen region. This points to either 107 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 108 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 109 * support stolen. 110 */ 111 struct intel_memory_region *stolen_region; 112 /** Memory allocator for GTT stolen memory */ 113 struct drm_mm stolen; 114 /** Protects the usage of the GTT stolen memory allocator. This is 115 * always the inner lock when overlapping with struct_mutex. */ 116 struct mutex stolen_lock; 117 118 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 119 spinlock_t obj_lock; 120 121 /** 122 * List of objects which are purgeable. 123 */ 124 struct list_head purge_list; 125 126 /** 127 * List of objects which have allocated pages and are shrinkable. 128 */ 129 struct list_head shrink_list; 130 131 /** 132 * List of objects which are pending destruction. 133 */ 134 struct llist_head free_list; 135 struct work_struct free_work; 136 /** 137 * Count of objects pending destructions. Used to skip needlessly 138 * waiting on an RCU barrier if no objects are waiting to be freed. 139 */ 140 atomic_t free_count; 141 142 /** 143 * tmpfs instance used for shmem backed objects 144 */ 145 struct vfsmount *gemfs; 146 147 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 148 149 struct notifier_block oom_notifier; 150 struct notifier_block vmap_notifier; 151 struct shrinker shrinker; 152 153 #ifdef CONFIG_MMU_NOTIFIER 154 /** 155 * notifier_lock for mmu notifiers, memory may not be allocated 156 * while holding this lock. 157 */ 158 rwlock_t notifier_lock; 159 #endif 160 161 /* shrinker accounting, also useful for userland debugging */ 162 u64 shrink_memory; 163 u32 shrink_count; 164 }; 165 166 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 167 168 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 169 u64 context); 170 171 static inline unsigned long 172 i915_fence_timeout(const struct drm_i915_private *i915) 173 { 174 return i915_fence_context_timeout(i915, U64_MAX); 175 } 176 177 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 178 179 struct i915_virtual_gpu { 180 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 181 bool active; 182 u32 caps; 183 u32 *initial_mmio; 184 u8 *initial_cfg_space; 185 struct list_head entry; 186 }; 187 188 struct i915_selftest_stash { 189 atomic_t counter; 190 struct ida mock_region_instances; 191 }; 192 193 struct drm_i915_private { 194 struct drm_device drm; 195 196 struct intel_display display; 197 198 /* FIXME: Device release actions should all be moved to drmm_ */ 199 bool do_release; 200 201 /* i915 device parameters */ 202 struct i915_params params; 203 204 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 205 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 206 struct intel_driver_caps caps; 207 208 /** 209 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 210 * end of stolen which we can optionally use to create GEM objects 211 * backed by stolen memory. Note that stolen_usable_size tells us 212 * exactly how much of this we are actually allowed to use, given that 213 * some portion of it is in fact reserved for use by hardware functions. 214 */ 215 struct resource dsm; 216 /** 217 * Reseved portion of Data Stolen Memory 218 */ 219 struct resource dsm_reserved; 220 221 /* 222 * Stolen memory is segmented in hardware with different portions 223 * offlimits to certain functions. 224 * 225 * The drm_mm is initialised to the total accessible range, as found 226 * from the PCI config. On Broadwell+, this is further restricted to 227 * avoid the first page! The upper end of stolen memory is reserved for 228 * hardware functions and similarly removed from the accessible range. 229 */ 230 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 231 232 struct intel_uncore uncore; 233 struct intel_uncore_mmio_debug mmio_debug; 234 235 struct i915_virtual_gpu vgpu; 236 237 struct intel_gvt *gvt; 238 239 struct intel_wopcm wopcm; 240 241 struct pci_dev *bridge_dev; 242 243 struct rb_root uabi_engines; 244 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 245 246 struct resource mch_res; 247 248 /* protects the irq masks */ 249 spinlock_t irq_lock; 250 251 bool display_irqs_enabled; 252 253 /* Sideband mailbox protection */ 254 struct mutex sb_lock; 255 struct pm_qos_request sb_qos; 256 257 /** Cached value of IMR to avoid reads in updating the bitfield */ 258 union { 259 u32 irq_mask; 260 u32 de_irq_mask[I915_MAX_PIPES]; 261 }; 262 u32 pipestat_irq_mask[I915_MAX_PIPES]; 263 264 bool preserve_bios_swizzle; 265 266 unsigned int fsb_freq, mem_freq, is_ddr3; 267 unsigned int skl_preferred_vco_freq; 268 269 unsigned int max_dotclk_freq; 270 unsigned int hpll_freq; 271 unsigned int czclk_freq; 272 273 /** 274 * wq - Driver workqueue for GEM. 275 * 276 * NOTE: Work items scheduled here are not allowed to grab any modeset 277 * locks, for otherwise the flushing done in the pageflip code will 278 * result in deadlocks. 279 */ 280 struct workqueue_struct *wq; 281 282 /* pm private clock gating functions */ 283 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 284 285 /* PCH chipset type */ 286 enum intel_pch pch_type; 287 unsigned short pch_id; 288 289 unsigned long gem_quirks; 290 291 struct drm_atomic_state *modeset_restore_state; 292 struct drm_modeset_acquire_ctx reset_ctx; 293 294 struct i915_gem_mm mm; 295 296 /* Kernel Modesetting */ 297 298 struct list_head global_obj_list; 299 300 bool mchbar_need_disable; 301 302 struct intel_l3_parity l3_parity; 303 304 /* 305 * HTI (aka HDPORT) state read during initial hw readout. Most 306 * platforms don't have HTI, so this will just stay 0. Those that do 307 * will use this later to figure out which PLLs and PHYs are unavailable 308 * for driver usage. 309 */ 310 u32 hti_state; 311 312 /* 313 * edram size in MB. 314 * Cannot be determined by PCIID. You must always read a register. 315 */ 316 u32 edram_size_mb; 317 318 struct i915_gpu_error gpu_error; 319 320 /* 321 * Shadows for CHV DPLL_MD regs to keep the state 322 * checker somewhat working in the presence hardware 323 * crappiness (can't read out DPLL_MD for pipes B & C). 324 */ 325 u32 chv_dpll_md[I915_MAX_PIPES]; 326 u32 bxt_phy_grc; 327 328 u32 suspend_count; 329 struct i915_suspend_saved_registers regfile; 330 struct vlv_s0ix_state *vlv_s0ix_state; 331 332 struct dram_info { 333 bool wm_lv_0_adjust_needed; 334 u8 num_channels; 335 bool symmetric_memory; 336 enum intel_dram_type { 337 INTEL_DRAM_UNKNOWN, 338 INTEL_DRAM_DDR3, 339 INTEL_DRAM_DDR4, 340 INTEL_DRAM_LPDDR3, 341 INTEL_DRAM_LPDDR4, 342 INTEL_DRAM_DDR5, 343 INTEL_DRAM_LPDDR5, 344 } type; 345 u8 num_qgv_points; 346 u8 num_psf_gv_points; 347 } dram_info; 348 349 struct intel_runtime_pm runtime_pm; 350 351 struct i915_perf perf; 352 353 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 354 struct intel_gt gt0; 355 356 /* 357 * i915->gt[0] == &i915->gt0 358 */ 359 #define I915_MAX_GT 4 360 struct intel_gt *gt[I915_MAX_GT]; 361 362 struct kobject *sysfs_gt; 363 364 struct { 365 struct i915_gem_contexts { 366 spinlock_t lock; /* locks list */ 367 struct list_head list; 368 } contexts; 369 370 /* 371 * We replace the local file with a global mappings as the 372 * backing storage for the mmap is on the device and not 373 * on the struct file, and we do not want to prolong the 374 * lifetime of the local fd. To minimise the number of 375 * anonymous inodes we create, we use a global singleton to 376 * share the global mapping. 377 */ 378 struct file *mmap_singleton; 379 } gem; 380 381 u8 pch_ssc_use; 382 383 /* For i915gm/i945gm vblank irq workaround */ 384 u8 vblank_enabled; 385 386 bool irq_enabled; 387 388 /* 389 * DG2: Mask of PHYs that were not calibrated by the firmware 390 * and should not be used. 391 */ 392 u8 snps_phy_failed_calibration; 393 394 struct i915_pmu pmu; 395 396 struct i915_drm_clients clients; 397 398 /* The TTM device structure. */ 399 struct ttm_device bdev; 400 401 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 402 403 /* 404 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 405 * will be rejected. Instead look for a better place. 406 */ 407 }; 408 409 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 410 { 411 return container_of(dev, struct drm_i915_private, drm); 412 } 413 414 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 415 { 416 return dev_get_drvdata(kdev); 417 } 418 419 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 420 { 421 return pci_get_drvdata(pdev); 422 } 423 424 static inline struct intel_gt *to_gt(struct drm_i915_private *i915) 425 { 426 return &i915->gt0; 427 } 428 429 /* Simple iterator over all initialised engines */ 430 #define for_each_engine(engine__, dev_priv__, id__) \ 431 for ((id__) = 0; \ 432 (id__) < I915_NUM_ENGINES; \ 433 (id__)++) \ 434 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 435 436 /* Iterator over subset of engines selected by mask */ 437 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 438 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 439 (tmp__) ? \ 440 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 441 0;) 442 443 #define rb_to_uabi_engine(rb) \ 444 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 445 446 #define for_each_uabi_engine(engine__, i915__) \ 447 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 448 (engine__); \ 449 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 450 451 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 452 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 453 (engine__) && (engine__)->uabi_class == (class__); \ 454 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 455 456 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 457 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 458 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 459 460 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 461 462 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 463 464 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 465 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 466 RUNTIME_INFO(i915)->graphics.ip.rel) 467 #define IS_GRAPHICS_VER(i915, from, until) \ 468 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 469 470 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 471 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 472 RUNTIME_INFO(i915)->media.ip.rel) 473 #define IS_MEDIA_VER(i915, from, until) \ 474 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 475 476 #define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver) 477 #define IS_DISPLAY_VER(i915, from, until) \ 478 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 479 480 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) 481 482 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 483 484 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 485 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 486 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 487 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 488 489 #define IS_DISPLAY_STEP(__i915, since, until) \ 490 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 491 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 492 493 #define IS_GRAPHICS_STEP(__i915, since, until) \ 494 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 495 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 496 497 #define IS_MEDIA_STEP(__i915, since, until) \ 498 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 499 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 500 501 #define IS_BASEDIE_STEP(__i915, since, until) \ 502 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 503 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 504 505 static __always_inline unsigned int 506 __platform_mask_index(const struct intel_runtime_info *info, 507 enum intel_platform p) 508 { 509 const unsigned int pbits = 510 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 511 512 /* Expand the platform_mask array if this fails. */ 513 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 514 pbits * ARRAY_SIZE(info->platform_mask)); 515 516 return p / pbits; 517 } 518 519 static __always_inline unsigned int 520 __platform_mask_bit(const struct intel_runtime_info *info, 521 enum intel_platform p) 522 { 523 const unsigned int pbits = 524 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 525 526 return p % pbits + INTEL_SUBPLATFORM_BITS; 527 } 528 529 static inline u32 530 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 531 { 532 const unsigned int pi = __platform_mask_index(info, p); 533 534 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 535 } 536 537 static __always_inline bool 538 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 539 { 540 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 541 const unsigned int pi = __platform_mask_index(info, p); 542 const unsigned int pb = __platform_mask_bit(info, p); 543 544 BUILD_BUG_ON(!__builtin_constant_p(p)); 545 546 return info->platform_mask[pi] & BIT(pb); 547 } 548 549 static __always_inline bool 550 IS_SUBPLATFORM(const struct drm_i915_private *i915, 551 enum intel_platform p, unsigned int s) 552 { 553 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 554 const unsigned int pi = __platform_mask_index(info, p); 555 const unsigned int pb = __platform_mask_bit(info, p); 556 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 557 const u32 mask = info->platform_mask[pi]; 558 559 BUILD_BUG_ON(!__builtin_constant_p(p)); 560 BUILD_BUG_ON(!__builtin_constant_p(s)); 561 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 562 563 /* Shift and test on the MSB position so sign flag can be used. */ 564 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 565 } 566 567 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 568 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 569 570 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 571 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 572 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 573 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 574 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 575 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 576 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 577 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 578 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 579 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 580 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 581 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 582 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 583 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 584 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 585 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 586 #define IS_IRONLAKE_M(dev_priv) \ 587 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 588 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) 589 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 590 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 591 INTEL_INFO(dev_priv)->gt == 1) 592 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 593 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 594 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 595 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 596 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 597 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 598 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 599 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 600 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 601 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 602 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 603 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 604 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 605 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 606 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 607 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 608 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) 609 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) 610 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) 611 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) 612 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) 613 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE) 614 615 #define IS_METEORLAKE_M(dev_priv) \ 616 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) 617 #define IS_METEORLAKE_P(dev_priv) \ 618 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) 619 #define IS_DG2_G10(dev_priv) \ 620 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) 621 #define IS_DG2_G11(dev_priv) \ 622 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) 623 #define IS_DG2_G12(dev_priv) \ 624 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) 625 #define IS_ADLS_RPLS(dev_priv) \ 626 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 627 #define IS_ADLP_N(dev_priv) \ 628 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 629 #define IS_ADLP_RPLP(dev_priv) \ 630 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 631 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 632 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 633 #define IS_BDW_ULT(dev_priv) \ 634 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 635 #define IS_BDW_ULX(dev_priv) \ 636 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 637 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 638 INTEL_INFO(dev_priv)->gt == 3) 639 #define IS_HSW_ULT(dev_priv) \ 640 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 641 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 642 INTEL_INFO(dev_priv)->gt == 3) 643 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 644 INTEL_INFO(dev_priv)->gt == 1) 645 /* ULX machines are also considered ULT. */ 646 #define IS_HSW_ULX(dev_priv) \ 647 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 648 #define IS_SKL_ULT(dev_priv) \ 649 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 650 #define IS_SKL_ULX(dev_priv) \ 651 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 652 #define IS_KBL_ULT(dev_priv) \ 653 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 654 #define IS_KBL_ULX(dev_priv) \ 655 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 656 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 657 INTEL_INFO(dev_priv)->gt == 2) 658 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 659 INTEL_INFO(dev_priv)->gt == 3) 660 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 661 INTEL_INFO(dev_priv)->gt == 4) 662 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 663 INTEL_INFO(dev_priv)->gt == 2) 664 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 665 INTEL_INFO(dev_priv)->gt == 3) 666 #define IS_CFL_ULT(dev_priv) \ 667 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 668 #define IS_CFL_ULX(dev_priv) \ 669 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 670 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 671 INTEL_INFO(dev_priv)->gt == 2) 672 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 673 INTEL_INFO(dev_priv)->gt == 3) 674 675 #define IS_CML_ULT(dev_priv) \ 676 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 677 #define IS_CML_ULX(dev_priv) \ 678 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 679 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 680 INTEL_INFO(dev_priv)->gt == 2) 681 682 #define IS_ICL_WITH_PORT_F(dev_priv) \ 683 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 684 685 #define IS_TGL_UY(dev_priv) \ 686 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 687 688 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) 689 690 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \ 691 (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until)) 692 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ 693 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) 694 695 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \ 696 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until)) 697 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ 698 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until)) 699 700 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ 701 (IS_TIGERLAKE(__i915) && \ 702 IS_DISPLAY_STEP(__i915, since, until)) 703 704 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ 705 (IS_TGL_UY(__i915) && \ 706 IS_GRAPHICS_STEP(__i915, since, until)) 707 708 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ 709 (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \ 710 IS_GRAPHICS_STEP(__i915, since, until)) 711 712 #define IS_RKL_DISPLAY_STEP(p, since, until) \ 713 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) 714 715 #define IS_DG1_GRAPHICS_STEP(p, since, until) \ 716 (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until)) 717 #define IS_DG1_DISPLAY_STEP(p, since, until) \ 718 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until)) 719 720 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ 721 (IS_ALDERLAKE_S(__i915) && \ 722 IS_DISPLAY_STEP(__i915, since, until)) 723 724 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \ 725 (IS_ALDERLAKE_S(__i915) && \ 726 IS_GRAPHICS_STEP(__i915, since, until)) 727 728 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ 729 (IS_ALDERLAKE_P(__i915) && \ 730 IS_DISPLAY_STEP(__i915, since, until)) 731 732 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ 733 (IS_ALDERLAKE_P(__i915) && \ 734 IS_GRAPHICS_STEP(__i915, since, until)) 735 736 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ 737 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) 738 739 /* 740 * DG2 hardware steppings are a bit unusual. The hardware design was forked to 741 * create three variants (G10, G11, and G12) which each have distinct 742 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT 743 * stepping back to "A0" for their first iterations, even though they're more 744 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of 745 * functionality and workarounds. However the display stepping does not reset 746 * in the same manner --- a specific stepping like "B0" has a consistent 747 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. 748 * 749 * TLDR: All GT workarounds and stepping-specific logic must be applied in 750 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds 751 * and stepping-specific logic will be applied with a general DG2-wide stepping 752 * number. 753 */ 754 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \ 755 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ 756 IS_GRAPHICS_STEP(__i915, since, until)) 757 758 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \ 759 (IS_DG2(__i915) && \ 760 IS_DISPLAY_STEP(__i915, since, until)) 761 762 #define IS_PVC_BD_STEP(__i915, since, until) \ 763 (IS_PONTEVECCHIO(__i915) && \ 764 IS_BASEDIE_STEP(__i915, since, until)) 765 766 #define IS_PVC_CT_STEP(__i915, since, until) \ 767 (IS_PONTEVECCHIO(__i915) && \ 768 IS_GRAPHICS_STEP(__i915, since, until)) 769 770 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 771 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) 772 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) 773 774 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 775 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 776 777 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ 778 unsigned int first__ = (first); \ 779 unsigned int count__ = (count); \ 780 ((gt)->info.engine_mask & \ 781 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 782 }) 783 #define RCS_MASK(gt) \ 784 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 785 #define BCS_MASK(gt) \ 786 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 787 #define VDBOX_MASK(gt) \ 788 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 789 #define VEBOX_MASK(gt) \ 790 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 791 #define CCS_MASK(gt) \ 792 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 793 794 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode) 795 796 /* 797 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 798 * All later gens can run the final buffer from the ppgtt 799 */ 800 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) 801 802 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 803 #define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) 804 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 805 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 806 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) 807 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 808 809 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 810 811 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 812 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 813 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 814 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 815 816 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 817 818 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type) 819 #define HAS_PPGTT(dev_priv) \ 820 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 821 #define HAS_FULL_PPGTT(dev_priv) \ 822 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 823 824 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 825 GEM_BUG_ON((sizes) == 0); \ 826 ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \ 827 }) 828 829 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 830 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 831 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 832 833 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 834 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 835 836 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 837 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9) 838 839 /* WaRsDisableCoarsePowerGating:skl,cnl */ 840 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 841 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) 842 843 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4) 844 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \ 845 IS_GEMINILAKE(dev_priv) || \ 846 IS_KABYLAKE(dev_priv)) 847 848 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 849 * rows, which changed the alignment requirements and fence programming. 850 */ 851 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ 852 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) 853 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 854 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 855 856 #define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2) 857 #define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0) 858 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7) 859 860 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 861 862 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 863 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 864 865 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 866 867 #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) 868 #define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash) 869 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 870 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) 871 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 872 #define HAS_PSR_HW_TRACKING(dev_priv) \ 873 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 874 #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) 875 #define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 876 877 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 878 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 879 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 880 881 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 882 883 #define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc) 884 885 #define HAS_HECI_PXP(dev_priv) \ 886 (INTEL_INFO(dev_priv)->has_heci_pxp) 887 888 #define HAS_HECI_GSCFI(dev_priv) \ 889 (INTEL_INFO(dev_priv)->has_heci_gscfi) 890 891 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv)) 892 893 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 894 895 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 896 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 897 898 /* 899 * Set this flag, when platform requires 64K GTT page sizes or larger for 900 * device local memory access. 901 */ 902 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages) 903 904 /* 905 * Set this flag when platform doesn't allow both 64k pages and 4k pages in 906 * the same PT. this flag means we need to support compact PT layout for the 907 * ppGTT when using the 64K GTT pages. 908 */ 909 #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt) 910 911 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 912 913 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i)) 914 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 915 916 /* 917 * Platform has the dedicated compression control state for each lmem surfaces 918 * stored in lmem to support the 3D and media compression formats. 919 */ 920 #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs) 921 922 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 923 924 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu) 925 926 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 927 928 #define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \ 929 INTEL_INFO(dev_priv)->has_pxp) && \ 930 VDBOX_MASK(to_gt(dev_priv))) 931 932 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 933 934 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 935 936 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10)) 937 938 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 939 940 /* DPF == dynamic parity feature */ 941 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 942 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 943 2 : HAS_L3_DPF(dev_priv)) 944 945 #define GT_FREQUENCY_MULTIPLIER 50 946 #define GEN9_FREQ_SCALER 3 947 948 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask)) 949 950 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0) 951 952 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 953 954 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 955 956 /* Only valid when HAS_DISPLAY() is true */ 957 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 958 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \ 959 !(dev_priv)->params.disable_display && \ 960 !intel_opregion_headless_sku(dev_priv)) 961 962 #define HAS_GUC_DEPRIVILEGE(dev_priv) \ 963 (INTEL_INFO(dev_priv)->has_guc_deprivilege) 964 965 #define HAS_PERCTX_PREEMPT_CTRL(i915) \ 966 ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) 967 968 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ 969 IS_ALDERLAKE_S(dev_priv)) 970 971 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 972 973 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 974 975 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 976 977 /* intel_device_info.c */ 978 static inline struct intel_device_info * 979 mkwrite_device_info(struct drm_i915_private *dev_priv) 980 { 981 return (struct intel_device_info *)INTEL_INFO(dev_priv); 982 } 983 984 static inline enum i915_map_type 985 i915_coherent_map_type(struct drm_i915_private *i915, 986 struct drm_i915_gem_object *obj, bool always_coherent) 987 { 988 if (i915_gem_object_is_lmem(obj)) 989 return I915_MAP_WC; 990 if (HAS_LLC(i915) || always_coherent) 991 return I915_MAP_WB; 992 else 993 return I915_MAP_WC; 994 } 995 996 #endif 997