1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include <linux/io-mapping.h> 36 37 /* General customization: 38 */ 39 40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 41 42 #define DRIVER_NAME "i915" 43 #define DRIVER_DESC "Intel Graphics" 44 #define DRIVER_DATE "20080730" 45 46 enum pipe { 47 PIPE_A = 0, 48 PIPE_B, 49 }; 50 51 #define I915_NUM_PIPE 2 52 53 /* Interface history: 54 * 55 * 1.1: Original. 56 * 1.2: Add Power Management 57 * 1.3: Add vblank support 58 * 1.4: Fix cmdbuffer path, add heap destroy 59 * 1.5: Add vblank pipe configuration 60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 61 * - Support vertical blank on secondary display pipe 62 */ 63 #define DRIVER_MAJOR 1 64 #define DRIVER_MINOR 6 65 #define DRIVER_PATCHLEVEL 0 66 67 #define WATCH_COHERENCY 0 68 #define WATCH_BUF 0 69 #define WATCH_EXEC 0 70 #define WATCH_LRU 0 71 #define WATCH_RELOC 0 72 #define WATCH_INACTIVE 0 73 #define WATCH_PWRITE 0 74 75 #define I915_GEM_PHYS_CURSOR_0 1 76 #define I915_GEM_PHYS_CURSOR_1 2 77 #define I915_GEM_PHYS_OVERLAY_REGS 3 78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 79 80 struct drm_i915_gem_phys_object { 81 int id; 82 struct page **page_list; 83 drm_dma_handle_t *handle; 84 struct drm_gem_object *cur_obj; 85 }; 86 87 typedef struct _drm_i915_ring_buffer { 88 int tail_mask; 89 unsigned long Size; 90 u8 *virtual_start; 91 int head; 92 int tail; 93 int space; 94 drm_local_map_t map; 95 struct drm_gem_object *ring_obj; 96 } drm_i915_ring_buffer_t; 97 98 struct mem_block { 99 struct mem_block *next; 100 struct mem_block *prev; 101 int start; 102 int size; 103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 104 }; 105 106 struct opregion_header; 107 struct opregion_acpi; 108 struct opregion_swsci; 109 struct opregion_asle; 110 111 struct intel_opregion { 112 struct opregion_header *header; 113 struct opregion_acpi *acpi; 114 struct opregion_swsci *swsci; 115 struct opregion_asle *asle; 116 int enabled; 117 }; 118 119 struct drm_i915_master_private { 120 drm_local_map_t *sarea; 121 struct _drm_i915_sarea *sarea_priv; 122 }; 123 #define I915_FENCE_REG_NONE -1 124 125 struct drm_i915_fence_reg { 126 struct drm_gem_object *obj; 127 }; 128 129 typedef struct drm_i915_private { 130 struct drm_device *dev; 131 132 int has_gem; 133 134 void __iomem *regs; 135 136 drm_i915_ring_buffer_t ring; 137 138 drm_dma_handle_t *status_page_dmah; 139 void *hw_status_page; 140 dma_addr_t dma_status_page; 141 uint32_t counter; 142 unsigned int status_gfx_addr; 143 drm_local_map_t hws_map; 144 struct drm_gem_object *hws_obj; 145 146 unsigned int cpp; 147 int back_offset; 148 int front_offset; 149 int current_page; 150 int page_flipping; 151 152 wait_queue_head_t irq_queue; 153 atomic_t irq_received; 154 /** Protects user_irq_refcount and irq_mask_reg */ 155 spinlock_t user_irq_lock; 156 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 157 int user_irq_refcount; 158 /** Cached value of IMR to avoid reads in updating the bitfield */ 159 u32 irq_mask_reg; 160 u32 pipestat[2]; 161 162 u32 hotplug_supported_mask; 163 struct work_struct hotplug_work; 164 165 int tex_lru_log_granularity; 166 int allow_batchbuffer; 167 struct mem_block *agp_heap; 168 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 169 int vblank_pipe; 170 171 bool cursor_needs_physical; 172 173 struct drm_mm vram; 174 175 int irq_enabled; 176 177 struct intel_opregion opregion; 178 179 /* LVDS info */ 180 int backlight_duty_cycle; /* restore backlight to this value */ 181 bool panel_wants_dither; 182 struct drm_display_mode *panel_fixed_mode; 183 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 184 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 185 186 /* Feature bits from the VBIOS */ 187 unsigned int int_tv_support:1; 188 unsigned int lvds_dither:1; 189 unsigned int lvds_vbt:1; 190 unsigned int int_crt_support:1; 191 unsigned int lvds_use_ssc:1; 192 int lvds_ssc_freq; 193 194 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 195 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 196 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 197 198 /* Register state */ 199 u8 saveLBB; 200 u32 saveDSPACNTR; 201 u32 saveDSPBCNTR; 202 u32 saveDSPARB; 203 u32 saveRENDERSTANDBY; 204 u32 saveHWS; 205 u32 savePIPEACONF; 206 u32 savePIPEBCONF; 207 u32 savePIPEASRC; 208 u32 savePIPEBSRC; 209 u32 saveFPA0; 210 u32 saveFPA1; 211 u32 saveDPLL_A; 212 u32 saveDPLL_A_MD; 213 u32 saveHTOTAL_A; 214 u32 saveHBLANK_A; 215 u32 saveHSYNC_A; 216 u32 saveVTOTAL_A; 217 u32 saveVBLANK_A; 218 u32 saveVSYNC_A; 219 u32 saveBCLRPAT_A; 220 u32 savePIPEASTAT; 221 u32 saveDSPASTRIDE; 222 u32 saveDSPASIZE; 223 u32 saveDSPAPOS; 224 u32 saveDSPAADDR; 225 u32 saveDSPASURF; 226 u32 saveDSPATILEOFF; 227 u32 savePFIT_PGM_RATIOS; 228 u32 saveBLC_PWM_CTL; 229 u32 saveBLC_PWM_CTL2; 230 u32 saveFPB0; 231 u32 saveFPB1; 232 u32 saveDPLL_B; 233 u32 saveDPLL_B_MD; 234 u32 saveHTOTAL_B; 235 u32 saveHBLANK_B; 236 u32 saveHSYNC_B; 237 u32 saveVTOTAL_B; 238 u32 saveVBLANK_B; 239 u32 saveVSYNC_B; 240 u32 saveBCLRPAT_B; 241 u32 savePIPEBSTAT; 242 u32 saveDSPBSTRIDE; 243 u32 saveDSPBSIZE; 244 u32 saveDSPBPOS; 245 u32 saveDSPBADDR; 246 u32 saveDSPBSURF; 247 u32 saveDSPBTILEOFF; 248 u32 saveVGA0; 249 u32 saveVGA1; 250 u32 saveVGA_PD; 251 u32 saveVGACNTRL; 252 u32 saveADPA; 253 u32 saveLVDS; 254 u32 savePP_ON_DELAYS; 255 u32 savePP_OFF_DELAYS; 256 u32 saveDVOA; 257 u32 saveDVOB; 258 u32 saveDVOC; 259 u32 savePP_ON; 260 u32 savePP_OFF; 261 u32 savePP_CONTROL; 262 u32 savePP_DIVISOR; 263 u32 savePFIT_CONTROL; 264 u32 save_palette_a[256]; 265 u32 save_palette_b[256]; 266 u32 saveFBC_CFB_BASE; 267 u32 saveFBC_LL_BASE; 268 u32 saveFBC_CONTROL; 269 u32 saveFBC_CONTROL2; 270 u32 saveIER; 271 u32 saveIIR; 272 u32 saveIMR; 273 u32 saveCACHE_MODE_0; 274 u32 saveD_STATE; 275 u32 saveCG_2D_DIS; 276 u32 saveMI_ARB_STATE; 277 u32 saveSWF0[16]; 278 u32 saveSWF1[16]; 279 u32 saveSWF2[3]; 280 u8 saveMSR; 281 u8 saveSR[8]; 282 u8 saveGR[25]; 283 u8 saveAR_INDEX; 284 u8 saveAR[21]; 285 u8 saveDACMASK; 286 u8 saveCR[37]; 287 uint64_t saveFENCE[16]; 288 289 struct { 290 struct drm_mm gtt_space; 291 292 struct io_mapping *gtt_mapping; 293 int gtt_mtrr; 294 295 /** 296 * List of objects currently involved in rendering from the 297 * ringbuffer. 298 * 299 * Includes buffers having the contents of their GPU caches 300 * flushed, not necessarily primitives. last_rendering_seqno 301 * represents when the rendering involved will be completed. 302 * 303 * A reference is held on the buffer while on this list. 304 */ 305 spinlock_t active_list_lock; 306 struct list_head active_list; 307 308 /** 309 * List of objects which are not in the ringbuffer but which 310 * still have a write_domain which needs to be flushed before 311 * unbinding. 312 * 313 * last_rendering_seqno is 0 while an object is in this list. 314 * 315 * A reference is held on the buffer while on this list. 316 */ 317 struct list_head flushing_list; 318 319 /** 320 * LRU list of objects which are not in the ringbuffer and 321 * are ready to unbind, but are still in the GTT. 322 * 323 * last_rendering_seqno is 0 while an object is in this list. 324 * 325 * A reference is not held on the buffer while on this list, 326 * as merely being GTT-bound shouldn't prevent its being 327 * freed, and we'll pull it off the list in the free path. 328 */ 329 struct list_head inactive_list; 330 331 /** 332 * List of breadcrumbs associated with GPU requests currently 333 * outstanding. 334 */ 335 struct list_head request_list; 336 337 /** 338 * We leave the user IRQ off as much as possible, 339 * but this means that requests will finish and never 340 * be retired once the system goes idle. Set a timer to 341 * fire periodically while the ring is running. When it 342 * fires, go retire requests. 343 */ 344 struct delayed_work retire_work; 345 346 uint32_t next_gem_seqno; 347 348 /** 349 * Waiting sequence number, if any 350 */ 351 uint32_t waiting_gem_seqno; 352 353 /** 354 * Last seq seen at irq time 355 */ 356 uint32_t irq_gem_seqno; 357 358 /** 359 * Flag if the X Server, and thus DRM, is not currently in 360 * control of the device. 361 * 362 * This is set between LeaveVT and EnterVT. It needs to be 363 * replaced with a semaphore. It also needs to be 364 * transitioned away from for kernel modesetting. 365 */ 366 int suspended; 367 368 /** 369 * Flag if the hardware appears to be wedged. 370 * 371 * This is set when attempts to idle the device timeout. 372 * It prevents command submission from occuring and makes 373 * every pending request fail 374 */ 375 int wedged; 376 377 /** Bit 6 swizzling required for X tiling */ 378 uint32_t bit_6_swizzle_x; 379 /** Bit 6 swizzling required for Y tiling */ 380 uint32_t bit_6_swizzle_y; 381 382 /* storage for physical objects */ 383 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 384 } mm; 385 } drm_i915_private_t; 386 387 /** driver private structure attached to each drm_gem_object */ 388 struct drm_i915_gem_object { 389 struct drm_gem_object *obj; 390 391 /** Current space allocated to this object in the GTT, if any. */ 392 struct drm_mm_node *gtt_space; 393 394 /** This object's place on the active/flushing/inactive lists */ 395 struct list_head list; 396 397 /** 398 * This is set if the object is on the active or flushing lists 399 * (has pending rendering), and is not set if it's on inactive (ready 400 * to be unbound). 401 */ 402 int active; 403 404 /** 405 * This is set if the object has been written to since last bound 406 * to the GTT 407 */ 408 int dirty; 409 410 /** AGP memory structure for our GTT binding. */ 411 DRM_AGP_MEM *agp_mem; 412 413 struct page **pages; 414 int pages_refcount; 415 416 /** 417 * Current offset of the object in GTT space. 418 * 419 * This is the same as gtt_space->start 420 */ 421 uint32_t gtt_offset; 422 /** 423 * Required alignment for the object 424 */ 425 uint32_t gtt_alignment; 426 /** 427 * Fake offset for use by mmap(2) 428 */ 429 uint64_t mmap_offset; 430 431 /** 432 * Fence register bits (if any) for this object. Will be set 433 * as needed when mapped into the GTT. 434 * Protected by dev->struct_mutex. 435 */ 436 int fence_reg; 437 438 /** Boolean whether this object has a valid gtt offset. */ 439 int gtt_bound; 440 441 /** How many users have pinned this object in GTT space */ 442 int pin_count; 443 444 /** Breadcrumb of last rendering to the buffer. */ 445 uint32_t last_rendering_seqno; 446 447 /** Current tiling mode for the object. */ 448 uint32_t tiling_mode; 449 uint32_t stride; 450 451 /** Record of address bit 17 of each page at last unbind. */ 452 long *bit_17; 453 454 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 455 uint32_t agp_type; 456 457 /** 458 * If present, while GEM_DOMAIN_CPU is in the read domain this array 459 * flags which individual pages are valid. 460 */ 461 uint8_t *page_cpu_valid; 462 463 /** User space pin count and filp owning the pin */ 464 uint32_t user_pin_count; 465 struct drm_file *pin_filp; 466 467 /** for phy allocated objects */ 468 struct drm_i915_gem_phys_object *phys_obj; 469 470 /** 471 * Used for checking the object doesn't appear more than once 472 * in an execbuffer object list. 473 */ 474 int in_execbuffer; 475 }; 476 477 /** 478 * Request queue structure. 479 * 480 * The request queue allows us to note sequence numbers that have been emitted 481 * and may be associated with active buffers to be retired. 482 * 483 * By keeping this list, we can avoid having to do questionable 484 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 485 * an emission time with seqnos for tracking how far ahead of the GPU we are. 486 */ 487 struct drm_i915_gem_request { 488 /** GEM sequence number associated with this request. */ 489 uint32_t seqno; 490 491 /** Time at which this request was emitted, in jiffies. */ 492 unsigned long emitted_jiffies; 493 494 struct list_head list; 495 }; 496 497 struct drm_i915_file_private { 498 struct { 499 uint32_t last_gem_seqno; 500 uint32_t last_gem_throttle_seqno; 501 } mm; 502 }; 503 504 enum intel_chip_family { 505 CHIP_I8XX = 0x01, 506 CHIP_I9XX = 0x02, 507 CHIP_I915 = 0x04, 508 CHIP_I965 = 0x08, 509 }; 510 511 extern struct drm_ioctl_desc i915_ioctls[]; 512 extern int i915_max_ioctl; 513 extern unsigned int i915_fbpercrtc; 514 515 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 516 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 517 518 /* i915_dma.c */ 519 extern void i915_kernel_lost_context(struct drm_device * dev); 520 extern int i915_driver_load(struct drm_device *, unsigned long flags); 521 extern int i915_driver_unload(struct drm_device *); 522 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 523 extern void i915_driver_lastclose(struct drm_device * dev); 524 extern void i915_driver_preclose(struct drm_device *dev, 525 struct drm_file *file_priv); 526 extern void i915_driver_postclose(struct drm_device *dev, 527 struct drm_file *file_priv); 528 extern int i915_driver_device_is_agp(struct drm_device * dev); 529 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 530 unsigned long arg); 531 extern int i915_emit_box(struct drm_device *dev, 532 struct drm_clip_rect *boxes, 533 int i, int DR1, int DR4); 534 535 /* i915_irq.c */ 536 extern int i915_irq_emit(struct drm_device *dev, void *data, 537 struct drm_file *file_priv); 538 extern int i915_irq_wait(struct drm_device *dev, void *data, 539 struct drm_file *file_priv); 540 void i915_user_irq_get(struct drm_device *dev); 541 void i915_user_irq_put(struct drm_device *dev); 542 extern void i915_enable_interrupt (struct drm_device *dev); 543 544 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 545 extern void i915_driver_irq_preinstall(struct drm_device * dev); 546 extern int i915_driver_irq_postinstall(struct drm_device *dev); 547 extern void i915_driver_irq_uninstall(struct drm_device * dev); 548 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 549 struct drm_file *file_priv); 550 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 551 struct drm_file *file_priv); 552 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 553 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 554 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 555 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 556 extern int i915_vblank_swap(struct drm_device *dev, void *data, 557 struct drm_file *file_priv); 558 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 559 560 void 561 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 562 563 void 564 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 565 566 567 /* i915_mem.c */ 568 extern int i915_mem_alloc(struct drm_device *dev, void *data, 569 struct drm_file *file_priv); 570 extern int i915_mem_free(struct drm_device *dev, void *data, 571 struct drm_file *file_priv); 572 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 573 struct drm_file *file_priv); 574 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 575 struct drm_file *file_priv); 576 extern void i915_mem_takedown(struct mem_block **heap); 577 extern void i915_mem_release(struct drm_device * dev, 578 struct drm_file *file_priv, struct mem_block *heap); 579 /* i915_gem.c */ 580 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 581 struct drm_file *file_priv); 582 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *file_priv); 584 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 585 struct drm_file *file_priv); 586 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 587 struct drm_file *file_priv); 588 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 589 struct drm_file *file_priv); 590 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 591 struct drm_file *file_priv); 592 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 593 struct drm_file *file_priv); 594 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 595 struct drm_file *file_priv); 596 int i915_gem_execbuffer(struct drm_device *dev, void *data, 597 struct drm_file *file_priv); 598 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 599 struct drm_file *file_priv); 600 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 601 struct drm_file *file_priv); 602 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 603 struct drm_file *file_priv); 604 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 605 struct drm_file *file_priv); 606 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 607 struct drm_file *file_priv); 608 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 609 struct drm_file *file_priv); 610 int i915_gem_set_tiling(struct drm_device *dev, void *data, 611 struct drm_file *file_priv); 612 int i915_gem_get_tiling(struct drm_device *dev, void *data, 613 struct drm_file *file_priv); 614 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 615 struct drm_file *file_priv); 616 void i915_gem_load(struct drm_device *dev); 617 int i915_gem_init_object(struct drm_gem_object *obj); 618 void i915_gem_free_object(struct drm_gem_object *obj); 619 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 620 void i915_gem_object_unpin(struct drm_gem_object *obj); 621 int i915_gem_object_unbind(struct drm_gem_object *obj); 622 void i915_gem_lastclose(struct drm_device *dev); 623 uint32_t i915_get_gem_seqno(struct drm_device *dev); 624 void i915_gem_retire_requests(struct drm_device *dev); 625 void i915_gem_retire_work_handler(struct work_struct *work); 626 void i915_gem_clflush_object(struct drm_gem_object *obj); 627 int i915_gem_object_set_domain(struct drm_gem_object *obj, 628 uint32_t read_domains, 629 uint32_t write_domain); 630 int i915_gem_init_ringbuffer(struct drm_device *dev); 631 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 632 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 633 unsigned long end); 634 int i915_gem_idle(struct drm_device *dev); 635 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 636 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 637 int write); 638 int i915_gem_attach_phys_object(struct drm_device *dev, 639 struct drm_gem_object *obj, int id); 640 void i915_gem_detach_phys_object(struct drm_device *dev, 641 struct drm_gem_object *obj); 642 void i915_gem_free_all_phys_object(struct drm_device *dev); 643 int i915_gem_object_get_pages(struct drm_gem_object *obj); 644 void i915_gem_object_put_pages(struct drm_gem_object *obj); 645 646 /* i915_gem_tiling.c */ 647 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 648 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 649 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 650 651 /* i915_gem_debug.c */ 652 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 653 const char *where, uint32_t mark); 654 #if WATCH_INACTIVE 655 void i915_verify_inactive(struct drm_device *dev, char *file, int line); 656 #else 657 #define i915_verify_inactive(dev, file, line) 658 #endif 659 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 660 void i915_gem_dump_object(struct drm_gem_object *obj, int len, 661 const char *where, uint32_t mark); 662 void i915_dump_lru(struct drm_device *dev, const char *where); 663 664 /* i915_debugfs.c */ 665 int i915_gem_debugfs_init(struct drm_minor *minor); 666 void i915_gem_debugfs_cleanup(struct drm_minor *minor); 667 668 /* i915_suspend.c */ 669 extern int i915_save_state(struct drm_device *dev); 670 extern int i915_restore_state(struct drm_device *dev); 671 672 /* i915_suspend.c */ 673 extern int i915_save_state(struct drm_device *dev); 674 extern int i915_restore_state(struct drm_device *dev); 675 676 #ifdef CONFIG_ACPI 677 /* i915_opregion.c */ 678 extern int intel_opregion_init(struct drm_device *dev, int resume); 679 extern void intel_opregion_free(struct drm_device *dev, int suspend); 680 extern void opregion_asle_intr(struct drm_device *dev); 681 extern void opregion_enable_asle(struct drm_device *dev); 682 #else 683 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } 684 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } 685 static inline void opregion_asle_intr(struct drm_device *dev) { return; } 686 static inline void opregion_enable_asle(struct drm_device *dev) { return; } 687 #endif 688 689 /* modesetting */ 690 extern void intel_modeset_init(struct drm_device *dev); 691 extern void intel_modeset_cleanup(struct drm_device *dev); 692 693 /** 694 * Lock test for when it's just for synchronization of ring access. 695 * 696 * In that case, we don't need to do it when GEM is initialized as nobody else 697 * has access to the ring. 698 */ 699 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 700 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 701 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 702 } while (0) 703 704 #define I915_READ(reg) readl(dev_priv->regs + (reg)) 705 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) 706 #define I915_READ16(reg) readw(dev_priv->regs + (reg)) 707 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) 708 #define I915_READ8(reg) readb(dev_priv->regs + (reg)) 709 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) 710 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) 711 #define I915_READ64(reg) readq(dev_priv->regs + (reg)) 712 #define POSTING_READ(reg) (void)I915_READ(reg) 713 714 #define I915_VERBOSE 0 715 716 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 717 volatile char *virt; 718 719 #define BEGIN_LP_RING(n) do { \ 720 if (I915_VERBOSE) \ 721 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 722 if (dev_priv->ring.space < (n)*4) \ 723 i915_wait_ring(dev, (n)*4, __func__); \ 724 outcount = 0; \ 725 outring = dev_priv->ring.tail; \ 726 ringmask = dev_priv->ring.tail_mask; \ 727 virt = dev_priv->ring.virtual_start; \ 728 } while (0) 729 730 #define OUT_RING(n) do { \ 731 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 732 *(volatile unsigned int *)(virt + outring) = (n); \ 733 outcount++; \ 734 outring += 4; \ 735 outring &= ringmask; \ 736 } while (0) 737 738 #define ADVANCE_LP_RING() do { \ 739 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 740 dev_priv->ring.tail = outring; \ 741 dev_priv->ring.space -= outcount * 4; \ 742 I915_WRITE(PRB0_TAIL, outring); \ 743 } while(0) 744 745 /** 746 * Reads a dword out of the status page, which is written to from the command 747 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 748 * MI_STORE_DATA_IMM. 749 * 750 * The following dwords have a reserved meaning: 751 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 752 * 0x04: ring 0 head pointer 753 * 0x05: ring 1 head pointer (915-class) 754 * 0x06: ring 2 head pointer (915-class) 755 * 0x10-0x1b: Context status DWords (GM45) 756 * 0x1f: Last written status offset. (GM45) 757 * 758 * The area from dword 0x20 to 0x3ff is available for driver usage. 759 */ 760 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 761 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 762 #define I915_GEM_HWS_INDEX 0x20 763 #define I915_BREADCRUMB_INDEX 0x21 764 765 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 766 767 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 768 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 769 #define IS_I85X(dev) ((dev)->pci_device == 0x3582) 770 #define IS_I855(dev) ((dev)->pci_device == 0x3582) 771 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 772 773 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 774 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 775 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 776 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 777 (dev)->pci_device == 0x27AE) 778 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 779 (dev)->pci_device == 0x2982 || \ 780 (dev)->pci_device == 0x2992 || \ 781 (dev)->pci_device == 0x29A2 || \ 782 (dev)->pci_device == 0x2A02 || \ 783 (dev)->pci_device == 0x2A12 || \ 784 (dev)->pci_device == 0x2A42 || \ 785 (dev)->pci_device == 0x2E02 || \ 786 (dev)->pci_device == 0x2E12 || \ 787 (dev)->pci_device == 0x2E22 || \ 788 (dev)->pci_device == 0x2E32) 789 790 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \ 791 (dev)->pci_device == 0x2A12) 792 793 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 794 795 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 796 (dev)->pci_device == 0x2E12 || \ 797 (dev)->pci_device == 0x2E22 || \ 798 (dev)->pci_device == 0x2E32 || \ 799 IS_GM45(dev)) 800 801 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 802 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 803 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 804 805 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 806 (dev)->pci_device == 0x29B2 || \ 807 (dev)->pci_device == 0x29D2 || \ 808 (IS_IGD(dev))) 809 810 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 811 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 812 813 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 814 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 815 IS_IGD(dev)) 816 817 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 818 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 819 * rows, which changed the alignment requirements and fence programming. 820 */ 821 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 822 IS_I915GM(dev))) 823 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev)) 824 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev)) 825 826 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 827 828 #endif 829