1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/dma-resv.h> 47 #include <linux/shmem_fs.h> 48 #include <linux/stackdepot.h> 49 50 #include <drm/intel-gtt.h> 51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 52 #include <drm/drm_gem.h> 53 #include <drm/drm_auth.h> 54 #include <drm/drm_cache.h> 55 #include <drm/drm_util.h> 56 #include <drm/drm_dsc.h> 57 #include <drm/drm_atomic.h> 58 #include <drm/drm_connector.h> 59 #include <drm/i915_mei_hdcp_interface.h> 60 61 #include "i915_fixed.h" 62 #include "i915_params.h" 63 #include "i915_reg.h" 64 #include "i915_utils.h" 65 66 #include "display/intel_bios.h" 67 #include "display/intel_display.h" 68 #include "display/intel_display_power.h" 69 #include "display/intel_dpll_mgr.h" 70 #include "display/intel_dsb.h" 71 #include "display/intel_frontbuffer.h" 72 #include "display/intel_gmbus.h" 73 #include "display/intel_opregion.h" 74 75 #include "gem/i915_gem_context_types.h" 76 #include "gem/i915_gem_shrinker.h" 77 #include "gem/i915_gem_stolen.h" 78 79 #include "gt/intel_lrc.h" 80 #include "gt/intel_engine.h" 81 #include "gt/intel_gt_types.h" 82 #include "gt/intel_workarounds.h" 83 #include "gt/uc/intel_uc.h" 84 85 #include "intel_device_info.h" 86 #include "intel_pch.h" 87 #include "intel_runtime_pm.h" 88 #include "intel_memory_region.h" 89 #include "intel_uncore.h" 90 #include "intel_wakeref.h" 91 #include "intel_wopcm.h" 92 93 #include "i915_gem.h" 94 #include "i915_gem_fence_reg.h" 95 #include "i915_gem_gtt.h" 96 #include "i915_gpu_error.h" 97 #include "i915_perf_types.h" 98 #include "i915_request.h" 99 #include "i915_scheduler.h" 100 #include "gt/intel_timeline.h" 101 #include "i915_vma.h" 102 #include "i915_irq.h" 103 104 #include "intel_region_lmem.h" 105 106 #include "intel_gvt.h" 107 108 /* General customization: 109 */ 110 111 #define DRIVER_NAME "i915" 112 #define DRIVER_DESC "Intel Graphics" 113 #define DRIVER_DATE "20191101" 114 #define DRIVER_TIMESTAMP 1572604873 115 116 struct drm_i915_gem_object; 117 118 enum hpd_pin { 119 HPD_NONE = 0, 120 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 121 HPD_CRT, 122 HPD_SDVO_B, 123 HPD_SDVO_C, 124 HPD_PORT_A, 125 HPD_PORT_B, 126 HPD_PORT_C, 127 HPD_PORT_D, 128 HPD_PORT_E, 129 HPD_PORT_F, 130 HPD_PORT_G, 131 HPD_PORT_H, 132 HPD_PORT_I, 133 134 HPD_NUM_PINS 135 }; 136 137 #define for_each_hpd_pin(__pin) \ 138 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 139 140 /* Threshold == 5 for long IRQs, 50 for short */ 141 #define HPD_STORM_DEFAULT_THRESHOLD 50 142 143 struct i915_hotplug { 144 struct delayed_work hotplug_work; 145 146 struct { 147 unsigned long last_jiffies; 148 int count; 149 enum { 150 HPD_ENABLED = 0, 151 HPD_DISABLED = 1, 152 HPD_MARK_DISABLED = 2 153 } state; 154 } stats[HPD_NUM_PINS]; 155 u32 event_bits; 156 u32 retry_bits; 157 struct delayed_work reenable_work; 158 159 u32 long_port_mask; 160 u32 short_port_mask; 161 struct work_struct dig_port_work; 162 163 struct work_struct poll_init_work; 164 bool poll_enabled; 165 166 unsigned int hpd_storm_threshold; 167 /* Whether or not to count short HPD IRQs in HPD storms */ 168 u8 hpd_short_storm_enabled; 169 170 /* 171 * if we get a HPD irq from DP and a HPD irq from non-DP 172 * the non-DP HPD could block the workqueue on a mode config 173 * mutex getting, that userspace may have taken. However 174 * userspace is waiting on the DP workqueue to run which is 175 * blocked behind the non-DP one. 176 */ 177 struct workqueue_struct *dp_wq; 178 }; 179 180 #define I915_GEM_GPU_DOMAINS \ 181 (I915_GEM_DOMAIN_RENDER | \ 182 I915_GEM_DOMAIN_SAMPLER | \ 183 I915_GEM_DOMAIN_COMMAND | \ 184 I915_GEM_DOMAIN_INSTRUCTION | \ 185 I915_GEM_DOMAIN_VERTEX) 186 187 struct drm_i915_private; 188 struct i915_mm_struct; 189 struct i915_mmu_object; 190 191 struct drm_i915_file_private { 192 struct drm_i915_private *dev_priv; 193 194 union { 195 struct drm_file *file; 196 struct rcu_head rcu; 197 }; 198 199 struct { 200 spinlock_t lock; 201 struct list_head request_list; 202 } mm; 203 204 struct idr context_idr; 205 struct mutex context_idr_lock; /* guards context_idr */ 206 207 struct idr vm_idr; 208 struct mutex vm_idr_lock; /* guards vm_idr */ 209 210 unsigned int bsd_engine; 211 212 /* 213 * Every context ban increments per client ban score. Also 214 * hangs in short succession increments ban score. If ban threshold 215 * is reached, client is considered banned and submitting more work 216 * will fail. This is a stop gap measure to limit the badly behaving 217 * clients access to gpu. Note that unbannable contexts never increment 218 * the client ban score. 219 */ 220 #define I915_CLIENT_SCORE_HANG_FAST 1 221 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 222 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 223 #define I915_CLIENT_SCORE_BANNED 9 224 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 225 atomic_t ban_score; 226 unsigned long hang_timestamp; 227 }; 228 229 /* Interface history: 230 * 231 * 1.1: Original. 232 * 1.2: Add Power Management 233 * 1.3: Add vblank support 234 * 1.4: Fix cmdbuffer path, add heap destroy 235 * 1.5: Add vblank pipe configuration 236 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 237 * - Support vertical blank on secondary display pipe 238 */ 239 #define DRIVER_MAJOR 1 240 #define DRIVER_MINOR 6 241 #define DRIVER_PATCHLEVEL 0 242 243 struct intel_overlay; 244 struct intel_overlay_error_state; 245 246 struct sdvo_device_mapping { 247 u8 initialized; 248 u8 dvo_port; 249 u8 slave_addr; 250 u8 dvo_wiring; 251 u8 i2c_pin; 252 u8 ddc_pin; 253 }; 254 255 struct intel_connector; 256 struct intel_encoder; 257 struct intel_atomic_state; 258 struct intel_crtc_state; 259 struct intel_initial_plane_config; 260 struct intel_crtc; 261 struct intel_limit; 262 struct dpll; 263 struct intel_cdclk_state; 264 265 struct drm_i915_display_funcs { 266 void (*get_cdclk)(struct drm_i915_private *dev_priv, 267 struct intel_cdclk_state *cdclk_state); 268 void (*set_cdclk)(struct drm_i915_private *dev_priv, 269 const struct intel_cdclk_state *cdclk_state, 270 enum pipe pipe); 271 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 272 enum i9xx_plane_id i9xx_plane); 273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 275 void (*initial_watermarks)(struct intel_atomic_state *state, 276 struct intel_crtc_state *crtc_state); 277 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 278 struct intel_crtc_state *crtc_state); 279 void (*optimize_watermarks)(struct intel_atomic_state *state, 280 struct intel_crtc_state *crtc_state); 281 int (*compute_global_watermarks)(struct intel_atomic_state *state); 282 void (*update_wm)(struct intel_crtc *crtc); 283 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 284 u8 (*calc_voltage_level)(int cdclk); 285 /* Returns the active state of the crtc, and if the crtc is active, 286 * fills out the pipe-config with the hw state. */ 287 bool (*get_pipe_config)(struct intel_crtc *, 288 struct intel_crtc_state *); 289 void (*get_initial_plane_config)(struct intel_crtc *, 290 struct intel_initial_plane_config *); 291 int (*crtc_compute_clock)(struct intel_crtc *crtc, 292 struct intel_crtc_state *crtc_state); 293 void (*crtc_enable)(struct intel_crtc_state *pipe_config, 294 struct intel_atomic_state *old_state); 295 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, 296 struct intel_atomic_state *old_state); 297 void (*commit_modeset_enables)(struct intel_atomic_state *state); 298 void (*commit_modeset_disables)(struct intel_atomic_state *state); 299 void (*audio_codec_enable)(struct intel_encoder *encoder, 300 const struct intel_crtc_state *crtc_state, 301 const struct drm_connector_state *conn_state); 302 void (*audio_codec_disable)(struct intel_encoder *encoder, 303 const struct intel_crtc_state *old_crtc_state, 304 const struct drm_connector_state *old_conn_state); 305 void (*fdi_link_train)(struct intel_crtc *crtc, 306 const struct intel_crtc_state *crtc_state); 307 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 309 /* clock updates for mode set */ 310 /* cursor updates */ 311 /* render clock increase/decrease */ 312 /* display clock increase/decrease */ 313 /* pll clock increase/decrease */ 314 315 int (*color_check)(struct intel_crtc_state *crtc_state); 316 /* 317 * Program double buffered color management registers during 318 * vblank evasion. The registers should then latch during the 319 * next vblank start, alongside any other double buffered registers 320 * involved with the same commit. 321 */ 322 void (*color_commit)(const struct intel_crtc_state *crtc_state); 323 /* 324 * Load LUTs (and other single buffered color management 325 * registers). Will (hopefully) be called during the vblank 326 * following the latching of any double buffered registers 327 * involved with the same commit. 328 */ 329 void (*load_luts)(const struct intel_crtc_state *crtc_state); 330 void (*read_luts)(struct intel_crtc_state *crtc_state); 331 }; 332 333 struct intel_csr { 334 struct work_struct work; 335 const char *fw_path; 336 u32 required_version; 337 u32 max_fw_size; /* bytes */ 338 u32 *dmc_payload; 339 u32 dmc_fw_size; /* dwords */ 340 u32 version; 341 u32 mmio_count; 342 i915_reg_t mmioaddr[20]; 343 u32 mmiodata[20]; 344 u32 dc_state; 345 u32 target_dc_state; 346 u32 allowed_dc_mask; 347 intel_wakeref_t wakeref; 348 }; 349 350 enum i915_cache_level { 351 I915_CACHE_NONE = 0, 352 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 353 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 354 caches, eg sampler/render caches, and the 355 large Last-Level-Cache. LLC is coherent with 356 the CPU, but L3 is only visible to the GPU. */ 357 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 358 }; 359 360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 361 362 struct intel_fbc { 363 /* This is always the inner lock when overlapping with struct_mutex and 364 * it's the outer lock when overlapping with stolen_lock. */ 365 struct mutex lock; 366 unsigned threshold; 367 unsigned int possible_framebuffer_bits; 368 unsigned int busy_bits; 369 unsigned int visible_pipes_mask; 370 struct intel_crtc *crtc; 371 372 struct drm_mm_node compressed_fb; 373 struct drm_mm_node *compressed_llb; 374 375 bool false_color; 376 377 bool enabled; 378 bool active; 379 bool flip_pending; 380 381 bool underrun_detected; 382 struct work_struct underrun_work; 383 384 /* 385 * Due to the atomic rules we can't access some structures without the 386 * appropriate locking, so we cache information here in order to avoid 387 * these problems. 388 */ 389 struct intel_fbc_state_cache { 390 struct i915_vma *vma; 391 unsigned long flags; 392 393 struct { 394 unsigned int mode_flags; 395 u32 hsw_bdw_pixel_rate; 396 } crtc; 397 398 struct { 399 unsigned int rotation; 400 int src_w; 401 int src_h; 402 bool visible; 403 /* 404 * Display surface base address adjustement for 405 * pageflips. Note that on gen4+ this only adjusts up 406 * to a tile, offsets within a tile are handled in 407 * the hw itself (with the TILEOFF register). 408 */ 409 int adjusted_x; 410 int adjusted_y; 411 412 int y; 413 414 u16 pixel_blend_mode; 415 } plane; 416 417 struct { 418 const struct drm_format_info *format; 419 unsigned int stride; 420 } fb; 421 } state_cache; 422 423 /* 424 * This structure contains everything that's relevant to program the 425 * hardware registers. When we want to figure out if we need to disable 426 * and re-enable FBC for a new configuration we just check if there's 427 * something different in the struct. The genx_fbc_activate functions 428 * are supposed to read from it in order to program the registers. 429 */ 430 struct intel_fbc_reg_params { 431 struct i915_vma *vma; 432 unsigned long flags; 433 434 struct { 435 enum pipe pipe; 436 enum i9xx_plane_id i9xx_plane; 437 unsigned int fence_y_offset; 438 } crtc; 439 440 struct { 441 const struct drm_format_info *format; 442 unsigned int stride; 443 } fb; 444 445 int cfb_size; 446 unsigned int gen9_wa_cfb_stride; 447 } params; 448 449 const char *no_fbc_reason; 450 }; 451 452 /* 453 * HIGH_RR is the highest eDP panel refresh rate read from EDID 454 * LOW_RR is the lowest eDP panel refresh rate found from EDID 455 * parsing for same resolution. 456 */ 457 enum drrs_refresh_rate_type { 458 DRRS_HIGH_RR, 459 DRRS_LOW_RR, 460 DRRS_MAX_RR, /* RR count */ 461 }; 462 463 enum drrs_support_type { 464 DRRS_NOT_SUPPORTED = 0, 465 STATIC_DRRS_SUPPORT = 1, 466 SEAMLESS_DRRS_SUPPORT = 2 467 }; 468 469 struct intel_dp; 470 struct i915_drrs { 471 struct mutex mutex; 472 struct delayed_work work; 473 struct intel_dp *dp; 474 unsigned busy_frontbuffer_bits; 475 enum drrs_refresh_rate_type refresh_rate_type; 476 enum drrs_support_type type; 477 }; 478 479 struct i915_psr { 480 struct mutex lock; 481 482 #define I915_PSR_DEBUG_MODE_MASK 0x0f 483 #define I915_PSR_DEBUG_DEFAULT 0x00 484 #define I915_PSR_DEBUG_DISABLE 0x01 485 #define I915_PSR_DEBUG_ENABLE 0x02 486 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 487 #define I915_PSR_DEBUG_IRQ 0x10 488 489 u32 debug; 490 bool sink_support; 491 bool enabled; 492 struct intel_dp *dp; 493 enum pipe pipe; 494 enum transcoder transcoder; 495 bool active; 496 struct work_struct work; 497 unsigned busy_frontbuffer_bits; 498 bool sink_psr2_support; 499 bool link_standby; 500 bool colorimetry_support; 501 bool psr2_enabled; 502 u8 sink_sync_latency; 503 ktime_t last_entry_attempt; 504 ktime_t last_exit; 505 bool sink_not_reliable; 506 bool irq_aux_error; 507 u16 su_x_granularity; 508 bool dc3co_enabled; 509 u32 dc3co_exit_delay; 510 struct delayed_work idle_work; 511 }; 512 513 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 514 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 515 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 516 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 517 #define QUIRK_INCREASE_T12_DELAY (1<<6) 518 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 519 520 struct intel_fbdev; 521 struct intel_fbc_work; 522 523 struct intel_gmbus { 524 struct i2c_adapter adapter; 525 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 526 u32 force_bit; 527 u32 reg0; 528 i915_reg_t gpio_reg; 529 struct i2c_algo_bit_data bit_algo; 530 struct drm_i915_private *dev_priv; 531 }; 532 533 struct i915_suspend_saved_registers { 534 u32 saveDSPARB; 535 u32 saveFBC_CONTROL; 536 u32 saveCACHE_MODE_0; 537 u32 saveMI_ARB_STATE; 538 u32 saveSWF0[16]; 539 u32 saveSWF1[16]; 540 u32 saveSWF3[3]; 541 u64 saveFENCE[I915_MAX_NUM_FENCES]; 542 u32 savePCH_PORT_HOTPLUG; 543 u16 saveGCDGMBUS; 544 }; 545 546 struct vlv_s0ix_state; 547 548 #define MAX_L3_SLICES 2 549 struct intel_l3_parity { 550 u32 *remap_info[MAX_L3_SLICES]; 551 struct work_struct error_work; 552 int which_slice; 553 }; 554 555 struct i915_gem_mm { 556 /** Memory allocator for GTT stolen memory */ 557 struct drm_mm stolen; 558 /** Protects the usage of the GTT stolen memory allocator. This is 559 * always the inner lock when overlapping with struct_mutex. */ 560 struct mutex stolen_lock; 561 562 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 563 spinlock_t obj_lock; 564 565 /** 566 * List of objects which are purgeable. 567 */ 568 struct list_head purge_list; 569 570 /** 571 * List of objects which have allocated pages and are shrinkable. 572 */ 573 struct list_head shrink_list; 574 575 /** 576 * List of objects which are pending destruction. 577 */ 578 struct llist_head free_list; 579 struct work_struct free_work; 580 /** 581 * Count of objects pending destructions. Used to skip needlessly 582 * waiting on an RCU barrier if no objects are waiting to be freed. 583 */ 584 atomic_t free_count; 585 586 /** 587 * Small stash of WC pages 588 */ 589 struct pagestash wc_stash; 590 591 /** 592 * tmpfs instance used for shmem backed objects 593 */ 594 struct vfsmount *gemfs; 595 596 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 597 598 struct notifier_block oom_notifier; 599 struct notifier_block vmap_notifier; 600 struct shrinker shrinker; 601 602 /** 603 * Workqueue to fault in userptr pages, flushed by the execbuf 604 * when required but otherwise left to userspace to try again 605 * on EAGAIN. 606 */ 607 struct workqueue_struct *userptr_wq; 608 609 /* shrinker accounting, also useful for userland debugging */ 610 u64 shrink_memory; 611 u32 shrink_count; 612 }; 613 614 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 615 616 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 617 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 618 619 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 620 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 621 622 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 623 624 struct ddi_vbt_port_info { 625 /* Non-NULL if port present. */ 626 const struct child_device_config *child; 627 628 int max_tmds_clock; 629 630 /* 631 * This is an index in the HDMI/DVI DDI buffer translation table. 632 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 633 * populate this field. 634 */ 635 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 636 u8 hdmi_level_shift; 637 638 u8 supports_dvi:1; 639 u8 supports_hdmi:1; 640 u8 supports_dp:1; 641 u8 supports_edp:1; 642 u8 supports_typec_usb:1; 643 u8 supports_tbt:1; 644 645 u8 alternate_aux_channel; 646 u8 alternate_ddc_pin; 647 648 u8 dp_boost_level; 649 u8 hdmi_boost_level; 650 int dp_max_link_rate; /* 0 for not limited by VBT */ 651 }; 652 653 enum psr_lines_to_wait { 654 PSR_0_LINES_TO_WAIT = 0, 655 PSR_1_LINE_TO_WAIT, 656 PSR_4_LINES_TO_WAIT, 657 PSR_8_LINES_TO_WAIT 658 }; 659 660 struct intel_vbt_data { 661 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 662 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 663 664 /* Feature bits */ 665 unsigned int int_tv_support:1; 666 unsigned int lvds_dither:1; 667 unsigned int int_crt_support:1; 668 unsigned int lvds_use_ssc:1; 669 unsigned int int_lvds_support:1; 670 unsigned int display_clock_mode:1; 671 unsigned int fdi_rx_polarity_inverted:1; 672 unsigned int panel_type:4; 673 int lvds_ssc_freq; 674 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 675 enum drm_panel_orientation orientation; 676 677 enum drrs_support_type drrs_type; 678 679 struct { 680 int rate; 681 int lanes; 682 int preemphasis; 683 int vswing; 684 bool low_vswing; 685 bool initialized; 686 int bpp; 687 struct edp_power_seq pps; 688 } edp; 689 690 struct { 691 bool enable; 692 bool full_link; 693 bool require_aux_wakeup; 694 int idle_frames; 695 enum psr_lines_to_wait lines_to_wait; 696 int tp1_wakeup_time_us; 697 int tp2_tp3_wakeup_time_us; 698 int psr2_tp2_tp3_wakeup_time_us; 699 } psr; 700 701 struct { 702 u16 pwm_freq_hz; 703 bool present; 704 bool active_low_pwm; 705 u8 min_brightness; /* min_brightness/255 of max */ 706 u8 controller; /* brightness controller number */ 707 enum intel_backlight_type type; 708 } backlight; 709 710 /* MIPI DSI */ 711 struct { 712 u16 panel_id; 713 struct mipi_config *config; 714 struct mipi_pps_data *pps; 715 u16 bl_ports; 716 u16 cabc_ports; 717 u8 seq_version; 718 u32 size; 719 u8 *data; 720 const u8 *sequence[MIPI_SEQ_MAX]; 721 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 722 enum drm_panel_orientation orientation; 723 } dsi; 724 725 int crt_ddc_pin; 726 727 int child_dev_num; 728 struct child_device_config *child_dev; 729 730 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 731 struct sdvo_device_mapping sdvo_mappings[2]; 732 }; 733 734 enum intel_ddb_partitioning { 735 INTEL_DDB_PART_1_2, 736 INTEL_DDB_PART_5_6, /* IVB+ */ 737 }; 738 739 struct intel_wm_level { 740 bool enable; 741 u32 pri_val; 742 u32 spr_val; 743 u32 cur_val; 744 u32 fbc_val; 745 }; 746 747 struct ilk_wm_values { 748 u32 wm_pipe[3]; 749 u32 wm_lp[3]; 750 u32 wm_lp_spr[3]; 751 u32 wm_linetime[3]; 752 bool enable_fbc_wm; 753 enum intel_ddb_partitioning partitioning; 754 }; 755 756 struct g4x_pipe_wm { 757 u16 plane[I915_MAX_PLANES]; 758 u16 fbc; 759 }; 760 761 struct g4x_sr_wm { 762 u16 plane; 763 u16 cursor; 764 u16 fbc; 765 }; 766 767 struct vlv_wm_ddl_values { 768 u8 plane[I915_MAX_PLANES]; 769 }; 770 771 struct vlv_wm_values { 772 struct g4x_pipe_wm pipe[3]; 773 struct g4x_sr_wm sr; 774 struct vlv_wm_ddl_values ddl[3]; 775 u8 level; 776 bool cxsr; 777 }; 778 779 struct g4x_wm_values { 780 struct g4x_pipe_wm pipe[2]; 781 struct g4x_sr_wm sr; 782 struct g4x_sr_wm hpll; 783 bool cxsr; 784 bool hpll_en; 785 bool fbc_en; 786 }; 787 788 struct skl_ddb_entry { 789 u16 start, end; /* in number of blocks, 'end' is exclusive */ 790 }; 791 792 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 793 { 794 return entry->end - entry->start; 795 } 796 797 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 798 const struct skl_ddb_entry *e2) 799 { 800 if (e1->start == e2->start && e1->end == e2->end) 801 return true; 802 803 return false; 804 } 805 806 struct skl_ddb_allocation { 807 u8 enabled_slices; /* GEN11 has configurable 2 slices */ 808 }; 809 810 struct skl_ddb_values { 811 unsigned dirty_pipes; 812 struct skl_ddb_allocation ddb; 813 }; 814 815 struct skl_wm_level { 816 u16 min_ddb_alloc; 817 u16 plane_res_b; 818 u8 plane_res_l; 819 bool plane_en; 820 bool ignore_lines; 821 }; 822 823 /* Stores plane specific WM parameters */ 824 struct skl_wm_params { 825 bool x_tiled, y_tiled; 826 bool rc_surface; 827 bool is_planar; 828 u32 width; 829 u8 cpp; 830 u32 plane_pixel_rate; 831 u32 y_min_scanlines; 832 u32 plane_bytes_per_line; 833 uint_fixed_16_16_t plane_blocks_per_line; 834 uint_fixed_16_16_t y_tile_minimum; 835 u32 linetime_us; 836 u32 dbuf_block_size; 837 }; 838 839 enum intel_pipe_crc_source { 840 INTEL_PIPE_CRC_SOURCE_NONE, 841 INTEL_PIPE_CRC_SOURCE_PLANE1, 842 INTEL_PIPE_CRC_SOURCE_PLANE2, 843 INTEL_PIPE_CRC_SOURCE_PLANE3, 844 INTEL_PIPE_CRC_SOURCE_PLANE4, 845 INTEL_PIPE_CRC_SOURCE_PLANE5, 846 INTEL_PIPE_CRC_SOURCE_PLANE6, 847 INTEL_PIPE_CRC_SOURCE_PLANE7, 848 INTEL_PIPE_CRC_SOURCE_PIPE, 849 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 850 INTEL_PIPE_CRC_SOURCE_TV, 851 INTEL_PIPE_CRC_SOURCE_DP_B, 852 INTEL_PIPE_CRC_SOURCE_DP_C, 853 INTEL_PIPE_CRC_SOURCE_DP_D, 854 INTEL_PIPE_CRC_SOURCE_AUTO, 855 INTEL_PIPE_CRC_SOURCE_MAX, 856 }; 857 858 #define INTEL_PIPE_CRC_ENTRIES_NR 128 859 struct intel_pipe_crc { 860 spinlock_t lock; 861 int skipped; 862 enum intel_pipe_crc_source source; 863 }; 864 865 struct i915_frontbuffer_tracking { 866 spinlock_t lock; 867 868 /* 869 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 870 * scheduled flips. 871 */ 872 unsigned busy_bits; 873 unsigned flip_bits; 874 }; 875 876 struct i915_virtual_gpu { 877 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 878 bool active; 879 u32 caps; 880 }; 881 882 /* used in computing the new watermarks state */ 883 struct intel_wm_config { 884 unsigned int num_pipes_active; 885 bool sprites_enabled; 886 bool sprites_scaled; 887 }; 888 889 struct intel_cdclk_state { 890 unsigned int cdclk, vco, ref, bypass; 891 u8 voltage_level; 892 }; 893 894 struct drm_i915_private { 895 struct drm_device drm; 896 897 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 898 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 899 struct intel_driver_caps caps; 900 901 /** 902 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 903 * end of stolen which we can optionally use to create GEM objects 904 * backed by stolen memory. Note that stolen_usable_size tells us 905 * exactly how much of this we are actually allowed to use, given that 906 * some portion of it is in fact reserved for use by hardware functions. 907 */ 908 struct resource dsm; 909 /** 910 * Reseved portion of Data Stolen Memory 911 */ 912 struct resource dsm_reserved; 913 914 /* 915 * Stolen memory is segmented in hardware with different portions 916 * offlimits to certain functions. 917 * 918 * The drm_mm is initialised to the total accessible range, as found 919 * from the PCI config. On Broadwell+, this is further restricted to 920 * avoid the first page! The upper end of stolen memory is reserved for 921 * hardware functions and similarly removed from the accessible range. 922 */ 923 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 924 925 struct intel_uncore uncore; 926 struct intel_uncore_mmio_debug mmio_debug; 927 928 struct i915_virtual_gpu vgpu; 929 930 struct intel_gvt *gvt; 931 932 struct intel_wopcm wopcm; 933 934 struct intel_csr csr; 935 936 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 937 938 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 939 * controller on different i2c buses. */ 940 struct mutex gmbus_mutex; 941 942 /** 943 * Base address of where the gmbus and gpio blocks are located (either 944 * on PCH or on SoC for platforms without PCH). 945 */ 946 u32 gpio_mmio_base; 947 948 u32 hsw_psr_mmio_adjust; 949 950 /* MMIO base address for MIPI regs */ 951 u32 mipi_mmio_base; 952 953 u32 pps_mmio_base; 954 955 wait_queue_head_t gmbus_wait_queue; 956 957 struct pci_dev *bridge_dev; 958 959 /* Context used internally to idle the GPU and setup initial state */ 960 struct i915_gem_context *kernel_context; 961 962 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 963 struct rb_root uabi_engines; 964 965 struct resource mch_res; 966 967 /* protects the irq masks */ 968 spinlock_t irq_lock; 969 970 bool display_irqs_enabled; 971 972 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 973 struct pm_qos_request pm_qos; 974 975 /* Sideband mailbox protection */ 976 struct mutex sb_lock; 977 struct pm_qos_request sb_qos; 978 979 /** Cached value of IMR to avoid reads in updating the bitfield */ 980 union { 981 u32 irq_mask; 982 u32 de_irq_mask[I915_MAX_PIPES]; 983 }; 984 u32 pipestat_irq_mask[I915_MAX_PIPES]; 985 986 struct i915_hotplug hotplug; 987 struct intel_fbc fbc; 988 struct i915_drrs drrs; 989 struct intel_opregion opregion; 990 struct intel_vbt_data vbt; 991 992 bool preserve_bios_swizzle; 993 994 /* overlay */ 995 struct intel_overlay *overlay; 996 997 /* backlight registers and fields in struct intel_panel */ 998 struct mutex backlight_lock; 999 1000 /* protects panel power sequencer state */ 1001 struct mutex pps_mutex; 1002 1003 unsigned int fsb_freq, mem_freq, is_ddr3; 1004 unsigned int skl_preferred_vco_freq; 1005 unsigned int max_cdclk_freq; 1006 1007 unsigned int max_dotclk_freq; 1008 unsigned int rawclk_freq; 1009 unsigned int hpll_freq; 1010 unsigned int fdi_pll_freq; 1011 unsigned int czclk_freq; 1012 1013 /* 1014 * For reading holding any crtc lock is sufficient, 1015 * for writing must hold all of them. 1016 */ 1017 struct { 1018 /* 1019 * The current logical cdclk state. 1020 * See intel_atomic_state.cdclk.logical 1021 */ 1022 struct intel_cdclk_state logical; 1023 /* 1024 * The current actual cdclk state. 1025 * See intel_atomic_state.cdclk.actual 1026 */ 1027 struct intel_cdclk_state actual; 1028 /* The current hardware cdclk state */ 1029 struct intel_cdclk_state hw; 1030 1031 /* cdclk, divider, and ratio table from bspec */ 1032 const struct intel_cdclk_vals *table; 1033 1034 int force_min_cdclk; 1035 } cdclk; 1036 1037 /** 1038 * wq - Driver workqueue for GEM. 1039 * 1040 * NOTE: Work items scheduled here are not allowed to grab any modeset 1041 * locks, for otherwise the flushing done in the pageflip code will 1042 * result in deadlocks. 1043 */ 1044 struct workqueue_struct *wq; 1045 1046 /* ordered wq for modesets */ 1047 struct workqueue_struct *modeset_wq; 1048 /* unbound hipri wq for page flips/plane updates */ 1049 struct workqueue_struct *flip_wq; 1050 1051 /* Display functions */ 1052 struct drm_i915_display_funcs display; 1053 1054 /* PCH chipset type */ 1055 enum intel_pch pch_type; 1056 unsigned short pch_id; 1057 1058 unsigned long quirks; 1059 1060 struct drm_atomic_state *modeset_restore_state; 1061 struct drm_modeset_acquire_ctx reset_ctx; 1062 1063 struct i915_ggtt ggtt; /* VM representing the global address space */ 1064 1065 struct i915_gem_mm mm; 1066 DECLARE_HASHTABLE(mm_structs, 7); 1067 struct mutex mm_lock; 1068 1069 /* Kernel Modesetting */ 1070 1071 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1072 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1073 1074 #ifdef CONFIG_DEBUG_FS 1075 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1076 #endif 1077 1078 /* dpll and cdclk state is protected by connection_mutex */ 1079 int num_shared_dpll; 1080 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1081 const struct intel_dpll_mgr *dpll_mgr; 1082 1083 /* 1084 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1085 * Must be global rather than per dpll, because on some platforms 1086 * plls share registers. 1087 */ 1088 struct mutex dpll_lock; 1089 1090 /* 1091 * For reading active_pipes, min_cdclk, min_voltage_level holding 1092 * any crtc lock is sufficient, for writing must hold all of them. 1093 */ 1094 u8 active_pipes; 1095 /* minimum acceptable cdclk for each pipe */ 1096 int min_cdclk[I915_MAX_PIPES]; 1097 /* minimum acceptable voltage level for each pipe */ 1098 u8 min_voltage_level[I915_MAX_PIPES]; 1099 1100 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1101 1102 struct i915_wa_list gt_wa_list; 1103 1104 struct i915_frontbuffer_tracking fb_tracking; 1105 1106 struct intel_atomic_helper { 1107 struct llist_head free_list; 1108 struct work_struct free_work; 1109 } atomic_helper; 1110 1111 u16 orig_clock; 1112 1113 bool mchbar_need_disable; 1114 1115 struct intel_l3_parity l3_parity; 1116 1117 /* 1118 * edram size in MB. 1119 * Cannot be determined by PCIID. You must always read a register. 1120 */ 1121 u32 edram_size_mb; 1122 1123 struct i915_power_domains power_domains; 1124 1125 struct i915_psr psr; 1126 1127 struct i915_gpu_error gpu_error; 1128 1129 struct drm_i915_gem_object *vlv_pctx; 1130 1131 /* list of fbdev register on this device */ 1132 struct intel_fbdev *fbdev; 1133 struct work_struct fbdev_suspend_work; 1134 1135 struct drm_property *broadcast_rgb_property; 1136 struct drm_property *force_audio_property; 1137 1138 /* hda/i915 audio component */ 1139 struct i915_audio_component *audio_component; 1140 bool audio_component_registered; 1141 /** 1142 * av_mutex - mutex for audio/video sync 1143 * 1144 */ 1145 struct mutex av_mutex; 1146 int audio_power_refcount; 1147 u32 audio_freq_cntrl; 1148 1149 u32 fdi_rx_config; 1150 1151 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1152 u32 chv_phy_control; 1153 /* 1154 * Shadows for CHV DPLL_MD regs to keep the state 1155 * checker somewhat working in the presence hardware 1156 * crappiness (can't read out DPLL_MD for pipes B & C). 1157 */ 1158 u32 chv_dpll_md[I915_MAX_PIPES]; 1159 u32 bxt_phy_grc; 1160 1161 u32 suspend_count; 1162 bool power_domains_suspended; 1163 struct i915_suspend_saved_registers regfile; 1164 struct vlv_s0ix_state *vlv_s0ix_state; 1165 1166 enum { 1167 I915_SAGV_UNKNOWN = 0, 1168 I915_SAGV_DISABLED, 1169 I915_SAGV_ENABLED, 1170 I915_SAGV_NOT_CONTROLLED 1171 } sagv_status; 1172 1173 u32 sagv_block_time_us; 1174 1175 struct { 1176 /* 1177 * Raw watermark latency values: 1178 * in 0.1us units for WM0, 1179 * in 0.5us units for WM1+. 1180 */ 1181 /* primary */ 1182 u16 pri_latency[5]; 1183 /* sprite */ 1184 u16 spr_latency[5]; 1185 /* cursor */ 1186 u16 cur_latency[5]; 1187 /* 1188 * Raw watermark memory latency values 1189 * for SKL for all 8 levels 1190 * in 1us units. 1191 */ 1192 u16 skl_latency[8]; 1193 1194 /* current hardware state */ 1195 union { 1196 struct ilk_wm_values hw; 1197 struct skl_ddb_values skl_hw; 1198 struct vlv_wm_values vlv; 1199 struct g4x_wm_values g4x; 1200 }; 1201 1202 u8 max_level; 1203 1204 /* 1205 * Should be held around atomic WM register writing; also 1206 * protects * intel_crtc->wm.active and 1207 * crtc_state->wm.need_postvbl_update. 1208 */ 1209 struct mutex wm_mutex; 1210 1211 /* 1212 * Set during HW readout of watermarks/DDB. Some platforms 1213 * need to know when we're still using BIOS-provided values 1214 * (which we don't fully trust). 1215 */ 1216 bool distrust_bios_wm; 1217 } wm; 1218 1219 struct dram_info { 1220 bool valid; 1221 bool is_16gb_dimm; 1222 u8 num_channels; 1223 u8 ranks; 1224 u32 bandwidth_kbps; 1225 bool symmetric_memory; 1226 enum intel_dram_type { 1227 INTEL_DRAM_UNKNOWN, 1228 INTEL_DRAM_DDR3, 1229 INTEL_DRAM_DDR4, 1230 INTEL_DRAM_LPDDR3, 1231 INTEL_DRAM_LPDDR4 1232 } type; 1233 } dram_info; 1234 1235 struct intel_bw_info { 1236 unsigned int deratedbw[3]; /* for each QGV point */ 1237 u8 num_qgv_points; 1238 u8 num_planes; 1239 } max_bw[6]; 1240 1241 struct drm_private_obj bw_obj; 1242 1243 struct intel_runtime_pm runtime_pm; 1244 1245 struct i915_perf perf; 1246 1247 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1248 struct intel_gt gt; 1249 1250 struct { 1251 struct notifier_block pm_notifier; 1252 1253 struct i915_gem_contexts { 1254 spinlock_t lock; /* locks list */ 1255 struct list_head list; 1256 1257 struct llist_head free_list; 1258 struct work_struct free_work; 1259 } contexts; 1260 } gem; 1261 1262 u8 pch_ssc_use; 1263 1264 /* For i915gm/i945gm vblank irq workaround */ 1265 u8 vblank_enabled; 1266 1267 /* perform PHY state sanity checks? */ 1268 bool chv_phy_assert[2]; 1269 1270 bool ipc_enabled; 1271 1272 /* Used to save the pipe-to-encoder mapping for audio */ 1273 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1274 1275 /* necessary resource sharing with HDMI LPE audio driver. */ 1276 struct { 1277 struct platform_device *platdev; 1278 int irq; 1279 } lpe_audio; 1280 1281 struct i915_pmu pmu; 1282 1283 struct i915_hdcp_comp_master *hdcp_master; 1284 bool hdcp_comp_added; 1285 1286 /* Mutex to protect the above hdcp component related values. */ 1287 struct mutex hdcp_comp_mutex; 1288 1289 /* 1290 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1291 * will be rejected. Instead look for a better place. 1292 */ 1293 }; 1294 1295 struct dram_dimm_info { 1296 u8 size, width, ranks; 1297 }; 1298 1299 struct dram_channel_info { 1300 struct dram_dimm_info dimm_l, dimm_s; 1301 u8 ranks; 1302 bool is_16gb_dimm; 1303 }; 1304 1305 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1306 { 1307 return container_of(dev, struct drm_i915_private, drm); 1308 } 1309 1310 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1311 { 1312 return dev_get_drvdata(kdev); 1313 } 1314 1315 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1316 { 1317 return pci_get_drvdata(pdev); 1318 } 1319 1320 /* Simple iterator over all initialised engines */ 1321 #define for_each_engine(engine__, dev_priv__, id__) \ 1322 for ((id__) = 0; \ 1323 (id__) < I915_NUM_ENGINES; \ 1324 (id__)++) \ 1325 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1326 1327 /* Iterator over subset of engines selected by mask */ 1328 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1329 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ 1330 (tmp__) ? \ 1331 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1332 0;) 1333 1334 #define rb_to_uabi_engine(rb) \ 1335 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1336 1337 #define for_each_uabi_engine(engine__, i915__) \ 1338 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1339 (engine__); \ 1340 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1341 1342 #define I915_GTT_OFFSET_NONE ((u32)-1) 1343 1344 /* 1345 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1346 * considered to be the frontbuffer for the given plane interface-wise. This 1347 * doesn't mean that the hw necessarily already scans it out, but that any 1348 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1349 * 1350 * We have one bit per pipe and per scanout plane type. 1351 */ 1352 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1353 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1354 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1355 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1356 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1357 }) 1358 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1359 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1360 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1361 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1362 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1363 1364 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1365 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1366 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1367 1368 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1369 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1370 1371 #define REVID_FOREVER 0xff 1372 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1373 1374 #define INTEL_GEN_MASK(s, e) ( \ 1375 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1376 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1377 GENMASK((e) - 1, (s) - 1)) 1378 1379 /* Returns true if Gen is in inclusive range [Start, End] */ 1380 #define IS_GEN_RANGE(dev_priv, s, e) \ 1381 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1382 1383 #define IS_GEN(dev_priv, n) \ 1384 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1385 INTEL_INFO(dev_priv)->gen == (n)) 1386 1387 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1388 1389 /* 1390 * Return true if revision is in range [since,until] inclusive. 1391 * 1392 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1393 */ 1394 #define IS_REVID(p, since, until) \ 1395 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1396 1397 static __always_inline unsigned int 1398 __platform_mask_index(const struct intel_runtime_info *info, 1399 enum intel_platform p) 1400 { 1401 const unsigned int pbits = 1402 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1403 1404 /* Expand the platform_mask array if this fails. */ 1405 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1406 pbits * ARRAY_SIZE(info->platform_mask)); 1407 1408 return p / pbits; 1409 } 1410 1411 static __always_inline unsigned int 1412 __platform_mask_bit(const struct intel_runtime_info *info, 1413 enum intel_platform p) 1414 { 1415 const unsigned int pbits = 1416 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1417 1418 return p % pbits + INTEL_SUBPLATFORM_BITS; 1419 } 1420 1421 static inline u32 1422 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1423 { 1424 const unsigned int pi = __platform_mask_index(info, p); 1425 1426 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1427 } 1428 1429 static __always_inline bool 1430 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1431 { 1432 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1433 const unsigned int pi = __platform_mask_index(info, p); 1434 const unsigned int pb = __platform_mask_bit(info, p); 1435 1436 BUILD_BUG_ON(!__builtin_constant_p(p)); 1437 1438 return info->platform_mask[pi] & BIT(pb); 1439 } 1440 1441 static __always_inline bool 1442 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1443 enum intel_platform p, unsigned int s) 1444 { 1445 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1446 const unsigned int pi = __platform_mask_index(info, p); 1447 const unsigned int pb = __platform_mask_bit(info, p); 1448 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1449 const u32 mask = info->platform_mask[pi]; 1450 1451 BUILD_BUG_ON(!__builtin_constant_p(p)); 1452 BUILD_BUG_ON(!__builtin_constant_p(s)); 1453 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1454 1455 /* Shift and test on the MSB position so sign flag can be used. */ 1456 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1457 } 1458 1459 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1460 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1461 1462 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1463 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1464 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1465 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1466 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1467 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1468 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1469 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1470 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1471 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1472 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1473 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1474 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1475 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1476 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1477 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1478 #define IS_IRONLAKE_M(dev_priv) \ 1479 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1480 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1481 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1482 INTEL_INFO(dev_priv)->gt == 1) 1483 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1484 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1485 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1486 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1487 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1488 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1489 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1490 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1491 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1492 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1493 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1494 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1495 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1496 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1497 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1498 #define IS_BDW_ULT(dev_priv) \ 1499 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1500 #define IS_BDW_ULX(dev_priv) \ 1501 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1502 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1503 INTEL_INFO(dev_priv)->gt == 3) 1504 #define IS_HSW_ULT(dev_priv) \ 1505 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1506 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1507 INTEL_INFO(dev_priv)->gt == 3) 1508 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1509 INTEL_INFO(dev_priv)->gt == 1) 1510 /* ULX machines are also considered ULT. */ 1511 #define IS_HSW_ULX(dev_priv) \ 1512 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1513 #define IS_SKL_ULT(dev_priv) \ 1514 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1515 #define IS_SKL_ULX(dev_priv) \ 1516 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1517 #define IS_KBL_ULT(dev_priv) \ 1518 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1519 #define IS_KBL_ULX(dev_priv) \ 1520 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1521 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1522 INTEL_INFO(dev_priv)->gt == 2) 1523 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1524 INTEL_INFO(dev_priv)->gt == 3) 1525 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1526 INTEL_INFO(dev_priv)->gt == 4) 1527 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1528 INTEL_INFO(dev_priv)->gt == 2) 1529 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1530 INTEL_INFO(dev_priv)->gt == 3) 1531 #define IS_CFL_ULT(dev_priv) \ 1532 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1533 #define IS_CFL_ULX(dev_priv) \ 1534 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1535 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1536 INTEL_INFO(dev_priv)->gt == 2) 1537 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1538 INTEL_INFO(dev_priv)->gt == 3) 1539 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1540 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1541 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1542 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1543 1544 #define SKL_REVID_A0 0x0 1545 #define SKL_REVID_B0 0x1 1546 #define SKL_REVID_C0 0x2 1547 #define SKL_REVID_D0 0x3 1548 #define SKL_REVID_E0 0x4 1549 #define SKL_REVID_F0 0x5 1550 #define SKL_REVID_G0 0x6 1551 #define SKL_REVID_H0 0x7 1552 1553 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1554 1555 #define BXT_REVID_A0 0x0 1556 #define BXT_REVID_A1 0x1 1557 #define BXT_REVID_B0 0x3 1558 #define BXT_REVID_B_LAST 0x8 1559 #define BXT_REVID_C0 0x9 1560 1561 #define IS_BXT_REVID(dev_priv, since, until) \ 1562 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1563 1564 #define KBL_REVID_A0 0x0 1565 #define KBL_REVID_B0 0x1 1566 #define KBL_REVID_C0 0x2 1567 #define KBL_REVID_D0 0x3 1568 #define KBL_REVID_E0 0x4 1569 1570 #define IS_KBL_REVID(dev_priv, since, until) \ 1571 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1572 1573 #define GLK_REVID_A0 0x0 1574 #define GLK_REVID_A1 0x1 1575 1576 #define IS_GLK_REVID(dev_priv, since, until) \ 1577 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1578 1579 #define CNL_REVID_A0 0x0 1580 #define CNL_REVID_B0 0x1 1581 #define CNL_REVID_C0 0x2 1582 1583 #define IS_CNL_REVID(p, since, until) \ 1584 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1585 1586 #define ICL_REVID_A0 0x0 1587 #define ICL_REVID_A2 0x1 1588 #define ICL_REVID_B0 0x3 1589 #define ICL_REVID_B2 0x4 1590 #define ICL_REVID_C0 0x5 1591 1592 #define IS_ICL_REVID(p, since, until) \ 1593 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1594 1595 #define TGL_REVID_A0 0x0 1596 1597 #define IS_TGL_REVID(p, since, until) \ 1598 (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) 1599 1600 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1601 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1602 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1603 1604 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 1605 1606 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 1607 unsigned int first__ = (first); \ 1608 unsigned int count__ = (count); \ 1609 (INTEL_INFO(dev_priv)->engine_mask & \ 1610 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1611 }) 1612 #define VDBOX_MASK(dev_priv) \ 1613 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 1614 #define VEBOX_MASK(dev_priv) \ 1615 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 1616 1617 /* 1618 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1619 * All later gens can run the final buffer from the ppgtt 1620 */ 1621 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1622 1623 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1624 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1625 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1626 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1627 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 1628 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 1629 1630 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1631 1632 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1633 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1634 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1635 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1636 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 1637 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 1638 1639 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1640 1641 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1642 #define HAS_PPGTT(dev_priv) \ 1643 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1644 #define HAS_FULL_PPGTT(dev_priv) \ 1645 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1646 1647 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1648 GEM_BUG_ON((sizes) == 0); \ 1649 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1650 }) 1651 1652 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1653 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1654 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1655 1656 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1657 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1658 1659 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1660 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1661 1662 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1663 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1664 (IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9)) 1665 1666 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1667 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1668 IS_GEMINILAKE(dev_priv) || \ 1669 IS_KABYLAKE(dev_priv)) 1670 1671 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1672 * rows, which changed the alignment requirements and fence programming. 1673 */ 1674 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1675 !(IS_I915G(dev_priv) || \ 1676 IS_I915GM(dev_priv))) 1677 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1678 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1679 1680 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1681 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1682 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1683 1684 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1685 1686 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1687 1688 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1689 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1690 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1691 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) 1692 1693 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1694 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1695 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1696 1697 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1698 1699 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1700 1701 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1702 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1703 1704 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1705 1706 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1707 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1708 1709 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1710 1711 /* Having GuC is not the same as using GuC */ 1712 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) 1713 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) 1714 1715 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1716 1717 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1718 1719 1720 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1721 1722 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1723 1724 /* DPF == dynamic parity feature */ 1725 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1726 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1727 2 : HAS_L3_DPF(dev_priv)) 1728 1729 #define GT_FREQUENCY_MULTIPLIER 50 1730 #define GEN9_FREQ_SCALER 3 1731 1732 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1733 1734 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1735 1736 /* Only valid when HAS_DISPLAY() is true */ 1737 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) 1738 1739 static inline bool intel_vtd_active(void) 1740 { 1741 #ifdef CONFIG_INTEL_IOMMU 1742 if (intel_iommu_gfx_mapped) 1743 return true; 1744 #endif 1745 return false; 1746 } 1747 1748 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1749 { 1750 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1751 } 1752 1753 static inline bool 1754 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1755 { 1756 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1757 } 1758 1759 /* i915_drv.c */ 1760 #ifdef CONFIG_COMPAT 1761 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 1762 #else 1763 #define i915_compat_ioctl NULL 1764 #endif 1765 extern const struct dev_pm_ops i915_pm_ops; 1766 1767 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1768 void i915_driver_remove(struct drm_i915_private *i915); 1769 1770 int i915_resume_switcheroo(struct drm_i915_private *i915); 1771 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1772 1773 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 1774 1775 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 1776 { 1777 return dev_priv->gvt; 1778 } 1779 1780 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 1781 { 1782 return dev_priv->vgpu.active; 1783 } 1784 1785 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1786 struct drm_file *file_priv); 1787 1788 /* i915_gem.c */ 1789 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1790 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1791 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1792 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1793 int i915_gem_freeze(struct drm_i915_private *dev_priv); 1794 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 1795 1796 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1797 1798 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1799 { 1800 /* 1801 * A single pass should suffice to release all the freed objects (along 1802 * most call paths) , but be a little more paranoid in that freeing 1803 * the objects does take a little amount of time, during which the rcu 1804 * callbacks could have added new objects into the freed list, and 1805 * armed the work again. 1806 */ 1807 while (atomic_read(&i915->mm.free_count)) { 1808 flush_work(&i915->mm.free_work); 1809 rcu_barrier(); 1810 } 1811 } 1812 1813 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1814 { 1815 /* 1816 * Similar to objects above (see i915_gem_drain_freed-objects), in 1817 * general we have workers that are armed by RCU and then rearm 1818 * themselves in their callbacks. To be paranoid, we need to 1819 * drain the workqueue a second time after waiting for the RCU 1820 * grace period so that we catch work queued via RCU from the first 1821 * pass. As neither drain_workqueue() nor flush_workqueue() report 1822 * a result, we make an assumption that we only don't require more 1823 * than 3 passes to catch all _recursive_ RCU delayed work. 1824 * 1825 */ 1826 int pass = 3; 1827 do { 1828 flush_workqueue(i915->wq); 1829 rcu_barrier(); 1830 i915_gem_drain_freed_objects(i915); 1831 } while (--pass); 1832 drain_workqueue(i915->wq); 1833 } 1834 1835 struct i915_vma * __must_check 1836 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1837 const struct i915_ggtt_view *view, 1838 u64 size, 1839 u64 alignment, 1840 u64 flags); 1841 1842 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1843 unsigned long flags); 1844 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1845 1846 struct i915_vma * __must_check 1847 i915_gem_object_pin(struct drm_i915_gem_object *obj, 1848 struct i915_address_space *vm, 1849 const struct i915_ggtt_view *view, 1850 u64 size, 1851 u64 alignment, 1852 u64 flags); 1853 1854 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1855 1856 static inline int __must_check 1857 i915_mutex_lock_interruptible(struct drm_device *dev) 1858 { 1859 return mutex_lock_interruptible(&dev->struct_mutex); 1860 } 1861 1862 int i915_gem_dumb_create(struct drm_file *file_priv, 1863 struct drm_device *dev, 1864 struct drm_mode_create_dumb *args); 1865 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1866 u32 handle, u64 *offset); 1867 int i915_gem_mmap_gtt_version(void); 1868 1869 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1870 1871 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1872 { 1873 return atomic_read(&error->reset_count); 1874 } 1875 1876 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1877 struct intel_engine_cs *engine) 1878 { 1879 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1880 } 1881 1882 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1883 void i915_gem_driver_register(struct drm_i915_private *i915); 1884 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1885 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1886 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1887 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1888 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1889 void i915_gem_resume(struct drm_i915_private *dev_priv); 1890 vm_fault_t i915_gem_fault(struct vm_fault *vmf); 1891 1892 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1893 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1894 1895 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1896 enum i915_cache_level cache_level); 1897 1898 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1899 struct dma_buf *dma_buf); 1900 1901 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1902 1903 static inline struct i915_gem_context * 1904 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1905 { 1906 return idr_find(&file_priv->context_idr, id); 1907 } 1908 1909 static inline struct i915_gem_context * 1910 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1911 { 1912 struct i915_gem_context *ctx; 1913 1914 rcu_read_lock(); 1915 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1916 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1917 ctx = NULL; 1918 rcu_read_unlock(); 1919 1920 return ctx; 1921 } 1922 1923 /* i915_gem_evict.c */ 1924 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1925 u64 min_size, u64 alignment, 1926 unsigned long color, 1927 u64 start, u64 end, 1928 unsigned flags); 1929 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1930 struct drm_mm_node *node, 1931 unsigned int flags); 1932 int i915_gem_evict_vm(struct i915_address_space *vm); 1933 1934 /* i915_gem_internal.c */ 1935 struct drm_i915_gem_object * 1936 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1937 phys_addr_t size); 1938 1939 /* i915_gem_tiling.c */ 1940 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1941 { 1942 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1943 1944 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1945 i915_gem_object_is_tiled(obj); 1946 } 1947 1948 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1949 unsigned int tiling, unsigned int stride); 1950 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1951 unsigned int tiling, unsigned int stride); 1952 1953 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1954 1955 /* i915_cmd_parser.c */ 1956 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1957 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1958 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1959 int intel_engine_cmd_parser(struct i915_gem_context *cxt, 1960 struct intel_engine_cs *engine, 1961 struct drm_i915_gem_object *batch_obj, 1962 u64 user_batch_start, 1963 u32 batch_start_offset, 1964 u32 batch_len, 1965 struct drm_i915_gem_object *shadow_batch_obj, 1966 u64 shadow_batch_start); 1967 1968 /* intel_device_info.c */ 1969 static inline struct intel_device_info * 1970 mkwrite_device_info(struct drm_i915_private *dev_priv) 1971 { 1972 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1973 } 1974 1975 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1976 struct drm_file *file); 1977 1978 #define __I915_REG_OP(op__, dev_priv__, ...) \ 1979 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 1980 1981 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 1982 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 1983 1984 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 1985 1986 /* These are untraced mmio-accessors that are only valid to be used inside 1987 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 1988 * controlled. 1989 * 1990 * Think twice, and think again, before using these. 1991 * 1992 * As an example, these accessors can possibly be used between: 1993 * 1994 * spin_lock_irq(&dev_priv->uncore.lock); 1995 * intel_uncore_forcewake_get__locked(); 1996 * 1997 * and 1998 * 1999 * intel_uncore_forcewake_put__locked(); 2000 * spin_unlock_irq(&dev_priv->uncore.lock); 2001 * 2002 * 2003 * Note: some registers may not need forcewake held, so 2004 * intel_uncore_forcewake_{get,put} can be omitted, see 2005 * intel_uncore_forcewake_for_reg(). 2006 * 2007 * Certain architectures will die if the same cacheline is concurrently accessed 2008 * by different clients (e.g. on Ivybridge). Access to registers should 2009 * therefore generally be serialised, by either the dev_priv->uncore.lock or 2010 * a more localised lock guarding all access to that bank of registers. 2011 */ 2012 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 2013 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 2014 2015 /* register wait wrappers for display regs */ 2016 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \ 2017 intel_wait_for_register(&(dev_priv_)->uncore, \ 2018 (reg_), (mask_), (value_), (timeout_)) 2019 2020 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \ 2021 u32 mask__ = (mask_); \ 2022 intel_de_wait_for_register((dev_priv_), (reg_), \ 2023 mask__, mask__, (timeout_)); \ 2024 }) 2025 2026 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ 2027 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_)) 2028 2029 /* i915_mm.c */ 2030 int remap_io_mapping(struct vm_area_struct *vma, 2031 unsigned long addr, unsigned long pfn, unsigned long size, 2032 struct io_mapping *iomap); 2033 2034 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 2035 { 2036 if (INTEL_GEN(i915) >= 10) 2037 return CNL_HWS_CSB_WRITE_INDEX; 2038 else 2039 return I915_HWS_CSB_WRITE_INDEX; 2040 } 2041 2042 static inline enum i915_map_type 2043 i915_coherent_map_type(struct drm_i915_private *i915) 2044 { 2045 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 2046 } 2047 2048 static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc) 2049 { 2050 return intel_guc_is_submission_supported(guc) && 2051 intel_guc_is_running(guc); 2052 } 2053 2054 #endif 2055