1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include "intel_lrc.h" 39 #include "i915_gem_gtt.h" 40 #include "i915_gem_render_state.h" 41 #include <linux/io-mapping.h> 42 #include <linux/i2c.h> 43 #include <linux/i2c-algo-bit.h> 44 #include <drm/intel-gtt.h> 45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 46 #include <drm/drm_gem.h> 47 #include <linux/backlight.h> 48 #include <linux/hashtable.h> 49 #include <linux/intel-iommu.h> 50 #include <linux/kref.h> 51 #include <linux/pm_qos.h> 52 53 /* General customization: 54 */ 55 56 #define DRIVER_NAME "i915" 57 #define DRIVER_DESC "Intel Graphics" 58 #define DRIVER_DATE "20141121" 59 60 #undef WARN_ON 61 #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")") 62 63 enum pipe { 64 INVALID_PIPE = -1, 65 PIPE_A = 0, 66 PIPE_B, 67 PIPE_C, 68 _PIPE_EDP, 69 I915_MAX_PIPES = _PIPE_EDP 70 }; 71 #define pipe_name(p) ((p) + 'A') 72 73 enum transcoder { 74 TRANSCODER_A = 0, 75 TRANSCODER_B, 76 TRANSCODER_C, 77 TRANSCODER_EDP, 78 I915_MAX_TRANSCODERS 79 }; 80 #define transcoder_name(t) ((t) + 'A') 81 82 /* 83 * This is the maximum (across all platforms) number of planes (primary + 84 * sprites) that can be active at the same time on one pipe. 85 * 86 * This value doesn't count the cursor plane. 87 */ 88 #define I915_MAX_PLANES 3 89 90 enum plane { 91 PLANE_A = 0, 92 PLANE_B, 93 PLANE_C, 94 }; 95 #define plane_name(p) ((p) + 'A') 96 97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 98 99 enum port { 100 PORT_A = 0, 101 PORT_B, 102 PORT_C, 103 PORT_D, 104 PORT_E, 105 I915_MAX_PORTS 106 }; 107 #define port_name(p) ((p) + 'A') 108 109 #define I915_NUM_PHYS_VLV 2 110 111 enum dpio_channel { 112 DPIO_CH0, 113 DPIO_CH1 114 }; 115 116 enum dpio_phy { 117 DPIO_PHY0, 118 DPIO_PHY1 119 }; 120 121 enum intel_display_power_domain { 122 POWER_DOMAIN_PIPE_A, 123 POWER_DOMAIN_PIPE_B, 124 POWER_DOMAIN_PIPE_C, 125 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 126 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 127 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 128 POWER_DOMAIN_TRANSCODER_A, 129 POWER_DOMAIN_TRANSCODER_B, 130 POWER_DOMAIN_TRANSCODER_C, 131 POWER_DOMAIN_TRANSCODER_EDP, 132 POWER_DOMAIN_PORT_DDI_A_2_LANES, 133 POWER_DOMAIN_PORT_DDI_A_4_LANES, 134 POWER_DOMAIN_PORT_DDI_B_2_LANES, 135 POWER_DOMAIN_PORT_DDI_B_4_LANES, 136 POWER_DOMAIN_PORT_DDI_C_2_LANES, 137 POWER_DOMAIN_PORT_DDI_C_4_LANES, 138 POWER_DOMAIN_PORT_DDI_D_2_LANES, 139 POWER_DOMAIN_PORT_DDI_D_4_LANES, 140 POWER_DOMAIN_PORT_DSI, 141 POWER_DOMAIN_PORT_CRT, 142 POWER_DOMAIN_PORT_OTHER, 143 POWER_DOMAIN_VGA, 144 POWER_DOMAIN_AUDIO, 145 POWER_DOMAIN_PLLS, 146 POWER_DOMAIN_INIT, 147 148 POWER_DOMAIN_NUM, 149 }; 150 151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 154 #define POWER_DOMAIN_TRANSCODER(tran) \ 155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 156 (tran) + POWER_DOMAIN_TRANSCODER_A) 157 158 enum hpd_pin { 159 HPD_NONE = 0, 160 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 161 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 162 HPD_CRT, 163 HPD_SDVO_B, 164 HPD_SDVO_C, 165 HPD_PORT_B, 166 HPD_PORT_C, 167 HPD_PORT_D, 168 HPD_NUM_PINS 169 }; 170 171 #define I915_GEM_GPU_DOMAINS \ 172 (I915_GEM_DOMAIN_RENDER | \ 173 I915_GEM_DOMAIN_SAMPLER | \ 174 I915_GEM_DOMAIN_COMMAND | \ 175 I915_GEM_DOMAIN_INSTRUCTION | \ 176 I915_GEM_DOMAIN_VERTEX) 177 178 #define for_each_pipe(__dev_priv, __p) \ 179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 180 #define for_each_plane(pipe, p) \ 181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) 182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 183 184 #define for_each_crtc(dev, crtc) \ 185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 186 187 #define for_each_intel_crtc(dev, intel_crtc) \ 188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 189 190 #define for_each_intel_encoder(dev, intel_encoder) \ 191 list_for_each_entry(intel_encoder, \ 192 &(dev)->mode_config.encoder_list, \ 193 base.head) 194 195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 197 if ((intel_encoder)->base.crtc == (__crtc)) 198 199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 201 if ((intel_connector)->base.encoder == (__encoder)) 202 203 #define for_each_power_domain(domain, mask) \ 204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 205 if ((1 << (domain)) & (mask)) 206 207 struct drm_i915_private; 208 struct i915_mm_struct; 209 struct i915_mmu_object; 210 211 enum intel_dpll_id { 212 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 213 /* real shared dpll ids must be >= 0 */ 214 DPLL_ID_PCH_PLL_A = 0, 215 DPLL_ID_PCH_PLL_B = 1, 216 /* hsw/bdw */ 217 DPLL_ID_WRPLL1 = 0, 218 DPLL_ID_WRPLL2 = 1, 219 /* skl */ 220 DPLL_ID_SKL_DPLL1 = 0, 221 DPLL_ID_SKL_DPLL2 = 1, 222 DPLL_ID_SKL_DPLL3 = 2, 223 }; 224 #define I915_NUM_PLLS 3 225 226 struct intel_dpll_hw_state { 227 /* i9xx, pch plls */ 228 uint32_t dpll; 229 uint32_t dpll_md; 230 uint32_t fp0; 231 uint32_t fp1; 232 233 /* hsw, bdw */ 234 uint32_t wrpll; 235 236 /* skl */ 237 /* 238 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 239 * lower part of crtl1 and they get shifted into position when writing 240 * the register. This allows us to easily compare the state to share 241 * the DPLL. 242 */ 243 uint32_t ctrl1; 244 /* HDMI only, 0 when used for DP */ 245 uint32_t cfgcr1, cfgcr2; 246 }; 247 248 struct intel_shared_dpll_config { 249 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ 250 struct intel_dpll_hw_state hw_state; 251 }; 252 253 struct intel_shared_dpll { 254 struct intel_shared_dpll_config config; 255 struct intel_shared_dpll_config *new_config; 256 257 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 258 bool on; /* is the PLL actually active? Disabled during modeset */ 259 const char *name; 260 /* should match the index in the dev_priv->shared_dplls array */ 261 enum intel_dpll_id id; 262 /* The mode_set hook is optional and should be used together with the 263 * intel_prepare_shared_dpll function. */ 264 void (*mode_set)(struct drm_i915_private *dev_priv, 265 struct intel_shared_dpll *pll); 266 void (*enable)(struct drm_i915_private *dev_priv, 267 struct intel_shared_dpll *pll); 268 void (*disable)(struct drm_i915_private *dev_priv, 269 struct intel_shared_dpll *pll); 270 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 271 struct intel_shared_dpll *pll, 272 struct intel_dpll_hw_state *hw_state); 273 }; 274 275 #define SKL_DPLL0 0 276 #define SKL_DPLL1 1 277 #define SKL_DPLL2 2 278 #define SKL_DPLL3 3 279 280 /* Used by dp and fdi links */ 281 struct intel_link_m_n { 282 uint32_t tu; 283 uint32_t gmch_m; 284 uint32_t gmch_n; 285 uint32_t link_m; 286 uint32_t link_n; 287 }; 288 289 void intel_link_compute_m_n(int bpp, int nlanes, 290 int pixel_clock, int link_clock, 291 struct intel_link_m_n *m_n); 292 293 /* Interface history: 294 * 295 * 1.1: Original. 296 * 1.2: Add Power Management 297 * 1.3: Add vblank support 298 * 1.4: Fix cmdbuffer path, add heap destroy 299 * 1.5: Add vblank pipe configuration 300 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 301 * - Support vertical blank on secondary display pipe 302 */ 303 #define DRIVER_MAJOR 1 304 #define DRIVER_MINOR 6 305 #define DRIVER_PATCHLEVEL 0 306 307 #define WATCH_LISTS 0 308 309 struct opregion_header; 310 struct opregion_acpi; 311 struct opregion_swsci; 312 struct opregion_asle; 313 314 struct intel_opregion { 315 struct opregion_header __iomem *header; 316 struct opregion_acpi __iomem *acpi; 317 struct opregion_swsci __iomem *swsci; 318 u32 swsci_gbda_sub_functions; 319 u32 swsci_sbcb_sub_functions; 320 struct opregion_asle __iomem *asle; 321 void __iomem *vbt; 322 u32 __iomem *lid_state; 323 struct work_struct asle_work; 324 }; 325 #define OPREGION_SIZE (8*1024) 326 327 struct intel_overlay; 328 struct intel_overlay_error_state; 329 330 #define I915_FENCE_REG_NONE -1 331 #define I915_MAX_NUM_FENCES 32 332 /* 32 fences + sign bit for FENCE_REG_NONE */ 333 #define I915_MAX_NUM_FENCE_BITS 6 334 335 struct drm_i915_fence_reg { 336 struct list_head lru_list; 337 struct drm_i915_gem_object *obj; 338 int pin_count; 339 }; 340 341 struct sdvo_device_mapping { 342 u8 initialized; 343 u8 dvo_port; 344 u8 slave_addr; 345 u8 dvo_wiring; 346 u8 i2c_pin; 347 u8 ddc_pin; 348 }; 349 350 struct intel_display_error_state; 351 352 struct drm_i915_error_state { 353 struct kref ref; 354 struct timeval time; 355 356 char error_msg[128]; 357 u32 reset_count; 358 u32 suspend_count; 359 360 /* Generic register state */ 361 u32 eir; 362 u32 pgtbl_er; 363 u32 ier; 364 u32 gtier[4]; 365 u32 ccid; 366 u32 derrmr; 367 u32 forcewake; 368 u32 error; /* gen6+ */ 369 u32 err_int; /* gen7 */ 370 u32 done_reg; 371 u32 gac_eco; 372 u32 gam_ecochk; 373 u32 gab_ctl; 374 u32 gfx_mode; 375 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 376 u64 fence[I915_MAX_NUM_FENCES]; 377 struct intel_overlay_error_state *overlay; 378 struct intel_display_error_state *display; 379 struct drm_i915_error_object *semaphore_obj; 380 381 struct drm_i915_error_ring { 382 bool valid; 383 /* Software tracked state */ 384 bool waiting; 385 int hangcheck_score; 386 enum intel_ring_hangcheck_action hangcheck_action; 387 int num_requests; 388 389 /* our own tracking of ring head and tail */ 390 u32 cpu_ring_head; 391 u32 cpu_ring_tail; 392 393 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 394 395 /* Register state */ 396 u32 tail; 397 u32 head; 398 u32 ctl; 399 u32 hws; 400 u32 ipeir; 401 u32 ipehr; 402 u32 instdone; 403 u32 bbstate; 404 u32 instpm; 405 u32 instps; 406 u32 seqno; 407 u64 bbaddr; 408 u64 acthd; 409 u32 fault_reg; 410 u64 faddr; 411 u32 rc_psmi; /* sleep state */ 412 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 413 414 struct drm_i915_error_object { 415 int page_count; 416 u32 gtt_offset; 417 u32 *pages[0]; 418 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 419 420 struct drm_i915_error_request { 421 long jiffies; 422 u32 seqno; 423 u32 tail; 424 } *requests; 425 426 struct { 427 u32 gfx_mode; 428 union { 429 u64 pdp[4]; 430 u32 pp_dir_base; 431 }; 432 } vm_info; 433 434 pid_t pid; 435 char comm[TASK_COMM_LEN]; 436 } ring[I915_NUM_RINGS]; 437 438 struct drm_i915_error_buffer { 439 u32 size; 440 u32 name; 441 u32 rseqno, wseqno; 442 u32 gtt_offset; 443 u32 read_domains; 444 u32 write_domain; 445 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 446 s32 pinned:2; 447 u32 tiling:2; 448 u32 dirty:1; 449 u32 purgeable:1; 450 u32 userptr:1; 451 s32 ring:4; 452 u32 cache_level:3; 453 } **active_bo, **pinned_bo; 454 455 u32 *active_bo_count, *pinned_bo_count; 456 u32 vm_count; 457 }; 458 459 struct intel_connector; 460 struct intel_encoder; 461 struct intel_crtc_config; 462 struct intel_plane_config; 463 struct intel_crtc; 464 struct intel_limit; 465 struct dpll; 466 467 struct drm_i915_display_funcs { 468 bool (*fbc_enabled)(struct drm_device *dev); 469 void (*enable_fbc)(struct drm_crtc *crtc); 470 void (*disable_fbc)(struct drm_device *dev); 471 int (*get_display_clock_speed)(struct drm_device *dev); 472 int (*get_fifo_size)(struct drm_device *dev, int plane); 473 /** 474 * find_dpll() - Find the best values for the PLL 475 * @limit: limits for the PLL 476 * @crtc: current CRTC 477 * @target: target frequency in kHz 478 * @refclk: reference clock frequency in kHz 479 * @match_clock: if provided, @best_clock P divider must 480 * match the P divider from @match_clock 481 * used for LVDS downclocking 482 * @best_clock: best PLL values found 483 * 484 * Returns true on success, false on failure. 485 */ 486 bool (*find_dpll)(const struct intel_limit *limit, 487 struct intel_crtc *crtc, 488 int target, int refclk, 489 struct dpll *match_clock, 490 struct dpll *best_clock); 491 void (*update_wm)(struct drm_crtc *crtc); 492 void (*update_sprite_wm)(struct drm_plane *plane, 493 struct drm_crtc *crtc, 494 uint32_t sprite_width, uint32_t sprite_height, 495 int pixel_size, bool enable, bool scaled); 496 void (*modeset_global_resources)(struct drm_device *dev); 497 /* Returns the active state of the crtc, and if the crtc is active, 498 * fills out the pipe-config with the hw state. */ 499 bool (*get_pipe_config)(struct intel_crtc *, 500 struct intel_crtc_config *); 501 void (*get_plane_config)(struct intel_crtc *, 502 struct intel_plane_config *); 503 int (*crtc_compute_clock)(struct intel_crtc *crtc); 504 void (*crtc_enable)(struct drm_crtc *crtc); 505 void (*crtc_disable)(struct drm_crtc *crtc); 506 void (*off)(struct drm_crtc *crtc); 507 void (*audio_codec_enable)(struct drm_connector *connector, 508 struct intel_encoder *encoder, 509 struct drm_display_mode *mode); 510 void (*audio_codec_disable)(struct intel_encoder *encoder); 511 void (*fdi_link_train)(struct drm_crtc *crtc); 512 void (*init_clock_gating)(struct drm_device *dev); 513 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 514 struct drm_framebuffer *fb, 515 struct drm_i915_gem_object *obj, 516 struct intel_engine_cs *ring, 517 uint32_t flags); 518 void (*update_primary_plane)(struct drm_crtc *crtc, 519 struct drm_framebuffer *fb, 520 int x, int y); 521 void (*hpd_irq_setup)(struct drm_device *dev); 522 /* clock updates for mode set */ 523 /* cursor updates */ 524 /* render clock increase/decrease */ 525 /* display clock increase/decrease */ 526 /* pll clock increase/decrease */ 527 528 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); 529 uint32_t (*get_backlight)(struct intel_connector *connector); 530 void (*set_backlight)(struct intel_connector *connector, 531 uint32_t level); 532 void (*disable_backlight)(struct intel_connector *connector); 533 void (*enable_backlight)(struct intel_connector *connector); 534 }; 535 536 struct intel_uncore_funcs { 537 void (*force_wake_get)(struct drm_i915_private *dev_priv, 538 int fw_engine); 539 void (*force_wake_put)(struct drm_i915_private *dev_priv, 540 int fw_engine); 541 542 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 543 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 544 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 545 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 546 547 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 548 uint8_t val, bool trace); 549 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 550 uint16_t val, bool trace); 551 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 552 uint32_t val, bool trace); 553 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 554 uint64_t val, bool trace); 555 }; 556 557 struct intel_uncore { 558 spinlock_t lock; /** lock is also taken in irq contexts. */ 559 560 struct intel_uncore_funcs funcs; 561 562 unsigned fifo_count; 563 unsigned forcewake_count; 564 565 unsigned fw_rendercount; 566 unsigned fw_mediacount; 567 unsigned fw_blittercount; 568 569 struct timer_list force_wake_timer; 570 }; 571 572 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 573 func(is_mobile) sep \ 574 func(is_i85x) sep \ 575 func(is_i915g) sep \ 576 func(is_i945gm) sep \ 577 func(is_g33) sep \ 578 func(need_gfx_hws) sep \ 579 func(is_g4x) sep \ 580 func(is_pineview) sep \ 581 func(is_broadwater) sep \ 582 func(is_crestline) sep \ 583 func(is_ivybridge) sep \ 584 func(is_valleyview) sep \ 585 func(is_haswell) sep \ 586 func(is_skylake) sep \ 587 func(is_preliminary) sep \ 588 func(has_fbc) sep \ 589 func(has_pipe_cxsr) sep \ 590 func(has_hotplug) sep \ 591 func(cursor_needs_physical) sep \ 592 func(has_overlay) sep \ 593 func(overlay_needs_physical) sep \ 594 func(supports_tv) sep \ 595 func(has_llc) sep \ 596 func(has_ddi) sep \ 597 func(has_fpga_dbg) 598 599 #define DEFINE_FLAG(name) u8 name:1 600 #define SEP_SEMICOLON ; 601 602 struct intel_device_info { 603 u32 display_mmio_offset; 604 u16 device_id; 605 u8 num_pipes:3; 606 u8 num_sprites[I915_MAX_PIPES]; 607 u8 gen; 608 u8 ring_mask; /* Rings supported by the HW */ 609 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 610 /* Register offsets for the various display pipes and transcoders */ 611 int pipe_offsets[I915_MAX_TRANSCODERS]; 612 int trans_offsets[I915_MAX_TRANSCODERS]; 613 int palette_offsets[I915_MAX_PIPES]; 614 int cursor_offsets[I915_MAX_PIPES]; 615 }; 616 617 #undef DEFINE_FLAG 618 #undef SEP_SEMICOLON 619 620 enum i915_cache_level { 621 I915_CACHE_NONE = 0, 622 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 623 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 624 caches, eg sampler/render caches, and the 625 large Last-Level-Cache. LLC is coherent with 626 the CPU, but L3 is only visible to the GPU. */ 627 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 628 }; 629 630 struct i915_ctx_hang_stats { 631 /* This context had batch pending when hang was declared */ 632 unsigned batch_pending; 633 634 /* This context had batch active when hang was declared */ 635 unsigned batch_active; 636 637 /* Time when this context was last blamed for a GPU reset */ 638 unsigned long guilty_ts; 639 640 /* This context is banned to submit more work */ 641 bool banned; 642 }; 643 644 /* This must match up with the value previously used for execbuf2.rsvd1. */ 645 #define DEFAULT_CONTEXT_HANDLE 0 646 /** 647 * struct intel_context - as the name implies, represents a context. 648 * @ref: reference count. 649 * @user_handle: userspace tracking identity for this context. 650 * @remap_slice: l3 row remapping information. 651 * @file_priv: filp associated with this context (NULL for global default 652 * context). 653 * @hang_stats: information about the role of this context in possible GPU 654 * hangs. 655 * @vm: virtual memory space used by this context. 656 * @legacy_hw_ctx: render context backing object and whether it is correctly 657 * initialized (legacy ring submission mechanism only). 658 * @link: link in the global list of contexts. 659 * 660 * Contexts are memory images used by the hardware to store copies of their 661 * internal state. 662 */ 663 struct intel_context { 664 struct kref ref; 665 int user_handle; 666 uint8_t remap_slice; 667 struct drm_i915_file_private *file_priv; 668 struct i915_ctx_hang_stats hang_stats; 669 struct i915_hw_ppgtt *ppgtt; 670 671 /* Legacy ring buffer submission */ 672 struct { 673 struct drm_i915_gem_object *rcs_state; 674 bool initialized; 675 } legacy_hw_ctx; 676 677 /* Execlists */ 678 bool rcs_initialized; 679 struct { 680 struct drm_i915_gem_object *state; 681 struct intel_ringbuffer *ringbuf; 682 int unpin_count; 683 } engine[I915_NUM_RINGS]; 684 685 struct list_head link; 686 }; 687 688 struct i915_fbc { 689 unsigned long size; 690 unsigned threshold; 691 unsigned int fb_id; 692 enum plane plane; 693 int y; 694 695 struct drm_mm_node compressed_fb; 696 struct drm_mm_node *compressed_llb; 697 698 bool false_color; 699 700 /* Tracks whether the HW is actually enabled, not whether the feature is 701 * possible. */ 702 bool enabled; 703 704 /* On gen8 some rings cannont perform fbc clean operation so for now 705 * we are doing this on SW with mmio. 706 * This variable works in the opposite information direction 707 * of ring->fbc_dirty telling software on frontbuffer tracking 708 * to perform the cache clean on sw side. 709 */ 710 bool need_sw_cache_clean; 711 712 struct intel_fbc_work { 713 struct delayed_work work; 714 struct drm_crtc *crtc; 715 struct drm_framebuffer *fb; 716 } *fbc_work; 717 718 enum no_fbc_reason { 719 FBC_OK, /* FBC is enabled */ 720 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 721 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 722 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 723 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 724 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 725 FBC_BAD_PLANE, /* fbc not supported on plane */ 726 FBC_NOT_TILED, /* buffer not tiled */ 727 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 728 FBC_MODULE_PARAM, 729 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 730 } no_fbc_reason; 731 }; 732 733 struct i915_drrs { 734 struct intel_connector *connector; 735 }; 736 737 struct intel_dp; 738 struct i915_psr { 739 struct mutex lock; 740 bool sink_support; 741 bool source_ok; 742 struct intel_dp *enabled; 743 bool active; 744 struct delayed_work work; 745 unsigned busy_frontbuffer_bits; 746 }; 747 748 enum intel_pch { 749 PCH_NONE = 0, /* No PCH present */ 750 PCH_IBX, /* Ibexpeak PCH */ 751 PCH_CPT, /* Cougarpoint PCH */ 752 PCH_LPT, /* Lynxpoint PCH */ 753 PCH_SPT, /* Sunrisepoint PCH */ 754 PCH_NOP, 755 }; 756 757 enum intel_sbi_destination { 758 SBI_ICLK, 759 SBI_MPHY, 760 }; 761 762 #define QUIRK_PIPEA_FORCE (1<<0) 763 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 764 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 765 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 766 #define QUIRK_PIPEB_FORCE (1<<4) 767 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 768 769 struct intel_fbdev; 770 struct intel_fbc_work; 771 772 struct intel_gmbus { 773 struct i2c_adapter adapter; 774 u32 force_bit; 775 u32 reg0; 776 u32 gpio_reg; 777 struct i2c_algo_bit_data bit_algo; 778 struct drm_i915_private *dev_priv; 779 }; 780 781 struct i915_suspend_saved_registers { 782 u8 saveLBB; 783 u32 saveDSPACNTR; 784 u32 saveDSPBCNTR; 785 u32 saveDSPARB; 786 u32 savePIPEACONF; 787 u32 savePIPEBCONF; 788 u32 savePIPEASRC; 789 u32 savePIPEBSRC; 790 u32 saveFPA0; 791 u32 saveFPA1; 792 u32 saveDPLL_A; 793 u32 saveDPLL_A_MD; 794 u32 saveHTOTAL_A; 795 u32 saveHBLANK_A; 796 u32 saveHSYNC_A; 797 u32 saveVTOTAL_A; 798 u32 saveVBLANK_A; 799 u32 saveVSYNC_A; 800 u32 saveBCLRPAT_A; 801 u32 saveTRANSACONF; 802 u32 saveTRANS_HTOTAL_A; 803 u32 saveTRANS_HBLANK_A; 804 u32 saveTRANS_HSYNC_A; 805 u32 saveTRANS_VTOTAL_A; 806 u32 saveTRANS_VBLANK_A; 807 u32 saveTRANS_VSYNC_A; 808 u32 savePIPEASTAT; 809 u32 saveDSPASTRIDE; 810 u32 saveDSPASIZE; 811 u32 saveDSPAPOS; 812 u32 saveDSPAADDR; 813 u32 saveDSPASURF; 814 u32 saveDSPATILEOFF; 815 u32 savePFIT_PGM_RATIOS; 816 u32 saveBLC_HIST_CTL; 817 u32 saveBLC_PWM_CTL; 818 u32 saveBLC_PWM_CTL2; 819 u32 saveBLC_CPU_PWM_CTL; 820 u32 saveBLC_CPU_PWM_CTL2; 821 u32 saveFPB0; 822 u32 saveFPB1; 823 u32 saveDPLL_B; 824 u32 saveDPLL_B_MD; 825 u32 saveHTOTAL_B; 826 u32 saveHBLANK_B; 827 u32 saveHSYNC_B; 828 u32 saveVTOTAL_B; 829 u32 saveVBLANK_B; 830 u32 saveVSYNC_B; 831 u32 saveBCLRPAT_B; 832 u32 saveTRANSBCONF; 833 u32 saveTRANS_HTOTAL_B; 834 u32 saveTRANS_HBLANK_B; 835 u32 saveTRANS_HSYNC_B; 836 u32 saveTRANS_VTOTAL_B; 837 u32 saveTRANS_VBLANK_B; 838 u32 saveTRANS_VSYNC_B; 839 u32 savePIPEBSTAT; 840 u32 saveDSPBSTRIDE; 841 u32 saveDSPBSIZE; 842 u32 saveDSPBPOS; 843 u32 saveDSPBADDR; 844 u32 saveDSPBSURF; 845 u32 saveDSPBTILEOFF; 846 u32 saveVGA0; 847 u32 saveVGA1; 848 u32 saveVGA_PD; 849 u32 saveVGACNTRL; 850 u32 saveADPA; 851 u32 saveLVDS; 852 u32 savePP_ON_DELAYS; 853 u32 savePP_OFF_DELAYS; 854 u32 saveDVOA; 855 u32 saveDVOB; 856 u32 saveDVOC; 857 u32 savePP_ON; 858 u32 savePP_OFF; 859 u32 savePP_CONTROL; 860 u32 savePP_DIVISOR; 861 u32 savePFIT_CONTROL; 862 u32 save_palette_a[256]; 863 u32 save_palette_b[256]; 864 u32 saveFBC_CONTROL; 865 u32 saveIER; 866 u32 saveIIR; 867 u32 saveIMR; 868 u32 saveDEIER; 869 u32 saveDEIMR; 870 u32 saveGTIER; 871 u32 saveGTIMR; 872 u32 saveFDI_RXA_IMR; 873 u32 saveFDI_RXB_IMR; 874 u32 saveCACHE_MODE_0; 875 u32 saveMI_ARB_STATE; 876 u32 saveSWF0[16]; 877 u32 saveSWF1[16]; 878 u32 saveSWF2[3]; 879 u8 saveMSR; 880 u8 saveSR[8]; 881 u8 saveGR[25]; 882 u8 saveAR_INDEX; 883 u8 saveAR[21]; 884 u8 saveDACMASK; 885 u8 saveCR[37]; 886 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 887 u32 saveCURACNTR; 888 u32 saveCURAPOS; 889 u32 saveCURABASE; 890 u32 saveCURBCNTR; 891 u32 saveCURBPOS; 892 u32 saveCURBBASE; 893 u32 saveCURSIZE; 894 u32 saveDP_B; 895 u32 saveDP_C; 896 u32 saveDP_D; 897 u32 savePIPEA_GMCH_DATA_M; 898 u32 savePIPEB_GMCH_DATA_M; 899 u32 savePIPEA_GMCH_DATA_N; 900 u32 savePIPEB_GMCH_DATA_N; 901 u32 savePIPEA_DP_LINK_M; 902 u32 savePIPEB_DP_LINK_M; 903 u32 savePIPEA_DP_LINK_N; 904 u32 savePIPEB_DP_LINK_N; 905 u32 saveFDI_RXA_CTL; 906 u32 saveFDI_TXA_CTL; 907 u32 saveFDI_RXB_CTL; 908 u32 saveFDI_TXB_CTL; 909 u32 savePFA_CTL_1; 910 u32 savePFB_CTL_1; 911 u32 savePFA_WIN_SZ; 912 u32 savePFB_WIN_SZ; 913 u32 savePFA_WIN_POS; 914 u32 savePFB_WIN_POS; 915 u32 savePCH_DREF_CONTROL; 916 u32 saveDISP_ARB_CTL; 917 u32 savePIPEA_DATA_M1; 918 u32 savePIPEA_DATA_N1; 919 u32 savePIPEA_LINK_M1; 920 u32 savePIPEA_LINK_N1; 921 u32 savePIPEB_DATA_M1; 922 u32 savePIPEB_DATA_N1; 923 u32 savePIPEB_LINK_M1; 924 u32 savePIPEB_LINK_N1; 925 u32 saveMCHBAR_RENDER_STANDBY; 926 u32 savePCH_PORT_HOTPLUG; 927 u16 saveGCDGMBUS; 928 }; 929 930 struct vlv_s0ix_state { 931 /* GAM */ 932 u32 wr_watermark; 933 u32 gfx_prio_ctrl; 934 u32 arb_mode; 935 u32 gfx_pend_tlb0; 936 u32 gfx_pend_tlb1; 937 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 938 u32 media_max_req_count; 939 u32 gfx_max_req_count; 940 u32 render_hwsp; 941 u32 ecochk; 942 u32 bsd_hwsp; 943 u32 blt_hwsp; 944 u32 tlb_rd_addr; 945 946 /* MBC */ 947 u32 g3dctl; 948 u32 gsckgctl; 949 u32 mbctl; 950 951 /* GCP */ 952 u32 ucgctl1; 953 u32 ucgctl3; 954 u32 rcgctl1; 955 u32 rcgctl2; 956 u32 rstctl; 957 u32 misccpctl; 958 959 /* GPM */ 960 u32 gfxpause; 961 u32 rpdeuhwtc; 962 u32 rpdeuc; 963 u32 ecobus; 964 u32 pwrdwnupctl; 965 u32 rp_down_timeout; 966 u32 rp_deucsw; 967 u32 rcubmabdtmr; 968 u32 rcedata; 969 u32 spare2gh; 970 971 /* Display 1 CZ domain */ 972 u32 gt_imr; 973 u32 gt_ier; 974 u32 pm_imr; 975 u32 pm_ier; 976 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 977 978 /* GT SA CZ domain */ 979 u32 tilectl; 980 u32 gt_fifoctl; 981 u32 gtlc_wake_ctrl; 982 u32 gtlc_survive; 983 u32 pmwgicz; 984 985 /* Display 2 CZ domain */ 986 u32 gu_ctl0; 987 u32 gu_ctl1; 988 u32 clock_gate_dis2; 989 }; 990 991 struct intel_rps_ei { 992 u32 cz_clock; 993 u32 render_c0; 994 u32 media_c0; 995 }; 996 997 struct intel_gen6_power_mgmt { 998 /* 999 * work, interrupts_enabled and pm_iir are protected by 1000 * dev_priv->irq_lock 1001 */ 1002 struct work_struct work; 1003 bool interrupts_enabled; 1004 u32 pm_iir; 1005 1006 /* Frequencies are stored in potentially platform dependent multiples. 1007 * In other words, *_freq needs to be multiplied by X to be interesting. 1008 * Soft limits are those which are used for the dynamic reclocking done 1009 * by the driver (raise frequencies under heavy loads, and lower for 1010 * lighter loads). Hard limits are those imposed by the hardware. 1011 * 1012 * A distinction is made for overclocking, which is never enabled by 1013 * default, and is considered to be above the hard limit if it's 1014 * possible at all. 1015 */ 1016 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 1017 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 1018 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 1019 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 1020 u8 min_freq; /* AKA RPn. Minimum frequency */ 1021 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 1022 u8 rp1_freq; /* "less than" RP0 power/freqency */ 1023 u8 rp0_freq; /* Non-overclocked max frequency. */ 1024 u32 cz_freq; 1025 1026 u32 ei_interrupt_count; 1027 1028 int last_adj; 1029 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 1030 1031 bool enabled; 1032 struct delayed_work delayed_resume_work; 1033 1034 /* manual wa residency calculations */ 1035 struct intel_rps_ei up_ei, down_ei; 1036 1037 /* 1038 * Protects RPS/RC6 register access and PCU communication. 1039 * Must be taken after struct_mutex if nested. 1040 */ 1041 struct mutex hw_lock; 1042 }; 1043 1044 /* defined intel_pm.c */ 1045 extern spinlock_t mchdev_lock; 1046 1047 struct intel_ilk_power_mgmt { 1048 u8 cur_delay; 1049 u8 min_delay; 1050 u8 max_delay; 1051 u8 fmax; 1052 u8 fstart; 1053 1054 u64 last_count1; 1055 unsigned long last_time1; 1056 unsigned long chipset_power; 1057 u64 last_count2; 1058 u64 last_time2; 1059 unsigned long gfx_power; 1060 u8 corr; 1061 1062 int c_m; 1063 int r_t; 1064 1065 struct drm_i915_gem_object *pwrctx; 1066 struct drm_i915_gem_object *renderctx; 1067 }; 1068 1069 struct drm_i915_private; 1070 struct i915_power_well; 1071 1072 struct i915_power_well_ops { 1073 /* 1074 * Synchronize the well's hw state to match the current sw state, for 1075 * example enable/disable it based on the current refcount. Called 1076 * during driver init and resume time, possibly after first calling 1077 * the enable/disable handlers. 1078 */ 1079 void (*sync_hw)(struct drm_i915_private *dev_priv, 1080 struct i915_power_well *power_well); 1081 /* 1082 * Enable the well and resources that depend on it (for example 1083 * interrupts located on the well). Called after the 0->1 refcount 1084 * transition. 1085 */ 1086 void (*enable)(struct drm_i915_private *dev_priv, 1087 struct i915_power_well *power_well); 1088 /* 1089 * Disable the well and resources that depend on it. Called after 1090 * the 1->0 refcount transition. 1091 */ 1092 void (*disable)(struct drm_i915_private *dev_priv, 1093 struct i915_power_well *power_well); 1094 /* Returns the hw enabled state. */ 1095 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1096 struct i915_power_well *power_well); 1097 }; 1098 1099 /* Power well structure for haswell */ 1100 struct i915_power_well { 1101 const char *name; 1102 bool always_on; 1103 /* power well enable/disable usage count */ 1104 int count; 1105 /* cached hw enabled state */ 1106 bool hw_enabled; 1107 unsigned long domains; 1108 unsigned long data; 1109 const struct i915_power_well_ops *ops; 1110 }; 1111 1112 struct i915_power_domains { 1113 /* 1114 * Power wells needed for initialization at driver init and suspend 1115 * time are on. They are kept on until after the first modeset. 1116 */ 1117 bool init_power_on; 1118 bool initializing; 1119 int power_well_count; 1120 1121 struct mutex lock; 1122 int domain_use_count[POWER_DOMAIN_NUM]; 1123 struct i915_power_well *power_wells; 1124 }; 1125 1126 #define MAX_L3_SLICES 2 1127 struct intel_l3_parity { 1128 u32 *remap_info[MAX_L3_SLICES]; 1129 struct work_struct error_work; 1130 int which_slice; 1131 }; 1132 1133 struct i915_gem_mm { 1134 /** Memory allocator for GTT stolen memory */ 1135 struct drm_mm stolen; 1136 /** List of all objects in gtt_space. Used to restore gtt 1137 * mappings on resume */ 1138 struct list_head bound_list; 1139 /** 1140 * List of objects which are not bound to the GTT (thus 1141 * are idle and not used by the GPU) but still have 1142 * (presumably uncached) pages still attached. 1143 */ 1144 struct list_head unbound_list; 1145 1146 /** Usable portion of the GTT for GEM */ 1147 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1148 1149 /** PPGTT used for aliasing the PPGTT with the GTT */ 1150 struct i915_hw_ppgtt *aliasing_ppgtt; 1151 1152 struct notifier_block oom_notifier; 1153 struct shrinker shrinker; 1154 bool shrinker_no_lock_stealing; 1155 1156 /** LRU list of objects with fence regs on them. */ 1157 struct list_head fence_list; 1158 1159 /** 1160 * We leave the user IRQ off as much as possible, 1161 * but this means that requests will finish and never 1162 * be retired once the system goes idle. Set a timer to 1163 * fire periodically while the ring is running. When it 1164 * fires, go retire requests. 1165 */ 1166 struct delayed_work retire_work; 1167 1168 /** 1169 * When we detect an idle GPU, we want to turn on 1170 * powersaving features. So once we see that there 1171 * are no more requests outstanding and no more 1172 * arrive within a small period of time, we fire 1173 * off the idle_work. 1174 */ 1175 struct delayed_work idle_work; 1176 1177 /** 1178 * Are we in a non-interruptible section of code like 1179 * modesetting? 1180 */ 1181 bool interruptible; 1182 1183 /** 1184 * Is the GPU currently considered idle, or busy executing userspace 1185 * requests? Whilst idle, we attempt to power down the hardware and 1186 * display clocks. In order to reduce the effect on performance, there 1187 * is a slight delay before we do so. 1188 */ 1189 bool busy; 1190 1191 /* the indicator for dispatch video commands on two BSD rings */ 1192 int bsd_ring_dispatch_index; 1193 1194 /** Bit 6 swizzling required for X tiling */ 1195 uint32_t bit_6_swizzle_x; 1196 /** Bit 6 swizzling required for Y tiling */ 1197 uint32_t bit_6_swizzle_y; 1198 1199 /* accounting, useful for userland debugging */ 1200 spinlock_t object_stat_lock; 1201 size_t object_memory; 1202 u32 object_count; 1203 }; 1204 1205 struct drm_i915_error_state_buf { 1206 struct drm_i915_private *i915; 1207 unsigned bytes; 1208 unsigned size; 1209 int err; 1210 u8 *buf; 1211 loff_t start; 1212 loff_t pos; 1213 }; 1214 1215 struct i915_error_state_file_priv { 1216 struct drm_device *dev; 1217 struct drm_i915_error_state *error; 1218 }; 1219 1220 struct i915_gpu_error { 1221 /* For hangcheck timer */ 1222 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1223 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1224 /* Hang gpu twice in this window and your context gets banned */ 1225 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1226 1227 struct timer_list hangcheck_timer; 1228 1229 /* For reset and error_state handling. */ 1230 spinlock_t lock; 1231 /* Protected by the above dev->gpu_error.lock. */ 1232 struct drm_i915_error_state *first_error; 1233 struct work_struct work; 1234 1235 1236 unsigned long missed_irq_rings; 1237 1238 /** 1239 * State variable controlling the reset flow and count 1240 * 1241 * This is a counter which gets incremented when reset is triggered, 1242 * and again when reset has been handled. So odd values (lowest bit set) 1243 * means that reset is in progress and even values that 1244 * (reset_counter >> 1):th reset was successfully completed. 1245 * 1246 * If reset is not completed succesfully, the I915_WEDGE bit is 1247 * set meaning that hardware is terminally sour and there is no 1248 * recovery. All waiters on the reset_queue will be woken when 1249 * that happens. 1250 * 1251 * This counter is used by the wait_seqno code to notice that reset 1252 * event happened and it needs to restart the entire ioctl (since most 1253 * likely the seqno it waited for won't ever signal anytime soon). 1254 * 1255 * This is important for lock-free wait paths, where no contended lock 1256 * naturally enforces the correct ordering between the bail-out of the 1257 * waiter and the gpu reset work code. 1258 */ 1259 atomic_t reset_counter; 1260 1261 #define I915_RESET_IN_PROGRESS_FLAG 1 1262 #define I915_WEDGED (1 << 31) 1263 1264 /** 1265 * Waitqueue to signal when the reset has completed. Used by clients 1266 * that wait for dev_priv->mm.wedged to settle. 1267 */ 1268 wait_queue_head_t reset_queue; 1269 1270 /* Userspace knobs for gpu hang simulation; 1271 * combines both a ring mask, and extra flags 1272 */ 1273 u32 stop_rings; 1274 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1275 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1276 1277 /* For missed irq/seqno simulation. */ 1278 unsigned int test_irq_rings; 1279 1280 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 1281 bool reload_in_reset; 1282 }; 1283 1284 enum modeset_restore { 1285 MODESET_ON_LID_OPEN, 1286 MODESET_DONE, 1287 MODESET_SUSPENDED, 1288 }; 1289 1290 struct ddi_vbt_port_info { 1291 /* 1292 * This is an index in the HDMI/DVI DDI buffer translation table. 1293 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1294 * populate this field. 1295 */ 1296 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1297 uint8_t hdmi_level_shift; 1298 1299 uint8_t supports_dvi:1; 1300 uint8_t supports_hdmi:1; 1301 uint8_t supports_dp:1; 1302 }; 1303 1304 enum drrs_support_type { 1305 DRRS_NOT_SUPPORTED = 0, 1306 STATIC_DRRS_SUPPORT = 1, 1307 SEAMLESS_DRRS_SUPPORT = 2 1308 }; 1309 1310 struct intel_vbt_data { 1311 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1312 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1313 1314 /* Feature bits */ 1315 unsigned int int_tv_support:1; 1316 unsigned int lvds_dither:1; 1317 unsigned int lvds_vbt:1; 1318 unsigned int int_crt_support:1; 1319 unsigned int lvds_use_ssc:1; 1320 unsigned int display_clock_mode:1; 1321 unsigned int fdi_rx_polarity_inverted:1; 1322 unsigned int has_mipi:1; 1323 int lvds_ssc_freq; 1324 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1325 1326 enum drrs_support_type drrs_type; 1327 1328 /* eDP */ 1329 int edp_rate; 1330 int edp_lanes; 1331 int edp_preemphasis; 1332 int edp_vswing; 1333 bool edp_initialized; 1334 bool edp_support; 1335 int edp_bpp; 1336 struct edp_power_seq edp_pps; 1337 1338 struct { 1339 u16 pwm_freq_hz; 1340 bool present; 1341 bool active_low_pwm; 1342 u8 min_brightness; /* min_brightness/255 of max */ 1343 } backlight; 1344 1345 /* MIPI DSI */ 1346 struct { 1347 u16 port; 1348 u16 panel_id; 1349 struct mipi_config *config; 1350 struct mipi_pps_data *pps; 1351 u8 seq_version; 1352 u32 size; 1353 u8 *data; 1354 u8 *sequence[MIPI_SEQ_MAX]; 1355 } dsi; 1356 1357 int crt_ddc_pin; 1358 1359 int child_dev_num; 1360 union child_device_config *child_dev; 1361 1362 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1363 }; 1364 1365 enum intel_ddb_partitioning { 1366 INTEL_DDB_PART_1_2, 1367 INTEL_DDB_PART_5_6, /* IVB+ */ 1368 }; 1369 1370 struct intel_wm_level { 1371 bool enable; 1372 uint32_t pri_val; 1373 uint32_t spr_val; 1374 uint32_t cur_val; 1375 uint32_t fbc_val; 1376 }; 1377 1378 struct ilk_wm_values { 1379 uint32_t wm_pipe[3]; 1380 uint32_t wm_lp[3]; 1381 uint32_t wm_lp_spr[3]; 1382 uint32_t wm_linetime[3]; 1383 bool enable_fbc_wm; 1384 enum intel_ddb_partitioning partitioning; 1385 }; 1386 1387 struct skl_ddb_entry { 1388 uint16_t start, end; /* in number of blocks, 'end' is exclusive */ 1389 }; 1390 1391 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) 1392 { 1393 return entry->end - entry->start; 1394 } 1395 1396 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 1397 const struct skl_ddb_entry *e2) 1398 { 1399 if (e1->start == e2->start && e1->end == e2->end) 1400 return true; 1401 1402 return false; 1403 } 1404 1405 struct skl_ddb_allocation { 1406 struct skl_ddb_entry pipe[I915_MAX_PIPES]; 1407 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; 1408 struct skl_ddb_entry cursor[I915_MAX_PIPES]; 1409 }; 1410 1411 struct skl_wm_values { 1412 bool dirty[I915_MAX_PIPES]; 1413 struct skl_ddb_allocation ddb; 1414 uint32_t wm_linetime[I915_MAX_PIPES]; 1415 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; 1416 uint32_t cursor[I915_MAX_PIPES][8]; 1417 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; 1418 uint32_t cursor_trans[I915_MAX_PIPES]; 1419 }; 1420 1421 struct skl_wm_level { 1422 bool plane_en[I915_MAX_PLANES]; 1423 bool cursor_en; 1424 uint16_t plane_res_b[I915_MAX_PLANES]; 1425 uint8_t plane_res_l[I915_MAX_PLANES]; 1426 uint16_t cursor_res_b; 1427 uint8_t cursor_res_l; 1428 }; 1429 1430 /* 1431 * This struct helps tracking the state needed for runtime PM, which puts the 1432 * device in PCI D3 state. Notice that when this happens, nothing on the 1433 * graphics device works, even register access, so we don't get interrupts nor 1434 * anything else. 1435 * 1436 * Every piece of our code that needs to actually touch the hardware needs to 1437 * either call intel_runtime_pm_get or call intel_display_power_get with the 1438 * appropriate power domain. 1439 * 1440 * Our driver uses the autosuspend delay feature, which means we'll only really 1441 * suspend if we stay with zero refcount for a certain amount of time. The 1442 * default value is currently very conservative (see intel_runtime_pm_enable), but 1443 * it can be changed with the standard runtime PM files from sysfs. 1444 * 1445 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1446 * goes back to false exactly before we reenable the IRQs. We use this variable 1447 * to check if someone is trying to enable/disable IRQs while they're supposed 1448 * to be disabled. This shouldn't happen and we'll print some error messages in 1449 * case it happens. 1450 * 1451 * For more, read the Documentation/power/runtime_pm.txt. 1452 */ 1453 struct i915_runtime_pm { 1454 bool suspended; 1455 bool irqs_enabled; 1456 }; 1457 1458 enum intel_pipe_crc_source { 1459 INTEL_PIPE_CRC_SOURCE_NONE, 1460 INTEL_PIPE_CRC_SOURCE_PLANE1, 1461 INTEL_PIPE_CRC_SOURCE_PLANE2, 1462 INTEL_PIPE_CRC_SOURCE_PF, 1463 INTEL_PIPE_CRC_SOURCE_PIPE, 1464 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1465 INTEL_PIPE_CRC_SOURCE_TV, 1466 INTEL_PIPE_CRC_SOURCE_DP_B, 1467 INTEL_PIPE_CRC_SOURCE_DP_C, 1468 INTEL_PIPE_CRC_SOURCE_DP_D, 1469 INTEL_PIPE_CRC_SOURCE_AUTO, 1470 INTEL_PIPE_CRC_SOURCE_MAX, 1471 }; 1472 1473 struct intel_pipe_crc_entry { 1474 uint32_t frame; 1475 uint32_t crc[5]; 1476 }; 1477 1478 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1479 struct intel_pipe_crc { 1480 spinlock_t lock; 1481 bool opened; /* exclusive access to the result file */ 1482 struct intel_pipe_crc_entry *entries; 1483 enum intel_pipe_crc_source source; 1484 int head, tail; 1485 wait_queue_head_t wq; 1486 }; 1487 1488 struct i915_frontbuffer_tracking { 1489 struct mutex lock; 1490 1491 /* 1492 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1493 * scheduled flips. 1494 */ 1495 unsigned busy_bits; 1496 unsigned flip_bits; 1497 }; 1498 1499 struct i915_wa_reg { 1500 u32 addr; 1501 u32 value; 1502 /* bitmask representing WA bits */ 1503 u32 mask; 1504 }; 1505 1506 #define I915_MAX_WA_REGS 16 1507 1508 struct i915_workarounds { 1509 struct i915_wa_reg reg[I915_MAX_WA_REGS]; 1510 u32 count; 1511 }; 1512 1513 struct drm_i915_private { 1514 struct drm_device *dev; 1515 struct kmem_cache *slab; 1516 1517 const struct intel_device_info info; 1518 1519 int relative_constants_mode; 1520 1521 void __iomem *regs; 1522 1523 struct intel_uncore uncore; 1524 1525 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 1526 1527 1528 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1529 * controller on different i2c buses. */ 1530 struct mutex gmbus_mutex; 1531 1532 /** 1533 * Base address of the gmbus and gpio block. 1534 */ 1535 uint32_t gpio_mmio_base; 1536 1537 /* MMIO base address for MIPI regs */ 1538 uint32_t mipi_mmio_base; 1539 1540 wait_queue_head_t gmbus_wait_queue; 1541 1542 struct pci_dev *bridge_dev; 1543 struct intel_engine_cs ring[I915_NUM_RINGS]; 1544 struct drm_i915_gem_object *semaphore_obj; 1545 uint32_t last_seqno, next_seqno; 1546 1547 struct drm_dma_handle *status_page_dmah; 1548 struct resource mch_res; 1549 1550 /* protects the irq masks */ 1551 spinlock_t irq_lock; 1552 1553 /* protects the mmio flip data */ 1554 spinlock_t mmio_flip_lock; 1555 1556 bool display_irqs_enabled; 1557 1558 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1559 struct pm_qos_request pm_qos; 1560 1561 /* DPIO indirect register protection */ 1562 struct mutex dpio_lock; 1563 1564 /** Cached value of IMR to avoid reads in updating the bitfield */ 1565 union { 1566 u32 irq_mask; 1567 u32 de_irq_mask[I915_MAX_PIPES]; 1568 }; 1569 u32 gt_irq_mask; 1570 u32 pm_irq_mask; 1571 u32 pm_rps_events; 1572 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1573 1574 struct work_struct hotplug_work; 1575 struct { 1576 unsigned long hpd_last_jiffies; 1577 int hpd_cnt; 1578 enum { 1579 HPD_ENABLED = 0, 1580 HPD_DISABLED = 1, 1581 HPD_MARK_DISABLED = 2 1582 } hpd_mark; 1583 } hpd_stats[HPD_NUM_PINS]; 1584 u32 hpd_event_bits; 1585 struct delayed_work hotplug_reenable_work; 1586 1587 struct i915_fbc fbc; 1588 struct i915_drrs drrs; 1589 struct intel_opregion opregion; 1590 struct intel_vbt_data vbt; 1591 1592 bool preserve_bios_swizzle; 1593 1594 /* overlay */ 1595 struct intel_overlay *overlay; 1596 1597 /* backlight registers and fields in struct intel_panel */ 1598 struct mutex backlight_lock; 1599 1600 /* LVDS info */ 1601 bool no_aux_handshake; 1602 1603 /* protects panel power sequencer state */ 1604 struct mutex pps_mutex; 1605 1606 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1607 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1608 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1609 1610 unsigned int fsb_freq, mem_freq, is_ddr3; 1611 unsigned int vlv_cdclk_freq; 1612 unsigned int hpll_freq; 1613 1614 /** 1615 * wq - Driver workqueue for GEM. 1616 * 1617 * NOTE: Work items scheduled here are not allowed to grab any modeset 1618 * locks, for otherwise the flushing done in the pageflip code will 1619 * result in deadlocks. 1620 */ 1621 struct workqueue_struct *wq; 1622 1623 /* Display functions */ 1624 struct drm_i915_display_funcs display; 1625 1626 /* PCH chipset type */ 1627 enum intel_pch pch_type; 1628 unsigned short pch_id; 1629 1630 unsigned long quirks; 1631 1632 enum modeset_restore modeset_restore; 1633 struct mutex modeset_restore_lock; 1634 1635 struct list_head vm_list; /* Global list of all address spaces */ 1636 struct i915_gtt gtt; /* VM representing the global address space */ 1637 1638 struct i915_gem_mm mm; 1639 DECLARE_HASHTABLE(mm_structs, 7); 1640 struct mutex mm_lock; 1641 1642 /* Kernel Modesetting */ 1643 1644 struct sdvo_device_mapping sdvo_mappings[2]; 1645 1646 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1647 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1648 wait_queue_head_t pending_flip_queue; 1649 1650 #ifdef CONFIG_DEBUG_FS 1651 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1652 #endif 1653 1654 int num_shared_dpll; 1655 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1656 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1657 1658 struct i915_workarounds workarounds; 1659 1660 /* Reclocking support */ 1661 bool render_reclock_avail; 1662 bool lvds_downclock_avail; 1663 /* indicates the reduced downclock for LVDS*/ 1664 int lvds_downclock; 1665 1666 struct i915_frontbuffer_tracking fb_tracking; 1667 1668 u16 orig_clock; 1669 1670 bool mchbar_need_disable; 1671 1672 struct intel_l3_parity l3_parity; 1673 1674 /* Cannot be determined by PCIID. You must always read a register. */ 1675 size_t ellc_size; 1676 1677 /* gen6+ rps state */ 1678 struct intel_gen6_power_mgmt rps; 1679 1680 /* ilk-only ips/rps state. Everything in here is protected by the global 1681 * mchdev_lock in intel_pm.c */ 1682 struct intel_ilk_power_mgmt ips; 1683 1684 struct i915_power_domains power_domains; 1685 1686 struct i915_psr psr; 1687 1688 struct i915_gpu_error gpu_error; 1689 1690 struct drm_i915_gem_object *vlv_pctx; 1691 1692 #ifdef CONFIG_DRM_I915_FBDEV 1693 /* list of fbdev register on this device */ 1694 struct intel_fbdev *fbdev; 1695 struct work_struct fbdev_suspend_work; 1696 #endif 1697 1698 struct drm_property *broadcast_rgb_property; 1699 struct drm_property *force_audio_property; 1700 1701 /* hda/i915 audio component */ 1702 bool audio_component_registered; 1703 1704 uint32_t hw_context_size; 1705 struct list_head context_list; 1706 1707 u32 fdi_rx_config; 1708 1709 u32 suspend_count; 1710 struct i915_suspend_saved_registers regfile; 1711 struct vlv_s0ix_state vlv_s0ix_state; 1712 1713 struct { 1714 /* 1715 * Raw watermark latency values: 1716 * in 0.1us units for WM0, 1717 * in 0.5us units for WM1+. 1718 */ 1719 /* primary */ 1720 uint16_t pri_latency[5]; 1721 /* sprite */ 1722 uint16_t spr_latency[5]; 1723 /* cursor */ 1724 uint16_t cur_latency[5]; 1725 /* 1726 * Raw watermark memory latency values 1727 * for SKL for all 8 levels 1728 * in 1us units. 1729 */ 1730 uint16_t skl_latency[8]; 1731 1732 /* 1733 * The skl_wm_values structure is a bit too big for stack 1734 * allocation, so we keep the staging struct where we store 1735 * intermediate results here instead. 1736 */ 1737 struct skl_wm_values skl_results; 1738 1739 /* current hardware state */ 1740 union { 1741 struct ilk_wm_values hw; 1742 struct skl_wm_values skl_hw; 1743 }; 1744 } wm; 1745 1746 struct i915_runtime_pm pm; 1747 1748 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; 1749 u32 long_hpd_port_mask; 1750 u32 short_hpd_port_mask; 1751 struct work_struct dig_port_work; 1752 1753 /* 1754 * if we get a HPD irq from DP and a HPD irq from non-DP 1755 * the non-DP HPD could block the workqueue on a mode config 1756 * mutex getting, that userspace may have taken. However 1757 * userspace is waiting on the DP workqueue to run which is 1758 * blocked behind the non-DP one. 1759 */ 1760 struct workqueue_struct *dp_wq; 1761 1762 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1763 struct { 1764 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, 1765 struct intel_engine_cs *ring, 1766 struct intel_context *ctx, 1767 struct drm_i915_gem_execbuffer2 *args, 1768 struct list_head *vmas, 1769 struct drm_i915_gem_object *batch_obj, 1770 u64 exec_start, u32 flags); 1771 int (*init_rings)(struct drm_device *dev); 1772 void (*cleanup_ring)(struct intel_engine_cs *ring); 1773 void (*stop_ring)(struct intel_engine_cs *ring); 1774 } gt; 1775 1776 /* 1777 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1778 * will be rejected. Instead look for a better place. 1779 */ 1780 }; 1781 1782 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1783 { 1784 return dev->dev_private; 1785 } 1786 1787 static inline struct drm_i915_private *dev_to_i915(struct device *dev) 1788 { 1789 return to_i915(dev_get_drvdata(dev)); 1790 } 1791 1792 /* Iterate over initialised rings */ 1793 #define for_each_ring(ring__, dev_priv__, i__) \ 1794 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1795 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1796 1797 enum hdmi_force_audio { 1798 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1799 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1800 HDMI_AUDIO_AUTO, /* trust EDID */ 1801 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1802 }; 1803 1804 #define I915_GTT_OFFSET_NONE ((u32)-1) 1805 1806 struct drm_i915_gem_object_ops { 1807 /* Interface between the GEM object and its backing storage. 1808 * get_pages() is called once prior to the use of the associated set 1809 * of pages before to binding them into the GTT, and put_pages() is 1810 * called after we no longer need them. As we expect there to be 1811 * associated cost with migrating pages between the backing storage 1812 * and making them available for the GPU (e.g. clflush), we may hold 1813 * onto the pages after they are no longer referenced by the GPU 1814 * in case they may be used again shortly (for example migrating the 1815 * pages to a different memory domain within the GTT). put_pages() 1816 * will therefore most likely be called when the object itself is 1817 * being released or under memory pressure (where we attempt to 1818 * reap pages for the shrinker). 1819 */ 1820 int (*get_pages)(struct drm_i915_gem_object *); 1821 void (*put_pages)(struct drm_i915_gem_object *); 1822 int (*dmabuf_export)(struct drm_i915_gem_object *); 1823 void (*release)(struct drm_i915_gem_object *); 1824 }; 1825 1826 /* 1827 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1828 * considered to be the frontbuffer for the given plane interface-vise. This 1829 * doesn't mean that the hw necessarily already scans it out, but that any 1830 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1831 * 1832 * We have one bit per pipe and per scanout plane type. 1833 */ 1834 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 1835 #define INTEL_FRONTBUFFER_BITS \ 1836 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 1837 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 1838 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1839 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 1840 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1841 #define INTEL_FRONTBUFFER_SPRITE(pipe) \ 1842 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1843 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1844 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1845 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1846 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1847 1848 struct drm_i915_gem_object { 1849 struct drm_gem_object base; 1850 1851 const struct drm_i915_gem_object_ops *ops; 1852 1853 /** List of VMAs backed by this object */ 1854 struct list_head vma_list; 1855 1856 /** Stolen memory for this object, instead of being backed by shmem. */ 1857 struct drm_mm_node *stolen; 1858 struct list_head global_list; 1859 1860 struct list_head ring_list; 1861 /** Used in execbuf to temporarily hold a ref */ 1862 struct list_head obj_exec_link; 1863 1864 /** 1865 * This is set if the object is on the active lists (has pending 1866 * rendering and so a non-zero seqno), and is not set if it i s on 1867 * inactive (ready to be unbound) list. 1868 */ 1869 unsigned int active:1; 1870 1871 /** 1872 * This is set if the object has been written to since last bound 1873 * to the GTT 1874 */ 1875 unsigned int dirty:1; 1876 1877 /** 1878 * Fence register bits (if any) for this object. Will be set 1879 * as needed when mapped into the GTT. 1880 * Protected by dev->struct_mutex. 1881 */ 1882 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1883 1884 /** 1885 * Advice: are the backing pages purgeable? 1886 */ 1887 unsigned int madv:2; 1888 1889 /** 1890 * Current tiling mode for the object. 1891 */ 1892 unsigned int tiling_mode:2; 1893 /** 1894 * Whether the tiling parameters for the currently associated fence 1895 * register have changed. Note that for the purposes of tracking 1896 * tiling changes we also treat the unfenced register, the register 1897 * slot that the object occupies whilst it executes a fenced 1898 * command (such as BLT on gen2/3), as a "fence". 1899 */ 1900 unsigned int fence_dirty:1; 1901 1902 /** 1903 * Is the object at the current location in the gtt mappable and 1904 * fenceable? Used to avoid costly recalculations. 1905 */ 1906 unsigned int map_and_fenceable:1; 1907 1908 /** 1909 * Whether the current gtt mapping needs to be mappable (and isn't just 1910 * mappable by accident). Track pin and fault separate for a more 1911 * accurate mappable working set. 1912 */ 1913 unsigned int fault_mappable:1; 1914 unsigned int pin_mappable:1; 1915 unsigned int pin_display:1; 1916 1917 /* 1918 * Is the object to be mapped as read-only to the GPU 1919 * Only honoured if hardware has relevant pte bit 1920 */ 1921 unsigned long gt_ro:1; 1922 unsigned int cache_level:3; 1923 1924 unsigned int has_dma_mapping:1; 1925 1926 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 1927 1928 struct sg_table *pages; 1929 int pages_pin_count; 1930 1931 /* prime dma-buf support */ 1932 void *dma_buf_vmapping; 1933 int vmapping_count; 1934 1935 struct intel_engine_cs *ring; 1936 1937 /** Breadcrumb of last rendering to the buffer. */ 1938 uint32_t last_read_seqno; 1939 uint32_t last_write_seqno; 1940 /** Breadcrumb of last fenced GPU access to the buffer. */ 1941 uint32_t last_fenced_seqno; 1942 1943 /** Current tiling stride for the object, if it's tiled. */ 1944 uint32_t stride; 1945 1946 /** References from framebuffers, locks out tiling changes. */ 1947 unsigned long framebuffer_references; 1948 1949 /** Record of address bit 17 of each page at last unbind. */ 1950 unsigned long *bit_17; 1951 1952 /** User space pin count and filp owning the pin */ 1953 unsigned long user_pin_count; 1954 struct drm_file *pin_filp; 1955 1956 union { 1957 /** for phy allocated objects */ 1958 struct drm_dma_handle *phys_handle; 1959 1960 struct i915_gem_userptr { 1961 uintptr_t ptr; 1962 unsigned read_only :1; 1963 unsigned workers :4; 1964 #define I915_GEM_USERPTR_MAX_WORKERS 15 1965 1966 struct i915_mm_struct *mm; 1967 struct i915_mmu_object *mmu_object; 1968 struct work_struct *work; 1969 } userptr; 1970 }; 1971 }; 1972 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1973 1974 void i915_gem_track_fb(struct drm_i915_gem_object *old, 1975 struct drm_i915_gem_object *new, 1976 unsigned frontbuffer_bits); 1977 1978 /** 1979 * Request queue structure. 1980 * 1981 * The request queue allows us to note sequence numbers that have been emitted 1982 * and may be associated with active buffers to be retired. 1983 * 1984 * By keeping this list, we can avoid having to do questionable 1985 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1986 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1987 */ 1988 struct drm_i915_gem_request { 1989 /** On Which ring this request was generated */ 1990 struct intel_engine_cs *ring; 1991 1992 /** GEM sequence number associated with this request. */ 1993 uint32_t seqno; 1994 1995 /** Position in the ringbuffer of the start of the request */ 1996 u32 head; 1997 1998 /** Position in the ringbuffer of the end of the request */ 1999 u32 tail; 2000 2001 /** Context related to this request */ 2002 struct intel_context *ctx; 2003 2004 /** Batch buffer related to this request if any */ 2005 struct drm_i915_gem_object *batch_obj; 2006 2007 /** Time at which this request was emitted, in jiffies. */ 2008 unsigned long emitted_jiffies; 2009 2010 /** global list entry for this request */ 2011 struct list_head list; 2012 2013 struct drm_i915_file_private *file_priv; 2014 /** file_priv list entry for this request */ 2015 struct list_head client_list; 2016 }; 2017 2018 struct drm_i915_file_private { 2019 struct drm_i915_private *dev_priv; 2020 struct drm_file *file; 2021 2022 struct { 2023 spinlock_t lock; 2024 struct list_head request_list; 2025 struct delayed_work idle_work; 2026 } mm; 2027 struct idr context_idr; 2028 2029 atomic_t rps_wait_boost; 2030 struct intel_engine_cs *bsd_ring; 2031 }; 2032 2033 /* 2034 * A command that requires special handling by the command parser. 2035 */ 2036 struct drm_i915_cmd_descriptor { 2037 /* 2038 * Flags describing how the command parser processes the command. 2039 * 2040 * CMD_DESC_FIXED: The command has a fixed length if this is set, 2041 * a length mask if not set 2042 * CMD_DESC_SKIP: The command is allowed but does not follow the 2043 * standard length encoding for the opcode range in 2044 * which it falls 2045 * CMD_DESC_REJECT: The command is never allowed 2046 * CMD_DESC_REGISTER: The command should be checked against the 2047 * register whitelist for the appropriate ring 2048 * CMD_DESC_MASTER: The command is allowed if the submitting process 2049 * is the DRM master 2050 */ 2051 u32 flags; 2052 #define CMD_DESC_FIXED (1<<0) 2053 #define CMD_DESC_SKIP (1<<1) 2054 #define CMD_DESC_REJECT (1<<2) 2055 #define CMD_DESC_REGISTER (1<<3) 2056 #define CMD_DESC_BITMASK (1<<4) 2057 #define CMD_DESC_MASTER (1<<5) 2058 2059 /* 2060 * The command's unique identification bits and the bitmask to get them. 2061 * This isn't strictly the opcode field as defined in the spec and may 2062 * also include type, subtype, and/or subop fields. 2063 */ 2064 struct { 2065 u32 value; 2066 u32 mask; 2067 } cmd; 2068 2069 /* 2070 * The command's length. The command is either fixed length (i.e. does 2071 * not include a length field) or has a length field mask. The flag 2072 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 2073 * a length mask. All command entries in a command table must include 2074 * length information. 2075 */ 2076 union { 2077 u32 fixed; 2078 u32 mask; 2079 } length; 2080 2081 /* 2082 * Describes where to find a register address in the command to check 2083 * against the ring's register whitelist. Only valid if flags has the 2084 * CMD_DESC_REGISTER bit set. 2085 */ 2086 struct { 2087 u32 offset; 2088 u32 mask; 2089 } reg; 2090 2091 #define MAX_CMD_DESC_BITMASKS 3 2092 /* 2093 * Describes command checks where a particular dword is masked and 2094 * compared against an expected value. If the command does not match 2095 * the expected value, the parser rejects it. Only valid if flags has 2096 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2097 * are valid. 2098 * 2099 * If the check specifies a non-zero condition_mask then the parser 2100 * only performs the check when the bits specified by condition_mask 2101 * are non-zero. 2102 */ 2103 struct { 2104 u32 offset; 2105 u32 mask; 2106 u32 expected; 2107 u32 condition_offset; 2108 u32 condition_mask; 2109 } bits[MAX_CMD_DESC_BITMASKS]; 2110 }; 2111 2112 /* 2113 * A table of commands requiring special handling by the command parser. 2114 * 2115 * Each ring has an array of tables. Each table consists of an array of command 2116 * descriptors, which must be sorted with command opcodes in ascending order. 2117 */ 2118 struct drm_i915_cmd_table { 2119 const struct drm_i915_cmd_descriptor *table; 2120 int count; 2121 }; 2122 2123 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2124 #define __I915__(p) ({ \ 2125 struct drm_i915_private *__p; \ 2126 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2127 __p = (struct drm_i915_private *)p; \ 2128 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2129 __p = to_i915((struct drm_device *)p); \ 2130 else \ 2131 BUILD_BUG(); \ 2132 __p; \ 2133 }) 2134 #define INTEL_INFO(p) (&__I915__(p)->info) 2135 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2136 2137 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2138 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2139 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2140 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2141 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2142 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2143 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2144 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2145 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2146 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2147 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2148 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2149 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2150 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2151 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2152 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2153 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2154 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2155 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2156 INTEL_DEVID(dev) == 0x0152 || \ 2157 INTEL_DEVID(dev) == 0x015a) 2158 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ 2159 INTEL_DEVID(dev) == 0x0106 || \ 2160 INTEL_DEVID(dev) == 0x010A) 2161 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2162 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2163 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2164 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2165 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) 2166 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2167 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2168 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2169 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2170 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ 2171 (INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2172 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2173 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2174 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2175 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2176 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2177 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2178 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2179 /* ULX machines are also considered ULT. */ 2180 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2181 INTEL_DEVID(dev) == 0x0A1E) 2182 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2183 2184 /* 2185 * The genX designation typically refers to the render engine, so render 2186 * capability related checks should use IS_GEN, while display and other checks 2187 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2188 * chips, etc.). 2189 */ 2190 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2191 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2192 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2193 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2194 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2195 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2196 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2197 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) 2198 2199 #define RENDER_RING (1<<RCS) 2200 #define BSD_RING (1<<VCS) 2201 #define BLT_RING (1<<BCS) 2202 #define VEBOX_RING (1<<VECS) 2203 #define BSD2_RING (1<<VCS2) 2204 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2205 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2206 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2207 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2208 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2209 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2210 __I915__(dev)->ellc_size) 2211 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2212 2213 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2214 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) 2215 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2216 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) 2217 2218 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2219 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2220 2221 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2222 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2223 /* 2224 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2225 * even when in MSI mode. This results in spurious interrupt warnings if the 2226 * legacy irq no. is shared with another device. The kernel then disables that 2227 * interrupt source and so prevents the other device from working properly. 2228 */ 2229 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2230 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2231 2232 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2233 * rows, which changed the alignment requirements and fence programming. 2234 */ 2235 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2236 IS_I915GM(dev))) 2237 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 2238 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2239 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2240 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2241 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2242 2243 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2244 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2245 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2246 2247 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) 2248 2249 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2250 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2251 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2252 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2253 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2254 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) 2255 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) 2256 2257 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2258 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2259 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2260 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2261 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2262 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2263 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 2264 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 2265 2266 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) 2267 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) 2268 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2269 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2270 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2271 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2272 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2273 2274 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2275 2276 /* DPF == dynamic parity feature */ 2277 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2278 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2279 2280 #define GT_FREQUENCY_MULTIPLIER 50 2281 2282 #include "i915_trace.h" 2283 2284 extern const struct drm_ioctl_desc i915_ioctls[]; 2285 extern int i915_max_ioctl; 2286 2287 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); 2288 extern int i915_resume_legacy(struct drm_device *dev); 2289 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 2290 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 2291 2292 /* i915_params.c */ 2293 struct i915_params { 2294 int modeset; 2295 int panel_ignore_lid; 2296 unsigned int powersave; 2297 int semaphores; 2298 unsigned int lvds_downclock; 2299 int lvds_channel_mode; 2300 int panel_use_ssc; 2301 int vbt_sdvo_panel_type; 2302 int enable_rc6; 2303 int enable_fbc; 2304 int enable_ppgtt; 2305 int enable_execlists; 2306 int enable_psr; 2307 unsigned int preliminary_hw_support; 2308 int disable_power_well; 2309 int enable_ips; 2310 int invert_brightness; 2311 int enable_cmd_parser; 2312 /* leave bools at the end to not create holes */ 2313 bool enable_hangcheck; 2314 bool fastboot; 2315 bool prefault_disable; 2316 bool reset; 2317 bool disable_display; 2318 bool disable_vtd_wa; 2319 int use_mmio_flip; 2320 bool mmio_debug; 2321 }; 2322 extern struct i915_params i915 __read_mostly; 2323 2324 /* i915_dma.c */ 2325 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2326 extern int i915_driver_unload(struct drm_device *); 2327 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2328 extern void i915_driver_lastclose(struct drm_device * dev); 2329 extern void i915_driver_preclose(struct drm_device *dev, 2330 struct drm_file *file); 2331 extern void i915_driver_postclose(struct drm_device *dev, 2332 struct drm_file *file); 2333 extern int i915_driver_device_is_agp(struct drm_device * dev); 2334 #ifdef CONFIG_COMPAT 2335 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2336 unsigned long arg); 2337 #endif 2338 extern int intel_gpu_reset(struct drm_device *dev); 2339 extern int i915_reset(struct drm_device *dev); 2340 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2341 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2342 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2343 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2344 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2345 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2346 2347 /* i915_irq.c */ 2348 void i915_queue_hangcheck(struct drm_device *dev); 2349 __printf(3, 4) 2350 void i915_handle_error(struct drm_device *dev, bool wedged, 2351 const char *fmt, ...); 2352 2353 extern void intel_irq_init(struct drm_i915_private *dev_priv); 2354 extern void intel_hpd_init(struct drm_i915_private *dev_priv); 2355 int intel_irq_install(struct drm_i915_private *dev_priv); 2356 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 2357 2358 extern void intel_uncore_sanitize(struct drm_device *dev); 2359 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2360 bool restore_forcewake); 2361 extern void intel_uncore_init(struct drm_device *dev); 2362 extern void intel_uncore_check_errors(struct drm_device *dev); 2363 extern void intel_uncore_fini(struct drm_device *dev); 2364 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); 2365 2366 void 2367 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2368 u32 status_mask); 2369 2370 void 2371 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2372 u32 status_mask); 2373 2374 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2375 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2376 void 2377 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2378 void 2379 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2380 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 2381 uint32_t interrupt_mask, 2382 uint32_t enabled_irq_mask); 2383 #define ibx_enable_display_interrupt(dev_priv, bits) \ 2384 ibx_display_interrupt_update((dev_priv), (bits), (bits)) 2385 #define ibx_disable_display_interrupt(dev_priv, bits) \ 2386 ibx_display_interrupt_update((dev_priv), (bits), 0) 2387 2388 /* i915_gem.c */ 2389 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2390 struct drm_file *file_priv); 2391 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2392 struct drm_file *file_priv); 2393 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2394 struct drm_file *file_priv); 2395 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2396 struct drm_file *file_priv); 2397 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2398 struct drm_file *file_priv); 2399 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2400 struct drm_file *file_priv); 2401 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2402 struct drm_file *file_priv); 2403 void i915_gem_execbuffer_move_to_active(struct list_head *vmas, 2404 struct intel_engine_cs *ring); 2405 void i915_gem_execbuffer_retire_commands(struct drm_device *dev, 2406 struct drm_file *file, 2407 struct intel_engine_cs *ring, 2408 struct drm_i915_gem_object *obj); 2409 int i915_gem_ringbuffer_submission(struct drm_device *dev, 2410 struct drm_file *file, 2411 struct intel_engine_cs *ring, 2412 struct intel_context *ctx, 2413 struct drm_i915_gem_execbuffer2 *args, 2414 struct list_head *vmas, 2415 struct drm_i915_gem_object *batch_obj, 2416 u64 exec_start, u32 flags); 2417 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2418 struct drm_file *file_priv); 2419 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2420 struct drm_file *file_priv); 2421 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 2422 struct drm_file *file_priv); 2423 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 2424 struct drm_file *file_priv); 2425 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2426 struct drm_file *file_priv); 2427 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2428 struct drm_file *file); 2429 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2430 struct drm_file *file); 2431 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2432 struct drm_file *file_priv); 2433 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2434 struct drm_file *file_priv); 2435 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2436 struct drm_file *file_priv); 2437 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2438 struct drm_file *file_priv); 2439 int i915_gem_init_userptr(struct drm_device *dev); 2440 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2441 struct drm_file *file); 2442 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2443 struct drm_file *file_priv); 2444 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2445 struct drm_file *file_priv); 2446 void i915_gem_load(struct drm_device *dev); 2447 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 2448 long target, 2449 unsigned flags); 2450 #define I915_SHRINK_PURGEABLE 0x1 2451 #define I915_SHRINK_UNBOUND 0x2 2452 #define I915_SHRINK_BOUND 0x4 2453 void *i915_gem_object_alloc(struct drm_device *dev); 2454 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2455 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2456 const struct drm_i915_gem_object_ops *ops); 2457 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2458 size_t size); 2459 void i915_init_vm(struct drm_i915_private *dev_priv, 2460 struct i915_address_space *vm); 2461 void i915_gem_free_object(struct drm_gem_object *obj); 2462 void i915_gem_vma_destroy(struct i915_vma *vma); 2463 2464 #define PIN_MAPPABLE 0x1 2465 #define PIN_NONBLOCK 0x2 2466 #define PIN_GLOBAL 0x4 2467 #define PIN_OFFSET_BIAS 0x8 2468 #define PIN_OFFSET_MASK (~4095) 2469 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2470 struct i915_address_space *vm, 2471 uint32_t alignment, 2472 uint64_t flags); 2473 int __must_check i915_vma_unbind(struct i915_vma *vma); 2474 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2475 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2476 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2477 2478 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2479 int *needs_clflush); 2480 2481 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2482 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2483 { 2484 struct sg_page_iter sg_iter; 2485 2486 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 2487 return sg_page_iter_page(&sg_iter); 2488 2489 return NULL; 2490 } 2491 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2492 { 2493 BUG_ON(obj->pages == NULL); 2494 obj->pages_pin_count++; 2495 } 2496 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2497 { 2498 BUG_ON(obj->pages_pin_count == 0); 2499 obj->pages_pin_count--; 2500 } 2501 2502 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2503 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2504 struct intel_engine_cs *to); 2505 void i915_vma_move_to_active(struct i915_vma *vma, 2506 struct intel_engine_cs *ring); 2507 int i915_gem_dumb_create(struct drm_file *file_priv, 2508 struct drm_device *dev, 2509 struct drm_mode_create_dumb *args); 2510 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2511 uint32_t handle, uint64_t *offset); 2512 /** 2513 * Returns true if seq1 is later than seq2. 2514 */ 2515 static inline bool 2516 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2517 { 2518 return (int32_t)(seq1 - seq2) >= 0; 2519 } 2520 2521 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2522 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2523 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2524 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2525 2526 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2527 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2528 2529 struct drm_i915_gem_request * 2530 i915_gem_find_active_request(struct intel_engine_cs *ring); 2531 2532 bool i915_gem_retire_requests(struct drm_device *dev); 2533 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2534 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2535 bool interruptible); 2536 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); 2537 2538 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2539 { 2540 return unlikely(atomic_read(&error->reset_counter) 2541 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2542 } 2543 2544 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2545 { 2546 return atomic_read(&error->reset_counter) & I915_WEDGED; 2547 } 2548 2549 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2550 { 2551 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2552 } 2553 2554 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2555 { 2556 return dev_priv->gpu_error.stop_rings == 0 || 2557 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2558 } 2559 2560 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2561 { 2562 return dev_priv->gpu_error.stop_rings == 0 || 2563 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2564 } 2565 2566 void i915_gem_reset(struct drm_device *dev); 2567 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2568 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2569 int __must_check i915_gem_init(struct drm_device *dev); 2570 int i915_gem_init_rings(struct drm_device *dev); 2571 int __must_check i915_gem_init_hw(struct drm_device *dev); 2572 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2573 void i915_gem_init_swizzling(struct drm_device *dev); 2574 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2575 int __must_check i915_gpu_idle(struct drm_device *dev); 2576 int __must_check i915_gem_suspend(struct drm_device *dev); 2577 int __i915_add_request(struct intel_engine_cs *ring, 2578 struct drm_file *file, 2579 struct drm_i915_gem_object *batch_obj, 2580 u32 *seqno); 2581 #define i915_add_request(ring, seqno) \ 2582 __i915_add_request(ring, NULL, NULL, seqno) 2583 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, 2584 unsigned reset_counter, 2585 bool interruptible, 2586 s64 *timeout, 2587 struct drm_i915_file_private *file_priv); 2588 int __must_check i915_wait_seqno(struct intel_engine_cs *ring, 2589 uint32_t seqno); 2590 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 2591 int __must_check 2592 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2593 bool write); 2594 int __must_check 2595 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2596 int __must_check 2597 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2598 u32 alignment, 2599 struct intel_engine_cs *pipelined); 2600 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2601 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2602 int align); 2603 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2604 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2605 2606 uint32_t 2607 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2608 uint32_t 2609 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2610 int tiling_mode, bool fenced); 2611 2612 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2613 enum i915_cache_level cache_level); 2614 2615 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2616 struct dma_buf *dma_buf); 2617 2618 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2619 struct drm_gem_object *gem_obj, int flags); 2620 2621 void i915_gem_restore_fences(struct drm_device *dev); 2622 2623 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2624 struct i915_address_space *vm); 2625 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2626 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2627 struct i915_address_space *vm); 2628 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2629 struct i915_address_space *vm); 2630 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2631 struct i915_address_space *vm); 2632 struct i915_vma * 2633 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2634 struct i915_address_space *vm); 2635 2636 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2637 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { 2638 struct i915_vma *vma; 2639 list_for_each_entry(vma, &obj->vma_list, vma_link) 2640 if (vma->pin_count > 0) 2641 return true; 2642 return false; 2643 } 2644 2645 /* Some GGTT VM helpers */ 2646 #define i915_obj_to_ggtt(obj) \ 2647 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2648 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2649 { 2650 struct i915_address_space *ggtt = 2651 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2652 return vm == ggtt; 2653 } 2654 2655 static inline struct i915_hw_ppgtt * 2656 i915_vm_to_ppgtt(struct i915_address_space *vm) 2657 { 2658 WARN_ON(i915_is_ggtt(vm)); 2659 2660 return container_of(vm, struct i915_hw_ppgtt, base); 2661 } 2662 2663 2664 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2665 { 2666 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); 2667 } 2668 2669 static inline unsigned long 2670 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2671 { 2672 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); 2673 } 2674 2675 static inline unsigned long 2676 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2677 { 2678 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); 2679 } 2680 2681 static inline int __must_check 2682 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2683 uint32_t alignment, 2684 unsigned flags) 2685 { 2686 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), 2687 alignment, flags | PIN_GLOBAL); 2688 } 2689 2690 static inline int 2691 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2692 { 2693 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 2694 } 2695 2696 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); 2697 2698 /* i915_gem_context.c */ 2699 int __must_check i915_gem_context_init(struct drm_device *dev); 2700 void i915_gem_context_fini(struct drm_device *dev); 2701 void i915_gem_context_reset(struct drm_device *dev); 2702 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 2703 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 2704 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2705 int i915_switch_context(struct intel_engine_cs *ring, 2706 struct intel_context *to); 2707 struct intel_context * 2708 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 2709 void i915_gem_context_free(struct kref *ctx_ref); 2710 struct drm_i915_gem_object * 2711 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); 2712 static inline void i915_gem_context_reference(struct intel_context *ctx) 2713 { 2714 kref_get(&ctx->ref); 2715 } 2716 2717 static inline void i915_gem_context_unreference(struct intel_context *ctx) 2718 { 2719 kref_put(&ctx->ref, i915_gem_context_free); 2720 } 2721 2722 static inline bool i915_gem_context_is_default(const struct intel_context *c) 2723 { 2724 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 2725 } 2726 2727 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2728 struct drm_file *file); 2729 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2730 struct drm_file *file); 2731 2732 /* i915_gem_evict.c */ 2733 int __must_check i915_gem_evict_something(struct drm_device *dev, 2734 struct i915_address_space *vm, 2735 int min_size, 2736 unsigned alignment, 2737 unsigned cache_level, 2738 unsigned long start, 2739 unsigned long end, 2740 unsigned flags); 2741 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2742 int i915_gem_evict_everything(struct drm_device *dev); 2743 2744 /* belongs in i915_gem_gtt.h */ 2745 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2746 { 2747 if (INTEL_INFO(dev)->gen < 6) 2748 intel_gtt_chipset_flush(); 2749 } 2750 2751 /* i915_gem_stolen.c */ 2752 int i915_gem_init_stolen(struct drm_device *dev); 2753 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); 2754 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2755 void i915_gem_cleanup_stolen(struct drm_device *dev); 2756 struct drm_i915_gem_object * 2757 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2758 struct drm_i915_gem_object * 2759 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2760 u32 stolen_offset, 2761 u32 gtt_offset, 2762 u32 size); 2763 2764 /* i915_gem_tiling.c */ 2765 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2766 { 2767 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2768 2769 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2770 obj->tiling_mode != I915_TILING_NONE; 2771 } 2772 2773 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2774 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2775 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2776 2777 /* i915_gem_debug.c */ 2778 #if WATCH_LISTS 2779 int i915_verify_lists(struct drm_device *dev); 2780 #else 2781 #define i915_verify_lists(dev) 0 2782 #endif 2783 2784 /* i915_debugfs.c */ 2785 int i915_debugfs_init(struct drm_minor *minor); 2786 void i915_debugfs_cleanup(struct drm_minor *minor); 2787 #ifdef CONFIG_DEBUG_FS 2788 void intel_display_crc_init(struct drm_device *dev); 2789 #else 2790 static inline void intel_display_crc_init(struct drm_device *dev) {} 2791 #endif 2792 2793 /* i915_gpu_error.c */ 2794 __printf(2, 3) 2795 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2796 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2797 const struct i915_error_state_file_priv *error); 2798 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2799 struct drm_i915_private *i915, 2800 size_t count, loff_t pos); 2801 static inline void i915_error_state_buf_release( 2802 struct drm_i915_error_state_buf *eb) 2803 { 2804 kfree(eb->buf); 2805 } 2806 void i915_capture_error_state(struct drm_device *dev, bool wedge, 2807 const char *error_msg); 2808 void i915_error_state_get(struct drm_device *dev, 2809 struct i915_error_state_file_priv *error_priv); 2810 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2811 void i915_destroy_error_state(struct drm_device *dev); 2812 2813 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2814 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 2815 2816 /* i915_cmd_parser.c */ 2817 int i915_cmd_parser_get_version(void); 2818 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 2819 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 2820 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 2821 int i915_parse_cmds(struct intel_engine_cs *ring, 2822 struct drm_i915_gem_object *batch_obj, 2823 u32 batch_start_offset, 2824 bool is_master); 2825 2826 /* i915_suspend.c */ 2827 extern int i915_save_state(struct drm_device *dev); 2828 extern int i915_restore_state(struct drm_device *dev); 2829 2830 /* i915_ums.c */ 2831 void i915_save_display_reg(struct drm_device *dev); 2832 void i915_restore_display_reg(struct drm_device *dev); 2833 2834 /* i915_sysfs.c */ 2835 void i915_setup_sysfs(struct drm_device *dev_priv); 2836 void i915_teardown_sysfs(struct drm_device *dev_priv); 2837 2838 /* intel_i2c.c */ 2839 extern int intel_setup_gmbus(struct drm_device *dev); 2840 extern void intel_teardown_gmbus(struct drm_device *dev); 2841 static inline bool intel_gmbus_is_port_valid(unsigned port) 2842 { 2843 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2844 } 2845 2846 extern struct i2c_adapter *intel_gmbus_get_adapter( 2847 struct drm_i915_private *dev_priv, unsigned port); 2848 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 2849 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 2850 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 2851 { 2852 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 2853 } 2854 extern void intel_i2c_reset(struct drm_device *dev); 2855 2856 /* intel_opregion.c */ 2857 #ifdef CONFIG_ACPI 2858 extern int intel_opregion_setup(struct drm_device *dev); 2859 extern void intel_opregion_init(struct drm_device *dev); 2860 extern void intel_opregion_fini(struct drm_device *dev); 2861 extern void intel_opregion_asle_intr(struct drm_device *dev); 2862 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2863 bool enable); 2864 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2865 pci_power_t state); 2866 #else 2867 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2868 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2869 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2870 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2871 static inline int 2872 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2873 { 2874 return 0; 2875 } 2876 static inline int 2877 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2878 { 2879 return 0; 2880 } 2881 #endif 2882 2883 /* intel_acpi.c */ 2884 #ifdef CONFIG_ACPI 2885 extern void intel_register_dsm_handler(void); 2886 extern void intel_unregister_dsm_handler(void); 2887 #else 2888 static inline void intel_register_dsm_handler(void) { return; } 2889 static inline void intel_unregister_dsm_handler(void) { return; } 2890 #endif /* CONFIG_ACPI */ 2891 2892 /* modesetting */ 2893 extern void intel_modeset_init_hw(struct drm_device *dev); 2894 extern void intel_modeset_init(struct drm_device *dev); 2895 extern void intel_modeset_gem_init(struct drm_device *dev); 2896 extern void intel_modeset_cleanup(struct drm_device *dev); 2897 extern void intel_connector_unregister(struct intel_connector *); 2898 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2899 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2900 bool force_restore); 2901 extern void i915_redisable_vga(struct drm_device *dev); 2902 extern void i915_redisable_vga_power_on(struct drm_device *dev); 2903 extern bool intel_fbc_enabled(struct drm_device *dev); 2904 extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value); 2905 extern void intel_disable_fbc(struct drm_device *dev); 2906 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2907 extern void intel_init_pch_refclk(struct drm_device *dev); 2908 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2909 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2910 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 2911 bool enable); 2912 extern void intel_detect_pch(struct drm_device *dev); 2913 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2914 extern int intel_enable_rc6(const struct drm_device *dev); 2915 2916 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2917 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2918 struct drm_file *file); 2919 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2920 struct drm_file *file); 2921 2922 void intel_notify_mmio_flip(struct intel_engine_cs *ring); 2923 2924 /* overlay */ 2925 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2926 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2927 struct intel_overlay_error_state *error); 2928 2929 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2930 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2931 struct drm_device *dev, 2932 struct intel_display_error_state *error); 2933 2934 /* On SNB platform, before reading ring registers forcewake bit 2935 * must be set to prevent GT core from power down and stale values being 2936 * returned. 2937 */ 2938 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2939 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2940 void assert_force_wake_inactive(struct drm_i915_private *dev_priv); 2941 2942 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 2943 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 2944 2945 /* intel_sideband.c */ 2946 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2947 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2948 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2949 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2950 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2951 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2952 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2953 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2954 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2955 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2956 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2957 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2958 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2959 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 2960 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 2961 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2962 enum intel_sbi_destination destination); 2963 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2964 enum intel_sbi_destination destination); 2965 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2966 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2967 2968 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2969 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2970 2971 #define FORCEWAKE_RENDER (1 << 0) 2972 #define FORCEWAKE_MEDIA (1 << 1) 2973 #define FORCEWAKE_BLITTER (1 << 2) 2974 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \ 2975 FORCEWAKE_BLITTER) 2976 2977 2978 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2979 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2980 2981 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2982 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2983 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2984 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2985 2986 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2987 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2988 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2989 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2990 2991 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 2992 * will be implemented using 2 32-bit writes in an arbitrary order with 2993 * an arbitrary delay between them. This can cause the hardware to 2994 * act upon the intermediate value, possibly leading to corruption and 2995 * machine death. You have been warned. 2996 */ 2997 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2998 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2999 3000 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 3001 u32 upper = I915_READ(upper_reg); \ 3002 u32 lower = I915_READ(lower_reg); \ 3003 u32 tmp = I915_READ(upper_reg); \ 3004 if (upper != tmp) { \ 3005 upper = tmp; \ 3006 lower = I915_READ(lower_reg); \ 3007 WARN_ON(I915_READ(upper_reg) != upper); \ 3008 } \ 3009 (u64)upper << 32 | lower; }) 3010 3011 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 3012 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 3013 3014 /* "Broadcast RGB" property */ 3015 #define INTEL_BROADCAST_RGB_AUTO 0 3016 #define INTEL_BROADCAST_RGB_FULL 1 3017 #define INTEL_BROADCAST_RGB_LIMITED 2 3018 3019 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 3020 { 3021 if (IS_VALLEYVIEW(dev)) 3022 return VLV_VGACNTRL; 3023 else if (INTEL_INFO(dev)->gen >= 5) 3024 return CPU_VGACNTRL; 3025 else 3026 return VGACNTRL; 3027 } 3028 3029 static inline void __user *to_user_ptr(u64 address) 3030 { 3031 return (void __user *)(uintptr_t)address; 3032 } 3033 3034 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 3035 { 3036 unsigned long j = msecs_to_jiffies(m); 3037 3038 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3039 } 3040 3041 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 3042 { 3043 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 3044 } 3045 3046 static inline unsigned long 3047 timespec_to_jiffies_timeout(const struct timespec *value) 3048 { 3049 unsigned long j = timespec_to_jiffies(value); 3050 3051 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3052 } 3053 3054 /* 3055 * If you need to wait X milliseconds between events A and B, but event B 3056 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 3057 * when event A happened, then just before event B you call this function and 3058 * pass the timestamp as the first argument, and X as the second argument. 3059 */ 3060 static inline void 3061 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 3062 { 3063 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 3064 3065 /* 3066 * Don't re-read the value of "jiffies" every time since it may change 3067 * behind our back and break the math. 3068 */ 3069 tmp_jiffies = jiffies; 3070 target_jiffies = timestamp_jiffies + 3071 msecs_to_jiffies_timeout(to_wait_ms); 3072 3073 if (time_after(target_jiffies, tmp_jiffies)) { 3074 remaining_jiffies = target_jiffies - tmp_jiffies; 3075 while (remaining_jiffies) 3076 remaining_jiffies = 3077 schedule_timeout_uninterruptible(remaining_jiffies); 3078 } 3079 } 3080 3081 #endif 3082