1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <drm/intel-gtt.h> 42 #include <linux/backlight.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/pm_qos.h> 46 47 /* General customization: 48 */ 49 50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 51 52 #define DRIVER_NAME "i915" 53 #define DRIVER_DESC "Intel Graphics" 54 #define DRIVER_DATE "20080730" 55 56 enum pipe { 57 INVALID_PIPE = -1, 58 PIPE_A = 0, 59 PIPE_B, 60 PIPE_C, 61 I915_MAX_PIPES 62 }; 63 #define pipe_name(p) ((p) + 'A') 64 65 enum transcoder { 66 TRANSCODER_A = 0, 67 TRANSCODER_B, 68 TRANSCODER_C, 69 TRANSCODER_EDP = 0xF, 70 }; 71 #define transcoder_name(t) ((t) + 'A') 72 73 enum plane { 74 PLANE_A = 0, 75 PLANE_B, 76 PLANE_C, 77 }; 78 #define plane_name(p) ((p) + 'A') 79 80 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') 81 82 enum port { 83 PORT_A = 0, 84 PORT_B, 85 PORT_C, 86 PORT_D, 87 PORT_E, 88 I915_MAX_PORTS 89 }; 90 #define port_name(p) ((p) + 'A') 91 92 #define I915_NUM_PHYS_VLV 1 93 94 enum dpio_channel { 95 DPIO_CH0, 96 DPIO_CH1 97 }; 98 99 enum dpio_phy { 100 DPIO_PHY0, 101 DPIO_PHY1 102 }; 103 104 enum intel_display_power_domain { 105 POWER_DOMAIN_PIPE_A, 106 POWER_DOMAIN_PIPE_B, 107 POWER_DOMAIN_PIPE_C, 108 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 109 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 110 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 111 POWER_DOMAIN_TRANSCODER_A, 112 POWER_DOMAIN_TRANSCODER_B, 113 POWER_DOMAIN_TRANSCODER_C, 114 POWER_DOMAIN_TRANSCODER_EDP, 115 POWER_DOMAIN_VGA, 116 POWER_DOMAIN_AUDIO, 117 POWER_DOMAIN_INIT, 118 119 POWER_DOMAIN_NUM, 120 }; 121 122 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 123 124 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 125 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 126 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 127 #define POWER_DOMAIN_TRANSCODER(tran) \ 128 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 129 (tran) + POWER_DOMAIN_TRANSCODER_A) 130 131 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 132 BIT(POWER_DOMAIN_PIPE_A) | \ 133 BIT(POWER_DOMAIN_TRANSCODER_EDP)) 134 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 135 BIT(POWER_DOMAIN_PIPE_A) | \ 136 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 137 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 138 139 enum hpd_pin { 140 HPD_NONE = 0, 141 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 142 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 143 HPD_CRT, 144 HPD_SDVO_B, 145 HPD_SDVO_C, 146 HPD_PORT_B, 147 HPD_PORT_C, 148 HPD_PORT_D, 149 HPD_NUM_PINS 150 }; 151 152 #define I915_GEM_GPU_DOMAINS \ 153 (I915_GEM_DOMAIN_RENDER | \ 154 I915_GEM_DOMAIN_SAMPLER | \ 155 I915_GEM_DOMAIN_COMMAND | \ 156 I915_GEM_DOMAIN_INSTRUCTION | \ 157 I915_GEM_DOMAIN_VERTEX) 158 159 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 160 161 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 162 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 163 if ((intel_encoder)->base.crtc == (__crtc)) 164 165 struct drm_i915_private; 166 167 enum intel_dpll_id { 168 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 169 /* real shared dpll ids must be >= 0 */ 170 DPLL_ID_PCH_PLL_A, 171 DPLL_ID_PCH_PLL_B, 172 }; 173 #define I915_NUM_PLLS 2 174 175 struct intel_dpll_hw_state { 176 uint32_t dpll; 177 uint32_t dpll_md; 178 uint32_t fp0; 179 uint32_t fp1; 180 }; 181 182 struct intel_shared_dpll { 183 int refcount; /* count of number of CRTCs sharing this PLL */ 184 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 185 bool on; /* is the PLL actually active? Disabled during modeset */ 186 const char *name; 187 /* should match the index in the dev_priv->shared_dplls array */ 188 enum intel_dpll_id id; 189 struct intel_dpll_hw_state hw_state; 190 void (*mode_set)(struct drm_i915_private *dev_priv, 191 struct intel_shared_dpll *pll); 192 void (*enable)(struct drm_i915_private *dev_priv, 193 struct intel_shared_dpll *pll); 194 void (*disable)(struct drm_i915_private *dev_priv, 195 struct intel_shared_dpll *pll); 196 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 197 struct intel_shared_dpll *pll, 198 struct intel_dpll_hw_state *hw_state); 199 }; 200 201 /* Used by dp and fdi links */ 202 struct intel_link_m_n { 203 uint32_t tu; 204 uint32_t gmch_m; 205 uint32_t gmch_n; 206 uint32_t link_m; 207 uint32_t link_n; 208 }; 209 210 void intel_link_compute_m_n(int bpp, int nlanes, 211 int pixel_clock, int link_clock, 212 struct intel_link_m_n *m_n); 213 214 struct intel_ddi_plls { 215 int spll_refcount; 216 int wrpll1_refcount; 217 int wrpll2_refcount; 218 }; 219 220 /* Interface history: 221 * 222 * 1.1: Original. 223 * 1.2: Add Power Management 224 * 1.3: Add vblank support 225 * 1.4: Fix cmdbuffer path, add heap destroy 226 * 1.5: Add vblank pipe configuration 227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 228 * - Support vertical blank on secondary display pipe 229 */ 230 #define DRIVER_MAJOR 1 231 #define DRIVER_MINOR 6 232 #define DRIVER_PATCHLEVEL 0 233 234 #define WATCH_LISTS 0 235 #define WATCH_GTT 0 236 237 #define I915_GEM_PHYS_CURSOR_0 1 238 #define I915_GEM_PHYS_CURSOR_1 2 239 #define I915_GEM_PHYS_OVERLAY_REGS 3 240 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 241 242 struct drm_i915_gem_phys_object { 243 int id; 244 struct page **page_list; 245 drm_dma_handle_t *handle; 246 struct drm_i915_gem_object *cur_obj; 247 }; 248 249 struct opregion_header; 250 struct opregion_acpi; 251 struct opregion_swsci; 252 struct opregion_asle; 253 254 struct intel_opregion { 255 struct opregion_header __iomem *header; 256 struct opregion_acpi __iomem *acpi; 257 struct opregion_swsci __iomem *swsci; 258 u32 swsci_gbda_sub_functions; 259 u32 swsci_sbcb_sub_functions; 260 struct opregion_asle __iomem *asle; 261 void __iomem *vbt; 262 u32 __iomem *lid_state; 263 struct work_struct asle_work; 264 }; 265 #define OPREGION_SIZE (8*1024) 266 267 struct intel_overlay; 268 struct intel_overlay_error_state; 269 270 struct drm_i915_master_private { 271 drm_local_map_t *sarea; 272 struct _drm_i915_sarea *sarea_priv; 273 }; 274 #define I915_FENCE_REG_NONE -1 275 #define I915_MAX_NUM_FENCES 32 276 /* 32 fences + sign bit for FENCE_REG_NONE */ 277 #define I915_MAX_NUM_FENCE_BITS 6 278 279 struct drm_i915_fence_reg { 280 struct list_head lru_list; 281 struct drm_i915_gem_object *obj; 282 int pin_count; 283 }; 284 285 struct sdvo_device_mapping { 286 u8 initialized; 287 u8 dvo_port; 288 u8 slave_addr; 289 u8 dvo_wiring; 290 u8 i2c_pin; 291 u8 ddc_pin; 292 }; 293 294 struct intel_display_error_state; 295 296 struct drm_i915_error_state { 297 struct kref ref; 298 u32 eir; 299 u32 pgtbl_er; 300 u32 ier; 301 u32 ccid; 302 u32 derrmr; 303 u32 forcewake; 304 bool waiting[I915_NUM_RINGS]; 305 u32 pipestat[I915_MAX_PIPES]; 306 u32 tail[I915_NUM_RINGS]; 307 u32 head[I915_NUM_RINGS]; 308 u32 ctl[I915_NUM_RINGS]; 309 u32 ipeir[I915_NUM_RINGS]; 310 u32 ipehr[I915_NUM_RINGS]; 311 u32 instdone[I915_NUM_RINGS]; 312 u32 acthd[I915_NUM_RINGS]; 313 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 314 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 315 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 316 /* our own tracking of ring head and tail */ 317 u32 cpu_ring_head[I915_NUM_RINGS]; 318 u32 cpu_ring_tail[I915_NUM_RINGS]; 319 u32 error; /* gen6+ */ 320 u32 err_int; /* gen7 */ 321 u32 bbstate[I915_NUM_RINGS]; 322 u32 instpm[I915_NUM_RINGS]; 323 u32 instps[I915_NUM_RINGS]; 324 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 325 u32 seqno[I915_NUM_RINGS]; 326 u64 bbaddr[I915_NUM_RINGS]; 327 u32 fault_reg[I915_NUM_RINGS]; 328 u32 done_reg; 329 u32 faddr[I915_NUM_RINGS]; 330 u64 fence[I915_MAX_NUM_FENCES]; 331 struct timeval time; 332 struct drm_i915_error_ring { 333 bool valid; 334 struct drm_i915_error_object { 335 int page_count; 336 u32 gtt_offset; 337 u32 *pages[0]; 338 } *ringbuffer, *batchbuffer, *ctx; 339 struct drm_i915_error_request { 340 long jiffies; 341 u32 seqno; 342 u32 tail; 343 } *requests; 344 int num_requests; 345 } ring[I915_NUM_RINGS]; 346 struct drm_i915_error_buffer { 347 u32 size; 348 u32 name; 349 u32 rseqno, wseqno; 350 u32 gtt_offset; 351 u32 read_domains; 352 u32 write_domain; 353 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 354 s32 pinned:2; 355 u32 tiling:2; 356 u32 dirty:1; 357 u32 purgeable:1; 358 s32 ring:4; 359 u32 cache_level:3; 360 } **active_bo, **pinned_bo; 361 u32 *active_bo_count, *pinned_bo_count; 362 struct intel_overlay_error_state *overlay; 363 struct intel_display_error_state *display; 364 int hangcheck_score[I915_NUM_RINGS]; 365 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; 366 }; 367 368 struct intel_connector; 369 struct intel_crtc_config; 370 struct intel_crtc; 371 struct intel_limit; 372 struct dpll; 373 374 struct drm_i915_display_funcs { 375 bool (*fbc_enabled)(struct drm_device *dev); 376 void (*enable_fbc)(struct drm_crtc *crtc); 377 void (*disable_fbc)(struct drm_device *dev); 378 int (*get_display_clock_speed)(struct drm_device *dev); 379 int (*get_fifo_size)(struct drm_device *dev, int plane); 380 /** 381 * find_dpll() - Find the best values for the PLL 382 * @limit: limits for the PLL 383 * @crtc: current CRTC 384 * @target: target frequency in kHz 385 * @refclk: reference clock frequency in kHz 386 * @match_clock: if provided, @best_clock P divider must 387 * match the P divider from @match_clock 388 * used for LVDS downclocking 389 * @best_clock: best PLL values found 390 * 391 * Returns true on success, false on failure. 392 */ 393 bool (*find_dpll)(const struct intel_limit *limit, 394 struct drm_crtc *crtc, 395 int target, int refclk, 396 struct dpll *match_clock, 397 struct dpll *best_clock); 398 void (*update_wm)(struct drm_crtc *crtc); 399 void (*update_sprite_wm)(struct drm_plane *plane, 400 struct drm_crtc *crtc, 401 uint32_t sprite_width, int pixel_size, 402 bool enable, bool scaled); 403 void (*modeset_global_resources)(struct drm_device *dev); 404 /* Returns the active state of the crtc, and if the crtc is active, 405 * fills out the pipe-config with the hw state. */ 406 bool (*get_pipe_config)(struct intel_crtc *, 407 struct intel_crtc_config *); 408 int (*crtc_mode_set)(struct drm_crtc *crtc, 409 int x, int y, 410 struct drm_framebuffer *old_fb); 411 void (*crtc_enable)(struct drm_crtc *crtc); 412 void (*crtc_disable)(struct drm_crtc *crtc); 413 void (*off)(struct drm_crtc *crtc); 414 void (*write_eld)(struct drm_connector *connector, 415 struct drm_crtc *crtc, 416 struct drm_display_mode *mode); 417 void (*fdi_link_train)(struct drm_crtc *crtc); 418 void (*init_clock_gating)(struct drm_device *dev); 419 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 420 struct drm_framebuffer *fb, 421 struct drm_i915_gem_object *obj, 422 uint32_t flags); 423 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 424 int x, int y); 425 void (*hpd_irq_setup)(struct drm_device *dev); 426 /* clock updates for mode set */ 427 /* cursor updates */ 428 /* render clock increase/decrease */ 429 /* display clock increase/decrease */ 430 /* pll clock increase/decrease */ 431 432 int (*setup_backlight)(struct intel_connector *connector); 433 uint32_t (*get_backlight)(struct intel_connector *connector); 434 void (*set_backlight)(struct intel_connector *connector, 435 uint32_t level); 436 void (*disable_backlight)(struct intel_connector *connector); 437 void (*enable_backlight)(struct intel_connector *connector); 438 }; 439 440 struct intel_uncore_funcs { 441 void (*force_wake_get)(struct drm_i915_private *dev_priv, 442 int fw_engine); 443 void (*force_wake_put)(struct drm_i915_private *dev_priv, 444 int fw_engine); 445 446 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 447 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 448 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 449 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 450 451 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 452 uint8_t val, bool trace); 453 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 454 uint16_t val, bool trace); 455 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 456 uint32_t val, bool trace); 457 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 458 uint64_t val, bool trace); 459 }; 460 461 struct intel_uncore { 462 spinlock_t lock; /** lock is also taken in irq contexts. */ 463 464 struct intel_uncore_funcs funcs; 465 466 unsigned fifo_count; 467 unsigned forcewake_count; 468 469 unsigned fw_rendercount; 470 unsigned fw_mediacount; 471 472 struct delayed_work force_wake_work; 473 }; 474 475 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 476 func(is_mobile) sep \ 477 func(is_i85x) sep \ 478 func(is_i915g) sep \ 479 func(is_i945gm) sep \ 480 func(is_g33) sep \ 481 func(need_gfx_hws) sep \ 482 func(is_g4x) sep \ 483 func(is_pineview) sep \ 484 func(is_broadwater) sep \ 485 func(is_crestline) sep \ 486 func(is_ivybridge) sep \ 487 func(is_valleyview) sep \ 488 func(is_haswell) sep \ 489 func(is_preliminary) sep \ 490 func(has_fbc) sep \ 491 func(has_pipe_cxsr) sep \ 492 func(has_hotplug) sep \ 493 func(cursor_needs_physical) sep \ 494 func(has_overlay) sep \ 495 func(overlay_needs_physical) sep \ 496 func(supports_tv) sep \ 497 func(has_llc) sep \ 498 func(has_ddi) sep \ 499 func(has_fpga_dbg) 500 501 #define DEFINE_FLAG(name) u8 name:1 502 #define SEP_SEMICOLON ; 503 504 struct intel_device_info { 505 u32 display_mmio_offset; 506 u8 num_pipes:3; 507 u8 gen; 508 u8 ring_mask; /* Rings supported by the HW */ 509 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 510 }; 511 512 #undef DEFINE_FLAG 513 #undef SEP_SEMICOLON 514 515 enum i915_cache_level { 516 I915_CACHE_NONE = 0, 517 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 518 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 519 caches, eg sampler/render caches, and the 520 large Last-Level-Cache. LLC is coherent with 521 the CPU, but L3 is only visible to the GPU. */ 522 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 523 }; 524 525 typedef uint32_t gen6_gtt_pte_t; 526 527 struct i915_address_space { 528 struct drm_mm mm; 529 struct drm_device *dev; 530 struct list_head global_link; 531 unsigned long start; /* Start offset always 0 for dri2 */ 532 size_t total; /* size addr space maps (ex. 2GB for ggtt) */ 533 534 struct { 535 dma_addr_t addr; 536 struct page *page; 537 } scratch; 538 539 /** 540 * List of objects currently involved in rendering. 541 * 542 * Includes buffers having the contents of their GPU caches 543 * flushed, not necessarily primitives. last_rendering_seqno 544 * represents when the rendering involved will be completed. 545 * 546 * A reference is held on the buffer while on this list. 547 */ 548 struct list_head active_list; 549 550 /** 551 * LRU list of objects which are not in the ringbuffer and 552 * are ready to unbind, but are still in the GTT. 553 * 554 * last_rendering_seqno is 0 while an object is in this list. 555 * 556 * A reference is not held on the buffer while on this list, 557 * as merely being GTT-bound shouldn't prevent its being 558 * freed, and we'll pull it off the list in the free path. 559 */ 560 struct list_head inactive_list; 561 562 /* FIXME: Need a more generic return type */ 563 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 564 enum i915_cache_level level, 565 bool valid); /* Create a valid PTE */ 566 void (*clear_range)(struct i915_address_space *vm, 567 unsigned int first_entry, 568 unsigned int num_entries, 569 bool use_scratch); 570 void (*insert_entries)(struct i915_address_space *vm, 571 struct sg_table *st, 572 unsigned int first_entry, 573 enum i915_cache_level cache_level); 574 void (*cleanup)(struct i915_address_space *vm); 575 }; 576 577 /* The Graphics Translation Table is the way in which GEN hardware translates a 578 * Graphics Virtual Address into a Physical Address. In addition to the normal 579 * collateral associated with any va->pa translations GEN hardware also has a 580 * portion of the GTT which can be mapped by the CPU and remain both coherent 581 * and correct (in cases like swizzling). That region is referred to as GMADR in 582 * the spec. 583 */ 584 struct i915_gtt { 585 struct i915_address_space base; 586 size_t stolen_size; /* Total size of stolen memory */ 587 588 unsigned long mappable_end; /* End offset that we can CPU map */ 589 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 590 phys_addr_t mappable_base; /* PA of our GMADR */ 591 592 /** "Graphics Stolen Memory" holds the global PTEs */ 593 void __iomem *gsm; 594 595 bool do_idle_maps; 596 597 int mtrr; 598 599 /* global gtt ops */ 600 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 601 size_t *stolen, phys_addr_t *mappable_base, 602 unsigned long *mappable_end); 603 }; 604 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 605 606 struct i915_hw_ppgtt { 607 struct i915_address_space base; 608 unsigned num_pd_entries; 609 union { 610 struct page **pt_pages; 611 struct page *gen8_pt_pages; 612 }; 613 struct page *pd_pages; 614 int num_pd_pages; 615 int num_pt_pages; 616 union { 617 uint32_t pd_offset; 618 dma_addr_t pd_dma_addr[4]; 619 }; 620 union { 621 dma_addr_t *pt_dma_addr; 622 dma_addr_t *gen8_pt_dma_addr[4]; 623 }; 624 int (*enable)(struct drm_device *dev); 625 }; 626 627 /** 628 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 629 * VMA's presence cannot be guaranteed before binding, or after unbinding the 630 * object into/from the address space. 631 * 632 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 633 * will always be <= an objects lifetime. So object refcounting should cover us. 634 */ 635 struct i915_vma { 636 struct drm_mm_node node; 637 struct drm_i915_gem_object *obj; 638 struct i915_address_space *vm; 639 640 /** This object's place on the active/inactive lists */ 641 struct list_head mm_list; 642 643 struct list_head vma_link; /* Link in the object's VMA list */ 644 645 /** This vma's place in the batchbuffer or on the eviction list */ 646 struct list_head exec_list; 647 648 /** 649 * Used for performing relocations during execbuffer insertion. 650 */ 651 struct hlist_node exec_node; 652 unsigned long exec_handle; 653 struct drm_i915_gem_exec_object2 *exec_entry; 654 655 }; 656 657 struct i915_ctx_hang_stats { 658 /* This context had batch pending when hang was declared */ 659 unsigned batch_pending; 660 661 /* This context had batch active when hang was declared */ 662 unsigned batch_active; 663 664 /* Time when this context was last blamed for a GPU reset */ 665 unsigned long guilty_ts; 666 667 /* This context is banned to submit more work */ 668 bool banned; 669 }; 670 671 /* This must match up with the value previously used for execbuf2.rsvd1. */ 672 #define DEFAULT_CONTEXT_ID 0 673 struct i915_hw_context { 674 struct kref ref; 675 int id; 676 bool is_initialized; 677 uint8_t remap_slice; 678 struct drm_i915_file_private *file_priv; 679 struct intel_ring_buffer *ring; 680 struct drm_i915_gem_object *obj; 681 struct i915_ctx_hang_stats hang_stats; 682 683 struct list_head link; 684 }; 685 686 struct i915_fbc { 687 unsigned long size; 688 unsigned int fb_id; 689 enum plane plane; 690 int y; 691 692 struct drm_mm_node *compressed_fb; 693 struct drm_mm_node *compressed_llb; 694 695 struct intel_fbc_work { 696 struct delayed_work work; 697 struct drm_crtc *crtc; 698 struct drm_framebuffer *fb; 699 } *fbc_work; 700 701 enum no_fbc_reason { 702 FBC_OK, /* FBC is enabled */ 703 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 704 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 705 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 706 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 707 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 708 FBC_BAD_PLANE, /* fbc not supported on plane */ 709 FBC_NOT_TILED, /* buffer not tiled */ 710 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 711 FBC_MODULE_PARAM, 712 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 713 } no_fbc_reason; 714 }; 715 716 struct i915_psr { 717 bool sink_support; 718 bool source_ok; 719 }; 720 721 enum intel_pch { 722 PCH_NONE = 0, /* No PCH present */ 723 PCH_IBX, /* Ibexpeak PCH */ 724 PCH_CPT, /* Cougarpoint PCH */ 725 PCH_LPT, /* Lynxpoint PCH */ 726 PCH_NOP, 727 }; 728 729 enum intel_sbi_destination { 730 SBI_ICLK, 731 SBI_MPHY, 732 }; 733 734 #define QUIRK_PIPEA_FORCE (1<<0) 735 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 736 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 737 738 struct intel_fbdev; 739 struct intel_fbc_work; 740 741 struct intel_gmbus { 742 struct i2c_adapter adapter; 743 u32 force_bit; 744 u32 reg0; 745 u32 gpio_reg; 746 struct i2c_algo_bit_data bit_algo; 747 struct drm_i915_private *dev_priv; 748 }; 749 750 struct i915_suspend_saved_registers { 751 u8 saveLBB; 752 u32 saveDSPACNTR; 753 u32 saveDSPBCNTR; 754 u32 saveDSPARB; 755 u32 savePIPEACONF; 756 u32 savePIPEBCONF; 757 u32 savePIPEASRC; 758 u32 savePIPEBSRC; 759 u32 saveFPA0; 760 u32 saveFPA1; 761 u32 saveDPLL_A; 762 u32 saveDPLL_A_MD; 763 u32 saveHTOTAL_A; 764 u32 saveHBLANK_A; 765 u32 saveHSYNC_A; 766 u32 saveVTOTAL_A; 767 u32 saveVBLANK_A; 768 u32 saveVSYNC_A; 769 u32 saveBCLRPAT_A; 770 u32 saveTRANSACONF; 771 u32 saveTRANS_HTOTAL_A; 772 u32 saveTRANS_HBLANK_A; 773 u32 saveTRANS_HSYNC_A; 774 u32 saveTRANS_VTOTAL_A; 775 u32 saveTRANS_VBLANK_A; 776 u32 saveTRANS_VSYNC_A; 777 u32 savePIPEASTAT; 778 u32 saveDSPASTRIDE; 779 u32 saveDSPASIZE; 780 u32 saveDSPAPOS; 781 u32 saveDSPAADDR; 782 u32 saveDSPASURF; 783 u32 saveDSPATILEOFF; 784 u32 savePFIT_PGM_RATIOS; 785 u32 saveBLC_HIST_CTL; 786 u32 saveBLC_PWM_CTL; 787 u32 saveBLC_PWM_CTL2; 788 u32 saveBLC_HIST_CTL_B; 789 u32 saveBLC_CPU_PWM_CTL; 790 u32 saveBLC_CPU_PWM_CTL2; 791 u32 saveFPB0; 792 u32 saveFPB1; 793 u32 saveDPLL_B; 794 u32 saveDPLL_B_MD; 795 u32 saveHTOTAL_B; 796 u32 saveHBLANK_B; 797 u32 saveHSYNC_B; 798 u32 saveVTOTAL_B; 799 u32 saveVBLANK_B; 800 u32 saveVSYNC_B; 801 u32 saveBCLRPAT_B; 802 u32 saveTRANSBCONF; 803 u32 saveTRANS_HTOTAL_B; 804 u32 saveTRANS_HBLANK_B; 805 u32 saveTRANS_HSYNC_B; 806 u32 saveTRANS_VTOTAL_B; 807 u32 saveTRANS_VBLANK_B; 808 u32 saveTRANS_VSYNC_B; 809 u32 savePIPEBSTAT; 810 u32 saveDSPBSTRIDE; 811 u32 saveDSPBSIZE; 812 u32 saveDSPBPOS; 813 u32 saveDSPBADDR; 814 u32 saveDSPBSURF; 815 u32 saveDSPBTILEOFF; 816 u32 saveVGA0; 817 u32 saveVGA1; 818 u32 saveVGA_PD; 819 u32 saveVGACNTRL; 820 u32 saveADPA; 821 u32 saveLVDS; 822 u32 savePP_ON_DELAYS; 823 u32 savePP_OFF_DELAYS; 824 u32 saveDVOA; 825 u32 saveDVOB; 826 u32 saveDVOC; 827 u32 savePP_ON; 828 u32 savePP_OFF; 829 u32 savePP_CONTROL; 830 u32 savePP_DIVISOR; 831 u32 savePFIT_CONTROL; 832 u32 save_palette_a[256]; 833 u32 save_palette_b[256]; 834 u32 saveDPFC_CB_BASE; 835 u32 saveFBC_CFB_BASE; 836 u32 saveFBC_LL_BASE; 837 u32 saveFBC_CONTROL; 838 u32 saveFBC_CONTROL2; 839 u32 saveIER; 840 u32 saveIIR; 841 u32 saveIMR; 842 u32 saveDEIER; 843 u32 saveDEIMR; 844 u32 saveGTIER; 845 u32 saveGTIMR; 846 u32 saveFDI_RXA_IMR; 847 u32 saveFDI_RXB_IMR; 848 u32 saveCACHE_MODE_0; 849 u32 saveMI_ARB_STATE; 850 u32 saveSWF0[16]; 851 u32 saveSWF1[16]; 852 u32 saveSWF2[3]; 853 u8 saveMSR; 854 u8 saveSR[8]; 855 u8 saveGR[25]; 856 u8 saveAR_INDEX; 857 u8 saveAR[21]; 858 u8 saveDACMASK; 859 u8 saveCR[37]; 860 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 861 u32 saveCURACNTR; 862 u32 saveCURAPOS; 863 u32 saveCURABASE; 864 u32 saveCURBCNTR; 865 u32 saveCURBPOS; 866 u32 saveCURBBASE; 867 u32 saveCURSIZE; 868 u32 saveDP_B; 869 u32 saveDP_C; 870 u32 saveDP_D; 871 u32 savePIPEA_GMCH_DATA_M; 872 u32 savePIPEB_GMCH_DATA_M; 873 u32 savePIPEA_GMCH_DATA_N; 874 u32 savePIPEB_GMCH_DATA_N; 875 u32 savePIPEA_DP_LINK_M; 876 u32 savePIPEB_DP_LINK_M; 877 u32 savePIPEA_DP_LINK_N; 878 u32 savePIPEB_DP_LINK_N; 879 u32 saveFDI_RXA_CTL; 880 u32 saveFDI_TXA_CTL; 881 u32 saveFDI_RXB_CTL; 882 u32 saveFDI_TXB_CTL; 883 u32 savePFA_CTL_1; 884 u32 savePFB_CTL_1; 885 u32 savePFA_WIN_SZ; 886 u32 savePFB_WIN_SZ; 887 u32 savePFA_WIN_POS; 888 u32 savePFB_WIN_POS; 889 u32 savePCH_DREF_CONTROL; 890 u32 saveDISP_ARB_CTL; 891 u32 savePIPEA_DATA_M1; 892 u32 savePIPEA_DATA_N1; 893 u32 savePIPEA_LINK_M1; 894 u32 savePIPEA_LINK_N1; 895 u32 savePIPEB_DATA_M1; 896 u32 savePIPEB_DATA_N1; 897 u32 savePIPEB_LINK_M1; 898 u32 savePIPEB_LINK_N1; 899 u32 saveMCHBAR_RENDER_STANDBY; 900 u32 savePCH_PORT_HOTPLUG; 901 }; 902 903 struct intel_gen6_power_mgmt { 904 /* work and pm_iir are protected by dev_priv->irq_lock */ 905 struct work_struct work; 906 u32 pm_iir; 907 908 /* The below variables an all the rps hw state are protected by 909 * dev->struct mutext. */ 910 u8 cur_delay; 911 u8 min_delay; 912 u8 max_delay; 913 u8 rpe_delay; 914 u8 rp1_delay; 915 u8 rp0_delay; 916 u8 hw_max; 917 918 int last_adj; 919 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 920 921 bool enabled; 922 struct delayed_work delayed_resume_work; 923 924 /* 925 * Protects RPS/RC6 register access and PCU communication. 926 * Must be taken after struct_mutex if nested. 927 */ 928 struct mutex hw_lock; 929 }; 930 931 /* defined intel_pm.c */ 932 extern spinlock_t mchdev_lock; 933 934 struct intel_ilk_power_mgmt { 935 u8 cur_delay; 936 u8 min_delay; 937 u8 max_delay; 938 u8 fmax; 939 u8 fstart; 940 941 u64 last_count1; 942 unsigned long last_time1; 943 unsigned long chipset_power; 944 u64 last_count2; 945 struct timespec last_time2; 946 unsigned long gfx_power; 947 u8 corr; 948 949 int c_m; 950 int r_t; 951 952 struct drm_i915_gem_object *pwrctx; 953 struct drm_i915_gem_object *renderctx; 954 }; 955 956 /* Power well structure for haswell */ 957 struct i915_power_well { 958 const char *name; 959 bool always_on; 960 /* power well enable/disable usage count */ 961 int count; 962 unsigned long domains; 963 void *data; 964 void (*set)(struct drm_device *dev, struct i915_power_well *power_well, 965 bool enable); 966 bool (*is_enabled)(struct drm_device *dev, 967 struct i915_power_well *power_well); 968 }; 969 970 struct i915_power_domains { 971 /* 972 * Power wells needed for initialization at driver init and suspend 973 * time are on. They are kept on until after the first modeset. 974 */ 975 bool init_power_on; 976 int power_well_count; 977 978 struct mutex lock; 979 int domain_use_count[POWER_DOMAIN_NUM]; 980 struct i915_power_well *power_wells; 981 }; 982 983 struct i915_dri1_state { 984 unsigned allow_batchbuffer : 1; 985 u32 __iomem *gfx_hws_cpu_addr; 986 987 unsigned int cpp; 988 int back_offset; 989 int front_offset; 990 int current_page; 991 int page_flipping; 992 993 uint32_t counter; 994 }; 995 996 struct i915_ums_state { 997 /** 998 * Flag if the X Server, and thus DRM, is not currently in 999 * control of the device. 1000 * 1001 * This is set between LeaveVT and EnterVT. It needs to be 1002 * replaced with a semaphore. It also needs to be 1003 * transitioned away from for kernel modesetting. 1004 */ 1005 int mm_suspended; 1006 }; 1007 1008 #define MAX_L3_SLICES 2 1009 struct intel_l3_parity { 1010 u32 *remap_info[MAX_L3_SLICES]; 1011 struct work_struct error_work; 1012 int which_slice; 1013 }; 1014 1015 struct i915_gem_mm { 1016 /** Memory allocator for GTT stolen memory */ 1017 struct drm_mm stolen; 1018 /** List of all objects in gtt_space. Used to restore gtt 1019 * mappings on resume */ 1020 struct list_head bound_list; 1021 /** 1022 * List of objects which are not bound to the GTT (thus 1023 * are idle and not used by the GPU) but still have 1024 * (presumably uncached) pages still attached. 1025 */ 1026 struct list_head unbound_list; 1027 1028 /** Usable portion of the GTT for GEM */ 1029 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1030 1031 /** PPGTT used for aliasing the PPGTT with the GTT */ 1032 struct i915_hw_ppgtt *aliasing_ppgtt; 1033 1034 struct shrinker inactive_shrinker; 1035 bool shrinker_no_lock_stealing; 1036 1037 /** LRU list of objects with fence regs on them. */ 1038 struct list_head fence_list; 1039 1040 /** 1041 * We leave the user IRQ off as much as possible, 1042 * but this means that requests will finish and never 1043 * be retired once the system goes idle. Set a timer to 1044 * fire periodically while the ring is running. When it 1045 * fires, go retire requests. 1046 */ 1047 struct delayed_work retire_work; 1048 1049 /** 1050 * When we detect an idle GPU, we want to turn on 1051 * powersaving features. So once we see that there 1052 * are no more requests outstanding and no more 1053 * arrive within a small period of time, we fire 1054 * off the idle_work. 1055 */ 1056 struct delayed_work idle_work; 1057 1058 /** 1059 * Are we in a non-interruptible section of code like 1060 * modesetting? 1061 */ 1062 bool interruptible; 1063 1064 /** Bit 6 swizzling required for X tiling */ 1065 uint32_t bit_6_swizzle_x; 1066 /** Bit 6 swizzling required for Y tiling */ 1067 uint32_t bit_6_swizzle_y; 1068 1069 /* storage for physical objects */ 1070 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 1071 1072 /* accounting, useful for userland debugging */ 1073 spinlock_t object_stat_lock; 1074 size_t object_memory; 1075 u32 object_count; 1076 }; 1077 1078 struct drm_i915_error_state_buf { 1079 unsigned bytes; 1080 unsigned size; 1081 int err; 1082 u8 *buf; 1083 loff_t start; 1084 loff_t pos; 1085 }; 1086 1087 struct i915_error_state_file_priv { 1088 struct drm_device *dev; 1089 struct drm_i915_error_state *error; 1090 }; 1091 1092 struct i915_gpu_error { 1093 /* For hangcheck timer */ 1094 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1095 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1096 /* Hang gpu twice in this window and your context gets banned */ 1097 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1098 1099 struct timer_list hangcheck_timer; 1100 1101 /* For reset and error_state handling. */ 1102 spinlock_t lock; 1103 /* Protected by the above dev->gpu_error.lock. */ 1104 struct drm_i915_error_state *first_error; 1105 struct work_struct work; 1106 1107 1108 unsigned long missed_irq_rings; 1109 1110 /** 1111 * State variable controlling the reset flow and count 1112 * 1113 * This is a counter which gets incremented when reset is triggered, 1114 * and again when reset has been handled. So odd values (lowest bit set) 1115 * means that reset is in progress and even values that 1116 * (reset_counter >> 1):th reset was successfully completed. 1117 * 1118 * If reset is not completed succesfully, the I915_WEDGE bit is 1119 * set meaning that hardware is terminally sour and there is no 1120 * recovery. All waiters on the reset_queue will be woken when 1121 * that happens. 1122 * 1123 * This counter is used by the wait_seqno code to notice that reset 1124 * event happened and it needs to restart the entire ioctl (since most 1125 * likely the seqno it waited for won't ever signal anytime soon). 1126 * 1127 * This is important for lock-free wait paths, where no contended lock 1128 * naturally enforces the correct ordering between the bail-out of the 1129 * waiter and the gpu reset work code. 1130 */ 1131 atomic_t reset_counter; 1132 1133 #define I915_RESET_IN_PROGRESS_FLAG 1 1134 #define I915_WEDGED (1 << 31) 1135 1136 /** 1137 * Waitqueue to signal when the reset has completed. Used by clients 1138 * that wait for dev_priv->mm.wedged to settle. 1139 */ 1140 wait_queue_head_t reset_queue; 1141 1142 /* For gpu hang simulation. */ 1143 unsigned int stop_rings; 1144 1145 /* For missed irq/seqno simulation. */ 1146 unsigned int test_irq_rings; 1147 }; 1148 1149 enum modeset_restore { 1150 MODESET_ON_LID_OPEN, 1151 MODESET_DONE, 1152 MODESET_SUSPENDED, 1153 }; 1154 1155 struct ddi_vbt_port_info { 1156 uint8_t hdmi_level_shift; 1157 1158 uint8_t supports_dvi:1; 1159 uint8_t supports_hdmi:1; 1160 uint8_t supports_dp:1; 1161 }; 1162 1163 struct intel_vbt_data { 1164 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1165 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1166 1167 /* Feature bits */ 1168 unsigned int int_tv_support:1; 1169 unsigned int lvds_dither:1; 1170 unsigned int lvds_vbt:1; 1171 unsigned int int_crt_support:1; 1172 unsigned int lvds_use_ssc:1; 1173 unsigned int display_clock_mode:1; 1174 unsigned int fdi_rx_polarity_inverted:1; 1175 int lvds_ssc_freq; 1176 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1177 1178 /* eDP */ 1179 int edp_rate; 1180 int edp_lanes; 1181 int edp_preemphasis; 1182 int edp_vswing; 1183 bool edp_initialized; 1184 bool edp_support; 1185 int edp_bpp; 1186 struct edp_power_seq edp_pps; 1187 1188 struct { 1189 u16 pwm_freq_hz; 1190 bool active_low_pwm; 1191 } backlight; 1192 1193 /* MIPI DSI */ 1194 struct { 1195 u16 panel_id; 1196 } dsi; 1197 1198 int crt_ddc_pin; 1199 1200 int child_dev_num; 1201 union child_device_config *child_dev; 1202 1203 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1204 }; 1205 1206 enum intel_ddb_partitioning { 1207 INTEL_DDB_PART_1_2, 1208 INTEL_DDB_PART_5_6, /* IVB+ */ 1209 }; 1210 1211 struct intel_wm_level { 1212 bool enable; 1213 uint32_t pri_val; 1214 uint32_t spr_val; 1215 uint32_t cur_val; 1216 uint32_t fbc_val; 1217 }; 1218 1219 struct ilk_wm_values { 1220 uint32_t wm_pipe[3]; 1221 uint32_t wm_lp[3]; 1222 uint32_t wm_lp_spr[3]; 1223 uint32_t wm_linetime[3]; 1224 bool enable_fbc_wm; 1225 enum intel_ddb_partitioning partitioning; 1226 }; 1227 1228 /* 1229 * This struct tracks the state needed for the Package C8+ feature. 1230 * 1231 * Package states C8 and deeper are really deep PC states that can only be 1232 * reached when all the devices on the system allow it, so even if the graphics 1233 * device allows PC8+, it doesn't mean the system will actually get to these 1234 * states. 1235 * 1236 * Our driver only allows PC8+ when all the outputs are disabled, the power well 1237 * is disabled and the GPU is idle. When these conditions are met, we manually 1238 * do the other conditions: disable the interrupts, clocks and switch LCPLL 1239 * refclk to Fclk. 1240 * 1241 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1242 * the state of some registers, so when we come back from PC8+ we need to 1243 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1244 * need to take care of the registers kept by RC6. 1245 * 1246 * The interrupt disabling is part of the requirements. We can only leave the 1247 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we 1248 * can lock the machine. 1249 * 1250 * Ideally every piece of our code that needs PC8+ disabled would call 1251 * hsw_disable_package_c8, which would increment disable_count and prevent the 1252 * system from reaching PC8+. But we don't have a symmetric way to do this for 1253 * everything, so we have the requirements_met and gpu_idle variables. When we 1254 * switch requirements_met or gpu_idle to true we decrease disable_count, and 1255 * increase it in the opposite case. The requirements_met variable is true when 1256 * all the CRTCs, encoders and the power well are disabled. The gpu_idle 1257 * variable is true when the GPU is idle. 1258 * 1259 * In addition to everything, we only actually enable PC8+ if disable_count 1260 * stays at zero for at least some seconds. This is implemented with the 1261 * enable_work variable. We do this so we don't enable/disable PC8 dozens of 1262 * consecutive times when all screens are disabled and some background app 1263 * queries the state of our connectors, or we have some application constantly 1264 * waking up to use the GPU. Only after the enable_work function actually 1265 * enables PC8+ the "enable" variable will become true, which means that it can 1266 * be false even if disable_count is 0. 1267 * 1268 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1269 * goes back to false exactly before we reenable the IRQs. We use this variable 1270 * to check if someone is trying to enable/disable IRQs while they're supposed 1271 * to be disabled. This shouldn't happen and we'll print some error messages in 1272 * case it happens, but if it actually happens we'll also update the variables 1273 * inside struct regsave so when we restore the IRQs they will contain the 1274 * latest expected values. 1275 * 1276 * For more, read "Display Sequences for Package C8" on our documentation. 1277 */ 1278 struct i915_package_c8 { 1279 bool requirements_met; 1280 bool gpu_idle; 1281 bool irqs_disabled; 1282 /* Only true after the delayed work task actually enables it. */ 1283 bool enabled; 1284 int disable_count; 1285 struct mutex lock; 1286 struct delayed_work enable_work; 1287 1288 struct { 1289 uint32_t deimr; 1290 uint32_t sdeimr; 1291 uint32_t gtimr; 1292 uint32_t gtier; 1293 uint32_t gen6_pmimr; 1294 } regsave; 1295 }; 1296 1297 struct i915_runtime_pm { 1298 bool suspended; 1299 }; 1300 1301 enum intel_pipe_crc_source { 1302 INTEL_PIPE_CRC_SOURCE_NONE, 1303 INTEL_PIPE_CRC_SOURCE_PLANE1, 1304 INTEL_PIPE_CRC_SOURCE_PLANE2, 1305 INTEL_PIPE_CRC_SOURCE_PF, 1306 INTEL_PIPE_CRC_SOURCE_PIPE, 1307 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1308 INTEL_PIPE_CRC_SOURCE_TV, 1309 INTEL_PIPE_CRC_SOURCE_DP_B, 1310 INTEL_PIPE_CRC_SOURCE_DP_C, 1311 INTEL_PIPE_CRC_SOURCE_DP_D, 1312 INTEL_PIPE_CRC_SOURCE_AUTO, 1313 INTEL_PIPE_CRC_SOURCE_MAX, 1314 }; 1315 1316 struct intel_pipe_crc_entry { 1317 uint32_t frame; 1318 uint32_t crc[5]; 1319 }; 1320 1321 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1322 struct intel_pipe_crc { 1323 spinlock_t lock; 1324 bool opened; /* exclusive access to the result file */ 1325 struct intel_pipe_crc_entry *entries; 1326 enum intel_pipe_crc_source source; 1327 int head, tail; 1328 wait_queue_head_t wq; 1329 }; 1330 1331 typedef struct drm_i915_private { 1332 struct drm_device *dev; 1333 struct kmem_cache *slab; 1334 1335 const struct intel_device_info *info; 1336 1337 int relative_constants_mode; 1338 1339 void __iomem *regs; 1340 1341 struct intel_uncore uncore; 1342 1343 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 1344 1345 1346 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1347 * controller on different i2c buses. */ 1348 struct mutex gmbus_mutex; 1349 1350 /** 1351 * Base address of the gmbus and gpio block. 1352 */ 1353 uint32_t gpio_mmio_base; 1354 1355 wait_queue_head_t gmbus_wait_queue; 1356 1357 struct pci_dev *bridge_dev; 1358 struct intel_ring_buffer ring[I915_NUM_RINGS]; 1359 uint32_t last_seqno, next_seqno; 1360 1361 drm_dma_handle_t *status_page_dmah; 1362 struct resource mch_res; 1363 1364 atomic_t irq_received; 1365 1366 /* protects the irq masks */ 1367 spinlock_t irq_lock; 1368 1369 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1370 struct pm_qos_request pm_qos; 1371 1372 /* DPIO indirect register protection */ 1373 struct mutex dpio_lock; 1374 1375 /** Cached value of IMR to avoid reads in updating the bitfield */ 1376 union { 1377 u32 irq_mask; 1378 u32 de_irq_mask[I915_MAX_PIPES]; 1379 }; 1380 u32 gt_irq_mask; 1381 u32 pm_irq_mask; 1382 1383 struct work_struct hotplug_work; 1384 bool enable_hotplug_processing; 1385 struct { 1386 unsigned long hpd_last_jiffies; 1387 int hpd_cnt; 1388 enum { 1389 HPD_ENABLED = 0, 1390 HPD_DISABLED = 1, 1391 HPD_MARK_DISABLED = 2 1392 } hpd_mark; 1393 } hpd_stats[HPD_NUM_PINS]; 1394 u32 hpd_event_bits; 1395 struct timer_list hotplug_reenable_timer; 1396 1397 int num_plane; 1398 1399 struct i915_fbc fbc; 1400 struct intel_opregion opregion; 1401 struct intel_vbt_data vbt; 1402 1403 /* overlay */ 1404 struct intel_overlay *overlay; 1405 1406 /* backlight registers and fields in struct intel_panel */ 1407 spinlock_t backlight_lock; 1408 1409 /* LVDS info */ 1410 bool no_aux_handshake; 1411 1412 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1413 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1414 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1415 1416 unsigned int fsb_freq, mem_freq, is_ddr3; 1417 1418 /** 1419 * wq - Driver workqueue for GEM. 1420 * 1421 * NOTE: Work items scheduled here are not allowed to grab any modeset 1422 * locks, for otherwise the flushing done in the pageflip code will 1423 * result in deadlocks. 1424 */ 1425 struct workqueue_struct *wq; 1426 1427 /* Display functions */ 1428 struct drm_i915_display_funcs display; 1429 1430 /* PCH chipset type */ 1431 enum intel_pch pch_type; 1432 unsigned short pch_id; 1433 1434 unsigned long quirks; 1435 1436 enum modeset_restore modeset_restore; 1437 struct mutex modeset_restore_lock; 1438 1439 struct list_head vm_list; /* Global list of all address spaces */ 1440 struct i915_gtt gtt; /* VMA representing the global address space */ 1441 1442 struct i915_gem_mm mm; 1443 1444 /* Kernel Modesetting */ 1445 1446 struct sdvo_device_mapping sdvo_mappings[2]; 1447 1448 struct drm_crtc *plane_to_crtc_mapping[3]; 1449 struct drm_crtc *pipe_to_crtc_mapping[3]; 1450 wait_queue_head_t pending_flip_queue; 1451 1452 #ifdef CONFIG_DEBUG_FS 1453 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1454 #endif 1455 1456 int num_shared_dpll; 1457 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1458 struct intel_ddi_plls ddi_plls; 1459 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1460 1461 /* Reclocking support */ 1462 bool render_reclock_avail; 1463 bool lvds_downclock_avail; 1464 /* indicates the reduced downclock for LVDS*/ 1465 int lvds_downclock; 1466 u16 orig_clock; 1467 1468 bool mchbar_need_disable; 1469 1470 struct intel_l3_parity l3_parity; 1471 1472 /* Cannot be determined by PCIID. You must always read a register. */ 1473 size_t ellc_size; 1474 1475 /* gen6+ rps state */ 1476 struct intel_gen6_power_mgmt rps; 1477 1478 /* ilk-only ips/rps state. Everything in here is protected by the global 1479 * mchdev_lock in intel_pm.c */ 1480 struct intel_ilk_power_mgmt ips; 1481 1482 struct i915_power_domains power_domains; 1483 1484 struct i915_psr psr; 1485 1486 struct i915_gpu_error gpu_error; 1487 1488 struct drm_i915_gem_object *vlv_pctx; 1489 1490 #ifdef CONFIG_DRM_I915_FBDEV 1491 /* list of fbdev register on this device */ 1492 struct intel_fbdev *fbdev; 1493 #endif 1494 1495 /* 1496 * The console may be contended at resume, but we don't 1497 * want it to block on it. 1498 */ 1499 struct work_struct console_resume_work; 1500 1501 struct drm_property *broadcast_rgb_property; 1502 struct drm_property *force_audio_property; 1503 1504 uint32_t hw_context_size; 1505 struct list_head context_list; 1506 1507 u32 fdi_rx_config; 1508 1509 struct i915_suspend_saved_registers regfile; 1510 1511 struct { 1512 /* 1513 * Raw watermark latency values: 1514 * in 0.1us units for WM0, 1515 * in 0.5us units for WM1+. 1516 */ 1517 /* primary */ 1518 uint16_t pri_latency[5]; 1519 /* sprite */ 1520 uint16_t spr_latency[5]; 1521 /* cursor */ 1522 uint16_t cur_latency[5]; 1523 1524 /* current hardware state */ 1525 struct ilk_wm_values hw; 1526 } wm; 1527 1528 struct i915_package_c8 pc8; 1529 1530 struct i915_runtime_pm pm; 1531 1532 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1533 * here! */ 1534 struct i915_dri1_state dri1; 1535 /* Old ums support infrastructure, same warning applies. */ 1536 struct i915_ums_state ums; 1537 } drm_i915_private_t; 1538 1539 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1540 { 1541 return dev->dev_private; 1542 } 1543 1544 /* Iterate over initialised rings */ 1545 #define for_each_ring(ring__, dev_priv__, i__) \ 1546 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1547 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1548 1549 enum hdmi_force_audio { 1550 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1551 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1552 HDMI_AUDIO_AUTO, /* trust EDID */ 1553 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1554 }; 1555 1556 #define I915_GTT_OFFSET_NONE ((u32)-1) 1557 1558 struct drm_i915_gem_object_ops { 1559 /* Interface between the GEM object and its backing storage. 1560 * get_pages() is called once prior to the use of the associated set 1561 * of pages before to binding them into the GTT, and put_pages() is 1562 * called after we no longer need them. As we expect there to be 1563 * associated cost with migrating pages between the backing storage 1564 * and making them available for the GPU (e.g. clflush), we may hold 1565 * onto the pages after they are no longer referenced by the GPU 1566 * in case they may be used again shortly (for example migrating the 1567 * pages to a different memory domain within the GTT). put_pages() 1568 * will therefore most likely be called when the object itself is 1569 * being released or under memory pressure (where we attempt to 1570 * reap pages for the shrinker). 1571 */ 1572 int (*get_pages)(struct drm_i915_gem_object *); 1573 void (*put_pages)(struct drm_i915_gem_object *); 1574 }; 1575 1576 struct drm_i915_gem_object { 1577 struct drm_gem_object base; 1578 1579 const struct drm_i915_gem_object_ops *ops; 1580 1581 /** List of VMAs backed by this object */ 1582 struct list_head vma_list; 1583 1584 /** Stolen memory for this object, instead of being backed by shmem. */ 1585 struct drm_mm_node *stolen; 1586 struct list_head global_list; 1587 1588 struct list_head ring_list; 1589 /** Used in execbuf to temporarily hold a ref */ 1590 struct list_head obj_exec_link; 1591 1592 /** 1593 * This is set if the object is on the active lists (has pending 1594 * rendering and so a non-zero seqno), and is not set if it i s on 1595 * inactive (ready to be unbound) list. 1596 */ 1597 unsigned int active:1; 1598 1599 /** 1600 * This is set if the object has been written to since last bound 1601 * to the GTT 1602 */ 1603 unsigned int dirty:1; 1604 1605 /** 1606 * Fence register bits (if any) for this object. Will be set 1607 * as needed when mapped into the GTT. 1608 * Protected by dev->struct_mutex. 1609 */ 1610 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1611 1612 /** 1613 * Advice: are the backing pages purgeable? 1614 */ 1615 unsigned int madv:2; 1616 1617 /** 1618 * Current tiling mode for the object. 1619 */ 1620 unsigned int tiling_mode:2; 1621 /** 1622 * Whether the tiling parameters for the currently associated fence 1623 * register have changed. Note that for the purposes of tracking 1624 * tiling changes we also treat the unfenced register, the register 1625 * slot that the object occupies whilst it executes a fenced 1626 * command (such as BLT on gen2/3), as a "fence". 1627 */ 1628 unsigned int fence_dirty:1; 1629 1630 /** How many users have pinned this object in GTT space. The following 1631 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1632 * (via user_pin_count), execbuffer (objects are not allowed multiple 1633 * times for the same batchbuffer), and the framebuffer code. When 1634 * switching/pageflipping, the framebuffer code has at most two buffers 1635 * pinned per crtc. 1636 * 1637 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1638 * bits with absolutely no headroom. So use 4 bits. */ 1639 unsigned int pin_count:4; 1640 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1641 1642 /** 1643 * Is the object at the current location in the gtt mappable and 1644 * fenceable? Used to avoid costly recalculations. 1645 */ 1646 unsigned int map_and_fenceable:1; 1647 1648 /** 1649 * Whether the current gtt mapping needs to be mappable (and isn't just 1650 * mappable by accident). Track pin and fault separate for a more 1651 * accurate mappable working set. 1652 */ 1653 unsigned int fault_mappable:1; 1654 unsigned int pin_mappable:1; 1655 unsigned int pin_display:1; 1656 1657 /* 1658 * Is the GPU currently using a fence to access this buffer, 1659 */ 1660 unsigned int pending_fenced_gpu_access:1; 1661 unsigned int fenced_gpu_access:1; 1662 1663 unsigned int cache_level:3; 1664 1665 unsigned int has_aliasing_ppgtt_mapping:1; 1666 unsigned int has_global_gtt_mapping:1; 1667 unsigned int has_dma_mapping:1; 1668 1669 struct sg_table *pages; 1670 int pages_pin_count; 1671 1672 /* prime dma-buf support */ 1673 void *dma_buf_vmapping; 1674 int vmapping_count; 1675 1676 struct intel_ring_buffer *ring; 1677 1678 /** Breadcrumb of last rendering to the buffer. */ 1679 uint32_t last_read_seqno; 1680 uint32_t last_write_seqno; 1681 /** Breadcrumb of last fenced GPU access to the buffer. */ 1682 uint32_t last_fenced_seqno; 1683 1684 /** Current tiling stride for the object, if it's tiled. */ 1685 uint32_t stride; 1686 1687 /** References from framebuffers, locks out tiling changes. */ 1688 unsigned long framebuffer_references; 1689 1690 /** Record of address bit 17 of each page at last unbind. */ 1691 unsigned long *bit_17; 1692 1693 /** User space pin count and filp owning the pin */ 1694 unsigned long user_pin_count; 1695 struct drm_file *pin_filp; 1696 1697 /** for phy allocated objects */ 1698 struct drm_i915_gem_phys_object *phys_obj; 1699 }; 1700 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1701 1702 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1703 1704 /** 1705 * Request queue structure. 1706 * 1707 * The request queue allows us to note sequence numbers that have been emitted 1708 * and may be associated with active buffers to be retired. 1709 * 1710 * By keeping this list, we can avoid having to do questionable 1711 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1712 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1713 */ 1714 struct drm_i915_gem_request { 1715 /** On Which ring this request was generated */ 1716 struct intel_ring_buffer *ring; 1717 1718 /** GEM sequence number associated with this request. */ 1719 uint32_t seqno; 1720 1721 /** Position in the ringbuffer of the start of the request */ 1722 u32 head; 1723 1724 /** Position in the ringbuffer of the end of the request */ 1725 u32 tail; 1726 1727 /** Context related to this request */ 1728 struct i915_hw_context *ctx; 1729 1730 /** Batch buffer related to this request if any */ 1731 struct drm_i915_gem_object *batch_obj; 1732 1733 /** Time at which this request was emitted, in jiffies. */ 1734 unsigned long emitted_jiffies; 1735 1736 /** global list entry for this request */ 1737 struct list_head list; 1738 1739 struct drm_i915_file_private *file_priv; 1740 /** file_priv list entry for this request */ 1741 struct list_head client_list; 1742 }; 1743 1744 struct drm_i915_file_private { 1745 struct drm_i915_private *dev_priv; 1746 1747 struct { 1748 spinlock_t lock; 1749 struct list_head request_list; 1750 struct delayed_work idle_work; 1751 } mm; 1752 struct idr context_idr; 1753 1754 struct i915_ctx_hang_stats hang_stats; 1755 atomic_t rps_wait_boost; 1756 }; 1757 1758 #define INTEL_INFO(dev) (to_i915(dev)->info) 1759 1760 #define IS_I830(dev) ((dev)->pdev->device == 0x3577) 1761 #define IS_845G(dev) ((dev)->pdev->device == 0x2562) 1762 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1763 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) 1764 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1765 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) 1766 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) 1767 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1768 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1769 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1770 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) 1771 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1772 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) 1773 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) 1774 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1775 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1776 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) 1777 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1778 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ 1779 (dev)->pdev->device == 0x0152 || \ 1780 (dev)->pdev->device == 0x015a) 1781 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ 1782 (dev)->pdev->device == 0x0106 || \ 1783 (dev)->pdev->device == 0x010A) 1784 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1785 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1786 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) 1787 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1788 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 1789 ((dev)->pdev->device & 0xFF00) == 0x0C00) 1790 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 1791 (((dev)->pdev->device & 0xf) == 0x2 || \ 1792 ((dev)->pdev->device & 0xf) == 0x6 || \ 1793 ((dev)->pdev->device & 0xf) == 0xe)) 1794 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 1795 ((dev)->pdev->device & 0xFF00) == 0x0A00) 1796 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 1797 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 1798 ((dev)->pdev->device & 0x00F0) == 0x0020) 1799 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 1800 1801 /* 1802 * The genX designation typically refers to the render engine, so render 1803 * capability related checks should use IS_GEN, while display and other checks 1804 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1805 * chips, etc.). 1806 */ 1807 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1808 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1809 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1810 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1811 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1812 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1813 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 1814 1815 #define RENDER_RING (1<<RCS) 1816 #define BSD_RING (1<<VCS) 1817 #define BLT_RING (1<<BCS) 1818 #define VEBOX_RING (1<<VECS) 1819 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 1820 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 1821 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 1822 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1823 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) 1824 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1825 1826 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1827 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1828 1829 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1830 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1831 1832 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1833 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1834 1835 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1836 * rows, which changed the alignment requirements and fence programming. 1837 */ 1838 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1839 IS_I915GM(dev))) 1840 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1841 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1842 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1843 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1844 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1845 1846 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1847 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1848 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1849 1850 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 1851 1852 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 1853 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 1854 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1855 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ 1856 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev)) 1857 1858 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1859 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1860 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1861 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1862 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1863 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1864 1865 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 1866 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1867 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1868 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1869 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 1870 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1871 1872 /* DPF == dynamic parity feature */ 1873 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1874 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 1875 1876 #define GT_FREQUENCY_MULTIPLIER 50 1877 1878 #include "i915_trace.h" 1879 1880 extern const struct drm_ioctl_desc i915_ioctls[]; 1881 extern int i915_max_ioctl; 1882 extern unsigned int i915_fbpercrtc __always_unused; 1883 extern int i915_panel_ignore_lid __read_mostly; 1884 extern unsigned int i915_powersave __read_mostly; 1885 extern int i915_semaphores __read_mostly; 1886 extern unsigned int i915_lvds_downclock __read_mostly; 1887 extern int i915_lvds_channel_mode __read_mostly; 1888 extern int i915_panel_use_ssc __read_mostly; 1889 extern int i915_vbt_sdvo_panel_type __read_mostly; 1890 extern int i915_enable_rc6 __read_mostly; 1891 extern int i915_enable_fbc __read_mostly; 1892 extern bool i915_enable_hangcheck __read_mostly; 1893 extern int i915_enable_ppgtt __read_mostly; 1894 extern int i915_enable_psr __read_mostly; 1895 extern unsigned int i915_preliminary_hw_support __read_mostly; 1896 extern int i915_disable_power_well __read_mostly; 1897 extern int i915_enable_ips __read_mostly; 1898 extern bool i915_fastboot __read_mostly; 1899 extern int i915_enable_pc8 __read_mostly; 1900 extern int i915_pc8_timeout __read_mostly; 1901 extern bool i915_prefault_disable __read_mostly; 1902 1903 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1904 extern int i915_resume(struct drm_device *dev); 1905 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1906 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1907 1908 /* i915_dma.c */ 1909 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1910 extern void i915_kernel_lost_context(struct drm_device * dev); 1911 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1912 extern int i915_driver_unload(struct drm_device *); 1913 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1914 extern void i915_driver_lastclose(struct drm_device * dev); 1915 extern void i915_driver_preclose(struct drm_device *dev, 1916 struct drm_file *file_priv); 1917 extern void i915_driver_postclose(struct drm_device *dev, 1918 struct drm_file *file_priv); 1919 extern int i915_driver_device_is_agp(struct drm_device * dev); 1920 #ifdef CONFIG_COMPAT 1921 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1922 unsigned long arg); 1923 #endif 1924 extern int i915_emit_box(struct drm_device *dev, 1925 struct drm_clip_rect *box, 1926 int DR1, int DR4); 1927 extern int intel_gpu_reset(struct drm_device *dev); 1928 extern int i915_reset(struct drm_device *dev); 1929 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1930 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1931 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1932 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1933 1934 extern void intel_console_resume(struct work_struct *work); 1935 1936 /* i915_irq.c */ 1937 void i915_queue_hangcheck(struct drm_device *dev); 1938 void i915_handle_error(struct drm_device *dev, bool wedged); 1939 1940 extern void intel_irq_init(struct drm_device *dev); 1941 extern void intel_hpd_init(struct drm_device *dev); 1942 1943 extern void intel_uncore_sanitize(struct drm_device *dev); 1944 extern void intel_uncore_early_sanitize(struct drm_device *dev); 1945 extern void intel_uncore_init(struct drm_device *dev); 1946 extern void intel_uncore_check_errors(struct drm_device *dev); 1947 extern void intel_uncore_fini(struct drm_device *dev); 1948 1949 void 1950 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); 1951 1952 void 1953 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); 1954 1955 /* i915_gem.c */ 1956 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1957 struct drm_file *file_priv); 1958 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1959 struct drm_file *file_priv); 1960 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1961 struct drm_file *file_priv); 1962 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1963 struct drm_file *file_priv); 1964 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1965 struct drm_file *file_priv); 1966 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1967 struct drm_file *file_priv); 1968 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1969 struct drm_file *file_priv); 1970 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1971 struct drm_file *file_priv); 1972 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1973 struct drm_file *file_priv); 1974 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1975 struct drm_file *file_priv); 1976 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1977 struct drm_file *file_priv); 1978 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1979 struct drm_file *file_priv); 1980 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1981 struct drm_file *file_priv); 1982 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1983 struct drm_file *file); 1984 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1985 struct drm_file *file); 1986 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1987 struct drm_file *file_priv); 1988 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1989 struct drm_file *file_priv); 1990 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1991 struct drm_file *file_priv); 1992 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1993 struct drm_file *file_priv); 1994 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1995 struct drm_file *file_priv); 1996 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1997 struct drm_file *file_priv); 1998 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1999 struct drm_file *file_priv); 2000 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2001 struct drm_file *file_priv); 2002 void i915_gem_load(struct drm_device *dev); 2003 void *i915_gem_object_alloc(struct drm_device *dev); 2004 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2005 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2006 const struct drm_i915_gem_object_ops *ops); 2007 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2008 size_t size); 2009 void i915_gem_free_object(struct drm_gem_object *obj); 2010 void i915_gem_vma_destroy(struct i915_vma *vma); 2011 2012 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2013 struct i915_address_space *vm, 2014 uint32_t alignment, 2015 bool map_and_fenceable, 2016 bool nonblocking); 2017 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 2018 int __must_check i915_vma_unbind(struct i915_vma *vma); 2019 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); 2020 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2021 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2022 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2023 void i915_gem_lastclose(struct drm_device *dev); 2024 2025 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2026 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2027 { 2028 struct sg_page_iter sg_iter; 2029 2030 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 2031 return sg_page_iter_page(&sg_iter); 2032 2033 return NULL; 2034 } 2035 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2036 { 2037 BUG_ON(obj->pages == NULL); 2038 obj->pages_pin_count++; 2039 } 2040 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2041 { 2042 BUG_ON(obj->pages_pin_count == 0); 2043 obj->pages_pin_count--; 2044 } 2045 2046 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2047 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2048 struct intel_ring_buffer *to); 2049 void i915_vma_move_to_active(struct i915_vma *vma, 2050 struct intel_ring_buffer *ring); 2051 int i915_gem_dumb_create(struct drm_file *file_priv, 2052 struct drm_device *dev, 2053 struct drm_mode_create_dumb *args); 2054 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2055 uint32_t handle, uint64_t *offset); 2056 /** 2057 * Returns true if seq1 is later than seq2. 2058 */ 2059 static inline bool 2060 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2061 { 2062 return (int32_t)(seq1 - seq2) >= 0; 2063 } 2064 2065 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2066 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2067 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2068 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2069 2070 static inline bool 2071 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 2072 { 2073 if (obj->fence_reg != I915_FENCE_REG_NONE) { 2074 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2075 dev_priv->fence_regs[obj->fence_reg].pin_count++; 2076 return true; 2077 } else 2078 return false; 2079 } 2080 2081 static inline void 2082 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 2083 { 2084 if (obj->fence_reg != I915_FENCE_REG_NONE) { 2085 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2086 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); 2087 dev_priv->fence_regs[obj->fence_reg].pin_count--; 2088 } 2089 } 2090 2091 bool i915_gem_retire_requests(struct drm_device *dev); 2092 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 2093 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2094 bool interruptible); 2095 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2096 { 2097 return unlikely(atomic_read(&error->reset_counter) 2098 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2099 } 2100 2101 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2102 { 2103 return atomic_read(&error->reset_counter) & I915_WEDGED; 2104 } 2105 2106 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2107 { 2108 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2109 } 2110 2111 void i915_gem_reset(struct drm_device *dev); 2112 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2113 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2114 int __must_check i915_gem_init(struct drm_device *dev); 2115 int __must_check i915_gem_init_hw(struct drm_device *dev); 2116 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); 2117 void i915_gem_init_swizzling(struct drm_device *dev); 2118 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2119 int __must_check i915_gpu_idle(struct drm_device *dev); 2120 int __must_check i915_gem_suspend(struct drm_device *dev); 2121 int __i915_add_request(struct intel_ring_buffer *ring, 2122 struct drm_file *file, 2123 struct drm_i915_gem_object *batch_obj, 2124 u32 *seqno); 2125 #define i915_add_request(ring, seqno) \ 2126 __i915_add_request(ring, NULL, NULL, seqno) 2127 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 2128 uint32_t seqno); 2129 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 2130 int __must_check 2131 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2132 bool write); 2133 int __must_check 2134 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2135 int __must_check 2136 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2137 u32 alignment, 2138 struct intel_ring_buffer *pipelined); 2139 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2140 int i915_gem_attach_phys_object(struct drm_device *dev, 2141 struct drm_i915_gem_object *obj, 2142 int id, 2143 int align); 2144 void i915_gem_detach_phys_object(struct drm_device *dev, 2145 struct drm_i915_gem_object *obj); 2146 void i915_gem_free_all_phys_object(struct drm_device *dev); 2147 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2148 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2149 2150 uint32_t 2151 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2152 uint32_t 2153 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2154 int tiling_mode, bool fenced); 2155 2156 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2157 enum i915_cache_level cache_level); 2158 2159 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2160 struct dma_buf *dma_buf); 2161 2162 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2163 struct drm_gem_object *gem_obj, int flags); 2164 2165 void i915_gem_restore_fences(struct drm_device *dev); 2166 2167 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2168 struct i915_address_space *vm); 2169 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2170 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2171 struct i915_address_space *vm); 2172 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2173 struct i915_address_space *vm); 2174 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2175 struct i915_address_space *vm); 2176 struct i915_vma * 2177 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2178 struct i915_address_space *vm); 2179 2180 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2181 2182 /* Some GGTT VM helpers */ 2183 #define obj_to_ggtt(obj) \ 2184 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2185 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2186 { 2187 struct i915_address_space *ggtt = 2188 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2189 return vm == ggtt; 2190 } 2191 2192 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2193 { 2194 return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); 2195 } 2196 2197 static inline unsigned long 2198 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2199 { 2200 return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); 2201 } 2202 2203 static inline unsigned long 2204 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2205 { 2206 return i915_gem_obj_size(obj, obj_to_ggtt(obj)); 2207 } 2208 2209 static inline int __must_check 2210 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2211 uint32_t alignment, 2212 bool map_and_fenceable, 2213 bool nonblocking) 2214 { 2215 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, 2216 map_and_fenceable, nonblocking); 2217 } 2218 2219 /* i915_gem_context.c */ 2220 int __must_check i915_gem_context_init(struct drm_device *dev); 2221 void i915_gem_context_fini(struct drm_device *dev); 2222 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2223 int i915_switch_context(struct intel_ring_buffer *ring, 2224 struct drm_file *file, int to_id); 2225 void i915_gem_context_free(struct kref *ctx_ref); 2226 static inline void i915_gem_context_reference(struct i915_hw_context *ctx) 2227 { 2228 kref_get(&ctx->ref); 2229 } 2230 2231 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) 2232 { 2233 kref_put(&ctx->ref, i915_gem_context_free); 2234 } 2235 2236 struct i915_ctx_hang_stats * __must_check 2237 i915_gem_context_get_hang_stats(struct drm_device *dev, 2238 struct drm_file *file, 2239 u32 id); 2240 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2241 struct drm_file *file); 2242 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2243 struct drm_file *file); 2244 2245 /* i915_gem_gtt.c */ 2246 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 2247 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 2248 struct drm_i915_gem_object *obj, 2249 enum i915_cache_level cache_level); 2250 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 2251 struct drm_i915_gem_object *obj); 2252 2253 void i915_check_and_clear_faults(struct drm_device *dev); 2254 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 2255 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 2256 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 2257 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 2258 enum i915_cache_level cache_level); 2259 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 2260 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 2261 void i915_gem_init_global_gtt(struct drm_device *dev); 2262 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 2263 unsigned long mappable_end, unsigned long end); 2264 int i915_gem_gtt_init(struct drm_device *dev); 2265 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2266 { 2267 if (INTEL_INFO(dev)->gen < 6) 2268 intel_gtt_chipset_flush(); 2269 } 2270 2271 2272 /* i915_gem_evict.c */ 2273 int __must_check i915_gem_evict_something(struct drm_device *dev, 2274 struct i915_address_space *vm, 2275 int min_size, 2276 unsigned alignment, 2277 unsigned cache_level, 2278 bool mappable, 2279 bool nonblock); 2280 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2281 int i915_gem_evict_everything(struct drm_device *dev); 2282 2283 /* i915_gem_stolen.c */ 2284 int i915_gem_init_stolen(struct drm_device *dev); 2285 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); 2286 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2287 void i915_gem_cleanup_stolen(struct drm_device *dev); 2288 struct drm_i915_gem_object * 2289 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2290 struct drm_i915_gem_object * 2291 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2292 u32 stolen_offset, 2293 u32 gtt_offset, 2294 u32 size); 2295 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 2296 2297 /* i915_gem_tiling.c */ 2298 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2299 { 2300 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 2301 2302 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2303 obj->tiling_mode != I915_TILING_NONE; 2304 } 2305 2306 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2307 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2308 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2309 2310 /* i915_gem_debug.c */ 2311 #if WATCH_LISTS 2312 int i915_verify_lists(struct drm_device *dev); 2313 #else 2314 #define i915_verify_lists(dev) 0 2315 #endif 2316 2317 /* i915_debugfs.c */ 2318 int i915_debugfs_init(struct drm_minor *minor); 2319 void i915_debugfs_cleanup(struct drm_minor *minor); 2320 #ifdef CONFIG_DEBUG_FS 2321 void intel_display_crc_init(struct drm_device *dev); 2322 #else 2323 static inline void intel_display_crc_init(struct drm_device *dev) {} 2324 #endif 2325 2326 /* i915_gpu_error.c */ 2327 __printf(2, 3) 2328 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2329 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2330 const struct i915_error_state_file_priv *error); 2331 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2332 size_t count, loff_t pos); 2333 static inline void i915_error_state_buf_release( 2334 struct drm_i915_error_state_buf *eb) 2335 { 2336 kfree(eb->buf); 2337 } 2338 void i915_capture_error_state(struct drm_device *dev); 2339 void i915_error_state_get(struct drm_device *dev, 2340 struct i915_error_state_file_priv *error_priv); 2341 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2342 void i915_destroy_error_state(struct drm_device *dev); 2343 2344 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2345 const char *i915_cache_level_str(int type); 2346 2347 /* i915_suspend.c */ 2348 extern int i915_save_state(struct drm_device *dev); 2349 extern int i915_restore_state(struct drm_device *dev); 2350 2351 /* i915_ums.c */ 2352 void i915_save_display_reg(struct drm_device *dev); 2353 void i915_restore_display_reg(struct drm_device *dev); 2354 2355 /* i915_sysfs.c */ 2356 void i915_setup_sysfs(struct drm_device *dev_priv); 2357 void i915_teardown_sysfs(struct drm_device *dev_priv); 2358 2359 /* intel_i2c.c */ 2360 extern int intel_setup_gmbus(struct drm_device *dev); 2361 extern void intel_teardown_gmbus(struct drm_device *dev); 2362 static inline bool intel_gmbus_is_port_valid(unsigned port) 2363 { 2364 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2365 } 2366 2367 extern struct i2c_adapter *intel_gmbus_get_adapter( 2368 struct drm_i915_private *dev_priv, unsigned port); 2369 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 2370 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 2371 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 2372 { 2373 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 2374 } 2375 extern void intel_i2c_reset(struct drm_device *dev); 2376 2377 /* intel_opregion.c */ 2378 struct intel_encoder; 2379 #ifdef CONFIG_ACPI 2380 extern int intel_opregion_setup(struct drm_device *dev); 2381 extern void intel_opregion_init(struct drm_device *dev); 2382 extern void intel_opregion_fini(struct drm_device *dev); 2383 extern void intel_opregion_asle_intr(struct drm_device *dev); 2384 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2385 bool enable); 2386 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2387 pci_power_t state); 2388 #else 2389 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2390 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2391 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2392 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2393 static inline int 2394 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2395 { 2396 return 0; 2397 } 2398 static inline int 2399 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2400 { 2401 return 0; 2402 } 2403 #endif 2404 2405 /* intel_acpi.c */ 2406 #ifdef CONFIG_ACPI 2407 extern void intel_register_dsm_handler(void); 2408 extern void intel_unregister_dsm_handler(void); 2409 #else 2410 static inline void intel_register_dsm_handler(void) { return; } 2411 static inline void intel_unregister_dsm_handler(void) { return; } 2412 #endif /* CONFIG_ACPI */ 2413 2414 /* modesetting */ 2415 extern void intel_modeset_init_hw(struct drm_device *dev); 2416 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2417 extern void intel_modeset_init(struct drm_device *dev); 2418 extern void intel_modeset_gem_init(struct drm_device *dev); 2419 extern void intel_modeset_cleanup(struct drm_device *dev); 2420 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2421 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2422 bool force_restore); 2423 extern void i915_redisable_vga(struct drm_device *dev); 2424 extern bool intel_fbc_enabled(struct drm_device *dev); 2425 extern void intel_disable_fbc(struct drm_device *dev); 2426 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2427 extern void intel_init_pch_refclk(struct drm_device *dev); 2428 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2429 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2430 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); 2431 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); 2432 extern void intel_detect_pch(struct drm_device *dev); 2433 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2434 extern int intel_enable_rc6(const struct drm_device *dev); 2435 2436 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2437 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2438 struct drm_file *file); 2439 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2440 struct drm_file *file); 2441 2442 /* overlay */ 2443 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2444 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2445 struct intel_overlay_error_state *error); 2446 2447 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2448 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2449 struct drm_device *dev, 2450 struct intel_display_error_state *error); 2451 2452 /* On SNB platform, before reading ring registers forcewake bit 2453 * must be set to prevent GT core from power down and stale values being 2454 * returned. 2455 */ 2456 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2457 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2458 2459 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2460 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2461 2462 /* intel_sideband.c */ 2463 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2464 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2465 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2466 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2467 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2468 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2469 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2470 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2471 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2472 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2473 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2474 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2475 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2476 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 2477 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 2478 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2479 enum intel_sbi_destination destination); 2480 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2481 enum intel_sbi_destination destination); 2482 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2483 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2484 2485 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2486 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2487 2488 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2489 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2490 2491 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ 2492 (((reg) >= 0x2000 && (reg) < 0x4000) ||\ 2493 ((reg) >= 0x5000 && (reg) < 0x8000) ||\ 2494 ((reg) >= 0xB000 && (reg) < 0x12000) ||\ 2495 ((reg) >= 0x2E000 && (reg) < 0x30000)) 2496 2497 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ 2498 (((reg) >= 0x12000 && (reg) < 0x14000) ||\ 2499 ((reg) >= 0x22000 && (reg) < 0x24000) ||\ 2500 ((reg) >= 0x30000 && (reg) < 0x40000)) 2501 2502 #define FORCEWAKE_RENDER (1 << 0) 2503 #define FORCEWAKE_MEDIA (1 << 1) 2504 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) 2505 2506 2507 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2508 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2509 2510 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2511 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2512 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2513 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2514 2515 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2516 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2517 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2518 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2519 2520 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2521 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2522 2523 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2524 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2525 2526 /* "Broadcast RGB" property */ 2527 #define INTEL_BROADCAST_RGB_AUTO 0 2528 #define INTEL_BROADCAST_RGB_FULL 1 2529 #define INTEL_BROADCAST_RGB_LIMITED 2 2530 2531 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2532 { 2533 if (HAS_PCH_SPLIT(dev)) 2534 return CPU_VGACNTRL; 2535 else if (IS_VALLEYVIEW(dev)) 2536 return VLV_VGACNTRL; 2537 else 2538 return VGACNTRL; 2539 } 2540 2541 static inline void __user *to_user_ptr(u64 address) 2542 { 2543 return (void __user *)(uintptr_t)address; 2544 } 2545 2546 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2547 { 2548 unsigned long j = msecs_to_jiffies(m); 2549 2550 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2551 } 2552 2553 static inline unsigned long 2554 timespec_to_jiffies_timeout(const struct timespec *value) 2555 { 2556 unsigned long j = timespec_to_jiffies(value); 2557 2558 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2559 } 2560 2561 #endif 2562