xref: /openbmc/linux/drivers/gpu/drm/i915/i915_drv.h (revision 4f205687)
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29 
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32 
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
35 
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
45 
46 #include <drm/drmP.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 
51 #include "i915_params.h"
52 #include "i915_reg.h"
53 
54 #include "intel_bios.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_guc.h"
57 #include "intel_lrc.h"
58 #include "intel_ringbuffer.h"
59 
60 #include "i915_gem.h"
61 #include "i915_gem_gtt.h"
62 #include "i915_gem_render_state.h"
63 
64 /* General customization:
65  */
66 
67 #define DRIVER_NAME		"i915"
68 #define DRIVER_DESC		"Intel Graphics"
69 #define DRIVER_DATE		"20160425"
70 
71 #undef WARN_ON
72 /* Many gcc seem to no see through this and fall over :( */
73 #if 0
74 #define WARN_ON(x) ({ \
75 	bool __i915_warn_cond = (x); \
76 	if (__builtin_constant_p(__i915_warn_cond)) \
77 		BUILD_BUG_ON(__i915_warn_cond); \
78 	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
79 #else
80 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
81 #endif
82 
83 #undef WARN_ON_ONCE
84 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
85 
86 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
87 			     (long) (x), __func__);
88 
89 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
90  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
91  * which may not necessarily be a user visible problem.  This will either
92  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
93  * enable distros and users to tailor their preferred amount of i915 abrt
94  * spam.
95  */
96 #define I915_STATE_WARN(condition, format...) ({			\
97 	int __ret_warn_on = !!(condition);				\
98 	if (unlikely(__ret_warn_on))					\
99 		if (!WARN(i915.verbose_state_checks, format))		\
100 			DRM_ERROR(format);				\
101 	unlikely(__ret_warn_on);					\
102 })
103 
104 #define I915_STATE_WARN_ON(x)						\
105 	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
106 
107 bool __i915_inject_load_failure(const char *func, int line);
108 #define i915_inject_load_failure() \
109 	__i915_inject_load_failure(__func__, __LINE__)
110 
111 static inline const char *yesno(bool v)
112 {
113 	return v ? "yes" : "no";
114 }
115 
116 static inline const char *onoff(bool v)
117 {
118 	return v ? "on" : "off";
119 }
120 
121 enum pipe {
122 	INVALID_PIPE = -1,
123 	PIPE_A = 0,
124 	PIPE_B,
125 	PIPE_C,
126 	_PIPE_EDP,
127 	I915_MAX_PIPES = _PIPE_EDP
128 };
129 #define pipe_name(p) ((p) + 'A')
130 
131 enum transcoder {
132 	TRANSCODER_A = 0,
133 	TRANSCODER_B,
134 	TRANSCODER_C,
135 	TRANSCODER_EDP,
136 	TRANSCODER_DSI_A,
137 	TRANSCODER_DSI_C,
138 	I915_MAX_TRANSCODERS
139 };
140 
141 static inline const char *transcoder_name(enum transcoder transcoder)
142 {
143 	switch (transcoder) {
144 	case TRANSCODER_A:
145 		return "A";
146 	case TRANSCODER_B:
147 		return "B";
148 	case TRANSCODER_C:
149 		return "C";
150 	case TRANSCODER_EDP:
151 		return "EDP";
152 	case TRANSCODER_DSI_A:
153 		return "DSI A";
154 	case TRANSCODER_DSI_C:
155 		return "DSI C";
156 	default:
157 		return "<invalid>";
158 	}
159 }
160 
161 static inline bool transcoder_is_dsi(enum transcoder transcoder)
162 {
163 	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
164 }
165 
166 /*
167  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
168  * number of planes per CRTC.  Not all platforms really have this many planes,
169  * which means some arrays of size I915_MAX_PLANES may have unused entries
170  * between the topmost sprite plane and the cursor plane.
171  */
172 enum plane {
173 	PLANE_A = 0,
174 	PLANE_B,
175 	PLANE_C,
176 	PLANE_CURSOR,
177 	I915_MAX_PLANES,
178 };
179 #define plane_name(p) ((p) + 'A')
180 
181 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
182 
183 enum port {
184 	PORT_A = 0,
185 	PORT_B,
186 	PORT_C,
187 	PORT_D,
188 	PORT_E,
189 	I915_MAX_PORTS
190 };
191 #define port_name(p) ((p) + 'A')
192 
193 #define I915_NUM_PHYS_VLV 2
194 
195 enum dpio_channel {
196 	DPIO_CH0,
197 	DPIO_CH1
198 };
199 
200 enum dpio_phy {
201 	DPIO_PHY0,
202 	DPIO_PHY1
203 };
204 
205 enum intel_display_power_domain {
206 	POWER_DOMAIN_PIPE_A,
207 	POWER_DOMAIN_PIPE_B,
208 	POWER_DOMAIN_PIPE_C,
209 	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
210 	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
211 	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
212 	POWER_DOMAIN_TRANSCODER_A,
213 	POWER_DOMAIN_TRANSCODER_B,
214 	POWER_DOMAIN_TRANSCODER_C,
215 	POWER_DOMAIN_TRANSCODER_EDP,
216 	POWER_DOMAIN_TRANSCODER_DSI_A,
217 	POWER_DOMAIN_TRANSCODER_DSI_C,
218 	POWER_DOMAIN_PORT_DDI_A_LANES,
219 	POWER_DOMAIN_PORT_DDI_B_LANES,
220 	POWER_DOMAIN_PORT_DDI_C_LANES,
221 	POWER_DOMAIN_PORT_DDI_D_LANES,
222 	POWER_DOMAIN_PORT_DDI_E_LANES,
223 	POWER_DOMAIN_PORT_DSI,
224 	POWER_DOMAIN_PORT_CRT,
225 	POWER_DOMAIN_PORT_OTHER,
226 	POWER_DOMAIN_VGA,
227 	POWER_DOMAIN_AUDIO,
228 	POWER_DOMAIN_PLLS,
229 	POWER_DOMAIN_AUX_A,
230 	POWER_DOMAIN_AUX_B,
231 	POWER_DOMAIN_AUX_C,
232 	POWER_DOMAIN_AUX_D,
233 	POWER_DOMAIN_GMBUS,
234 	POWER_DOMAIN_MODESET,
235 	POWER_DOMAIN_INIT,
236 
237 	POWER_DOMAIN_NUM,
238 };
239 
240 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
241 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
242 		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
243 #define POWER_DOMAIN_TRANSCODER(tran) \
244 	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
245 	 (tran) + POWER_DOMAIN_TRANSCODER_A)
246 
247 enum hpd_pin {
248 	HPD_NONE = 0,
249 	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
250 	HPD_CRT,
251 	HPD_SDVO_B,
252 	HPD_SDVO_C,
253 	HPD_PORT_A,
254 	HPD_PORT_B,
255 	HPD_PORT_C,
256 	HPD_PORT_D,
257 	HPD_PORT_E,
258 	HPD_NUM_PINS
259 };
260 
261 #define for_each_hpd_pin(__pin) \
262 	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
263 
264 struct i915_hotplug {
265 	struct work_struct hotplug_work;
266 
267 	struct {
268 		unsigned long last_jiffies;
269 		int count;
270 		enum {
271 			HPD_ENABLED = 0,
272 			HPD_DISABLED = 1,
273 			HPD_MARK_DISABLED = 2
274 		} state;
275 	} stats[HPD_NUM_PINS];
276 	u32 event_bits;
277 	struct delayed_work reenable_work;
278 
279 	struct intel_digital_port *irq_port[I915_MAX_PORTS];
280 	u32 long_port_mask;
281 	u32 short_port_mask;
282 	struct work_struct dig_port_work;
283 
284 	/*
285 	 * if we get a HPD irq from DP and a HPD irq from non-DP
286 	 * the non-DP HPD could block the workqueue on a mode config
287 	 * mutex getting, that userspace may have taken. However
288 	 * userspace is waiting on the DP workqueue to run which is
289 	 * blocked behind the non-DP one.
290 	 */
291 	struct workqueue_struct *dp_wq;
292 };
293 
294 #define I915_GEM_GPU_DOMAINS \
295 	(I915_GEM_DOMAIN_RENDER | \
296 	 I915_GEM_DOMAIN_SAMPLER | \
297 	 I915_GEM_DOMAIN_COMMAND | \
298 	 I915_GEM_DOMAIN_INSTRUCTION | \
299 	 I915_GEM_DOMAIN_VERTEX)
300 
301 #define for_each_pipe(__dev_priv, __p) \
302 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
303 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
304 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
305 		for_each_if ((__mask) & (1 << (__p)))
306 #define for_each_plane(__dev_priv, __pipe, __p)				\
307 	for ((__p) = 0;							\
308 	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
309 	     (__p)++)
310 #define for_each_sprite(__dev_priv, __p, __s)				\
311 	for ((__s) = 0;							\
312 	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
313 	     (__s)++)
314 
315 #define for_each_port_masked(__port, __ports_mask) \
316 	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
317 		for_each_if ((__ports_mask) & (1 << (__port)))
318 
319 #define for_each_crtc(dev, crtc) \
320 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
321 
322 #define for_each_intel_plane(dev, intel_plane) \
323 	list_for_each_entry(intel_plane,			\
324 			    &dev->mode_config.plane_list,	\
325 			    base.head)
326 
327 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
328 	list_for_each_entry(intel_plane,				\
329 			    &(dev)->mode_config.plane_list,		\
330 			    base.head)					\
331 		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
332 
333 #define for_each_intel_crtc(dev, intel_crtc) \
334 	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
335 
336 #define for_each_intel_encoder(dev, intel_encoder)		\
337 	list_for_each_entry(intel_encoder,			\
338 			    &(dev)->mode_config.encoder_list,	\
339 			    base.head)
340 
341 #define for_each_intel_connector(dev, intel_connector)		\
342 	list_for_each_entry(intel_connector,			\
343 			    &dev->mode_config.connector_list,	\
344 			    base.head)
345 
346 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
347 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
348 		for_each_if ((intel_encoder)->base.crtc == (__crtc))
349 
350 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
351 	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
352 		for_each_if ((intel_connector)->base.encoder == (__encoder))
353 
354 #define for_each_power_domain(domain, mask)				\
355 	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
356 		for_each_if ((1 << (domain)) & (mask))
357 
358 struct drm_i915_private;
359 struct i915_mm_struct;
360 struct i915_mmu_object;
361 
362 struct drm_i915_file_private {
363 	struct drm_i915_private *dev_priv;
364 	struct drm_file *file;
365 
366 	struct {
367 		spinlock_t lock;
368 		struct list_head request_list;
369 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
370  * chosen to prevent the CPU getting more than a frame ahead of the GPU
371  * (when using lax throttling for the frontbuffer). We also use it to
372  * offer free GPU waitboosts for severely congested workloads.
373  */
374 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
375 	} mm;
376 	struct idr context_idr;
377 
378 	struct intel_rps_client {
379 		struct list_head link;
380 		unsigned boosts;
381 	} rps;
382 
383 	unsigned int bsd_ring;
384 };
385 
386 /* Used by dp and fdi links */
387 struct intel_link_m_n {
388 	uint32_t	tu;
389 	uint32_t	gmch_m;
390 	uint32_t	gmch_n;
391 	uint32_t	link_m;
392 	uint32_t	link_n;
393 };
394 
395 void intel_link_compute_m_n(int bpp, int nlanes,
396 			    int pixel_clock, int link_clock,
397 			    struct intel_link_m_n *m_n);
398 
399 /* Interface history:
400  *
401  * 1.1: Original.
402  * 1.2: Add Power Management
403  * 1.3: Add vblank support
404  * 1.4: Fix cmdbuffer path, add heap destroy
405  * 1.5: Add vblank pipe configuration
406  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
407  *      - Support vertical blank on secondary display pipe
408  */
409 #define DRIVER_MAJOR		1
410 #define DRIVER_MINOR		6
411 #define DRIVER_PATCHLEVEL	0
412 
413 #define WATCH_LISTS	0
414 
415 struct opregion_header;
416 struct opregion_acpi;
417 struct opregion_swsci;
418 struct opregion_asle;
419 
420 struct intel_opregion {
421 	struct opregion_header *header;
422 	struct opregion_acpi *acpi;
423 	struct opregion_swsci *swsci;
424 	u32 swsci_gbda_sub_functions;
425 	u32 swsci_sbcb_sub_functions;
426 	struct opregion_asle *asle;
427 	void *rvda;
428 	const void *vbt;
429 	u32 vbt_size;
430 	u32 *lid_state;
431 	struct work_struct asle_work;
432 };
433 #define OPREGION_SIZE            (8*1024)
434 
435 struct intel_overlay;
436 struct intel_overlay_error_state;
437 
438 #define I915_FENCE_REG_NONE -1
439 #define I915_MAX_NUM_FENCES 32
440 /* 32 fences + sign bit for FENCE_REG_NONE */
441 #define I915_MAX_NUM_FENCE_BITS 6
442 
443 struct drm_i915_fence_reg {
444 	struct list_head lru_list;
445 	struct drm_i915_gem_object *obj;
446 	int pin_count;
447 };
448 
449 struct sdvo_device_mapping {
450 	u8 initialized;
451 	u8 dvo_port;
452 	u8 slave_addr;
453 	u8 dvo_wiring;
454 	u8 i2c_pin;
455 	u8 ddc_pin;
456 };
457 
458 struct intel_display_error_state;
459 
460 struct drm_i915_error_state {
461 	struct kref ref;
462 	struct timeval time;
463 
464 	char error_msg[128];
465 	int iommu;
466 	u32 reset_count;
467 	u32 suspend_count;
468 
469 	/* Generic register state */
470 	u32 eir;
471 	u32 pgtbl_er;
472 	u32 ier;
473 	u32 gtier[4];
474 	u32 ccid;
475 	u32 derrmr;
476 	u32 forcewake;
477 	u32 error; /* gen6+ */
478 	u32 err_int; /* gen7 */
479 	u32 fault_data0; /* gen8, gen9 */
480 	u32 fault_data1; /* gen8, gen9 */
481 	u32 done_reg;
482 	u32 gac_eco;
483 	u32 gam_ecochk;
484 	u32 gab_ctl;
485 	u32 gfx_mode;
486 	u32 extra_instdone[I915_NUM_INSTDONE_REG];
487 	u64 fence[I915_MAX_NUM_FENCES];
488 	struct intel_overlay_error_state *overlay;
489 	struct intel_display_error_state *display;
490 	struct drm_i915_error_object *semaphore_obj;
491 
492 	struct drm_i915_error_ring {
493 		bool valid;
494 		/* Software tracked state */
495 		bool waiting;
496 		int hangcheck_score;
497 		enum intel_ring_hangcheck_action hangcheck_action;
498 		int num_requests;
499 
500 		/* our own tracking of ring head and tail */
501 		u32 cpu_ring_head;
502 		u32 cpu_ring_tail;
503 
504 		u32 last_seqno;
505 		u32 semaphore_seqno[I915_NUM_ENGINES - 1];
506 
507 		/* Register state */
508 		u32 start;
509 		u32 tail;
510 		u32 head;
511 		u32 ctl;
512 		u32 hws;
513 		u32 ipeir;
514 		u32 ipehr;
515 		u32 instdone;
516 		u32 bbstate;
517 		u32 instpm;
518 		u32 instps;
519 		u32 seqno;
520 		u64 bbaddr;
521 		u64 acthd;
522 		u32 fault_reg;
523 		u64 faddr;
524 		u32 rc_psmi; /* sleep state */
525 		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
526 
527 		struct drm_i915_error_object {
528 			int page_count;
529 			u64 gtt_offset;
530 			u32 *pages[0];
531 		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
532 
533 		struct drm_i915_error_object *wa_ctx;
534 
535 		struct drm_i915_error_request {
536 			long jiffies;
537 			u32 seqno;
538 			u32 tail;
539 		} *requests;
540 
541 		struct {
542 			u32 gfx_mode;
543 			union {
544 				u64 pdp[4];
545 				u32 pp_dir_base;
546 			};
547 		} vm_info;
548 
549 		pid_t pid;
550 		char comm[TASK_COMM_LEN];
551 	} ring[I915_NUM_ENGINES];
552 
553 	struct drm_i915_error_buffer {
554 		u32 size;
555 		u32 name;
556 		u32 rseqno[I915_NUM_ENGINES], wseqno;
557 		u64 gtt_offset;
558 		u32 read_domains;
559 		u32 write_domain;
560 		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
561 		s32 pinned:2;
562 		u32 tiling:2;
563 		u32 dirty:1;
564 		u32 purgeable:1;
565 		u32 userptr:1;
566 		s32 ring:4;
567 		u32 cache_level:3;
568 	} **active_bo, **pinned_bo;
569 
570 	u32 *active_bo_count, *pinned_bo_count;
571 	u32 vm_count;
572 };
573 
574 struct intel_connector;
575 struct intel_encoder;
576 struct intel_crtc_state;
577 struct intel_initial_plane_config;
578 struct intel_crtc;
579 struct intel_limit;
580 struct dpll;
581 
582 struct drm_i915_display_funcs {
583 	int (*get_display_clock_speed)(struct drm_device *dev);
584 	int (*get_fifo_size)(struct drm_device *dev, int plane);
585 	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
586 	int (*compute_intermediate_wm)(struct drm_device *dev,
587 				       struct intel_crtc *intel_crtc,
588 				       struct intel_crtc_state *newstate);
589 	void (*initial_watermarks)(struct intel_crtc_state *cstate);
590 	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
591 	void (*update_wm)(struct drm_crtc *crtc);
592 	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
593 	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
594 	/* Returns the active state of the crtc, and if the crtc is active,
595 	 * fills out the pipe-config with the hw state. */
596 	bool (*get_pipe_config)(struct intel_crtc *,
597 				struct intel_crtc_state *);
598 	void (*get_initial_plane_config)(struct intel_crtc *,
599 					 struct intel_initial_plane_config *);
600 	int (*crtc_compute_clock)(struct intel_crtc *crtc,
601 				  struct intel_crtc_state *crtc_state);
602 	void (*crtc_enable)(struct drm_crtc *crtc);
603 	void (*crtc_disable)(struct drm_crtc *crtc);
604 	void (*audio_codec_enable)(struct drm_connector *connector,
605 				   struct intel_encoder *encoder,
606 				   const struct drm_display_mode *adjusted_mode);
607 	void (*audio_codec_disable)(struct intel_encoder *encoder);
608 	void (*fdi_link_train)(struct drm_crtc *crtc);
609 	void (*init_clock_gating)(struct drm_device *dev);
610 	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
611 			  struct drm_framebuffer *fb,
612 			  struct drm_i915_gem_object *obj,
613 			  struct drm_i915_gem_request *req,
614 			  uint32_t flags);
615 	void (*hpd_irq_setup)(struct drm_device *dev);
616 	/* clock updates for mode set */
617 	/* cursor updates */
618 	/* render clock increase/decrease */
619 	/* display clock increase/decrease */
620 	/* pll clock increase/decrease */
621 
622 	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
623 	void (*load_luts)(struct drm_crtc_state *crtc_state);
624 };
625 
626 enum forcewake_domain_id {
627 	FW_DOMAIN_ID_RENDER = 0,
628 	FW_DOMAIN_ID_BLITTER,
629 	FW_DOMAIN_ID_MEDIA,
630 
631 	FW_DOMAIN_ID_COUNT
632 };
633 
634 enum forcewake_domains {
635 	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
636 	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
637 	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
638 	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
639 			 FORCEWAKE_BLITTER |
640 			 FORCEWAKE_MEDIA)
641 };
642 
643 #define FW_REG_READ  (1)
644 #define FW_REG_WRITE (2)
645 
646 enum forcewake_domains
647 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
648 			       i915_reg_t reg, unsigned int op);
649 
650 struct intel_uncore_funcs {
651 	void (*force_wake_get)(struct drm_i915_private *dev_priv,
652 							enum forcewake_domains domains);
653 	void (*force_wake_put)(struct drm_i915_private *dev_priv,
654 							enum forcewake_domains domains);
655 
656 	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
657 	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
658 	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
659 	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
660 
661 	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
662 				uint8_t val, bool trace);
663 	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
664 				uint16_t val, bool trace);
665 	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
666 				uint32_t val, bool trace);
667 	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
668 				uint64_t val, bool trace);
669 };
670 
671 struct intel_uncore {
672 	spinlock_t lock; /** lock is also taken in irq contexts. */
673 
674 	struct intel_uncore_funcs funcs;
675 
676 	unsigned fifo_count;
677 	enum forcewake_domains fw_domains;
678 
679 	struct intel_uncore_forcewake_domain {
680 		struct drm_i915_private *i915;
681 		enum forcewake_domain_id id;
682 		enum forcewake_domains mask;
683 		unsigned wake_count;
684 		struct hrtimer timer;
685 		i915_reg_t reg_set;
686 		u32 val_set;
687 		u32 val_clear;
688 		i915_reg_t reg_ack;
689 		i915_reg_t reg_post;
690 		u32 val_reset;
691 	} fw_domain[FW_DOMAIN_ID_COUNT];
692 
693 	int unclaimed_mmio_check;
694 };
695 
696 /* Iterate over initialised fw domains */
697 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
698 	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
699 	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
700 	     (domain__)++) \
701 		for_each_if ((mask__) & (domain__)->mask)
702 
703 #define for_each_fw_domain(domain__, dev_priv__) \
704 	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
705 
706 #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
707 #define CSR_VERSION_MAJOR(version)	((version) >> 16)
708 #define CSR_VERSION_MINOR(version)	((version) & 0xffff)
709 
710 struct intel_csr {
711 	struct work_struct work;
712 	const char *fw_path;
713 	uint32_t *dmc_payload;
714 	uint32_t dmc_fw_size;
715 	uint32_t version;
716 	uint32_t mmio_count;
717 	i915_reg_t mmioaddr[8];
718 	uint32_t mmiodata[8];
719 	uint32_t dc_state;
720 	uint32_t allowed_dc_mask;
721 };
722 
723 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
724 	func(is_mobile) sep \
725 	func(is_i85x) sep \
726 	func(is_i915g) sep \
727 	func(is_i945gm) sep \
728 	func(is_g33) sep \
729 	func(need_gfx_hws) sep \
730 	func(is_g4x) sep \
731 	func(is_pineview) sep \
732 	func(is_broadwater) sep \
733 	func(is_crestline) sep \
734 	func(is_ivybridge) sep \
735 	func(is_valleyview) sep \
736 	func(is_cherryview) sep \
737 	func(is_haswell) sep \
738 	func(is_skylake) sep \
739 	func(is_broxton) sep \
740 	func(is_kabylake) sep \
741 	func(is_preliminary) sep \
742 	func(has_fbc) sep \
743 	func(has_pipe_cxsr) sep \
744 	func(has_hotplug) sep \
745 	func(cursor_needs_physical) sep \
746 	func(has_overlay) sep \
747 	func(overlay_needs_physical) sep \
748 	func(supports_tv) sep \
749 	func(has_llc) sep \
750 	func(has_snoop) sep \
751 	func(has_ddi) sep \
752 	func(has_fpga_dbg)
753 
754 #define DEFINE_FLAG(name) u8 name:1
755 #define SEP_SEMICOLON ;
756 
757 struct intel_device_info {
758 	u32 display_mmio_offset;
759 	u16 device_id;
760 	u8 num_pipes:3;
761 	u8 num_sprites[I915_MAX_PIPES];
762 	u8 gen;
763 	u8 ring_mask; /* Rings supported by the HW */
764 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
765 	/* Register offsets for the various display pipes and transcoders */
766 	int pipe_offsets[I915_MAX_TRANSCODERS];
767 	int trans_offsets[I915_MAX_TRANSCODERS];
768 	int palette_offsets[I915_MAX_PIPES];
769 	int cursor_offsets[I915_MAX_PIPES];
770 
771 	/* Slice/subslice/EU info */
772 	u8 slice_total;
773 	u8 subslice_total;
774 	u8 subslice_per_slice;
775 	u8 eu_total;
776 	u8 eu_per_subslice;
777 	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
778 	u8 subslice_7eu[3];
779 	u8 has_slice_pg:1;
780 	u8 has_subslice_pg:1;
781 	u8 has_eu_pg:1;
782 
783 	struct color_luts {
784 		u16 degamma_lut_size;
785 		u16 gamma_lut_size;
786 	} color;
787 };
788 
789 #undef DEFINE_FLAG
790 #undef SEP_SEMICOLON
791 
792 enum i915_cache_level {
793 	I915_CACHE_NONE = 0,
794 	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
795 	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
796 			      caches, eg sampler/render caches, and the
797 			      large Last-Level-Cache. LLC is coherent with
798 			      the CPU, but L3 is only visible to the GPU. */
799 	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
800 };
801 
802 struct i915_ctx_hang_stats {
803 	/* This context had batch pending when hang was declared */
804 	unsigned batch_pending;
805 
806 	/* This context had batch active when hang was declared */
807 	unsigned batch_active;
808 
809 	/* Time when this context was last blamed for a GPU reset */
810 	unsigned long guilty_ts;
811 
812 	/* If the contexts causes a second GPU hang within this time,
813 	 * it is permanently banned from submitting any more work.
814 	 */
815 	unsigned long ban_period_seconds;
816 
817 	/* This context is banned to submit more work */
818 	bool banned;
819 };
820 
821 /* This must match up with the value previously used for execbuf2.rsvd1. */
822 #define DEFAULT_CONTEXT_HANDLE 0
823 
824 #define CONTEXT_NO_ZEROMAP (1<<0)
825 /**
826  * struct intel_context - as the name implies, represents a context.
827  * @ref: reference count.
828  * @user_handle: userspace tracking identity for this context.
829  * @remap_slice: l3 row remapping information.
830  * @flags: context specific flags:
831  *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
832  * @file_priv: filp associated with this context (NULL for global default
833  *	       context).
834  * @hang_stats: information about the role of this context in possible GPU
835  *		hangs.
836  * @ppgtt: virtual memory space used by this context.
837  * @legacy_hw_ctx: render context backing object and whether it is correctly
838  *                initialized (legacy ring submission mechanism only).
839  * @link: link in the global list of contexts.
840  *
841  * Contexts are memory images used by the hardware to store copies of their
842  * internal state.
843  */
844 struct intel_context {
845 	struct kref ref;
846 	int user_handle;
847 	uint8_t remap_slice;
848 	struct drm_i915_private *i915;
849 	int flags;
850 	struct drm_i915_file_private *file_priv;
851 	struct i915_ctx_hang_stats hang_stats;
852 	struct i915_hw_ppgtt *ppgtt;
853 
854 	/* Legacy ring buffer submission */
855 	struct {
856 		struct drm_i915_gem_object *rcs_state;
857 		bool initialized;
858 	} legacy_hw_ctx;
859 
860 	/* Execlists */
861 	struct {
862 		struct drm_i915_gem_object *state;
863 		struct intel_ringbuffer *ringbuf;
864 		int pin_count;
865 		struct i915_vma *lrc_vma;
866 		u64 lrc_desc;
867 		uint32_t *lrc_reg_state;
868 	} engine[I915_NUM_ENGINES];
869 
870 	struct list_head link;
871 };
872 
873 enum fb_op_origin {
874 	ORIGIN_GTT,
875 	ORIGIN_CPU,
876 	ORIGIN_CS,
877 	ORIGIN_FLIP,
878 	ORIGIN_DIRTYFB,
879 };
880 
881 struct intel_fbc {
882 	/* This is always the inner lock when overlapping with struct_mutex and
883 	 * it's the outer lock when overlapping with stolen_lock. */
884 	struct mutex lock;
885 	unsigned threshold;
886 	unsigned int possible_framebuffer_bits;
887 	unsigned int busy_bits;
888 	unsigned int visible_pipes_mask;
889 	struct intel_crtc *crtc;
890 
891 	struct drm_mm_node compressed_fb;
892 	struct drm_mm_node *compressed_llb;
893 
894 	bool false_color;
895 
896 	bool enabled;
897 	bool active;
898 
899 	struct intel_fbc_state_cache {
900 		struct {
901 			unsigned int mode_flags;
902 			uint32_t hsw_bdw_pixel_rate;
903 		} crtc;
904 
905 		struct {
906 			unsigned int rotation;
907 			int src_w;
908 			int src_h;
909 			bool visible;
910 		} plane;
911 
912 		struct {
913 			u64 ilk_ggtt_offset;
914 			uint32_t pixel_format;
915 			unsigned int stride;
916 			int fence_reg;
917 			unsigned int tiling_mode;
918 		} fb;
919 	} state_cache;
920 
921 	struct intel_fbc_reg_params {
922 		struct {
923 			enum pipe pipe;
924 			enum plane plane;
925 			unsigned int fence_y_offset;
926 		} crtc;
927 
928 		struct {
929 			u64 ggtt_offset;
930 			uint32_t pixel_format;
931 			unsigned int stride;
932 			int fence_reg;
933 		} fb;
934 
935 		int cfb_size;
936 	} params;
937 
938 	struct intel_fbc_work {
939 		bool scheduled;
940 		u32 scheduled_vblank;
941 		struct work_struct work;
942 	} work;
943 
944 	const char *no_fbc_reason;
945 };
946 
947 /**
948  * HIGH_RR is the highest eDP panel refresh rate read from EDID
949  * LOW_RR is the lowest eDP panel refresh rate found from EDID
950  * parsing for same resolution.
951  */
952 enum drrs_refresh_rate_type {
953 	DRRS_HIGH_RR,
954 	DRRS_LOW_RR,
955 	DRRS_MAX_RR, /* RR count */
956 };
957 
958 enum drrs_support_type {
959 	DRRS_NOT_SUPPORTED = 0,
960 	STATIC_DRRS_SUPPORT = 1,
961 	SEAMLESS_DRRS_SUPPORT = 2
962 };
963 
964 struct intel_dp;
965 struct i915_drrs {
966 	struct mutex mutex;
967 	struct delayed_work work;
968 	struct intel_dp *dp;
969 	unsigned busy_frontbuffer_bits;
970 	enum drrs_refresh_rate_type refresh_rate_type;
971 	enum drrs_support_type type;
972 };
973 
974 struct i915_psr {
975 	struct mutex lock;
976 	bool sink_support;
977 	bool source_ok;
978 	struct intel_dp *enabled;
979 	bool active;
980 	struct delayed_work work;
981 	unsigned busy_frontbuffer_bits;
982 	bool psr2_support;
983 	bool aux_frame_sync;
984 	bool link_standby;
985 };
986 
987 enum intel_pch {
988 	PCH_NONE = 0,	/* No PCH present */
989 	PCH_IBX,	/* Ibexpeak PCH */
990 	PCH_CPT,	/* Cougarpoint PCH */
991 	PCH_LPT,	/* Lynxpoint PCH */
992 	PCH_SPT,        /* Sunrisepoint PCH */
993 	PCH_KBP,        /* Kabypoint PCH */
994 	PCH_NOP,
995 };
996 
997 enum intel_sbi_destination {
998 	SBI_ICLK,
999 	SBI_MPHY,
1000 };
1001 
1002 #define QUIRK_PIPEA_FORCE (1<<0)
1003 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1004 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1005 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1006 #define QUIRK_PIPEB_FORCE (1<<4)
1007 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1008 
1009 struct intel_fbdev;
1010 struct intel_fbc_work;
1011 
1012 struct intel_gmbus {
1013 	struct i2c_adapter adapter;
1014 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1015 	u32 force_bit;
1016 	u32 reg0;
1017 	i915_reg_t gpio_reg;
1018 	struct i2c_algo_bit_data bit_algo;
1019 	struct drm_i915_private *dev_priv;
1020 };
1021 
1022 struct i915_suspend_saved_registers {
1023 	u32 saveDSPARB;
1024 	u32 saveLVDS;
1025 	u32 savePP_ON_DELAYS;
1026 	u32 savePP_OFF_DELAYS;
1027 	u32 savePP_ON;
1028 	u32 savePP_OFF;
1029 	u32 savePP_CONTROL;
1030 	u32 savePP_DIVISOR;
1031 	u32 saveFBC_CONTROL;
1032 	u32 saveCACHE_MODE_0;
1033 	u32 saveMI_ARB_STATE;
1034 	u32 saveSWF0[16];
1035 	u32 saveSWF1[16];
1036 	u32 saveSWF3[3];
1037 	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1038 	u32 savePCH_PORT_HOTPLUG;
1039 	u16 saveGCDGMBUS;
1040 };
1041 
1042 struct vlv_s0ix_state {
1043 	/* GAM */
1044 	u32 wr_watermark;
1045 	u32 gfx_prio_ctrl;
1046 	u32 arb_mode;
1047 	u32 gfx_pend_tlb0;
1048 	u32 gfx_pend_tlb1;
1049 	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1050 	u32 media_max_req_count;
1051 	u32 gfx_max_req_count;
1052 	u32 render_hwsp;
1053 	u32 ecochk;
1054 	u32 bsd_hwsp;
1055 	u32 blt_hwsp;
1056 	u32 tlb_rd_addr;
1057 
1058 	/* MBC */
1059 	u32 g3dctl;
1060 	u32 gsckgctl;
1061 	u32 mbctl;
1062 
1063 	/* GCP */
1064 	u32 ucgctl1;
1065 	u32 ucgctl3;
1066 	u32 rcgctl1;
1067 	u32 rcgctl2;
1068 	u32 rstctl;
1069 	u32 misccpctl;
1070 
1071 	/* GPM */
1072 	u32 gfxpause;
1073 	u32 rpdeuhwtc;
1074 	u32 rpdeuc;
1075 	u32 ecobus;
1076 	u32 pwrdwnupctl;
1077 	u32 rp_down_timeout;
1078 	u32 rp_deucsw;
1079 	u32 rcubmabdtmr;
1080 	u32 rcedata;
1081 	u32 spare2gh;
1082 
1083 	/* Display 1 CZ domain */
1084 	u32 gt_imr;
1085 	u32 gt_ier;
1086 	u32 pm_imr;
1087 	u32 pm_ier;
1088 	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1089 
1090 	/* GT SA CZ domain */
1091 	u32 tilectl;
1092 	u32 gt_fifoctl;
1093 	u32 gtlc_wake_ctrl;
1094 	u32 gtlc_survive;
1095 	u32 pmwgicz;
1096 
1097 	/* Display 2 CZ domain */
1098 	u32 gu_ctl0;
1099 	u32 gu_ctl1;
1100 	u32 pcbr;
1101 	u32 clock_gate_dis2;
1102 };
1103 
1104 struct intel_rps_ei {
1105 	u32 cz_clock;
1106 	u32 render_c0;
1107 	u32 media_c0;
1108 };
1109 
1110 struct intel_gen6_power_mgmt {
1111 	/*
1112 	 * work, interrupts_enabled and pm_iir are protected by
1113 	 * dev_priv->irq_lock
1114 	 */
1115 	struct work_struct work;
1116 	bool interrupts_enabled;
1117 	u32 pm_iir;
1118 
1119 	/* Frequencies are stored in potentially platform dependent multiples.
1120 	 * In other words, *_freq needs to be multiplied by X to be interesting.
1121 	 * Soft limits are those which are used for the dynamic reclocking done
1122 	 * by the driver (raise frequencies under heavy loads, and lower for
1123 	 * lighter loads). Hard limits are those imposed by the hardware.
1124 	 *
1125 	 * A distinction is made for overclocking, which is never enabled by
1126 	 * default, and is considered to be above the hard limit if it's
1127 	 * possible at all.
1128 	 */
1129 	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
1130 	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
1131 	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
1132 	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
1133 	u8 min_freq;		/* AKA RPn. Minimum frequency */
1134 	u8 idle_freq;		/* Frequency to request when we are idle */
1135 	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
1136 	u8 rp1_freq;		/* "less than" RP0 power/freqency */
1137 	u8 rp0_freq;		/* Non-overclocked max frequency. */
1138 	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1139 
1140 	u8 up_threshold; /* Current %busy required to uplock */
1141 	u8 down_threshold; /* Current %busy required to downclock */
1142 
1143 	int last_adj;
1144 	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1145 
1146 	spinlock_t client_lock;
1147 	struct list_head clients;
1148 	bool client_boost;
1149 
1150 	bool enabled;
1151 	struct delayed_work delayed_resume_work;
1152 	unsigned boosts;
1153 
1154 	struct intel_rps_client semaphores, mmioflips;
1155 
1156 	/* manual wa residency calculations */
1157 	struct intel_rps_ei up_ei, down_ei;
1158 
1159 	/*
1160 	 * Protects RPS/RC6 register access and PCU communication.
1161 	 * Must be taken after struct_mutex if nested. Note that
1162 	 * this lock may be held for long periods of time when
1163 	 * talking to hw - so only take it when talking to hw!
1164 	 */
1165 	struct mutex hw_lock;
1166 };
1167 
1168 /* defined intel_pm.c */
1169 extern spinlock_t mchdev_lock;
1170 
1171 struct intel_ilk_power_mgmt {
1172 	u8 cur_delay;
1173 	u8 min_delay;
1174 	u8 max_delay;
1175 	u8 fmax;
1176 	u8 fstart;
1177 
1178 	u64 last_count1;
1179 	unsigned long last_time1;
1180 	unsigned long chipset_power;
1181 	u64 last_count2;
1182 	u64 last_time2;
1183 	unsigned long gfx_power;
1184 	u8 corr;
1185 
1186 	int c_m;
1187 	int r_t;
1188 };
1189 
1190 struct drm_i915_private;
1191 struct i915_power_well;
1192 
1193 struct i915_power_well_ops {
1194 	/*
1195 	 * Synchronize the well's hw state to match the current sw state, for
1196 	 * example enable/disable it based on the current refcount. Called
1197 	 * during driver init and resume time, possibly after first calling
1198 	 * the enable/disable handlers.
1199 	 */
1200 	void (*sync_hw)(struct drm_i915_private *dev_priv,
1201 			struct i915_power_well *power_well);
1202 	/*
1203 	 * Enable the well and resources that depend on it (for example
1204 	 * interrupts located on the well). Called after the 0->1 refcount
1205 	 * transition.
1206 	 */
1207 	void (*enable)(struct drm_i915_private *dev_priv,
1208 		       struct i915_power_well *power_well);
1209 	/*
1210 	 * Disable the well and resources that depend on it. Called after
1211 	 * the 1->0 refcount transition.
1212 	 */
1213 	void (*disable)(struct drm_i915_private *dev_priv,
1214 			struct i915_power_well *power_well);
1215 	/* Returns the hw enabled state. */
1216 	bool (*is_enabled)(struct drm_i915_private *dev_priv,
1217 			   struct i915_power_well *power_well);
1218 };
1219 
1220 /* Power well structure for haswell */
1221 struct i915_power_well {
1222 	const char *name;
1223 	bool always_on;
1224 	/* power well enable/disable usage count */
1225 	int count;
1226 	/* cached hw enabled state */
1227 	bool hw_enabled;
1228 	unsigned long domains;
1229 	unsigned long data;
1230 	const struct i915_power_well_ops *ops;
1231 };
1232 
1233 struct i915_power_domains {
1234 	/*
1235 	 * Power wells needed for initialization at driver init and suspend
1236 	 * time are on. They are kept on until after the first modeset.
1237 	 */
1238 	bool init_power_on;
1239 	bool initializing;
1240 	int power_well_count;
1241 
1242 	struct mutex lock;
1243 	int domain_use_count[POWER_DOMAIN_NUM];
1244 	struct i915_power_well *power_wells;
1245 };
1246 
1247 #define MAX_L3_SLICES 2
1248 struct intel_l3_parity {
1249 	u32 *remap_info[MAX_L3_SLICES];
1250 	struct work_struct error_work;
1251 	int which_slice;
1252 };
1253 
1254 struct i915_gem_mm {
1255 	/** Memory allocator for GTT stolen memory */
1256 	struct drm_mm stolen;
1257 	/** Protects the usage of the GTT stolen memory allocator. This is
1258 	 * always the inner lock when overlapping with struct_mutex. */
1259 	struct mutex stolen_lock;
1260 
1261 	/** List of all objects in gtt_space. Used to restore gtt
1262 	 * mappings on resume */
1263 	struct list_head bound_list;
1264 	/**
1265 	 * List of objects which are not bound to the GTT (thus
1266 	 * are idle and not used by the GPU) but still have
1267 	 * (presumably uncached) pages still attached.
1268 	 */
1269 	struct list_head unbound_list;
1270 
1271 	/** Usable portion of the GTT for GEM */
1272 	unsigned long stolen_base; /* limited to low memory (32-bit) */
1273 
1274 	/** PPGTT used for aliasing the PPGTT with the GTT */
1275 	struct i915_hw_ppgtt *aliasing_ppgtt;
1276 
1277 	struct notifier_block oom_notifier;
1278 	struct notifier_block vmap_notifier;
1279 	struct shrinker shrinker;
1280 	bool shrinker_no_lock_stealing;
1281 
1282 	/** LRU list of objects with fence regs on them. */
1283 	struct list_head fence_list;
1284 
1285 	/**
1286 	 * We leave the user IRQ off as much as possible,
1287 	 * but this means that requests will finish and never
1288 	 * be retired once the system goes idle. Set a timer to
1289 	 * fire periodically while the ring is running. When it
1290 	 * fires, go retire requests.
1291 	 */
1292 	struct delayed_work retire_work;
1293 
1294 	/**
1295 	 * When we detect an idle GPU, we want to turn on
1296 	 * powersaving features. So once we see that there
1297 	 * are no more requests outstanding and no more
1298 	 * arrive within a small period of time, we fire
1299 	 * off the idle_work.
1300 	 */
1301 	struct delayed_work idle_work;
1302 
1303 	/**
1304 	 * Are we in a non-interruptible section of code like
1305 	 * modesetting?
1306 	 */
1307 	bool interruptible;
1308 
1309 	/**
1310 	 * Is the GPU currently considered idle, or busy executing userspace
1311 	 * requests?  Whilst idle, we attempt to power down the hardware and
1312 	 * display clocks. In order to reduce the effect on performance, there
1313 	 * is a slight delay before we do so.
1314 	 */
1315 	bool busy;
1316 
1317 	/* the indicator for dispatch video commands on two BSD rings */
1318 	unsigned int bsd_ring_dispatch_index;
1319 
1320 	/** Bit 6 swizzling required for X tiling */
1321 	uint32_t bit_6_swizzle_x;
1322 	/** Bit 6 swizzling required for Y tiling */
1323 	uint32_t bit_6_swizzle_y;
1324 
1325 	/* accounting, useful for userland debugging */
1326 	spinlock_t object_stat_lock;
1327 	size_t object_memory;
1328 	u32 object_count;
1329 };
1330 
1331 struct drm_i915_error_state_buf {
1332 	struct drm_i915_private *i915;
1333 	unsigned bytes;
1334 	unsigned size;
1335 	int err;
1336 	u8 *buf;
1337 	loff_t start;
1338 	loff_t pos;
1339 };
1340 
1341 struct i915_error_state_file_priv {
1342 	struct drm_device *dev;
1343 	struct drm_i915_error_state *error;
1344 };
1345 
1346 struct i915_gpu_error {
1347 	/* For hangcheck timer */
1348 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1349 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1350 	/* Hang gpu twice in this window and your context gets banned */
1351 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1352 
1353 	struct workqueue_struct *hangcheck_wq;
1354 	struct delayed_work hangcheck_work;
1355 
1356 	/* For reset and error_state handling. */
1357 	spinlock_t lock;
1358 	/* Protected by the above dev->gpu_error.lock. */
1359 	struct drm_i915_error_state *first_error;
1360 
1361 	unsigned long missed_irq_rings;
1362 
1363 	/**
1364 	 * State variable controlling the reset flow and count
1365 	 *
1366 	 * This is a counter which gets incremented when reset is triggered,
1367 	 * and again when reset has been handled. So odd values (lowest bit set)
1368 	 * means that reset is in progress and even values that
1369 	 * (reset_counter >> 1):th reset was successfully completed.
1370 	 *
1371 	 * If reset is not completed succesfully, the I915_WEDGE bit is
1372 	 * set meaning that hardware is terminally sour and there is no
1373 	 * recovery. All waiters on the reset_queue will be woken when
1374 	 * that happens.
1375 	 *
1376 	 * This counter is used by the wait_seqno code to notice that reset
1377 	 * event happened and it needs to restart the entire ioctl (since most
1378 	 * likely the seqno it waited for won't ever signal anytime soon).
1379 	 *
1380 	 * This is important for lock-free wait paths, where no contended lock
1381 	 * naturally enforces the correct ordering between the bail-out of the
1382 	 * waiter and the gpu reset work code.
1383 	 */
1384 	atomic_t reset_counter;
1385 
1386 #define I915_RESET_IN_PROGRESS_FLAG	1
1387 #define I915_WEDGED			(1 << 31)
1388 
1389 	/**
1390 	 * Waitqueue to signal when the reset has completed. Used by clients
1391 	 * that wait for dev_priv->mm.wedged to settle.
1392 	 */
1393 	wait_queue_head_t reset_queue;
1394 
1395 	/* Userspace knobs for gpu hang simulation;
1396 	 * combines both a ring mask, and extra flags
1397 	 */
1398 	u32 stop_rings;
1399 #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1400 #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1401 
1402 	/* For missed irq/seqno simulation. */
1403 	unsigned int test_irq_rings;
1404 };
1405 
1406 enum modeset_restore {
1407 	MODESET_ON_LID_OPEN,
1408 	MODESET_DONE,
1409 	MODESET_SUSPENDED,
1410 };
1411 
1412 #define DP_AUX_A 0x40
1413 #define DP_AUX_B 0x10
1414 #define DP_AUX_C 0x20
1415 #define DP_AUX_D 0x30
1416 
1417 #define DDC_PIN_B  0x05
1418 #define DDC_PIN_C  0x04
1419 #define DDC_PIN_D  0x06
1420 
1421 struct ddi_vbt_port_info {
1422 	/*
1423 	 * This is an index in the HDMI/DVI DDI buffer translation table.
1424 	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1425 	 * populate this field.
1426 	 */
1427 #define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1428 	uint8_t hdmi_level_shift;
1429 
1430 	uint8_t supports_dvi:1;
1431 	uint8_t supports_hdmi:1;
1432 	uint8_t supports_dp:1;
1433 
1434 	uint8_t alternate_aux_channel;
1435 	uint8_t alternate_ddc_pin;
1436 
1437 	uint8_t dp_boost_level;
1438 	uint8_t hdmi_boost_level;
1439 };
1440 
1441 enum psr_lines_to_wait {
1442 	PSR_0_LINES_TO_WAIT = 0,
1443 	PSR_1_LINE_TO_WAIT,
1444 	PSR_4_LINES_TO_WAIT,
1445 	PSR_8_LINES_TO_WAIT
1446 };
1447 
1448 struct intel_vbt_data {
1449 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1450 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1451 
1452 	/* Feature bits */
1453 	unsigned int int_tv_support:1;
1454 	unsigned int lvds_dither:1;
1455 	unsigned int lvds_vbt:1;
1456 	unsigned int int_crt_support:1;
1457 	unsigned int lvds_use_ssc:1;
1458 	unsigned int display_clock_mode:1;
1459 	unsigned int fdi_rx_polarity_inverted:1;
1460 	unsigned int panel_type:4;
1461 	int lvds_ssc_freq;
1462 	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1463 
1464 	enum drrs_support_type drrs_type;
1465 
1466 	struct {
1467 		int rate;
1468 		int lanes;
1469 		int preemphasis;
1470 		int vswing;
1471 		bool low_vswing;
1472 		bool initialized;
1473 		bool support;
1474 		int bpp;
1475 		struct edp_power_seq pps;
1476 	} edp;
1477 
1478 	struct {
1479 		bool full_link;
1480 		bool require_aux_wakeup;
1481 		int idle_frames;
1482 		enum psr_lines_to_wait lines_to_wait;
1483 		int tp1_wakeup_time;
1484 		int tp2_tp3_wakeup_time;
1485 	} psr;
1486 
1487 	struct {
1488 		u16 pwm_freq_hz;
1489 		bool present;
1490 		bool active_low_pwm;
1491 		u8 min_brightness;	/* min_brightness/255 of max */
1492 	} backlight;
1493 
1494 	/* MIPI DSI */
1495 	struct {
1496 		u16 panel_id;
1497 		struct mipi_config *config;
1498 		struct mipi_pps_data *pps;
1499 		u8 seq_version;
1500 		u32 size;
1501 		u8 *data;
1502 		const u8 *sequence[MIPI_SEQ_MAX];
1503 	} dsi;
1504 
1505 	int crt_ddc_pin;
1506 
1507 	int child_dev_num;
1508 	union child_device_config *child_dev;
1509 
1510 	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1511 	struct sdvo_device_mapping sdvo_mappings[2];
1512 };
1513 
1514 enum intel_ddb_partitioning {
1515 	INTEL_DDB_PART_1_2,
1516 	INTEL_DDB_PART_5_6, /* IVB+ */
1517 };
1518 
1519 struct intel_wm_level {
1520 	bool enable;
1521 	uint32_t pri_val;
1522 	uint32_t spr_val;
1523 	uint32_t cur_val;
1524 	uint32_t fbc_val;
1525 };
1526 
1527 struct ilk_wm_values {
1528 	uint32_t wm_pipe[3];
1529 	uint32_t wm_lp[3];
1530 	uint32_t wm_lp_spr[3];
1531 	uint32_t wm_linetime[3];
1532 	bool enable_fbc_wm;
1533 	enum intel_ddb_partitioning partitioning;
1534 };
1535 
1536 struct vlv_pipe_wm {
1537 	uint16_t primary;
1538 	uint16_t sprite[2];
1539 	uint8_t cursor;
1540 };
1541 
1542 struct vlv_sr_wm {
1543 	uint16_t plane;
1544 	uint8_t cursor;
1545 };
1546 
1547 struct vlv_wm_values {
1548 	struct vlv_pipe_wm pipe[3];
1549 	struct vlv_sr_wm sr;
1550 	struct {
1551 		uint8_t cursor;
1552 		uint8_t sprite[2];
1553 		uint8_t primary;
1554 	} ddl[3];
1555 	uint8_t level;
1556 	bool cxsr;
1557 };
1558 
1559 struct skl_ddb_entry {
1560 	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1561 };
1562 
1563 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1564 {
1565 	return entry->end - entry->start;
1566 }
1567 
1568 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1569 				       const struct skl_ddb_entry *e2)
1570 {
1571 	if (e1->start == e2->start && e1->end == e2->end)
1572 		return true;
1573 
1574 	return false;
1575 }
1576 
1577 struct skl_ddb_allocation {
1578 	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1579 	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1580 	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1581 };
1582 
1583 struct skl_wm_values {
1584 	bool dirty[I915_MAX_PIPES];
1585 	struct skl_ddb_allocation ddb;
1586 	uint32_t wm_linetime[I915_MAX_PIPES];
1587 	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1588 	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1589 };
1590 
1591 struct skl_wm_level {
1592 	bool plane_en[I915_MAX_PLANES];
1593 	uint16_t plane_res_b[I915_MAX_PLANES];
1594 	uint8_t plane_res_l[I915_MAX_PLANES];
1595 };
1596 
1597 /*
1598  * This struct helps tracking the state needed for runtime PM, which puts the
1599  * device in PCI D3 state. Notice that when this happens, nothing on the
1600  * graphics device works, even register access, so we don't get interrupts nor
1601  * anything else.
1602  *
1603  * Every piece of our code that needs to actually touch the hardware needs to
1604  * either call intel_runtime_pm_get or call intel_display_power_get with the
1605  * appropriate power domain.
1606  *
1607  * Our driver uses the autosuspend delay feature, which means we'll only really
1608  * suspend if we stay with zero refcount for a certain amount of time. The
1609  * default value is currently very conservative (see intel_runtime_pm_enable), but
1610  * it can be changed with the standard runtime PM files from sysfs.
1611  *
1612  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1613  * goes back to false exactly before we reenable the IRQs. We use this variable
1614  * to check if someone is trying to enable/disable IRQs while they're supposed
1615  * to be disabled. This shouldn't happen and we'll print some error messages in
1616  * case it happens.
1617  *
1618  * For more, read the Documentation/power/runtime_pm.txt.
1619  */
1620 struct i915_runtime_pm {
1621 	atomic_t wakeref_count;
1622 	atomic_t atomic_seq;
1623 	bool suspended;
1624 	bool irqs_enabled;
1625 };
1626 
1627 enum intel_pipe_crc_source {
1628 	INTEL_PIPE_CRC_SOURCE_NONE,
1629 	INTEL_PIPE_CRC_SOURCE_PLANE1,
1630 	INTEL_PIPE_CRC_SOURCE_PLANE2,
1631 	INTEL_PIPE_CRC_SOURCE_PF,
1632 	INTEL_PIPE_CRC_SOURCE_PIPE,
1633 	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
1634 	INTEL_PIPE_CRC_SOURCE_TV,
1635 	INTEL_PIPE_CRC_SOURCE_DP_B,
1636 	INTEL_PIPE_CRC_SOURCE_DP_C,
1637 	INTEL_PIPE_CRC_SOURCE_DP_D,
1638 	INTEL_PIPE_CRC_SOURCE_AUTO,
1639 	INTEL_PIPE_CRC_SOURCE_MAX,
1640 };
1641 
1642 struct intel_pipe_crc_entry {
1643 	uint32_t frame;
1644 	uint32_t crc[5];
1645 };
1646 
1647 #define INTEL_PIPE_CRC_ENTRIES_NR	128
1648 struct intel_pipe_crc {
1649 	spinlock_t lock;
1650 	bool opened;		/* exclusive access to the result file */
1651 	struct intel_pipe_crc_entry *entries;
1652 	enum intel_pipe_crc_source source;
1653 	int head, tail;
1654 	wait_queue_head_t wq;
1655 };
1656 
1657 struct i915_frontbuffer_tracking {
1658 	struct mutex lock;
1659 
1660 	/*
1661 	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1662 	 * scheduled flips.
1663 	 */
1664 	unsigned busy_bits;
1665 	unsigned flip_bits;
1666 };
1667 
1668 struct i915_wa_reg {
1669 	i915_reg_t addr;
1670 	u32 value;
1671 	/* bitmask representing WA bits */
1672 	u32 mask;
1673 };
1674 
1675 /*
1676  * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1677  * allowing it for RCS as we don't foresee any requirement of having
1678  * a whitelist for other engines. When it is really required for
1679  * other engines then the limit need to be increased.
1680  */
1681 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1682 
1683 struct i915_workarounds {
1684 	struct i915_wa_reg reg[I915_MAX_WA_REGS];
1685 	u32 count;
1686 	u32 hw_whitelist_count[I915_NUM_ENGINES];
1687 };
1688 
1689 struct i915_virtual_gpu {
1690 	bool active;
1691 };
1692 
1693 struct i915_execbuffer_params {
1694 	struct drm_device               *dev;
1695 	struct drm_file                 *file;
1696 	uint32_t                        dispatch_flags;
1697 	uint32_t                        args_batch_start_offset;
1698 	uint64_t                        batch_obj_vm_offset;
1699 	struct intel_engine_cs *engine;
1700 	struct drm_i915_gem_object      *batch_obj;
1701 	struct intel_context            *ctx;
1702 	struct drm_i915_gem_request     *request;
1703 };
1704 
1705 /* used in computing the new watermarks state */
1706 struct intel_wm_config {
1707 	unsigned int num_pipes_active;
1708 	bool sprites_enabled;
1709 	bool sprites_scaled;
1710 };
1711 
1712 struct drm_i915_private {
1713 	struct drm_device *dev;
1714 	struct kmem_cache *objects;
1715 	struct kmem_cache *vmas;
1716 	struct kmem_cache *requests;
1717 
1718 	const struct intel_device_info info;
1719 
1720 	int relative_constants_mode;
1721 
1722 	void __iomem *regs;
1723 
1724 	struct intel_uncore uncore;
1725 
1726 	struct i915_virtual_gpu vgpu;
1727 
1728 	struct intel_guc guc;
1729 
1730 	struct intel_csr csr;
1731 
1732 	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1733 
1734 	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
1735 	 * controller on different i2c buses. */
1736 	struct mutex gmbus_mutex;
1737 
1738 	/**
1739 	 * Base address of the gmbus and gpio block.
1740 	 */
1741 	uint32_t gpio_mmio_base;
1742 
1743 	/* MMIO base address for MIPI regs */
1744 	uint32_t mipi_mmio_base;
1745 
1746 	uint32_t psr_mmio_base;
1747 
1748 	wait_queue_head_t gmbus_wait_queue;
1749 
1750 	struct pci_dev *bridge_dev;
1751 	struct intel_engine_cs engine[I915_NUM_ENGINES];
1752 	struct drm_i915_gem_object *semaphore_obj;
1753 	uint32_t last_seqno, next_seqno;
1754 
1755 	struct drm_dma_handle *status_page_dmah;
1756 	struct resource mch_res;
1757 
1758 	/* protects the irq masks */
1759 	spinlock_t irq_lock;
1760 
1761 	/* protects the mmio flip data */
1762 	spinlock_t mmio_flip_lock;
1763 
1764 	bool display_irqs_enabled;
1765 
1766 	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1767 	struct pm_qos_request pm_qos;
1768 
1769 	/* Sideband mailbox protection */
1770 	struct mutex sb_lock;
1771 
1772 	/** Cached value of IMR to avoid reads in updating the bitfield */
1773 	union {
1774 		u32 irq_mask;
1775 		u32 de_irq_mask[I915_MAX_PIPES];
1776 	};
1777 	u32 gt_irq_mask;
1778 	u32 pm_irq_mask;
1779 	u32 pm_rps_events;
1780 	u32 pipestat_irq_mask[I915_MAX_PIPES];
1781 
1782 	struct i915_hotplug hotplug;
1783 	struct intel_fbc fbc;
1784 	struct i915_drrs drrs;
1785 	struct intel_opregion opregion;
1786 	struct intel_vbt_data vbt;
1787 
1788 	bool preserve_bios_swizzle;
1789 
1790 	/* overlay */
1791 	struct intel_overlay *overlay;
1792 
1793 	/* backlight registers and fields in struct intel_panel */
1794 	struct mutex backlight_lock;
1795 
1796 	/* LVDS info */
1797 	bool no_aux_handshake;
1798 
1799 	/* protects panel power sequencer state */
1800 	struct mutex pps_mutex;
1801 
1802 	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1803 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1804 
1805 	unsigned int fsb_freq, mem_freq, is_ddr3;
1806 	unsigned int skl_boot_cdclk;
1807 	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1808 	unsigned int max_dotclk_freq;
1809 	unsigned int rawclk_freq;
1810 	unsigned int hpll_freq;
1811 	unsigned int czclk_freq;
1812 
1813 	/**
1814 	 * wq - Driver workqueue for GEM.
1815 	 *
1816 	 * NOTE: Work items scheduled here are not allowed to grab any modeset
1817 	 * locks, for otherwise the flushing done in the pageflip code will
1818 	 * result in deadlocks.
1819 	 */
1820 	struct workqueue_struct *wq;
1821 
1822 	/* Display functions */
1823 	struct drm_i915_display_funcs display;
1824 
1825 	/* PCH chipset type */
1826 	enum intel_pch pch_type;
1827 	unsigned short pch_id;
1828 
1829 	unsigned long quirks;
1830 
1831 	enum modeset_restore modeset_restore;
1832 	struct mutex modeset_restore_lock;
1833 	struct drm_atomic_state *modeset_restore_state;
1834 
1835 	struct list_head vm_list; /* Global list of all address spaces */
1836 	struct i915_ggtt ggtt; /* VM representing the global address space */
1837 
1838 	struct i915_gem_mm mm;
1839 	DECLARE_HASHTABLE(mm_structs, 7);
1840 	struct mutex mm_lock;
1841 
1842 	/* Kernel Modesetting */
1843 
1844 	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1845 	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1846 	wait_queue_head_t pending_flip_queue;
1847 
1848 #ifdef CONFIG_DEBUG_FS
1849 	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1850 #endif
1851 
1852 	/* dpll and cdclk state is protected by connection_mutex */
1853 	int num_shared_dpll;
1854 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1855 	const struct intel_dpll_mgr *dpll_mgr;
1856 
1857 	/*
1858 	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1859 	 * Must be global rather than per dpll, because on some platforms
1860 	 * plls share registers.
1861 	 */
1862 	struct mutex dpll_lock;
1863 
1864 	unsigned int active_crtcs;
1865 	unsigned int min_pixclk[I915_MAX_PIPES];
1866 
1867 	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1868 
1869 	struct i915_workarounds workarounds;
1870 
1871 	struct i915_frontbuffer_tracking fb_tracking;
1872 
1873 	u16 orig_clock;
1874 
1875 	bool mchbar_need_disable;
1876 
1877 	struct intel_l3_parity l3_parity;
1878 
1879 	/* Cannot be determined by PCIID. You must always read a register. */
1880 	u32 edram_cap;
1881 
1882 	/* gen6+ rps state */
1883 	struct intel_gen6_power_mgmt rps;
1884 
1885 	/* ilk-only ips/rps state. Everything in here is protected by the global
1886 	 * mchdev_lock in intel_pm.c */
1887 	struct intel_ilk_power_mgmt ips;
1888 
1889 	struct i915_power_domains power_domains;
1890 
1891 	struct i915_psr psr;
1892 
1893 	struct i915_gpu_error gpu_error;
1894 
1895 	struct drm_i915_gem_object *vlv_pctx;
1896 
1897 #ifdef CONFIG_DRM_FBDEV_EMULATION
1898 	/* list of fbdev register on this device */
1899 	struct intel_fbdev *fbdev;
1900 	struct work_struct fbdev_suspend_work;
1901 #endif
1902 
1903 	struct drm_property *broadcast_rgb_property;
1904 	struct drm_property *force_audio_property;
1905 
1906 	/* hda/i915 audio component */
1907 	struct i915_audio_component *audio_component;
1908 	bool audio_component_registered;
1909 	/**
1910 	 * av_mutex - mutex for audio/video sync
1911 	 *
1912 	 */
1913 	struct mutex av_mutex;
1914 
1915 	uint32_t hw_context_size;
1916 	struct list_head context_list;
1917 
1918 	u32 fdi_rx_config;
1919 
1920 	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1921 	u32 chv_phy_control;
1922 	/*
1923 	 * Shadows for CHV DPLL_MD regs to keep the state
1924 	 * checker somewhat working in the presence hardware
1925 	 * crappiness (can't read out DPLL_MD for pipes B & C).
1926 	 */
1927 	u32 chv_dpll_md[I915_MAX_PIPES];
1928 	u32 bxt_phy_grc;
1929 
1930 	u32 suspend_count;
1931 	bool suspended_to_idle;
1932 	struct i915_suspend_saved_registers regfile;
1933 	struct vlv_s0ix_state vlv_s0ix_state;
1934 
1935 	struct {
1936 		/*
1937 		 * Raw watermark latency values:
1938 		 * in 0.1us units for WM0,
1939 		 * in 0.5us units for WM1+.
1940 		 */
1941 		/* primary */
1942 		uint16_t pri_latency[5];
1943 		/* sprite */
1944 		uint16_t spr_latency[5];
1945 		/* cursor */
1946 		uint16_t cur_latency[5];
1947 		/*
1948 		 * Raw watermark memory latency values
1949 		 * for SKL for all 8 levels
1950 		 * in 1us units.
1951 		 */
1952 		uint16_t skl_latency[8];
1953 
1954 		/* Committed wm config */
1955 		struct intel_wm_config config;
1956 
1957 		/*
1958 		 * The skl_wm_values structure is a bit too big for stack
1959 		 * allocation, so we keep the staging struct where we store
1960 		 * intermediate results here instead.
1961 		 */
1962 		struct skl_wm_values skl_results;
1963 
1964 		/* current hardware state */
1965 		union {
1966 			struct ilk_wm_values hw;
1967 			struct skl_wm_values skl_hw;
1968 			struct vlv_wm_values vlv;
1969 		};
1970 
1971 		uint8_t max_level;
1972 
1973 		/*
1974 		 * Should be held around atomic WM register writing; also
1975 		 * protects * intel_crtc->wm.active and
1976 		 * cstate->wm.need_postvbl_update.
1977 		 */
1978 		struct mutex wm_mutex;
1979 	} wm;
1980 
1981 	struct i915_runtime_pm pm;
1982 
1983 	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1984 	struct {
1985 		int (*execbuf_submit)(struct i915_execbuffer_params *params,
1986 				      struct drm_i915_gem_execbuffer2 *args,
1987 				      struct list_head *vmas);
1988 		int (*init_engines)(struct drm_device *dev);
1989 		void (*cleanup_engine)(struct intel_engine_cs *engine);
1990 		void (*stop_engine)(struct intel_engine_cs *engine);
1991 	} gt;
1992 
1993 	struct intel_context *kernel_context;
1994 
1995 	/* perform PHY state sanity checks? */
1996 	bool chv_phy_assert[2];
1997 
1998 	struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1999 
2000 	/*
2001 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2002 	 * will be rejected. Instead look for a better place.
2003 	 */
2004 };
2005 
2006 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2007 {
2008 	return dev->dev_private;
2009 }
2010 
2011 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2012 {
2013 	return to_i915(dev_get_drvdata(dev));
2014 }
2015 
2016 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2017 {
2018 	return container_of(guc, struct drm_i915_private, guc);
2019 }
2020 
2021 /* Simple iterator over all initialised engines */
2022 #define for_each_engine(engine__, dev_priv__) \
2023 	for ((engine__) = &(dev_priv__)->engine[0]; \
2024 	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2025 	     (engine__)++) \
2026 		for_each_if (intel_engine_initialized(engine__))
2027 
2028 /* Iterator with engine_id */
2029 #define for_each_engine_id(engine__, dev_priv__, id__) \
2030 	for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2031 	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2032 	     (engine__)++) \
2033 		for_each_if (((id__) = (engine__)->id, \
2034 			      intel_engine_initialized(engine__)))
2035 
2036 /* Iterator over subset of engines selected by mask */
2037 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2038 	for ((engine__) = &(dev_priv__)->engine[0]; \
2039 	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2040 	     (engine__)++) \
2041 		for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2042 			     intel_engine_initialized(engine__))
2043 
2044 enum hdmi_force_audio {
2045 	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
2046 	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
2047 	HDMI_AUDIO_AUTO,		/* trust EDID */
2048 	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
2049 };
2050 
2051 #define I915_GTT_OFFSET_NONE ((u32)-1)
2052 
2053 struct drm_i915_gem_object_ops {
2054 	unsigned int flags;
2055 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2056 
2057 	/* Interface between the GEM object and its backing storage.
2058 	 * get_pages() is called once prior to the use of the associated set
2059 	 * of pages before to binding them into the GTT, and put_pages() is
2060 	 * called after we no longer need them. As we expect there to be
2061 	 * associated cost with migrating pages between the backing storage
2062 	 * and making them available for the GPU (e.g. clflush), we may hold
2063 	 * onto the pages after they are no longer referenced by the GPU
2064 	 * in case they may be used again shortly (for example migrating the
2065 	 * pages to a different memory domain within the GTT). put_pages()
2066 	 * will therefore most likely be called when the object itself is
2067 	 * being released or under memory pressure (where we attempt to
2068 	 * reap pages for the shrinker).
2069 	 */
2070 	int (*get_pages)(struct drm_i915_gem_object *);
2071 	void (*put_pages)(struct drm_i915_gem_object *);
2072 
2073 	int (*dmabuf_export)(struct drm_i915_gem_object *);
2074 	void (*release)(struct drm_i915_gem_object *);
2075 };
2076 
2077 /*
2078  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2079  * considered to be the frontbuffer for the given plane interface-wise. This
2080  * doesn't mean that the hw necessarily already scans it out, but that any
2081  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2082  *
2083  * We have one bit per pipe and per scanout plane type.
2084  */
2085 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2086 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2087 #define INTEL_FRONTBUFFER_BITS \
2088 	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2089 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2090 	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2091 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2092 	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2093 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2094 	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2095 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2096 	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2097 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2098 	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2099 
2100 struct drm_i915_gem_object {
2101 	struct drm_gem_object base;
2102 
2103 	const struct drm_i915_gem_object_ops *ops;
2104 
2105 	/** List of VMAs backed by this object */
2106 	struct list_head vma_list;
2107 
2108 	/** Stolen memory for this object, instead of being backed by shmem. */
2109 	struct drm_mm_node *stolen;
2110 	struct list_head global_list;
2111 
2112 	struct list_head engine_list[I915_NUM_ENGINES];
2113 	/** Used in execbuf to temporarily hold a ref */
2114 	struct list_head obj_exec_link;
2115 
2116 	struct list_head batch_pool_link;
2117 
2118 	/**
2119 	 * This is set if the object is on the active lists (has pending
2120 	 * rendering and so a non-zero seqno), and is not set if it i s on
2121 	 * inactive (ready to be unbound) list.
2122 	 */
2123 	unsigned int active:I915_NUM_ENGINES;
2124 
2125 	/**
2126 	 * This is set if the object has been written to since last bound
2127 	 * to the GTT
2128 	 */
2129 	unsigned int dirty:1;
2130 
2131 	/**
2132 	 * Fence register bits (if any) for this object.  Will be set
2133 	 * as needed when mapped into the GTT.
2134 	 * Protected by dev->struct_mutex.
2135 	 */
2136 	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2137 
2138 	/**
2139 	 * Advice: are the backing pages purgeable?
2140 	 */
2141 	unsigned int madv:2;
2142 
2143 	/**
2144 	 * Current tiling mode for the object.
2145 	 */
2146 	unsigned int tiling_mode:2;
2147 	/**
2148 	 * Whether the tiling parameters for the currently associated fence
2149 	 * register have changed. Note that for the purposes of tracking
2150 	 * tiling changes we also treat the unfenced register, the register
2151 	 * slot that the object occupies whilst it executes a fenced
2152 	 * command (such as BLT on gen2/3), as a "fence".
2153 	 */
2154 	unsigned int fence_dirty:1;
2155 
2156 	/**
2157 	 * Is the object at the current location in the gtt mappable and
2158 	 * fenceable? Used to avoid costly recalculations.
2159 	 */
2160 	unsigned int map_and_fenceable:1;
2161 
2162 	/**
2163 	 * Whether the current gtt mapping needs to be mappable (and isn't just
2164 	 * mappable by accident). Track pin and fault separate for a more
2165 	 * accurate mappable working set.
2166 	 */
2167 	unsigned int fault_mappable:1;
2168 
2169 	/*
2170 	 * Is the object to be mapped as read-only to the GPU
2171 	 * Only honoured if hardware has relevant pte bit
2172 	 */
2173 	unsigned long gt_ro:1;
2174 	unsigned int cache_level:3;
2175 	unsigned int cache_dirty:1;
2176 
2177 	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2178 
2179 	unsigned int pin_display;
2180 
2181 	struct sg_table *pages;
2182 	int pages_pin_count;
2183 	struct get_page {
2184 		struct scatterlist *sg;
2185 		int last;
2186 	} get_page;
2187 	void *mapping;
2188 
2189 	/** Breadcrumb of last rendering to the buffer.
2190 	 * There can only be one writer, but we allow for multiple readers.
2191 	 * If there is a writer that necessarily implies that all other
2192 	 * read requests are complete - but we may only be lazily clearing
2193 	 * the read requests. A read request is naturally the most recent
2194 	 * request on a ring, so we may have two different write and read
2195 	 * requests on one ring where the write request is older than the
2196 	 * read request. This allows for the CPU to read from an active
2197 	 * buffer by only waiting for the write to complete.
2198 	 * */
2199 	struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2200 	struct drm_i915_gem_request *last_write_req;
2201 	/** Breadcrumb of last fenced GPU access to the buffer. */
2202 	struct drm_i915_gem_request *last_fenced_req;
2203 
2204 	/** Current tiling stride for the object, if it's tiled. */
2205 	uint32_t stride;
2206 
2207 	/** References from framebuffers, locks out tiling changes. */
2208 	unsigned long framebuffer_references;
2209 
2210 	/** Record of address bit 17 of each page at last unbind. */
2211 	unsigned long *bit_17;
2212 
2213 	union {
2214 		/** for phy allocated objects */
2215 		struct drm_dma_handle *phys_handle;
2216 
2217 		struct i915_gem_userptr {
2218 			uintptr_t ptr;
2219 			unsigned read_only :1;
2220 			unsigned workers :4;
2221 #define I915_GEM_USERPTR_MAX_WORKERS 15
2222 
2223 			struct i915_mm_struct *mm;
2224 			struct i915_mmu_object *mmu_object;
2225 			struct work_struct *work;
2226 		} userptr;
2227 	};
2228 };
2229 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2230 
2231 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2232 		       struct drm_i915_gem_object *new,
2233 		       unsigned frontbuffer_bits);
2234 
2235 /**
2236  * Request queue structure.
2237  *
2238  * The request queue allows us to note sequence numbers that have been emitted
2239  * and may be associated with active buffers to be retired.
2240  *
2241  * By keeping this list, we can avoid having to do questionable sequence
2242  * number comparisons on buffer last_read|write_seqno. It also allows an
2243  * emission time to be associated with the request for tracking how far ahead
2244  * of the GPU the submission is.
2245  *
2246  * The requests are reference counted, so upon creation they should have an
2247  * initial reference taken using kref_init
2248  */
2249 struct drm_i915_gem_request {
2250 	struct kref ref;
2251 
2252 	/** On Which ring this request was generated */
2253 	struct drm_i915_private *i915;
2254 	struct intel_engine_cs *engine;
2255 	unsigned reset_counter;
2256 
2257 	 /** GEM sequence number associated with the previous request,
2258 	  * when the HWS breadcrumb is equal to this the GPU is processing
2259 	  * this request.
2260 	  */
2261 	u32 previous_seqno;
2262 
2263 	 /** GEM sequence number associated with this request,
2264 	  * when the HWS breadcrumb is equal or greater than this the GPU
2265 	  * has finished processing this request.
2266 	  */
2267 	u32 seqno;
2268 
2269 	/** Position in the ringbuffer of the start of the request */
2270 	u32 head;
2271 
2272 	/**
2273 	 * Position in the ringbuffer of the start of the postfix.
2274 	 * This is required to calculate the maximum available ringbuffer
2275 	 * space without overwriting the postfix.
2276 	 */
2277 	 u32 postfix;
2278 
2279 	/** Position in the ringbuffer of the end of the whole request */
2280 	u32 tail;
2281 
2282 	/**
2283 	 * Context and ring buffer related to this request
2284 	 * Contexts are refcounted, so when this request is associated with a
2285 	 * context, we must increment the context's refcount, to guarantee that
2286 	 * it persists while any request is linked to it. Requests themselves
2287 	 * are also refcounted, so the request will only be freed when the last
2288 	 * reference to it is dismissed, and the code in
2289 	 * i915_gem_request_free() will then decrement the refcount on the
2290 	 * context.
2291 	 */
2292 	struct intel_context *ctx;
2293 	struct intel_ringbuffer *ringbuf;
2294 
2295 	/** Batch buffer related to this request if any (used for
2296 	    error state dump only) */
2297 	struct drm_i915_gem_object *batch_obj;
2298 
2299 	/** Time at which this request was emitted, in jiffies. */
2300 	unsigned long emitted_jiffies;
2301 
2302 	/** global list entry for this request */
2303 	struct list_head list;
2304 
2305 	struct drm_i915_file_private *file_priv;
2306 	/** file_priv list entry for this request */
2307 	struct list_head client_list;
2308 
2309 	/** process identifier submitting this request */
2310 	struct pid *pid;
2311 
2312 	/**
2313 	 * The ELSP only accepts two elements at a time, so we queue
2314 	 * context/tail pairs on a given queue (ring->execlist_queue) until the
2315 	 * hardware is available. The queue serves a double purpose: we also use
2316 	 * it to keep track of the up to 2 contexts currently in the hardware
2317 	 * (usually one in execution and the other queued up by the GPU): We
2318 	 * only remove elements from the head of the queue when the hardware
2319 	 * informs us that an element has been completed.
2320 	 *
2321 	 * All accesses to the queue are mediated by a spinlock
2322 	 * (ring->execlist_lock).
2323 	 */
2324 
2325 	/** Execlist link in the submission queue.*/
2326 	struct list_head execlist_link;
2327 
2328 	/** Execlists no. of times this request has been sent to the ELSP */
2329 	int elsp_submitted;
2330 
2331 };
2332 
2333 struct drm_i915_gem_request * __must_check
2334 i915_gem_request_alloc(struct intel_engine_cs *engine,
2335 		       struct intel_context *ctx);
2336 void i915_gem_request_free(struct kref *req_ref);
2337 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2338 				   struct drm_file *file);
2339 
2340 static inline uint32_t
2341 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2342 {
2343 	return req ? req->seqno : 0;
2344 }
2345 
2346 static inline struct intel_engine_cs *
2347 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2348 {
2349 	return req ? req->engine : NULL;
2350 }
2351 
2352 static inline struct drm_i915_gem_request *
2353 i915_gem_request_reference(struct drm_i915_gem_request *req)
2354 {
2355 	if (req)
2356 		kref_get(&req->ref);
2357 	return req;
2358 }
2359 
2360 static inline void
2361 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2362 {
2363 	WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
2364 	kref_put(&req->ref, i915_gem_request_free);
2365 }
2366 
2367 static inline void
2368 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2369 {
2370 	struct drm_device *dev;
2371 
2372 	if (!req)
2373 		return;
2374 
2375 	dev = req->engine->dev;
2376 	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2377 		mutex_unlock(&dev->struct_mutex);
2378 }
2379 
2380 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2381 					   struct drm_i915_gem_request *src)
2382 {
2383 	if (src)
2384 		i915_gem_request_reference(src);
2385 
2386 	if (*pdst)
2387 		i915_gem_request_unreference(*pdst);
2388 
2389 	*pdst = src;
2390 }
2391 
2392 /*
2393  * XXX: i915_gem_request_completed should be here but currently needs the
2394  * definition of i915_seqno_passed() which is below. It will be moved in
2395  * a later patch when the call to i915_seqno_passed() is obsoleted...
2396  */
2397 
2398 /*
2399  * A command that requires special handling by the command parser.
2400  */
2401 struct drm_i915_cmd_descriptor {
2402 	/*
2403 	 * Flags describing how the command parser processes the command.
2404 	 *
2405 	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2406 	 *                 a length mask if not set
2407 	 * CMD_DESC_SKIP: The command is allowed but does not follow the
2408 	 *                standard length encoding for the opcode range in
2409 	 *                which it falls
2410 	 * CMD_DESC_REJECT: The command is never allowed
2411 	 * CMD_DESC_REGISTER: The command should be checked against the
2412 	 *                    register whitelist for the appropriate ring
2413 	 * CMD_DESC_MASTER: The command is allowed if the submitting process
2414 	 *                  is the DRM master
2415 	 */
2416 	u32 flags;
2417 #define CMD_DESC_FIXED    (1<<0)
2418 #define CMD_DESC_SKIP     (1<<1)
2419 #define CMD_DESC_REJECT   (1<<2)
2420 #define CMD_DESC_REGISTER (1<<3)
2421 #define CMD_DESC_BITMASK  (1<<4)
2422 #define CMD_DESC_MASTER   (1<<5)
2423 
2424 	/*
2425 	 * The command's unique identification bits and the bitmask to get them.
2426 	 * This isn't strictly the opcode field as defined in the spec and may
2427 	 * also include type, subtype, and/or subop fields.
2428 	 */
2429 	struct {
2430 		u32 value;
2431 		u32 mask;
2432 	} cmd;
2433 
2434 	/*
2435 	 * The command's length. The command is either fixed length (i.e. does
2436 	 * not include a length field) or has a length field mask. The flag
2437 	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2438 	 * a length mask. All command entries in a command table must include
2439 	 * length information.
2440 	 */
2441 	union {
2442 		u32 fixed;
2443 		u32 mask;
2444 	} length;
2445 
2446 	/*
2447 	 * Describes where to find a register address in the command to check
2448 	 * against the ring's register whitelist. Only valid if flags has the
2449 	 * CMD_DESC_REGISTER bit set.
2450 	 *
2451 	 * A non-zero step value implies that the command may access multiple
2452 	 * registers in sequence (e.g. LRI), in that case step gives the
2453 	 * distance in dwords between individual offset fields.
2454 	 */
2455 	struct {
2456 		u32 offset;
2457 		u32 mask;
2458 		u32 step;
2459 	} reg;
2460 
2461 #define MAX_CMD_DESC_BITMASKS 3
2462 	/*
2463 	 * Describes command checks where a particular dword is masked and
2464 	 * compared against an expected value. If the command does not match
2465 	 * the expected value, the parser rejects it. Only valid if flags has
2466 	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2467 	 * are valid.
2468 	 *
2469 	 * If the check specifies a non-zero condition_mask then the parser
2470 	 * only performs the check when the bits specified by condition_mask
2471 	 * are non-zero.
2472 	 */
2473 	struct {
2474 		u32 offset;
2475 		u32 mask;
2476 		u32 expected;
2477 		u32 condition_offset;
2478 		u32 condition_mask;
2479 	} bits[MAX_CMD_DESC_BITMASKS];
2480 };
2481 
2482 /*
2483  * A table of commands requiring special handling by the command parser.
2484  *
2485  * Each ring has an array of tables. Each table consists of an array of command
2486  * descriptors, which must be sorted with command opcodes in ascending order.
2487  */
2488 struct drm_i915_cmd_table {
2489 	const struct drm_i915_cmd_descriptor *table;
2490 	int count;
2491 };
2492 
2493 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2494 #define __I915__(p) ({ \
2495 	struct drm_i915_private *__p; \
2496 	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2497 		__p = (struct drm_i915_private *)p; \
2498 	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2499 		__p = to_i915((struct drm_device *)p); \
2500 	else \
2501 		BUILD_BUG(); \
2502 	__p; \
2503 })
2504 #define INTEL_INFO(p) 	(&__I915__(p)->info)
2505 #define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
2506 #define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2507 #define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
2508 
2509 #define REVID_FOREVER		0xff
2510 /*
2511  * Return true if revision is in range [since,until] inclusive.
2512  *
2513  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2514  */
2515 #define IS_REVID(p, since, until) \
2516 	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2517 
2518 #define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
2519 #define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2520 #define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2521 #define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2522 #define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2523 #define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
2524 #define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2525 #define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
2526 #define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
2527 #define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2528 #define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2529 #define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2530 #define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
2531 #define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2532 #define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
2533 #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2534 #define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2535 #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2536 #define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
2537 				 INTEL_DEVID(dev) == 0x0152 || \
2538 				 INTEL_DEVID(dev) == 0x015a)
2539 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2540 #define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2541 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2542 #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2543 #define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2544 #define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2545 #define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2546 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2547 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2548 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2549 #define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2550 				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2551 				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2552 				 (INTEL_DEVID(dev) & 0xf) == 0xe))
2553 /* ULX machines are also considered ULT. */
2554 #define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
2555 				 (INTEL_DEVID(dev) & 0xf) == 0xe)
2556 #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
2557 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2558 #define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2559 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2560 #define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2561 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2562 /* ULX machines are also considered ULT. */
2563 #define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
2564 				 INTEL_DEVID(dev) == 0x0A1E)
2565 #define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
2566 				 INTEL_DEVID(dev) == 0x1913 || \
2567 				 INTEL_DEVID(dev) == 0x1916 || \
2568 				 INTEL_DEVID(dev) == 0x1921 || \
2569 				 INTEL_DEVID(dev) == 0x1926)
2570 #define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
2571 				 INTEL_DEVID(dev) == 0x1915 || \
2572 				 INTEL_DEVID(dev) == 0x191E)
2573 #define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
2574 				 INTEL_DEVID(dev) == 0x5913 || \
2575 				 INTEL_DEVID(dev) == 0x5916 || \
2576 				 INTEL_DEVID(dev) == 0x5921 || \
2577 				 INTEL_DEVID(dev) == 0x5926)
2578 #define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
2579 				 INTEL_DEVID(dev) == 0x5915 || \
2580 				 INTEL_DEVID(dev) == 0x591E)
2581 #define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
2582 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2583 #define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
2584 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2585 
2586 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2587 
2588 #define SKL_REVID_A0		0x0
2589 #define SKL_REVID_B0		0x1
2590 #define SKL_REVID_C0		0x2
2591 #define SKL_REVID_D0		0x3
2592 #define SKL_REVID_E0		0x4
2593 #define SKL_REVID_F0		0x5
2594 
2595 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2596 
2597 #define BXT_REVID_A0		0x0
2598 #define BXT_REVID_A1		0x1
2599 #define BXT_REVID_B0		0x3
2600 #define BXT_REVID_C0		0x9
2601 
2602 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2603 
2604 #define KBL_REVID_A0		0x0
2605 #define KBL_REVID_B0		0x1
2606 #define KBL_REVID_C0		0x2
2607 #define KBL_REVID_D0		0x3
2608 #define KBL_REVID_E0		0x4
2609 
2610 #define IS_KBL_REVID(p, since, until) \
2611 	(IS_KABYLAKE(p) && IS_REVID(p, since, until))
2612 
2613 /*
2614  * The genX designation typically refers to the render engine, so render
2615  * capability related checks should use IS_GEN, while display and other checks
2616  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2617  * chips, etc.).
2618  */
2619 #define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
2620 #define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
2621 #define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
2622 #define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
2623 #define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2624 #define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
2625 #define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2626 #define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2627 
2628 #define RENDER_RING		(1<<RCS)
2629 #define BSD_RING		(1<<VCS)
2630 #define BLT_RING		(1<<BCS)
2631 #define VEBOX_RING		(1<<VECS)
2632 #define BSD2_RING		(1<<VCS2)
2633 #define ALL_ENGINES		(~0)
2634 
2635 #define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2636 #define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2637 #define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
2638 #define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2639 #define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2640 #define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
2641 #define HAS_EDRAM(dev)		(__I915__(dev)->edram_cap & EDRAM_ENABLED)
2642 #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2643 				 HAS_EDRAM(dev))
2644 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
2645 
2646 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2647 #define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2648 #define USES_PPGTT(dev)		(i915.enable_ppgtt)
2649 #define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
2650 #define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2651 
2652 #define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2653 #define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
2654 
2655 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2656 #define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2657 
2658 /* WaRsDisableCoarsePowerGating:skl,bxt */
2659 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2660 						 IS_SKL_GT3(dev) || \
2661 						 IS_SKL_GT4(dev))
2662 
2663 /*
2664  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2665  * even when in MSI mode. This results in spurious interrupt warnings if the
2666  * legacy irq no. is shared with another device. The kernel then disables that
2667  * interrupt source and so prevents the other device from working properly.
2668  */
2669 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2670 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2671 
2672 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2673  * rows, which changed the alignment requirements and fence programming.
2674  */
2675 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2676 						      IS_I915GM(dev)))
2677 #define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
2678 #define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
2679 
2680 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2681 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2682 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2683 
2684 #define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2685 
2686 #define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2687 				 INTEL_INFO(dev)->gen >= 9)
2688 
2689 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2690 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2691 #define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2692 				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2693 				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2694 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
2695 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2696 				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2697 				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2698 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
2699 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2700 
2701 #define HAS_CSR(dev)	(IS_GEN9(dev))
2702 
2703 #define HAS_GUC_UCODE(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
2704 #define HAS_GUC_SCHED(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
2705 
2706 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2707 				    INTEL_INFO(dev)->gen >= 8)
2708 
2709 #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2710 				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2711 				 !IS_BROXTON(dev))
2712 
2713 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
2714 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
2715 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
2716 #define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
2717 #define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
2718 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2719 #define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
2720 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2721 #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2722 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2723 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2724 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2725 
2726 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2727 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2728 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2729 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2730 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2731 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2732 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2733 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2734 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2735 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2736 
2737 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2738 			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2739 
2740 /* DPF == dynamic parity feature */
2741 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2742 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2743 
2744 #define GT_FREQUENCY_MULTIPLIER 50
2745 #define GEN9_FREQ_SCALER 3
2746 
2747 #include "i915_trace.h"
2748 
2749 extern const struct drm_ioctl_desc i915_ioctls[];
2750 extern int i915_max_ioctl;
2751 
2752 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2753 extern int i915_resume_switcheroo(struct drm_device *dev);
2754 
2755 /* i915_dma.c */
2756 void __printf(3, 4)
2757 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2758 	      const char *fmt, ...);
2759 
2760 #define i915_report_error(dev_priv, fmt, ...)				   \
2761 	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2762 
2763 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2764 extern int i915_driver_unload(struct drm_device *);
2765 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2766 extern void i915_driver_lastclose(struct drm_device * dev);
2767 extern void i915_driver_preclose(struct drm_device *dev,
2768 				 struct drm_file *file);
2769 extern void i915_driver_postclose(struct drm_device *dev,
2770 				  struct drm_file *file);
2771 #ifdef CONFIG_COMPAT
2772 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2773 			      unsigned long arg);
2774 #endif
2775 extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
2776 extern bool intel_has_gpu_reset(struct drm_device *dev);
2777 extern int i915_reset(struct drm_device *dev);
2778 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2779 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2780 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2781 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2782 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2783 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2784 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2785 
2786 /* intel_hotplug.c */
2787 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2788 void intel_hpd_init(struct drm_i915_private *dev_priv);
2789 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2790 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2791 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2792 
2793 /* i915_irq.c */
2794 void i915_queue_hangcheck(struct drm_device *dev);
2795 __printf(3, 4)
2796 void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2797 		       const char *fmt, ...);
2798 
2799 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2800 int intel_irq_install(struct drm_i915_private *dev_priv);
2801 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2802 
2803 extern void intel_uncore_sanitize(struct drm_device *dev);
2804 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2805 					bool restore_forcewake);
2806 extern void intel_uncore_init(struct drm_device *dev);
2807 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2808 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2809 extern void intel_uncore_fini(struct drm_device *dev);
2810 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2811 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2812 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2813 				enum forcewake_domains domains);
2814 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2815 				enum forcewake_domains domains);
2816 /* Like above but the caller must manage the uncore.lock itself.
2817  * Must be used with I915_READ_FW and friends.
2818  */
2819 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2820 					enum forcewake_domains domains);
2821 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2822 					enum forcewake_domains domains);
2823 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2824 
2825 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2826 static inline bool intel_vgpu_active(struct drm_device *dev)
2827 {
2828 	return to_i915(dev)->vgpu.active;
2829 }
2830 
2831 void
2832 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2833 		     u32 status_mask);
2834 
2835 void
2836 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2837 		      u32 status_mask);
2838 
2839 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2840 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2841 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2842 				   uint32_t mask,
2843 				   uint32_t bits);
2844 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2845 			    uint32_t interrupt_mask,
2846 			    uint32_t enabled_irq_mask);
2847 static inline void
2848 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2849 {
2850 	ilk_update_display_irq(dev_priv, bits, bits);
2851 }
2852 static inline void
2853 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2854 {
2855 	ilk_update_display_irq(dev_priv, bits, 0);
2856 }
2857 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2858 			 enum pipe pipe,
2859 			 uint32_t interrupt_mask,
2860 			 uint32_t enabled_irq_mask);
2861 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2862 				       enum pipe pipe, uint32_t bits)
2863 {
2864 	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2865 }
2866 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2867 					enum pipe pipe, uint32_t bits)
2868 {
2869 	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2870 }
2871 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2872 				  uint32_t interrupt_mask,
2873 				  uint32_t enabled_irq_mask);
2874 static inline void
2875 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2876 {
2877 	ibx_display_interrupt_update(dev_priv, bits, bits);
2878 }
2879 static inline void
2880 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2881 {
2882 	ibx_display_interrupt_update(dev_priv, bits, 0);
2883 }
2884 
2885 
2886 /* i915_gem.c */
2887 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2888 			  struct drm_file *file_priv);
2889 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2890 			 struct drm_file *file_priv);
2891 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2892 			  struct drm_file *file_priv);
2893 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2894 			struct drm_file *file_priv);
2895 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2896 			struct drm_file *file_priv);
2897 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2898 			      struct drm_file *file_priv);
2899 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2900 			     struct drm_file *file_priv);
2901 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2902 					struct drm_i915_gem_request *req);
2903 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2904 				   struct drm_i915_gem_execbuffer2 *args,
2905 				   struct list_head *vmas);
2906 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2907 			struct drm_file *file_priv);
2908 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2909 			 struct drm_file *file_priv);
2910 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2911 			struct drm_file *file_priv);
2912 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2913 			       struct drm_file *file);
2914 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2915 			       struct drm_file *file);
2916 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2917 			    struct drm_file *file_priv);
2918 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2919 			   struct drm_file *file_priv);
2920 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2921 			struct drm_file *file_priv);
2922 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2923 			struct drm_file *file_priv);
2924 int i915_gem_init_userptr(struct drm_device *dev);
2925 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2926 			   struct drm_file *file);
2927 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2928 				struct drm_file *file_priv);
2929 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2930 			struct drm_file *file_priv);
2931 void i915_gem_load_init(struct drm_device *dev);
2932 void i915_gem_load_cleanup(struct drm_device *dev);
2933 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2934 void *i915_gem_object_alloc(struct drm_device *dev);
2935 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2936 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2937 			 const struct drm_i915_gem_object_ops *ops);
2938 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2939 						  size_t size);
2940 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2941 		struct drm_device *dev, const void *data, size_t size);
2942 void i915_gem_free_object(struct drm_gem_object *obj);
2943 void i915_gem_vma_destroy(struct i915_vma *vma);
2944 
2945 /* Flags used by pin/bind&friends. */
2946 #define PIN_MAPPABLE	(1<<0)
2947 #define PIN_NONBLOCK	(1<<1)
2948 #define PIN_GLOBAL	(1<<2)
2949 #define PIN_OFFSET_BIAS	(1<<3)
2950 #define PIN_USER	(1<<4)
2951 #define PIN_UPDATE	(1<<5)
2952 #define PIN_ZONE_4G	(1<<6)
2953 #define PIN_HIGH	(1<<7)
2954 #define PIN_OFFSET_FIXED	(1<<8)
2955 #define PIN_OFFSET_MASK (~4095)
2956 int __must_check
2957 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2958 		    struct i915_address_space *vm,
2959 		    uint32_t alignment,
2960 		    uint64_t flags);
2961 int __must_check
2962 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2963 			 const struct i915_ggtt_view *view,
2964 			 uint32_t alignment,
2965 			 uint64_t flags);
2966 
2967 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2968 		  u32 flags);
2969 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2970 int __must_check i915_vma_unbind(struct i915_vma *vma);
2971 /*
2972  * BEWARE: Do not use the function below unless you can _absolutely_
2973  * _guarantee_ VMA in question is _not in use_ anywhere.
2974  */
2975 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2976 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2977 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2978 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2979 
2980 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2981 				    int *needs_clflush);
2982 
2983 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2984 
2985 static inline int __sg_page_count(struct scatterlist *sg)
2986 {
2987 	return sg->length >> PAGE_SHIFT;
2988 }
2989 
2990 struct page *
2991 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2992 
2993 static inline struct page *
2994 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2995 {
2996 	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2997 		return NULL;
2998 
2999 	if (n < obj->get_page.last) {
3000 		obj->get_page.sg = obj->pages->sgl;
3001 		obj->get_page.last = 0;
3002 	}
3003 
3004 	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3005 		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3006 		if (unlikely(sg_is_chain(obj->get_page.sg)))
3007 			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3008 	}
3009 
3010 	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3011 }
3012 
3013 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3014 {
3015 	BUG_ON(obj->pages == NULL);
3016 	obj->pages_pin_count++;
3017 }
3018 
3019 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3020 {
3021 	BUG_ON(obj->pages_pin_count == 0);
3022 	obj->pages_pin_count--;
3023 }
3024 
3025 /**
3026  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3027  * @obj - the object to map into kernel address space
3028  *
3029  * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3030  * pages and then returns a contiguous mapping of the backing storage into
3031  * the kernel address space.
3032  *
3033  * The caller must hold the struct_mutex, and is responsible for calling
3034  * i915_gem_object_unpin_map() when the mapping is no longer required.
3035  *
3036  * Returns the pointer through which to access the mapped object, or an
3037  * ERR_PTR() on error.
3038  */
3039 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3040 
3041 /**
3042  * i915_gem_object_unpin_map - releases an earlier mapping
3043  * @obj - the object to unmap
3044  *
3045  * After pinning the object and mapping its pages, once you are finished
3046  * with your access, call i915_gem_object_unpin_map() to release the pin
3047  * upon the mapping. Once the pin count reaches zero, that mapping may be
3048  * removed.
3049  *
3050  * The caller must hold the struct_mutex.
3051  */
3052 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3053 {
3054 	lockdep_assert_held(&obj->base.dev->struct_mutex);
3055 	i915_gem_object_unpin_pages(obj);
3056 }
3057 
3058 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3059 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3060 			 struct intel_engine_cs *to,
3061 			 struct drm_i915_gem_request **to_req);
3062 void i915_vma_move_to_active(struct i915_vma *vma,
3063 			     struct drm_i915_gem_request *req);
3064 int i915_gem_dumb_create(struct drm_file *file_priv,
3065 			 struct drm_device *dev,
3066 			 struct drm_mode_create_dumb *args);
3067 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3068 		      uint32_t handle, uint64_t *offset);
3069 /**
3070  * Returns true if seq1 is later than seq2.
3071  */
3072 static inline bool
3073 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3074 {
3075 	return (int32_t)(seq1 - seq2) >= 0;
3076 }
3077 
3078 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3079 					   bool lazy_coherency)
3080 {
3081 	if (!lazy_coherency && req->engine->irq_seqno_barrier)
3082 		req->engine->irq_seqno_barrier(req->engine);
3083 	return i915_seqno_passed(req->engine->get_seqno(req->engine),
3084 				 req->previous_seqno);
3085 }
3086 
3087 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3088 					      bool lazy_coherency)
3089 {
3090 	if (!lazy_coherency && req->engine->irq_seqno_barrier)
3091 		req->engine->irq_seqno_barrier(req->engine);
3092 	return i915_seqno_passed(req->engine->get_seqno(req->engine),
3093 				 req->seqno);
3094 }
3095 
3096 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3097 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3098 
3099 struct drm_i915_gem_request *
3100 i915_gem_find_active_request(struct intel_engine_cs *engine);
3101 
3102 bool i915_gem_retire_requests(struct drm_device *dev);
3103 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3104 
3105 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3106 {
3107 	return atomic_read(&error->reset_counter);
3108 }
3109 
3110 static inline bool __i915_reset_in_progress(u32 reset)
3111 {
3112 	return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3113 }
3114 
3115 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3116 {
3117 	return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3118 }
3119 
3120 static inline bool __i915_terminally_wedged(u32 reset)
3121 {
3122 	return unlikely(reset & I915_WEDGED);
3123 }
3124 
3125 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3126 {
3127 	return __i915_reset_in_progress(i915_reset_counter(error));
3128 }
3129 
3130 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3131 {
3132 	return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3133 }
3134 
3135 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3136 {
3137 	return __i915_terminally_wedged(i915_reset_counter(error));
3138 }
3139 
3140 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3141 {
3142 	return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3143 }
3144 
3145 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3146 {
3147 	return dev_priv->gpu_error.stop_rings == 0 ||
3148 		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3149 }
3150 
3151 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3152 {
3153 	return dev_priv->gpu_error.stop_rings == 0 ||
3154 		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3155 }
3156 
3157 void i915_gem_reset(struct drm_device *dev);
3158 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3159 int __must_check i915_gem_init(struct drm_device *dev);
3160 int i915_gem_init_engines(struct drm_device *dev);
3161 int __must_check i915_gem_init_hw(struct drm_device *dev);
3162 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3163 void i915_gem_init_swizzling(struct drm_device *dev);
3164 void i915_gem_cleanup_engines(struct drm_device *dev);
3165 int __must_check i915_gpu_idle(struct drm_device *dev);
3166 int __must_check i915_gem_suspend(struct drm_device *dev);
3167 void __i915_add_request(struct drm_i915_gem_request *req,
3168 			struct drm_i915_gem_object *batch_obj,
3169 			bool flush_caches);
3170 #define i915_add_request(req) \
3171 	__i915_add_request(req, NULL, true)
3172 #define i915_add_request_no_flush(req) \
3173 	__i915_add_request(req, NULL, false)
3174 int __i915_wait_request(struct drm_i915_gem_request *req,
3175 			bool interruptible,
3176 			s64 *timeout,
3177 			struct intel_rps_client *rps);
3178 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3179 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3180 int __must_check
3181 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3182 			       bool readonly);
3183 int __must_check
3184 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3185 				  bool write);
3186 int __must_check
3187 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3188 int __must_check
3189 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3190 				     u32 alignment,
3191 				     const struct i915_ggtt_view *view);
3192 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3193 					      const struct i915_ggtt_view *view);
3194 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3195 				int align);
3196 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3197 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3198 
3199 uint32_t
3200 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3201 uint32_t
3202 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3203 			    int tiling_mode, bool fenced);
3204 
3205 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3206 				    enum i915_cache_level cache_level);
3207 
3208 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3209 				struct dma_buf *dma_buf);
3210 
3211 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3212 				struct drm_gem_object *gem_obj, int flags);
3213 
3214 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3215 				  const struct i915_ggtt_view *view);
3216 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3217 			struct i915_address_space *vm);
3218 static inline u64
3219 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3220 {
3221 	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3222 }
3223 
3224 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3225 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3226 				  const struct i915_ggtt_view *view);
3227 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3228 			struct i915_address_space *vm);
3229 
3230 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3231 				struct i915_address_space *vm);
3232 struct i915_vma *
3233 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3234 		    struct i915_address_space *vm);
3235 struct i915_vma *
3236 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3237 			  const struct i915_ggtt_view *view);
3238 
3239 struct i915_vma *
3240 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3241 				  struct i915_address_space *vm);
3242 struct i915_vma *
3243 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3244 				       const struct i915_ggtt_view *view);
3245 
3246 static inline struct i915_vma *
3247 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3248 {
3249 	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3250 }
3251 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3252 
3253 /* Some GGTT VM helpers */
3254 static inline struct i915_hw_ppgtt *
3255 i915_vm_to_ppgtt(struct i915_address_space *vm)
3256 {
3257 	return container_of(vm, struct i915_hw_ppgtt, base);
3258 }
3259 
3260 
3261 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3262 {
3263 	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3264 }
3265 
3266 static inline unsigned long
3267 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3268 {
3269 	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3270 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
3271 
3272 	return i915_gem_obj_size(obj, &ggtt->base);
3273 }
3274 
3275 static inline int __must_check
3276 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3277 		      uint32_t alignment,
3278 		      unsigned flags)
3279 {
3280 	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3281 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
3282 
3283 	return i915_gem_object_pin(obj, &ggtt->base,
3284 				   alignment, flags | PIN_GLOBAL);
3285 }
3286 
3287 static inline int
3288 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3289 {
3290 	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3291 }
3292 
3293 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3294 				     const struct i915_ggtt_view *view);
3295 static inline void
3296 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3297 {
3298 	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3299 }
3300 
3301 /* i915_gem_fence.c */
3302 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3303 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3304 
3305 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3306 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3307 
3308 void i915_gem_restore_fences(struct drm_device *dev);
3309 
3310 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3311 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3312 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3313 
3314 /* i915_gem_context.c */
3315 int __must_check i915_gem_context_init(struct drm_device *dev);
3316 void i915_gem_context_fini(struct drm_device *dev);
3317 void i915_gem_context_reset(struct drm_device *dev);
3318 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3319 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3320 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3321 int i915_switch_context(struct drm_i915_gem_request *req);
3322 struct intel_context *
3323 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3324 void i915_gem_context_free(struct kref *ctx_ref);
3325 struct drm_i915_gem_object *
3326 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3327 static inline void i915_gem_context_reference(struct intel_context *ctx)
3328 {
3329 	kref_get(&ctx->ref);
3330 }
3331 
3332 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3333 {
3334 	kref_put(&ctx->ref, i915_gem_context_free);
3335 }
3336 
3337 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3338 {
3339 	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3340 }
3341 
3342 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3343 				  struct drm_file *file);
3344 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3345 				   struct drm_file *file);
3346 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3347 				    struct drm_file *file_priv);
3348 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3349 				    struct drm_file *file_priv);
3350 
3351 /* i915_gem_evict.c */
3352 int __must_check i915_gem_evict_something(struct drm_device *dev,
3353 					  struct i915_address_space *vm,
3354 					  int min_size,
3355 					  unsigned alignment,
3356 					  unsigned cache_level,
3357 					  unsigned long start,
3358 					  unsigned long end,
3359 					  unsigned flags);
3360 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3361 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3362 
3363 /* belongs in i915_gem_gtt.h */
3364 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3365 {
3366 	if (INTEL_INFO(dev)->gen < 6)
3367 		intel_gtt_chipset_flush();
3368 }
3369 
3370 /* i915_gem_stolen.c */
3371 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3372 				struct drm_mm_node *node, u64 size,
3373 				unsigned alignment);
3374 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3375 					 struct drm_mm_node *node, u64 size,
3376 					 unsigned alignment, u64 start,
3377 					 u64 end);
3378 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3379 				 struct drm_mm_node *node);
3380 int i915_gem_init_stolen(struct drm_device *dev);
3381 void i915_gem_cleanup_stolen(struct drm_device *dev);
3382 struct drm_i915_gem_object *
3383 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3384 struct drm_i915_gem_object *
3385 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3386 					       u32 stolen_offset,
3387 					       u32 gtt_offset,
3388 					       u32 size);
3389 
3390 /* i915_gem_shrinker.c */
3391 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3392 			      unsigned long target,
3393 			      unsigned flags);
3394 #define I915_SHRINK_PURGEABLE 0x1
3395 #define I915_SHRINK_UNBOUND 0x2
3396 #define I915_SHRINK_BOUND 0x4
3397 #define I915_SHRINK_ACTIVE 0x8
3398 #define I915_SHRINK_VMAPS 0x10
3399 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3400 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3401 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3402 
3403 
3404 /* i915_gem_tiling.c */
3405 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3406 {
3407 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3408 
3409 	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3410 		obj->tiling_mode != I915_TILING_NONE;
3411 }
3412 
3413 /* i915_gem_debug.c */
3414 #if WATCH_LISTS
3415 int i915_verify_lists(struct drm_device *dev);
3416 #else
3417 #define i915_verify_lists(dev) 0
3418 #endif
3419 
3420 /* i915_debugfs.c */
3421 int i915_debugfs_init(struct drm_minor *minor);
3422 void i915_debugfs_cleanup(struct drm_minor *minor);
3423 #ifdef CONFIG_DEBUG_FS
3424 int i915_debugfs_connector_add(struct drm_connector *connector);
3425 void intel_display_crc_init(struct drm_device *dev);
3426 #else
3427 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3428 { return 0; }
3429 static inline void intel_display_crc_init(struct drm_device *dev) {}
3430 #endif
3431 
3432 /* i915_gpu_error.c */
3433 __printf(2, 3)
3434 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3435 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3436 			    const struct i915_error_state_file_priv *error);
3437 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3438 			      struct drm_i915_private *i915,
3439 			      size_t count, loff_t pos);
3440 static inline void i915_error_state_buf_release(
3441 	struct drm_i915_error_state_buf *eb)
3442 {
3443 	kfree(eb->buf);
3444 }
3445 void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
3446 			      const char *error_msg);
3447 void i915_error_state_get(struct drm_device *dev,
3448 			  struct i915_error_state_file_priv *error_priv);
3449 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3450 void i915_destroy_error_state(struct drm_device *dev);
3451 
3452 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3453 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3454 
3455 /* i915_cmd_parser.c */
3456 int i915_cmd_parser_get_version(void);
3457 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3458 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3459 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3460 int i915_parse_cmds(struct intel_engine_cs *engine,
3461 		    struct drm_i915_gem_object *batch_obj,
3462 		    struct drm_i915_gem_object *shadow_batch_obj,
3463 		    u32 batch_start_offset,
3464 		    u32 batch_len,
3465 		    bool is_master);
3466 
3467 /* i915_suspend.c */
3468 extern int i915_save_state(struct drm_device *dev);
3469 extern int i915_restore_state(struct drm_device *dev);
3470 
3471 /* i915_sysfs.c */
3472 void i915_setup_sysfs(struct drm_device *dev_priv);
3473 void i915_teardown_sysfs(struct drm_device *dev_priv);
3474 
3475 /* intel_i2c.c */
3476 extern int intel_setup_gmbus(struct drm_device *dev);
3477 extern void intel_teardown_gmbus(struct drm_device *dev);
3478 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3479 				     unsigned int pin);
3480 
3481 extern struct i2c_adapter *
3482 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3483 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3484 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3485 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3486 {
3487 	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3488 }
3489 extern void intel_i2c_reset(struct drm_device *dev);
3490 
3491 /* intel_bios.c */
3492 int intel_bios_init(struct drm_i915_private *dev_priv);
3493 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3494 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3495 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3496 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3497 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3498 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3499 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3500 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3501 				     enum port port);
3502 
3503 /* intel_opregion.c */
3504 #ifdef CONFIG_ACPI
3505 extern int intel_opregion_setup(struct drm_device *dev);
3506 extern void intel_opregion_init(struct drm_device *dev);
3507 extern void intel_opregion_fini(struct drm_device *dev);
3508 extern void intel_opregion_asle_intr(struct drm_device *dev);
3509 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3510 					 bool enable);
3511 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3512 					 pci_power_t state);
3513 extern int intel_opregion_get_panel_type(struct drm_device *dev);
3514 #else
3515 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3516 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3517 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3518 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3519 static inline int
3520 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3521 {
3522 	return 0;
3523 }
3524 static inline int
3525 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3526 {
3527 	return 0;
3528 }
3529 static inline int intel_opregion_get_panel_type(struct drm_device *dev)
3530 {
3531 	return -ENODEV;
3532 }
3533 #endif
3534 
3535 /* intel_acpi.c */
3536 #ifdef CONFIG_ACPI
3537 extern void intel_register_dsm_handler(void);
3538 extern void intel_unregister_dsm_handler(void);
3539 #else
3540 static inline void intel_register_dsm_handler(void) { return; }
3541 static inline void intel_unregister_dsm_handler(void) { return; }
3542 #endif /* CONFIG_ACPI */
3543 
3544 /* modesetting */
3545 extern void intel_modeset_init_hw(struct drm_device *dev);
3546 extern void intel_modeset_init(struct drm_device *dev);
3547 extern void intel_modeset_gem_init(struct drm_device *dev);
3548 extern void intel_modeset_cleanup(struct drm_device *dev);
3549 extern void intel_connector_unregister(struct intel_connector *);
3550 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3551 extern void intel_display_resume(struct drm_device *dev);
3552 extern void i915_redisable_vga(struct drm_device *dev);
3553 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3554 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3555 extern void intel_init_pch_refclk(struct drm_device *dev);
3556 extern void intel_set_rps(struct drm_device *dev, u8 val);
3557 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3558 				  bool enable);
3559 extern void intel_detect_pch(struct drm_device *dev);
3560 extern int intel_enable_rc6(const struct drm_device *dev);
3561 
3562 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3563 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3564 			struct drm_file *file);
3565 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3566 			       struct drm_file *file);
3567 
3568 /* overlay */
3569 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3570 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3571 					    struct intel_overlay_error_state *error);
3572 
3573 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3574 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3575 					    struct drm_device *dev,
3576 					    struct intel_display_error_state *error);
3577 
3578 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3579 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3580 
3581 /* intel_sideband.c */
3582 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3583 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3584 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3585 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3586 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3587 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3588 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3589 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3590 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3591 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3592 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3593 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3594 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3595 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3596 		   enum intel_sbi_destination destination);
3597 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3598 		     enum intel_sbi_destination destination);
3599 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3600 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3601 
3602 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3603 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3604 
3605 #define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3606 #define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3607 
3608 #define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3609 #define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3610 #define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3611 #define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3612 
3613 #define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3614 #define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3615 #define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3616 #define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3617 
3618 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3619  * will be implemented using 2 32-bit writes in an arbitrary order with
3620  * an arbitrary delay between them. This can cause the hardware to
3621  * act upon the intermediate value, possibly leading to corruption and
3622  * machine death. You have been warned.
3623  */
3624 #define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3625 #define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3626 
3627 #define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3628 	u32 upper, lower, old_upper, loop = 0;				\
3629 	upper = I915_READ(upper_reg);					\
3630 	do {								\
3631 		old_upper = upper;					\
3632 		lower = I915_READ(lower_reg);				\
3633 		upper = I915_READ(upper_reg);				\
3634 	} while (upper != old_upper && loop++ < 2);			\
3635 	(u64)upper << 32 | lower; })
3636 
3637 #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
3638 #define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
3639 
3640 #define __raw_read(x, s) \
3641 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3642 					     i915_reg_t reg) \
3643 { \
3644 	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3645 }
3646 
3647 #define __raw_write(x, s) \
3648 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3649 				       i915_reg_t reg, uint##x##_t val) \
3650 { \
3651 	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3652 }
3653 __raw_read(8, b)
3654 __raw_read(16, w)
3655 __raw_read(32, l)
3656 __raw_read(64, q)
3657 
3658 __raw_write(8, b)
3659 __raw_write(16, w)
3660 __raw_write(32, l)
3661 __raw_write(64, q)
3662 
3663 #undef __raw_read
3664 #undef __raw_write
3665 
3666 /* These are untraced mmio-accessors that are only valid to be used inside
3667  * criticial sections inside IRQ handlers where forcewake is explicitly
3668  * controlled.
3669  * Think twice, and think again, before using these.
3670  * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3671  * intel_uncore_forcewake_irqunlock().
3672  */
3673 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3674 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3675 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3676 
3677 /* "Broadcast RGB" property */
3678 #define INTEL_BROADCAST_RGB_AUTO 0
3679 #define INTEL_BROADCAST_RGB_FULL 1
3680 #define INTEL_BROADCAST_RGB_LIMITED 2
3681 
3682 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3683 {
3684 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3685 		return VLV_VGACNTRL;
3686 	else if (INTEL_INFO(dev)->gen >= 5)
3687 		return CPU_VGACNTRL;
3688 	else
3689 		return VGACNTRL;
3690 }
3691 
3692 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3693 {
3694 	unsigned long j = msecs_to_jiffies(m);
3695 
3696 	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3697 }
3698 
3699 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3700 {
3701         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3702 }
3703 
3704 static inline unsigned long
3705 timespec_to_jiffies_timeout(const struct timespec *value)
3706 {
3707 	unsigned long j = timespec_to_jiffies(value);
3708 
3709 	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3710 }
3711 
3712 /*
3713  * If you need to wait X milliseconds between events A and B, but event B
3714  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3715  * when event A happened, then just before event B you call this function and
3716  * pass the timestamp as the first argument, and X as the second argument.
3717  */
3718 static inline void
3719 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3720 {
3721 	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3722 
3723 	/*
3724 	 * Don't re-read the value of "jiffies" every time since it may change
3725 	 * behind our back and break the math.
3726 	 */
3727 	tmp_jiffies = jiffies;
3728 	target_jiffies = timestamp_jiffies +
3729 			 msecs_to_jiffies_timeout(to_wait_ms);
3730 
3731 	if (time_after(target_jiffies, tmp_jiffies)) {
3732 		remaining_jiffies = target_jiffies - tmp_jiffies;
3733 		while (remaining_jiffies)
3734 			remaining_jiffies =
3735 			    schedule_timeout_uninterruptible(remaining_jiffies);
3736 	}
3737 }
3738 
3739 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3740 				      struct drm_i915_gem_request *req)
3741 {
3742 	if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3743 		i915_gem_request_assign(&engine->trace_irq_req, req);
3744 }
3745 
3746 #endif
3747