1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/reservation.h> 47 #include <linux/shmem_fs.h> 48 49 #include <drm/drmP.h> 50 #include <drm/intel-gtt.h> 51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 52 #include <drm/drm_gem.h> 53 #include <drm/drm_auth.h> 54 #include <drm/drm_cache.h> 55 #include <drm/drm_util.h> 56 57 #include "i915_params.h" 58 #include "i915_reg.h" 59 #include "i915_utils.h" 60 61 #include "intel_bios.h" 62 #include "intel_device_info.h" 63 #include "intel_display.h" 64 #include "intel_dpll_mgr.h" 65 #include "intel_lrc.h" 66 #include "intel_opregion.h" 67 #include "intel_ringbuffer.h" 68 #include "intel_uncore.h" 69 #include "intel_wopcm.h" 70 #include "intel_uc.h" 71 72 #include "i915_gem.h" 73 #include "i915_gem_context.h" 74 #include "i915_gem_fence_reg.h" 75 #include "i915_gem_object.h" 76 #include "i915_gem_gtt.h" 77 #include "i915_gpu_error.h" 78 #include "i915_request.h" 79 #include "i915_scheduler.h" 80 #include "i915_timeline.h" 81 #include "i915_vma.h" 82 83 #include "intel_gvt.h" 84 85 /* General customization: 86 */ 87 88 #define DRIVER_NAME "i915" 89 #define DRIVER_DESC "Intel Graphics" 90 #define DRIVER_DATE "20180921" 91 #define DRIVER_TIMESTAMP 1537521997 92 93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 95 * which may not necessarily be a user visible problem. This will either 96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 97 * enable distros and users to tailor their preferred amount of i915 abrt 98 * spam. 99 */ 100 #define I915_STATE_WARN(condition, format...) ({ \ 101 int __ret_warn_on = !!(condition); \ 102 if (unlikely(__ret_warn_on)) \ 103 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 104 DRM_ERROR(format); \ 105 unlikely(__ret_warn_on); \ 106 }) 107 108 #define I915_STATE_WARN_ON(x) \ 109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 110 111 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) 112 113 bool __i915_inject_load_failure(const char *func, int line); 114 #define i915_inject_load_failure() \ 115 __i915_inject_load_failure(__func__, __LINE__) 116 117 bool i915_error_injected(void); 118 119 #else 120 121 #define i915_inject_load_failure() false 122 #define i915_error_injected() false 123 124 #endif 125 126 #define i915_load_error(i915, fmt, ...) \ 127 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \ 128 fmt, ##__VA_ARGS__) 129 130 typedef struct { 131 uint32_t val; 132 } uint_fixed_16_16_t; 133 134 #define FP_16_16_MAX ({ \ 135 uint_fixed_16_16_t fp; \ 136 fp.val = UINT_MAX; \ 137 fp; \ 138 }) 139 140 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) 141 { 142 if (val.val == 0) 143 return true; 144 return false; 145 } 146 147 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) 148 { 149 uint_fixed_16_16_t fp; 150 151 WARN_ON(val > U16_MAX); 152 153 fp.val = val << 16; 154 return fp; 155 } 156 157 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp) 158 { 159 return DIV_ROUND_UP(fp.val, 1 << 16); 160 } 161 162 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp) 163 { 164 return fp.val >> 16; 165 } 166 167 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1, 168 uint_fixed_16_16_t min2) 169 { 170 uint_fixed_16_16_t min; 171 172 min.val = min(min1.val, min2.val); 173 return min; 174 } 175 176 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1, 177 uint_fixed_16_16_t max2) 178 { 179 uint_fixed_16_16_t max; 180 181 max.val = max(max1.val, max2.val); 182 return max; 183 } 184 185 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) 186 { 187 uint_fixed_16_16_t fp; 188 WARN_ON(val > U32_MAX); 189 fp.val = (uint32_t) val; 190 return fp; 191 } 192 193 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, 194 uint_fixed_16_16_t d) 195 { 196 return DIV_ROUND_UP(val.val, d.val); 197 } 198 199 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, 200 uint_fixed_16_16_t mul) 201 { 202 uint64_t intermediate_val; 203 204 intermediate_val = (uint64_t) val * mul.val; 205 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); 206 WARN_ON(intermediate_val > U32_MAX); 207 return (uint32_t) intermediate_val; 208 } 209 210 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, 211 uint_fixed_16_16_t mul) 212 { 213 uint64_t intermediate_val; 214 215 intermediate_val = (uint64_t) val.val * mul.val; 216 intermediate_val = intermediate_val >> 16; 217 return clamp_u64_to_fixed16(intermediate_val); 218 } 219 220 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d) 221 { 222 uint64_t interm_val; 223 224 interm_val = (uint64_t)val << 16; 225 interm_val = DIV_ROUND_UP_ULL(interm_val, d); 226 return clamp_u64_to_fixed16(interm_val); 227 } 228 229 static inline uint32_t div_round_up_u32_fixed16(uint32_t val, 230 uint_fixed_16_16_t d) 231 { 232 uint64_t interm_val; 233 234 interm_val = (uint64_t)val << 16; 235 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val); 236 WARN_ON(interm_val > U32_MAX); 237 return (uint32_t) interm_val; 238 } 239 240 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val, 241 uint_fixed_16_16_t mul) 242 { 243 uint64_t intermediate_val; 244 245 intermediate_val = (uint64_t) val * mul.val; 246 return clamp_u64_to_fixed16(intermediate_val); 247 } 248 249 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1, 250 uint_fixed_16_16_t add2) 251 { 252 uint64_t interm_sum; 253 254 interm_sum = (uint64_t) add1.val + add2.val; 255 return clamp_u64_to_fixed16(interm_sum); 256 } 257 258 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1, 259 uint32_t add2) 260 { 261 uint64_t interm_sum; 262 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2); 263 264 interm_sum = (uint64_t) add1.val + interm_add2.val; 265 return clamp_u64_to_fixed16(interm_sum); 266 } 267 268 enum hpd_pin { 269 HPD_NONE = 0, 270 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 271 HPD_CRT, 272 HPD_SDVO_B, 273 HPD_SDVO_C, 274 HPD_PORT_A, 275 HPD_PORT_B, 276 HPD_PORT_C, 277 HPD_PORT_D, 278 HPD_PORT_E, 279 HPD_PORT_F, 280 HPD_NUM_PINS 281 }; 282 283 #define for_each_hpd_pin(__pin) \ 284 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 285 286 #define HPD_STORM_DEFAULT_THRESHOLD 5 287 288 struct i915_hotplug { 289 struct work_struct hotplug_work; 290 291 struct { 292 unsigned long last_jiffies; 293 int count; 294 enum { 295 HPD_ENABLED = 0, 296 HPD_DISABLED = 1, 297 HPD_MARK_DISABLED = 2 298 } state; 299 } stats[HPD_NUM_PINS]; 300 u32 event_bits; 301 struct delayed_work reenable_work; 302 303 u32 long_port_mask; 304 u32 short_port_mask; 305 struct work_struct dig_port_work; 306 307 struct work_struct poll_init_work; 308 bool poll_enabled; 309 310 unsigned int hpd_storm_threshold; 311 312 /* 313 * if we get a HPD irq from DP and a HPD irq from non-DP 314 * the non-DP HPD could block the workqueue on a mode config 315 * mutex getting, that userspace may have taken. However 316 * userspace is waiting on the DP workqueue to run which is 317 * blocked behind the non-DP one. 318 */ 319 struct workqueue_struct *dp_wq; 320 }; 321 322 #define I915_GEM_GPU_DOMAINS \ 323 (I915_GEM_DOMAIN_RENDER | \ 324 I915_GEM_DOMAIN_SAMPLER | \ 325 I915_GEM_DOMAIN_COMMAND | \ 326 I915_GEM_DOMAIN_INSTRUCTION | \ 327 I915_GEM_DOMAIN_VERTEX) 328 329 struct drm_i915_private; 330 struct i915_mm_struct; 331 struct i915_mmu_object; 332 333 struct drm_i915_file_private { 334 struct drm_i915_private *dev_priv; 335 struct drm_file *file; 336 337 struct { 338 spinlock_t lock; 339 struct list_head request_list; 340 /* 20ms is a fairly arbitrary limit (greater than the average frame time) 341 * chosen to prevent the CPU getting more than a frame ahead of the GPU 342 * (when using lax throttling for the frontbuffer). We also use it to 343 * offer free GPU waitboosts for severely congested workloads. 344 */ 345 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) 346 } mm; 347 struct idr context_idr; 348 349 struct intel_rps_client { 350 atomic_t boosts; 351 } rps_client; 352 353 unsigned int bsd_engine; 354 355 /* 356 * Every context ban increments per client ban score. Also 357 * hangs in short succession increments ban score. If ban threshold 358 * is reached, client is considered banned and submitting more work 359 * will fail. This is a stop gap measure to limit the badly behaving 360 * clients access to gpu. Note that unbannable contexts never increment 361 * the client ban score. 362 */ 363 #define I915_CLIENT_SCORE_HANG_FAST 1 364 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 365 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 366 #define I915_CLIENT_SCORE_BANNED 9 367 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 368 atomic_t ban_score; 369 unsigned long hang_timestamp; 370 }; 371 372 /* Interface history: 373 * 374 * 1.1: Original. 375 * 1.2: Add Power Management 376 * 1.3: Add vblank support 377 * 1.4: Fix cmdbuffer path, add heap destroy 378 * 1.5: Add vblank pipe configuration 379 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 380 * - Support vertical blank on secondary display pipe 381 */ 382 #define DRIVER_MAJOR 1 383 #define DRIVER_MINOR 6 384 #define DRIVER_PATCHLEVEL 0 385 386 struct intel_overlay; 387 struct intel_overlay_error_state; 388 389 struct sdvo_device_mapping { 390 u8 initialized; 391 u8 dvo_port; 392 u8 slave_addr; 393 u8 dvo_wiring; 394 u8 i2c_pin; 395 u8 ddc_pin; 396 }; 397 398 struct intel_connector; 399 struct intel_encoder; 400 struct intel_atomic_state; 401 struct intel_crtc_state; 402 struct intel_initial_plane_config; 403 struct intel_crtc; 404 struct intel_limit; 405 struct dpll; 406 struct intel_cdclk_state; 407 408 struct drm_i915_display_funcs { 409 void (*get_cdclk)(struct drm_i915_private *dev_priv, 410 struct intel_cdclk_state *cdclk_state); 411 void (*set_cdclk)(struct drm_i915_private *dev_priv, 412 const struct intel_cdclk_state *cdclk_state); 413 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 414 enum i9xx_plane_id i9xx_plane); 415 int (*compute_pipe_wm)(struct intel_crtc_state *cstate); 416 int (*compute_intermediate_wm)(struct drm_device *dev, 417 struct intel_crtc *intel_crtc, 418 struct intel_crtc_state *newstate); 419 void (*initial_watermarks)(struct intel_atomic_state *state, 420 struct intel_crtc_state *cstate); 421 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 422 struct intel_crtc_state *cstate); 423 void (*optimize_watermarks)(struct intel_atomic_state *state, 424 struct intel_crtc_state *cstate); 425 int (*compute_global_watermarks)(struct drm_atomic_state *state); 426 void (*update_wm)(struct intel_crtc *crtc); 427 int (*modeset_calc_cdclk)(struct drm_atomic_state *state); 428 /* Returns the active state of the crtc, and if the crtc is active, 429 * fills out the pipe-config with the hw state. */ 430 bool (*get_pipe_config)(struct intel_crtc *, 431 struct intel_crtc_state *); 432 void (*get_initial_plane_config)(struct intel_crtc *, 433 struct intel_initial_plane_config *); 434 int (*crtc_compute_clock)(struct intel_crtc *crtc, 435 struct intel_crtc_state *crtc_state); 436 void (*crtc_enable)(struct intel_crtc_state *pipe_config, 437 struct drm_atomic_state *old_state); 438 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, 439 struct drm_atomic_state *old_state); 440 void (*update_crtcs)(struct drm_atomic_state *state); 441 void (*audio_codec_enable)(struct intel_encoder *encoder, 442 const struct intel_crtc_state *crtc_state, 443 const struct drm_connector_state *conn_state); 444 void (*audio_codec_disable)(struct intel_encoder *encoder, 445 const struct intel_crtc_state *old_crtc_state, 446 const struct drm_connector_state *old_conn_state); 447 void (*fdi_link_train)(struct intel_crtc *crtc, 448 const struct intel_crtc_state *crtc_state); 449 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 450 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 451 /* clock updates for mode set */ 452 /* cursor updates */ 453 /* render clock increase/decrease */ 454 /* display clock increase/decrease */ 455 /* pll clock increase/decrease */ 456 457 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); 458 void (*load_luts)(struct drm_crtc_state *crtc_state); 459 }; 460 461 #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) 462 #define CSR_VERSION_MAJOR(version) ((version) >> 16) 463 #define CSR_VERSION_MINOR(version) ((version) & 0xffff) 464 465 struct intel_csr { 466 struct work_struct work; 467 const char *fw_path; 468 uint32_t *dmc_payload; 469 uint32_t dmc_fw_size; 470 uint32_t version; 471 uint32_t mmio_count; 472 i915_reg_t mmioaddr[8]; 473 uint32_t mmiodata[8]; 474 uint32_t dc_state; 475 uint32_t allowed_dc_mask; 476 }; 477 478 enum i915_cache_level { 479 I915_CACHE_NONE = 0, 480 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 481 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 482 caches, eg sampler/render caches, and the 483 large Last-Level-Cache. LLC is coherent with 484 the CPU, but L3 is only visible to the GPU. */ 485 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 486 }; 487 488 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 489 490 enum fb_op_origin { 491 ORIGIN_GTT, 492 ORIGIN_CPU, 493 ORIGIN_CS, 494 ORIGIN_FLIP, 495 ORIGIN_DIRTYFB, 496 }; 497 498 struct intel_fbc { 499 /* This is always the inner lock when overlapping with struct_mutex and 500 * it's the outer lock when overlapping with stolen_lock. */ 501 struct mutex lock; 502 unsigned threshold; 503 unsigned int possible_framebuffer_bits; 504 unsigned int busy_bits; 505 unsigned int visible_pipes_mask; 506 struct intel_crtc *crtc; 507 508 struct drm_mm_node compressed_fb; 509 struct drm_mm_node *compressed_llb; 510 511 bool false_color; 512 513 bool enabled; 514 bool active; 515 bool flip_pending; 516 517 bool underrun_detected; 518 struct work_struct underrun_work; 519 520 /* 521 * Due to the atomic rules we can't access some structures without the 522 * appropriate locking, so we cache information here in order to avoid 523 * these problems. 524 */ 525 struct intel_fbc_state_cache { 526 struct i915_vma *vma; 527 unsigned long flags; 528 529 struct { 530 unsigned int mode_flags; 531 uint32_t hsw_bdw_pixel_rate; 532 } crtc; 533 534 struct { 535 unsigned int rotation; 536 int src_w; 537 int src_h; 538 bool visible; 539 /* 540 * Display surface base address adjustement for 541 * pageflips. Note that on gen4+ this only adjusts up 542 * to a tile, offsets within a tile are handled in 543 * the hw itself (with the TILEOFF register). 544 */ 545 int adjusted_x; 546 int adjusted_y; 547 548 int y; 549 } plane; 550 551 struct { 552 const struct drm_format_info *format; 553 unsigned int stride; 554 } fb; 555 } state_cache; 556 557 /* 558 * This structure contains everything that's relevant to program the 559 * hardware registers. When we want to figure out if we need to disable 560 * and re-enable FBC for a new configuration we just check if there's 561 * something different in the struct. The genx_fbc_activate functions 562 * are supposed to read from it in order to program the registers. 563 */ 564 struct intel_fbc_reg_params { 565 struct i915_vma *vma; 566 unsigned long flags; 567 568 struct { 569 enum pipe pipe; 570 enum i9xx_plane_id i9xx_plane; 571 unsigned int fence_y_offset; 572 } crtc; 573 574 struct { 575 const struct drm_format_info *format; 576 unsigned int stride; 577 } fb; 578 579 int cfb_size; 580 unsigned int gen9_wa_cfb_stride; 581 } params; 582 583 const char *no_fbc_reason; 584 }; 585 586 /* 587 * HIGH_RR is the highest eDP panel refresh rate read from EDID 588 * LOW_RR is the lowest eDP panel refresh rate found from EDID 589 * parsing for same resolution. 590 */ 591 enum drrs_refresh_rate_type { 592 DRRS_HIGH_RR, 593 DRRS_LOW_RR, 594 DRRS_MAX_RR, /* RR count */ 595 }; 596 597 enum drrs_support_type { 598 DRRS_NOT_SUPPORTED = 0, 599 STATIC_DRRS_SUPPORT = 1, 600 SEAMLESS_DRRS_SUPPORT = 2 601 }; 602 603 struct intel_dp; 604 struct i915_drrs { 605 struct mutex mutex; 606 struct delayed_work work; 607 struct intel_dp *dp; 608 unsigned busy_frontbuffer_bits; 609 enum drrs_refresh_rate_type refresh_rate_type; 610 enum drrs_support_type type; 611 }; 612 613 struct i915_psr { 614 struct mutex lock; 615 616 #define I915_PSR_DEBUG_MODE_MASK 0x0f 617 #define I915_PSR_DEBUG_DEFAULT 0x00 618 #define I915_PSR_DEBUG_DISABLE 0x01 619 #define I915_PSR_DEBUG_ENABLE 0x02 620 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 621 #define I915_PSR_DEBUG_IRQ 0x10 622 623 u32 debug; 624 bool sink_support; 625 bool prepared, enabled; 626 struct intel_dp *dp; 627 bool active; 628 struct work_struct work; 629 unsigned busy_frontbuffer_bits; 630 bool sink_psr2_support; 631 bool link_standby; 632 bool colorimetry_support; 633 bool alpm; 634 bool psr2_enabled; 635 u8 sink_sync_latency; 636 ktime_t last_entry_attempt; 637 ktime_t last_exit; 638 }; 639 640 enum intel_pch { 641 PCH_NONE = 0, /* No PCH present */ 642 PCH_IBX, /* Ibexpeak PCH */ 643 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ 644 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ 645 PCH_SPT, /* Sunrisepoint PCH */ 646 PCH_KBP, /* Kaby Lake PCH */ 647 PCH_CNP, /* Cannon Lake PCH */ 648 PCH_ICP, /* Ice Lake PCH */ 649 PCH_NOP, /* PCH without south display */ 650 }; 651 652 enum intel_sbi_destination { 653 SBI_ICLK, 654 SBI_MPHY, 655 }; 656 657 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 658 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 659 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 660 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 661 #define QUIRK_INCREASE_T12_DELAY (1<<6) 662 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 663 664 struct intel_fbdev; 665 struct intel_fbc_work; 666 667 struct intel_gmbus { 668 struct i2c_adapter adapter; 669 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 670 u32 force_bit; 671 u32 reg0; 672 i915_reg_t gpio_reg; 673 struct i2c_algo_bit_data bit_algo; 674 struct drm_i915_private *dev_priv; 675 }; 676 677 struct i915_suspend_saved_registers { 678 u32 saveDSPARB; 679 u32 saveFBC_CONTROL; 680 u32 saveCACHE_MODE_0; 681 u32 saveMI_ARB_STATE; 682 u32 saveSWF0[16]; 683 u32 saveSWF1[16]; 684 u32 saveSWF3[3]; 685 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 686 u32 savePCH_PORT_HOTPLUG; 687 u16 saveGCDGMBUS; 688 }; 689 690 struct vlv_s0ix_state { 691 /* GAM */ 692 u32 wr_watermark; 693 u32 gfx_prio_ctrl; 694 u32 arb_mode; 695 u32 gfx_pend_tlb0; 696 u32 gfx_pend_tlb1; 697 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 698 u32 media_max_req_count; 699 u32 gfx_max_req_count; 700 u32 render_hwsp; 701 u32 ecochk; 702 u32 bsd_hwsp; 703 u32 blt_hwsp; 704 u32 tlb_rd_addr; 705 706 /* MBC */ 707 u32 g3dctl; 708 u32 gsckgctl; 709 u32 mbctl; 710 711 /* GCP */ 712 u32 ucgctl1; 713 u32 ucgctl3; 714 u32 rcgctl1; 715 u32 rcgctl2; 716 u32 rstctl; 717 u32 misccpctl; 718 719 /* GPM */ 720 u32 gfxpause; 721 u32 rpdeuhwtc; 722 u32 rpdeuc; 723 u32 ecobus; 724 u32 pwrdwnupctl; 725 u32 rp_down_timeout; 726 u32 rp_deucsw; 727 u32 rcubmabdtmr; 728 u32 rcedata; 729 u32 spare2gh; 730 731 /* Display 1 CZ domain */ 732 u32 gt_imr; 733 u32 gt_ier; 734 u32 pm_imr; 735 u32 pm_ier; 736 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 737 738 /* GT SA CZ domain */ 739 u32 tilectl; 740 u32 gt_fifoctl; 741 u32 gtlc_wake_ctrl; 742 u32 gtlc_survive; 743 u32 pmwgicz; 744 745 /* Display 2 CZ domain */ 746 u32 gu_ctl0; 747 u32 gu_ctl1; 748 u32 pcbr; 749 u32 clock_gate_dis2; 750 }; 751 752 struct intel_rps_ei { 753 ktime_t ktime; 754 u32 render_c0; 755 u32 media_c0; 756 }; 757 758 struct intel_rps { 759 /* 760 * work, interrupts_enabled and pm_iir are protected by 761 * dev_priv->irq_lock 762 */ 763 struct work_struct work; 764 bool interrupts_enabled; 765 u32 pm_iir; 766 767 /* PM interrupt bits that should never be masked */ 768 u32 pm_intrmsk_mbz; 769 770 /* Frequencies are stored in potentially platform dependent multiples. 771 * In other words, *_freq needs to be multiplied by X to be interesting. 772 * Soft limits are those which are used for the dynamic reclocking done 773 * by the driver (raise frequencies under heavy loads, and lower for 774 * lighter loads). Hard limits are those imposed by the hardware. 775 * 776 * A distinction is made for overclocking, which is never enabled by 777 * default, and is considered to be above the hard limit if it's 778 * possible at all. 779 */ 780 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 781 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 782 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 783 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 784 u8 min_freq; /* AKA RPn. Minimum frequency */ 785 u8 boost_freq; /* Frequency to request when wait boosting */ 786 u8 idle_freq; /* Frequency to request when we are idle */ 787 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 788 u8 rp1_freq; /* "less than" RP0 power/freqency */ 789 u8 rp0_freq; /* Non-overclocked max frequency. */ 790 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ 791 792 int last_adj; 793 794 struct { 795 struct mutex mutex; 796 797 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode; 798 unsigned int interactive; 799 800 u8 up_threshold; /* Current %busy required to uplock */ 801 u8 down_threshold; /* Current %busy required to downclock */ 802 } power; 803 804 bool enabled; 805 atomic_t num_waiters; 806 atomic_t boosts; 807 808 /* manual wa residency calculations */ 809 struct intel_rps_ei ei; 810 }; 811 812 struct intel_rc6 { 813 bool enabled; 814 u64 prev_hw_residency[4]; 815 u64 cur_residency[4]; 816 }; 817 818 struct intel_llc_pstate { 819 bool enabled; 820 }; 821 822 struct intel_gen6_power_mgmt { 823 struct intel_rps rps; 824 struct intel_rc6 rc6; 825 struct intel_llc_pstate llc_pstate; 826 }; 827 828 /* defined intel_pm.c */ 829 extern spinlock_t mchdev_lock; 830 831 struct intel_ilk_power_mgmt { 832 u8 cur_delay; 833 u8 min_delay; 834 u8 max_delay; 835 u8 fmax; 836 u8 fstart; 837 838 u64 last_count1; 839 unsigned long last_time1; 840 unsigned long chipset_power; 841 u64 last_count2; 842 u64 last_time2; 843 unsigned long gfx_power; 844 u8 corr; 845 846 int c_m; 847 int r_t; 848 }; 849 850 struct drm_i915_private; 851 struct i915_power_well; 852 853 struct i915_power_well_ops { 854 /* 855 * Synchronize the well's hw state to match the current sw state, for 856 * example enable/disable it based on the current refcount. Called 857 * during driver init and resume time, possibly after first calling 858 * the enable/disable handlers. 859 */ 860 void (*sync_hw)(struct drm_i915_private *dev_priv, 861 struct i915_power_well *power_well); 862 /* 863 * Enable the well and resources that depend on it (for example 864 * interrupts located on the well). Called after the 0->1 refcount 865 * transition. 866 */ 867 void (*enable)(struct drm_i915_private *dev_priv, 868 struct i915_power_well *power_well); 869 /* 870 * Disable the well and resources that depend on it. Called after 871 * the 1->0 refcount transition. 872 */ 873 void (*disable)(struct drm_i915_private *dev_priv, 874 struct i915_power_well *power_well); 875 /* Returns the hw enabled state. */ 876 bool (*is_enabled)(struct drm_i915_private *dev_priv, 877 struct i915_power_well *power_well); 878 }; 879 880 struct i915_power_well_regs { 881 i915_reg_t bios; 882 i915_reg_t driver; 883 i915_reg_t kvmr; 884 i915_reg_t debug; 885 }; 886 887 /* Power well structure for haswell */ 888 struct i915_power_well_desc { 889 const char *name; 890 bool always_on; 891 u64 domains; 892 /* unique identifier for this power well */ 893 enum i915_power_well_id id; 894 /* 895 * Arbitraty data associated with this power well. Platform and power 896 * well specific. 897 */ 898 union { 899 struct { 900 /* 901 * request/status flag index in the PUNIT power well 902 * control/status registers. 903 */ 904 u8 idx; 905 } vlv; 906 struct { 907 enum dpio_phy phy; 908 } bxt; 909 struct { 910 const struct i915_power_well_regs *regs; 911 /* 912 * request/status flag index in the power well 913 * constrol/status registers. 914 */ 915 u8 idx; 916 /* Mask of pipes whose IRQ logic is backed by the pw */ 917 u8 irq_pipe_mask; 918 /* The pw is backing the VGA functionality */ 919 bool has_vga:1; 920 bool has_fuses:1; 921 } hsw; 922 }; 923 const struct i915_power_well_ops *ops; 924 }; 925 926 struct i915_power_well { 927 const struct i915_power_well_desc *desc; 928 /* power well enable/disable usage count */ 929 int count; 930 /* cached hw enabled state */ 931 bool hw_enabled; 932 }; 933 934 struct i915_power_domains { 935 /* 936 * Power wells needed for initialization at driver init and suspend 937 * time are on. They are kept on until after the first modeset. 938 */ 939 bool initializing; 940 bool display_core_suspended; 941 int power_well_count; 942 943 struct mutex lock; 944 int domain_use_count[POWER_DOMAIN_NUM]; 945 struct i915_power_well *power_wells; 946 }; 947 948 #define MAX_L3_SLICES 2 949 struct intel_l3_parity { 950 u32 *remap_info[MAX_L3_SLICES]; 951 struct work_struct error_work; 952 int which_slice; 953 }; 954 955 struct i915_gem_mm { 956 /** Memory allocator for GTT stolen memory */ 957 struct drm_mm stolen; 958 /** Protects the usage of the GTT stolen memory allocator. This is 959 * always the inner lock when overlapping with struct_mutex. */ 960 struct mutex stolen_lock; 961 962 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 963 spinlock_t obj_lock; 964 965 /** List of all objects in gtt_space. Used to restore gtt 966 * mappings on resume */ 967 struct list_head bound_list; 968 /** 969 * List of objects which are not bound to the GTT (thus 970 * are idle and not used by the GPU). These objects may or may 971 * not actually have any pages attached. 972 */ 973 struct list_head unbound_list; 974 975 /** List of all objects in gtt_space, currently mmaped by userspace. 976 * All objects within this list must also be on bound_list. 977 */ 978 struct list_head userfault_list; 979 980 /** 981 * List of objects which are pending destruction. 982 */ 983 struct llist_head free_list; 984 struct work_struct free_work; 985 spinlock_t free_lock; 986 /** 987 * Count of objects pending destructions. Used to skip needlessly 988 * waiting on an RCU barrier if no objects are waiting to be freed. 989 */ 990 atomic_t free_count; 991 992 /** 993 * Small stash of WC pages 994 */ 995 struct pagestash wc_stash; 996 997 /** 998 * tmpfs instance used for shmem backed objects 999 */ 1000 struct vfsmount *gemfs; 1001 1002 /** PPGTT used for aliasing the PPGTT with the GTT */ 1003 struct i915_hw_ppgtt *aliasing_ppgtt; 1004 1005 struct notifier_block oom_notifier; 1006 struct notifier_block vmap_notifier; 1007 struct shrinker shrinker; 1008 1009 /** LRU list of objects with fence regs on them. */ 1010 struct list_head fence_list; 1011 1012 /** 1013 * Workqueue to fault in userptr pages, flushed by the execbuf 1014 * when required but otherwise left to userspace to try again 1015 * on EAGAIN. 1016 */ 1017 struct workqueue_struct *userptr_wq; 1018 1019 u64 unordered_timeline; 1020 1021 /* the indicator for dispatch video commands on two BSD rings */ 1022 atomic_t bsd_engine_dispatch_index; 1023 1024 /** Bit 6 swizzling required for X tiling */ 1025 uint32_t bit_6_swizzle_x; 1026 /** Bit 6 swizzling required for Y tiling */ 1027 uint32_t bit_6_swizzle_y; 1028 1029 /* accounting, useful for userland debugging */ 1030 spinlock_t object_stat_lock; 1031 u64 object_memory; 1032 u32 object_count; 1033 }; 1034 1035 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 1036 1037 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 1038 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 1039 1040 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 1041 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 1042 1043 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 1044 1045 #define DP_AUX_A 0x40 1046 #define DP_AUX_B 0x10 1047 #define DP_AUX_C 0x20 1048 #define DP_AUX_D 0x30 1049 #define DP_AUX_E 0x50 1050 #define DP_AUX_F 0x60 1051 1052 #define DDC_PIN_B 0x05 1053 #define DDC_PIN_C 0x04 1054 #define DDC_PIN_D 0x06 1055 1056 struct ddi_vbt_port_info { 1057 int max_tmds_clock; 1058 1059 /* 1060 * This is an index in the HDMI/DVI DDI buffer translation table. 1061 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1062 * populate this field. 1063 */ 1064 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1065 uint8_t hdmi_level_shift; 1066 1067 uint8_t supports_dvi:1; 1068 uint8_t supports_hdmi:1; 1069 uint8_t supports_dp:1; 1070 uint8_t supports_edp:1; 1071 1072 uint8_t alternate_aux_channel; 1073 uint8_t alternate_ddc_pin; 1074 1075 uint8_t dp_boost_level; 1076 uint8_t hdmi_boost_level; 1077 int dp_max_link_rate; /* 0 for not limited by VBT */ 1078 }; 1079 1080 enum psr_lines_to_wait { 1081 PSR_0_LINES_TO_WAIT = 0, 1082 PSR_1_LINE_TO_WAIT, 1083 PSR_4_LINES_TO_WAIT, 1084 PSR_8_LINES_TO_WAIT 1085 }; 1086 1087 struct intel_vbt_data { 1088 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1089 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1090 1091 /* Feature bits */ 1092 unsigned int int_tv_support:1; 1093 unsigned int lvds_dither:1; 1094 unsigned int int_crt_support:1; 1095 unsigned int lvds_use_ssc:1; 1096 unsigned int int_lvds_support:1; 1097 unsigned int display_clock_mode:1; 1098 unsigned int fdi_rx_polarity_inverted:1; 1099 unsigned int panel_type:4; 1100 int lvds_ssc_freq; 1101 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1102 1103 enum drrs_support_type drrs_type; 1104 1105 struct { 1106 int rate; 1107 int lanes; 1108 int preemphasis; 1109 int vswing; 1110 bool low_vswing; 1111 bool initialized; 1112 int bpp; 1113 struct edp_power_seq pps; 1114 } edp; 1115 1116 struct { 1117 bool enable; 1118 bool full_link; 1119 bool require_aux_wakeup; 1120 int idle_frames; 1121 enum psr_lines_to_wait lines_to_wait; 1122 int tp1_wakeup_time_us; 1123 int tp2_tp3_wakeup_time_us; 1124 } psr; 1125 1126 struct { 1127 u16 pwm_freq_hz; 1128 bool present; 1129 bool active_low_pwm; 1130 u8 min_brightness; /* min_brightness/255 of max */ 1131 u8 controller; /* brightness controller number */ 1132 enum intel_backlight_type type; 1133 } backlight; 1134 1135 /* MIPI DSI */ 1136 struct { 1137 u16 panel_id; 1138 struct mipi_config *config; 1139 struct mipi_pps_data *pps; 1140 u16 bl_ports; 1141 u16 cabc_ports; 1142 u8 seq_version; 1143 u32 size; 1144 u8 *data; 1145 const u8 *sequence[MIPI_SEQ_MAX]; 1146 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 1147 } dsi; 1148 1149 int crt_ddc_pin; 1150 1151 int child_dev_num; 1152 struct child_device_config *child_dev; 1153 1154 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1155 struct sdvo_device_mapping sdvo_mappings[2]; 1156 }; 1157 1158 enum intel_ddb_partitioning { 1159 INTEL_DDB_PART_1_2, 1160 INTEL_DDB_PART_5_6, /* IVB+ */ 1161 }; 1162 1163 struct intel_wm_level { 1164 bool enable; 1165 uint32_t pri_val; 1166 uint32_t spr_val; 1167 uint32_t cur_val; 1168 uint32_t fbc_val; 1169 }; 1170 1171 struct ilk_wm_values { 1172 uint32_t wm_pipe[3]; 1173 uint32_t wm_lp[3]; 1174 uint32_t wm_lp_spr[3]; 1175 uint32_t wm_linetime[3]; 1176 bool enable_fbc_wm; 1177 enum intel_ddb_partitioning partitioning; 1178 }; 1179 1180 struct g4x_pipe_wm { 1181 uint16_t plane[I915_MAX_PLANES]; 1182 uint16_t fbc; 1183 }; 1184 1185 struct g4x_sr_wm { 1186 uint16_t plane; 1187 uint16_t cursor; 1188 uint16_t fbc; 1189 }; 1190 1191 struct vlv_wm_ddl_values { 1192 uint8_t plane[I915_MAX_PLANES]; 1193 }; 1194 1195 struct vlv_wm_values { 1196 struct g4x_pipe_wm pipe[3]; 1197 struct g4x_sr_wm sr; 1198 struct vlv_wm_ddl_values ddl[3]; 1199 uint8_t level; 1200 bool cxsr; 1201 }; 1202 1203 struct g4x_wm_values { 1204 struct g4x_pipe_wm pipe[2]; 1205 struct g4x_sr_wm sr; 1206 struct g4x_sr_wm hpll; 1207 bool cxsr; 1208 bool hpll_en; 1209 bool fbc_en; 1210 }; 1211 1212 struct skl_ddb_entry { 1213 uint16_t start, end; /* in number of blocks, 'end' is exclusive */ 1214 }; 1215 1216 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) 1217 { 1218 return entry->end - entry->start; 1219 } 1220 1221 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 1222 const struct skl_ddb_entry *e2) 1223 { 1224 if (e1->start == e2->start && e1->end == e2->end) 1225 return true; 1226 1227 return false; 1228 } 1229 1230 struct skl_ddb_allocation { 1231 /* packed/y */ 1232 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; 1233 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES]; 1234 u8 enabled_slices; /* GEN11 has configurable 2 slices */ 1235 }; 1236 1237 struct skl_ddb_values { 1238 unsigned dirty_pipes; 1239 struct skl_ddb_allocation ddb; 1240 }; 1241 1242 struct skl_wm_level { 1243 bool plane_en; 1244 uint16_t plane_res_b; 1245 uint8_t plane_res_l; 1246 }; 1247 1248 /* Stores plane specific WM parameters */ 1249 struct skl_wm_params { 1250 bool x_tiled, y_tiled; 1251 bool rc_surface; 1252 bool is_planar; 1253 uint32_t width; 1254 uint8_t cpp; 1255 uint32_t plane_pixel_rate; 1256 uint32_t y_min_scanlines; 1257 uint32_t plane_bytes_per_line; 1258 uint_fixed_16_16_t plane_blocks_per_line; 1259 uint_fixed_16_16_t y_tile_minimum; 1260 uint32_t linetime_us; 1261 uint32_t dbuf_block_size; 1262 }; 1263 1264 /* 1265 * This struct helps tracking the state needed for runtime PM, which puts the 1266 * device in PCI D3 state. Notice that when this happens, nothing on the 1267 * graphics device works, even register access, so we don't get interrupts nor 1268 * anything else. 1269 * 1270 * Every piece of our code that needs to actually touch the hardware needs to 1271 * either call intel_runtime_pm_get or call intel_display_power_get with the 1272 * appropriate power domain. 1273 * 1274 * Our driver uses the autosuspend delay feature, which means we'll only really 1275 * suspend if we stay with zero refcount for a certain amount of time. The 1276 * default value is currently very conservative (see intel_runtime_pm_enable), but 1277 * it can be changed with the standard runtime PM files from sysfs. 1278 * 1279 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1280 * goes back to false exactly before we reenable the IRQs. We use this variable 1281 * to check if someone is trying to enable/disable IRQs while they're supposed 1282 * to be disabled. This shouldn't happen and we'll print some error messages in 1283 * case it happens. 1284 * 1285 * For more, read the Documentation/power/runtime_pm.txt. 1286 */ 1287 struct i915_runtime_pm { 1288 atomic_t wakeref_count; 1289 bool suspended; 1290 bool irqs_enabled; 1291 }; 1292 1293 enum intel_pipe_crc_source { 1294 INTEL_PIPE_CRC_SOURCE_NONE, 1295 INTEL_PIPE_CRC_SOURCE_PLANE1, 1296 INTEL_PIPE_CRC_SOURCE_PLANE2, 1297 INTEL_PIPE_CRC_SOURCE_PF, 1298 INTEL_PIPE_CRC_SOURCE_PIPE, 1299 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1300 INTEL_PIPE_CRC_SOURCE_TV, 1301 INTEL_PIPE_CRC_SOURCE_DP_B, 1302 INTEL_PIPE_CRC_SOURCE_DP_C, 1303 INTEL_PIPE_CRC_SOURCE_DP_D, 1304 INTEL_PIPE_CRC_SOURCE_AUTO, 1305 INTEL_PIPE_CRC_SOURCE_MAX, 1306 }; 1307 1308 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1309 struct intel_pipe_crc { 1310 spinlock_t lock; 1311 int skipped; 1312 enum intel_pipe_crc_source source; 1313 }; 1314 1315 struct i915_frontbuffer_tracking { 1316 spinlock_t lock; 1317 1318 /* 1319 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1320 * scheduled flips. 1321 */ 1322 unsigned busy_bits; 1323 unsigned flip_bits; 1324 }; 1325 1326 struct i915_wa_reg { 1327 u32 addr; 1328 u32 value; 1329 /* bitmask representing WA bits */ 1330 u32 mask; 1331 }; 1332 1333 #define I915_MAX_WA_REGS 16 1334 1335 struct i915_workarounds { 1336 struct i915_wa_reg reg[I915_MAX_WA_REGS]; 1337 u32 count; 1338 }; 1339 1340 struct i915_virtual_gpu { 1341 bool active; 1342 u32 caps; 1343 }; 1344 1345 /* used in computing the new watermarks state */ 1346 struct intel_wm_config { 1347 unsigned int num_pipes_active; 1348 bool sprites_enabled; 1349 bool sprites_scaled; 1350 }; 1351 1352 struct i915_oa_format { 1353 u32 format; 1354 int size; 1355 }; 1356 1357 struct i915_oa_reg { 1358 i915_reg_t addr; 1359 u32 value; 1360 }; 1361 1362 struct i915_oa_config { 1363 char uuid[UUID_STRING_LEN + 1]; 1364 int id; 1365 1366 const struct i915_oa_reg *mux_regs; 1367 u32 mux_regs_len; 1368 const struct i915_oa_reg *b_counter_regs; 1369 u32 b_counter_regs_len; 1370 const struct i915_oa_reg *flex_regs; 1371 u32 flex_regs_len; 1372 1373 struct attribute_group sysfs_metric; 1374 struct attribute *attrs[2]; 1375 struct device_attribute sysfs_metric_id; 1376 1377 atomic_t ref_count; 1378 }; 1379 1380 struct i915_perf_stream; 1381 1382 /** 1383 * struct i915_perf_stream_ops - the OPs to support a specific stream type 1384 */ 1385 struct i915_perf_stream_ops { 1386 /** 1387 * @enable: Enables the collection of HW samples, either in response to 1388 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened 1389 * without `I915_PERF_FLAG_DISABLED`. 1390 */ 1391 void (*enable)(struct i915_perf_stream *stream); 1392 1393 /** 1394 * @disable: Disables the collection of HW samples, either in response 1395 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying 1396 * the stream. 1397 */ 1398 void (*disable)(struct i915_perf_stream *stream); 1399 1400 /** 1401 * @poll_wait: Call poll_wait, passing a wait queue that will be woken 1402 * once there is something ready to read() for the stream 1403 */ 1404 void (*poll_wait)(struct i915_perf_stream *stream, 1405 struct file *file, 1406 poll_table *wait); 1407 1408 /** 1409 * @wait_unlocked: For handling a blocking read, wait until there is 1410 * something to ready to read() for the stream. E.g. wait on the same 1411 * wait queue that would be passed to poll_wait(). 1412 */ 1413 int (*wait_unlocked)(struct i915_perf_stream *stream); 1414 1415 /** 1416 * @read: Copy buffered metrics as records to userspace 1417 * **buf**: the userspace, destination buffer 1418 * **count**: the number of bytes to copy, requested by userspace 1419 * **offset**: zero at the start of the read, updated as the read 1420 * proceeds, it represents how many bytes have been copied so far and 1421 * the buffer offset for copying the next record. 1422 * 1423 * Copy as many buffered i915 perf samples and records for this stream 1424 * to userspace as will fit in the given buffer. 1425 * 1426 * Only write complete records; returning -%ENOSPC if there isn't room 1427 * for a complete record. 1428 * 1429 * Return any error condition that results in a short read such as 1430 * -%ENOSPC or -%EFAULT, even though these may be squashed before 1431 * returning to userspace. 1432 */ 1433 int (*read)(struct i915_perf_stream *stream, 1434 char __user *buf, 1435 size_t count, 1436 size_t *offset); 1437 1438 /** 1439 * @destroy: Cleanup any stream specific resources. 1440 * 1441 * The stream will always be disabled before this is called. 1442 */ 1443 void (*destroy)(struct i915_perf_stream *stream); 1444 }; 1445 1446 /** 1447 * struct i915_perf_stream - state for a single open stream FD 1448 */ 1449 struct i915_perf_stream { 1450 /** 1451 * @dev_priv: i915 drm device 1452 */ 1453 struct drm_i915_private *dev_priv; 1454 1455 /** 1456 * @link: Links the stream into ``&drm_i915_private->streams`` 1457 */ 1458 struct list_head link; 1459 1460 /** 1461 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` 1462 * properties given when opening a stream, representing the contents 1463 * of a single sample as read() by userspace. 1464 */ 1465 u32 sample_flags; 1466 1467 /** 1468 * @sample_size: Considering the configured contents of a sample 1469 * combined with the required header size, this is the total size 1470 * of a single sample record. 1471 */ 1472 int sample_size; 1473 1474 /** 1475 * @ctx: %NULL if measuring system-wide across all contexts or a 1476 * specific context that is being monitored. 1477 */ 1478 struct i915_gem_context *ctx; 1479 1480 /** 1481 * @enabled: Whether the stream is currently enabled, considering 1482 * whether the stream was opened in a disabled state and based 1483 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. 1484 */ 1485 bool enabled; 1486 1487 /** 1488 * @ops: The callbacks providing the implementation of this specific 1489 * type of configured stream. 1490 */ 1491 const struct i915_perf_stream_ops *ops; 1492 1493 /** 1494 * @oa_config: The OA configuration used by the stream. 1495 */ 1496 struct i915_oa_config *oa_config; 1497 }; 1498 1499 /** 1500 * struct i915_oa_ops - Gen specific implementation of an OA unit stream 1501 */ 1502 struct i915_oa_ops { 1503 /** 1504 * @is_valid_b_counter_reg: Validates register's address for 1505 * programming boolean counters for a particular platform. 1506 */ 1507 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, 1508 u32 addr); 1509 1510 /** 1511 * @is_valid_mux_reg: Validates register's address for programming mux 1512 * for a particular platform. 1513 */ 1514 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); 1515 1516 /** 1517 * @is_valid_flex_reg: Validates register's address for programming 1518 * flex EU filtering for a particular platform. 1519 */ 1520 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); 1521 1522 /** 1523 * @init_oa_buffer: Resets the head and tail pointers of the 1524 * circular buffer for periodic OA reports. 1525 * 1526 * Called when first opening a stream for OA metrics, but also may be 1527 * called in response to an OA buffer overflow or other error 1528 * condition. 1529 * 1530 * Note it may be necessary to clear the full OA buffer here as part of 1531 * maintaining the invariable that new reports must be written to 1532 * zeroed memory for us to be able to reliable detect if an expected 1533 * report has not yet landed in memory. (At least on Haswell the OA 1534 * buffer tail pointer is not synchronized with reports being visible 1535 * to the CPU) 1536 */ 1537 void (*init_oa_buffer)(struct drm_i915_private *dev_priv); 1538 1539 /** 1540 * @enable_metric_set: Selects and applies any MUX configuration to set 1541 * up the Boolean and Custom (B/C) counters that are part of the 1542 * counter reports being sampled. May apply system constraints such as 1543 * disabling EU clock gating as required. 1544 */ 1545 int (*enable_metric_set)(struct drm_i915_private *dev_priv, 1546 const struct i915_oa_config *oa_config); 1547 1548 /** 1549 * @disable_metric_set: Remove system constraints associated with using 1550 * the OA unit. 1551 */ 1552 void (*disable_metric_set)(struct drm_i915_private *dev_priv); 1553 1554 /** 1555 * @oa_enable: Enable periodic sampling 1556 */ 1557 void (*oa_enable)(struct drm_i915_private *dev_priv); 1558 1559 /** 1560 * @oa_disable: Disable periodic sampling 1561 */ 1562 void (*oa_disable)(struct drm_i915_private *dev_priv); 1563 1564 /** 1565 * @read: Copy data from the circular OA buffer into a given userspace 1566 * buffer. 1567 */ 1568 int (*read)(struct i915_perf_stream *stream, 1569 char __user *buf, 1570 size_t count, 1571 size_t *offset); 1572 1573 /** 1574 * @oa_hw_tail_read: read the OA tail pointer register 1575 * 1576 * In particular this enables us to share all the fiddly code for 1577 * handling the OA unit tail pointer race that affects multiple 1578 * generations. 1579 */ 1580 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv); 1581 }; 1582 1583 struct intel_cdclk_state { 1584 unsigned int cdclk, vco, ref, bypass; 1585 u8 voltage_level; 1586 }; 1587 1588 struct drm_i915_private { 1589 struct drm_device drm; 1590 1591 struct kmem_cache *objects; 1592 struct kmem_cache *vmas; 1593 struct kmem_cache *luts; 1594 struct kmem_cache *requests; 1595 struct kmem_cache *dependencies; 1596 struct kmem_cache *priorities; 1597 1598 const struct intel_device_info info; 1599 struct intel_driver_caps caps; 1600 1601 /** 1602 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 1603 * end of stolen which we can optionally use to create GEM objects 1604 * backed by stolen memory. Note that stolen_usable_size tells us 1605 * exactly how much of this we are actually allowed to use, given that 1606 * some portion of it is in fact reserved for use by hardware functions. 1607 */ 1608 struct resource dsm; 1609 /** 1610 * Reseved portion of Data Stolen Memory 1611 */ 1612 struct resource dsm_reserved; 1613 1614 /* 1615 * Stolen memory is segmented in hardware with different portions 1616 * offlimits to certain functions. 1617 * 1618 * The drm_mm is initialised to the total accessible range, as found 1619 * from the PCI config. On Broadwell+, this is further restricted to 1620 * avoid the first page! The upper end of stolen memory is reserved for 1621 * hardware functions and similarly removed from the accessible range. 1622 */ 1623 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 1624 1625 void __iomem *regs; 1626 1627 struct intel_uncore uncore; 1628 1629 struct i915_virtual_gpu vgpu; 1630 1631 struct intel_gvt *gvt; 1632 1633 struct intel_wopcm wopcm; 1634 1635 struct intel_huc huc; 1636 struct intel_guc guc; 1637 1638 struct intel_csr csr; 1639 1640 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 1641 1642 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1643 * controller on different i2c buses. */ 1644 struct mutex gmbus_mutex; 1645 1646 /** 1647 * Base address of where the gmbus and gpio blocks are located (either 1648 * on PCH or on SoC for platforms without PCH). 1649 */ 1650 uint32_t gpio_mmio_base; 1651 1652 /* MMIO base address for MIPI regs */ 1653 uint32_t mipi_mmio_base; 1654 1655 uint32_t psr_mmio_base; 1656 1657 uint32_t pps_mmio_base; 1658 1659 wait_queue_head_t gmbus_wait_queue; 1660 1661 struct pci_dev *bridge_dev; 1662 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 1663 /* Context used internally to idle the GPU and setup initial state */ 1664 struct i915_gem_context *kernel_context; 1665 /* Context only to be used for injecting preemption commands */ 1666 struct i915_gem_context *preempt_context; 1667 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] 1668 [MAX_ENGINE_INSTANCE + 1]; 1669 1670 struct resource mch_res; 1671 1672 /* protects the irq masks */ 1673 spinlock_t irq_lock; 1674 1675 bool display_irqs_enabled; 1676 1677 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1678 struct pm_qos_request pm_qos; 1679 1680 /* Sideband mailbox protection */ 1681 struct mutex sb_lock; 1682 1683 /** Cached value of IMR to avoid reads in updating the bitfield */ 1684 union { 1685 u32 irq_mask; 1686 u32 de_irq_mask[I915_MAX_PIPES]; 1687 }; 1688 u32 gt_irq_mask; 1689 u32 pm_imr; 1690 u32 pm_ier; 1691 u32 pm_rps_events; 1692 u32 pm_guc_events; 1693 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1694 1695 struct i915_hotplug hotplug; 1696 struct intel_fbc fbc; 1697 struct i915_drrs drrs; 1698 struct intel_opregion opregion; 1699 struct intel_vbt_data vbt; 1700 1701 bool preserve_bios_swizzle; 1702 1703 /* overlay */ 1704 struct intel_overlay *overlay; 1705 1706 /* backlight registers and fields in struct intel_panel */ 1707 struct mutex backlight_lock; 1708 1709 /* LVDS info */ 1710 bool no_aux_handshake; 1711 1712 /* protects panel power sequencer state */ 1713 struct mutex pps_mutex; 1714 1715 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1716 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1717 1718 unsigned int fsb_freq, mem_freq, is_ddr3; 1719 unsigned int skl_preferred_vco_freq; 1720 unsigned int max_cdclk_freq; 1721 1722 unsigned int max_dotclk_freq; 1723 unsigned int rawclk_freq; 1724 unsigned int hpll_freq; 1725 unsigned int fdi_pll_freq; 1726 unsigned int czclk_freq; 1727 1728 struct { 1729 /* 1730 * The current logical cdclk state. 1731 * See intel_atomic_state.cdclk.logical 1732 * 1733 * For reading holding any crtc lock is sufficient, 1734 * for writing must hold all of them. 1735 */ 1736 struct intel_cdclk_state logical; 1737 /* 1738 * The current actual cdclk state. 1739 * See intel_atomic_state.cdclk.actual 1740 */ 1741 struct intel_cdclk_state actual; 1742 /* The current hardware cdclk state */ 1743 struct intel_cdclk_state hw; 1744 } cdclk; 1745 1746 /** 1747 * wq - Driver workqueue for GEM. 1748 * 1749 * NOTE: Work items scheduled here are not allowed to grab any modeset 1750 * locks, for otherwise the flushing done in the pageflip code will 1751 * result in deadlocks. 1752 */ 1753 struct workqueue_struct *wq; 1754 1755 /* ordered wq for modesets */ 1756 struct workqueue_struct *modeset_wq; 1757 1758 /* Display functions */ 1759 struct drm_i915_display_funcs display; 1760 1761 /* PCH chipset type */ 1762 enum intel_pch pch_type; 1763 unsigned short pch_id; 1764 1765 unsigned long quirks; 1766 1767 struct drm_atomic_state *modeset_restore_state; 1768 struct drm_modeset_acquire_ctx reset_ctx; 1769 1770 struct i915_ggtt ggtt; /* VM representing the global address space */ 1771 1772 struct i915_gem_mm mm; 1773 DECLARE_HASHTABLE(mm_structs, 7); 1774 struct mutex mm_lock; 1775 1776 struct intel_ppat ppat; 1777 1778 /* Kernel Modesetting */ 1779 1780 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1781 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1782 1783 #ifdef CONFIG_DEBUG_FS 1784 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1785 #endif 1786 1787 /* dpll and cdclk state is protected by connection_mutex */ 1788 int num_shared_dpll; 1789 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1790 const struct intel_dpll_mgr *dpll_mgr; 1791 1792 /* 1793 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1794 * Must be global rather than per dpll, because on some platforms 1795 * plls share registers. 1796 */ 1797 struct mutex dpll_lock; 1798 1799 unsigned int active_crtcs; 1800 /* minimum acceptable cdclk for each pipe */ 1801 int min_cdclk[I915_MAX_PIPES]; 1802 /* minimum acceptable voltage level for each pipe */ 1803 u8 min_voltage_level[I915_MAX_PIPES]; 1804 1805 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1806 1807 struct i915_workarounds workarounds; 1808 1809 struct i915_frontbuffer_tracking fb_tracking; 1810 1811 struct intel_atomic_helper { 1812 struct llist_head free_list; 1813 struct work_struct free_work; 1814 } atomic_helper; 1815 1816 u16 orig_clock; 1817 1818 bool mchbar_need_disable; 1819 1820 struct intel_l3_parity l3_parity; 1821 1822 /* Cannot be determined by PCIID. You must always read a register. */ 1823 u32 edram_cap; 1824 1825 /* 1826 * Protects RPS/RC6 register access and PCU communication. 1827 * Must be taken after struct_mutex if nested. Note that 1828 * this lock may be held for long periods of time when 1829 * talking to hw - so only take it when talking to hw! 1830 */ 1831 struct mutex pcu_lock; 1832 1833 /* gen6+ GT PM state */ 1834 struct intel_gen6_power_mgmt gt_pm; 1835 1836 /* ilk-only ips/rps state. Everything in here is protected by the global 1837 * mchdev_lock in intel_pm.c */ 1838 struct intel_ilk_power_mgmt ips; 1839 1840 struct i915_power_domains power_domains; 1841 1842 struct i915_psr psr; 1843 1844 struct i915_gpu_error gpu_error; 1845 1846 struct drm_i915_gem_object *vlv_pctx; 1847 1848 /* list of fbdev register on this device */ 1849 struct intel_fbdev *fbdev; 1850 struct work_struct fbdev_suspend_work; 1851 1852 struct drm_property *broadcast_rgb_property; 1853 struct drm_property *force_audio_property; 1854 1855 /* hda/i915 audio component */ 1856 struct i915_audio_component *audio_component; 1857 bool audio_component_registered; 1858 /** 1859 * av_mutex - mutex for audio/video sync 1860 * 1861 */ 1862 struct mutex av_mutex; 1863 1864 struct { 1865 struct mutex mutex; 1866 struct list_head list; 1867 struct llist_head free_list; 1868 struct work_struct free_work; 1869 1870 /* The hw wants to have a stable context identifier for the 1871 * lifetime of the context (for OA, PASID, faults, etc). 1872 * This is limited in execlists to 21 bits. 1873 */ 1874 struct ida hw_ida; 1875 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 1876 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 1877 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ 1878 struct list_head hw_id_list; 1879 } contexts; 1880 1881 u32 fdi_rx_config; 1882 1883 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1884 u32 chv_phy_control; 1885 /* 1886 * Shadows for CHV DPLL_MD regs to keep the state 1887 * checker somewhat working in the presence hardware 1888 * crappiness (can't read out DPLL_MD for pipes B & C). 1889 */ 1890 u32 chv_dpll_md[I915_MAX_PIPES]; 1891 u32 bxt_phy_grc; 1892 1893 u32 suspend_count; 1894 bool power_domains_suspended; 1895 struct i915_suspend_saved_registers regfile; 1896 struct vlv_s0ix_state vlv_s0ix_state; 1897 1898 enum { 1899 I915_SAGV_UNKNOWN = 0, 1900 I915_SAGV_DISABLED, 1901 I915_SAGV_ENABLED, 1902 I915_SAGV_NOT_CONTROLLED 1903 } sagv_status; 1904 1905 struct { 1906 /* 1907 * Raw watermark latency values: 1908 * in 0.1us units for WM0, 1909 * in 0.5us units for WM1+. 1910 */ 1911 /* primary */ 1912 uint16_t pri_latency[5]; 1913 /* sprite */ 1914 uint16_t spr_latency[5]; 1915 /* cursor */ 1916 uint16_t cur_latency[5]; 1917 /* 1918 * Raw watermark memory latency values 1919 * for SKL for all 8 levels 1920 * in 1us units. 1921 */ 1922 uint16_t skl_latency[8]; 1923 1924 /* current hardware state */ 1925 union { 1926 struct ilk_wm_values hw; 1927 struct skl_ddb_values skl_hw; 1928 struct vlv_wm_values vlv; 1929 struct g4x_wm_values g4x; 1930 }; 1931 1932 uint8_t max_level; 1933 1934 /* 1935 * Should be held around atomic WM register writing; also 1936 * protects * intel_crtc->wm.active and 1937 * cstate->wm.need_postvbl_update. 1938 */ 1939 struct mutex wm_mutex; 1940 1941 /* 1942 * Set during HW readout of watermarks/DDB. Some platforms 1943 * need to know when we're still using BIOS-provided values 1944 * (which we don't fully trust). 1945 */ 1946 bool distrust_bios_wm; 1947 } wm; 1948 1949 struct dram_info { 1950 bool valid; 1951 bool valid_dimm; 1952 bool is_16gb_dimm; 1953 u8 num_channels; 1954 enum dram_rank { 1955 I915_DRAM_RANK_INVALID = 0, 1956 I915_DRAM_RANK_SINGLE, 1957 I915_DRAM_RANK_DUAL 1958 } rank; 1959 u32 bandwidth_kbps; 1960 bool symmetric_memory; 1961 } dram_info; 1962 1963 struct i915_runtime_pm runtime_pm; 1964 1965 struct { 1966 bool initialized; 1967 1968 struct kobject *metrics_kobj; 1969 struct ctl_table_header *sysctl_header; 1970 1971 /* 1972 * Lock associated with adding/modifying/removing OA configs 1973 * in dev_priv->perf.metrics_idr. 1974 */ 1975 struct mutex metrics_lock; 1976 1977 /* 1978 * List of dynamic configurations, you need to hold 1979 * dev_priv->perf.metrics_lock to access it. 1980 */ 1981 struct idr metrics_idr; 1982 1983 /* 1984 * Lock associated with anything below within this structure 1985 * except exclusive_stream. 1986 */ 1987 struct mutex lock; 1988 struct list_head streams; 1989 1990 struct { 1991 /* 1992 * The stream currently using the OA unit. If accessed 1993 * outside a syscall associated to its file 1994 * descriptor, you need to hold 1995 * dev_priv->drm.struct_mutex. 1996 */ 1997 struct i915_perf_stream *exclusive_stream; 1998 1999 struct intel_context *pinned_ctx; 2000 u32 specific_ctx_id; 2001 u32 specific_ctx_id_mask; 2002 2003 struct hrtimer poll_check_timer; 2004 wait_queue_head_t poll_wq; 2005 bool pollin; 2006 2007 /** 2008 * For rate limiting any notifications of spurious 2009 * invalid OA reports 2010 */ 2011 struct ratelimit_state spurious_report_rs; 2012 2013 bool periodic; 2014 int period_exponent; 2015 2016 struct i915_oa_config test_config; 2017 2018 struct { 2019 struct i915_vma *vma; 2020 u8 *vaddr; 2021 u32 last_ctx_id; 2022 int format; 2023 int format_size; 2024 2025 /** 2026 * Locks reads and writes to all head/tail state 2027 * 2028 * Consider: the head and tail pointer state 2029 * needs to be read consistently from a hrtimer 2030 * callback (atomic context) and read() fop 2031 * (user context) with tail pointer updates 2032 * happening in atomic context and head updates 2033 * in user context and the (unlikely) 2034 * possibility of read() errors needing to 2035 * reset all head/tail state. 2036 * 2037 * Note: Contention or performance aren't 2038 * currently a significant concern here 2039 * considering the relatively low frequency of 2040 * hrtimer callbacks (5ms period) and that 2041 * reads typically only happen in response to a 2042 * hrtimer event and likely complete before the 2043 * next callback. 2044 * 2045 * Note: This lock is not held *while* reading 2046 * and copying data to userspace so the value 2047 * of head observed in htrimer callbacks won't 2048 * represent any partial consumption of data. 2049 */ 2050 spinlock_t ptr_lock; 2051 2052 /** 2053 * One 'aging' tail pointer and one 'aged' 2054 * tail pointer ready to used for reading. 2055 * 2056 * Initial values of 0xffffffff are invalid 2057 * and imply that an update is required 2058 * (and should be ignored by an attempted 2059 * read) 2060 */ 2061 struct { 2062 u32 offset; 2063 } tails[2]; 2064 2065 /** 2066 * Index for the aged tail ready to read() 2067 * data up to. 2068 */ 2069 unsigned int aged_tail_idx; 2070 2071 /** 2072 * A monotonic timestamp for when the current 2073 * aging tail pointer was read; used to 2074 * determine when it is old enough to trust. 2075 */ 2076 u64 aging_timestamp; 2077 2078 /** 2079 * Although we can always read back the head 2080 * pointer register, we prefer to avoid 2081 * trusting the HW state, just to avoid any 2082 * risk that some hardware condition could 2083 * somehow bump the head pointer unpredictably 2084 * and cause us to forward the wrong OA buffer 2085 * data to userspace. 2086 */ 2087 u32 head; 2088 } oa_buffer; 2089 2090 u32 gen7_latched_oastatus1; 2091 u32 ctx_oactxctrl_offset; 2092 u32 ctx_flexeu0_offset; 2093 2094 /** 2095 * The RPT_ID/reason field for Gen8+ includes a bit 2096 * to determine if the CTX ID in the report is valid 2097 * but the specific bit differs between Gen 8 and 9 2098 */ 2099 u32 gen8_valid_ctx_bit; 2100 2101 struct i915_oa_ops ops; 2102 const struct i915_oa_format *oa_formats; 2103 } oa; 2104 } perf; 2105 2106 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 2107 struct { 2108 void (*resume)(struct drm_i915_private *); 2109 void (*cleanup_engine)(struct intel_engine_cs *engine); 2110 2111 struct list_head timelines; 2112 2113 struct list_head active_rings; 2114 struct list_head closed_vma; 2115 u32 active_requests; 2116 u32 request_serial; 2117 2118 /** 2119 * Is the GPU currently considered idle, or busy executing 2120 * userspace requests? Whilst idle, we allow runtime power 2121 * management to power down the hardware and display clocks. 2122 * In order to reduce the effect on performance, there 2123 * is a slight delay before we do so. 2124 */ 2125 bool awake; 2126 2127 /** 2128 * The number of times we have woken up. 2129 */ 2130 unsigned int epoch; 2131 #define I915_EPOCH_INVALID 0 2132 2133 /** 2134 * We leave the user IRQ off as much as possible, 2135 * but this means that requests will finish and never 2136 * be retired once the system goes idle. Set a timer to 2137 * fire periodically while the ring is running. When it 2138 * fires, go retire requests. 2139 */ 2140 struct delayed_work retire_work; 2141 2142 /** 2143 * When we detect an idle GPU, we want to turn on 2144 * powersaving features. So once we see that there 2145 * are no more requests outstanding and no more 2146 * arrive within a small period of time, we fire 2147 * off the idle_work. 2148 */ 2149 struct delayed_work idle_work; 2150 2151 ktime_t last_init_time; 2152 } gt; 2153 2154 /* perform PHY state sanity checks? */ 2155 bool chv_phy_assert[2]; 2156 2157 bool ipc_enabled; 2158 2159 /* Used to save the pipe-to-encoder mapping for audio */ 2160 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 2161 2162 /* necessary resource sharing with HDMI LPE audio driver. */ 2163 struct { 2164 struct platform_device *platdev; 2165 int irq; 2166 } lpe_audio; 2167 2168 struct i915_pmu pmu; 2169 2170 /* 2171 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 2172 * will be rejected. Instead look for a better place. 2173 */ 2174 }; 2175 2176 struct dram_channel_info { 2177 struct info { 2178 u8 size, width; 2179 enum dram_rank rank; 2180 } l_info, s_info; 2181 enum dram_rank rank; 2182 bool is_16gb_dimm; 2183 }; 2184 2185 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 2186 { 2187 return container_of(dev, struct drm_i915_private, drm); 2188 } 2189 2190 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 2191 { 2192 return to_i915(dev_get_drvdata(kdev)); 2193 } 2194 2195 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm) 2196 { 2197 return container_of(wopcm, struct drm_i915_private, wopcm); 2198 } 2199 2200 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) 2201 { 2202 return container_of(guc, struct drm_i915_private, guc); 2203 } 2204 2205 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) 2206 { 2207 return container_of(huc, struct drm_i915_private, huc); 2208 } 2209 2210 /* Simple iterator over all initialised engines */ 2211 #define for_each_engine(engine__, dev_priv__, id__) \ 2212 for ((id__) = 0; \ 2213 (id__) < I915_NUM_ENGINES; \ 2214 (id__)++) \ 2215 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 2216 2217 /* Iterator over subset of engines selected by mask */ 2218 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ 2219 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \ 2220 (tmp__) ? \ 2221 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \ 2222 0;) 2223 2224 enum hdmi_force_audio { 2225 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 2226 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 2227 HDMI_AUDIO_AUTO, /* trust EDID */ 2228 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 2229 }; 2230 2231 #define I915_GTT_OFFSET_NONE ((u32)-1) 2232 2233 /* 2234 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 2235 * considered to be the frontbuffer for the given plane interface-wise. This 2236 * doesn't mean that the hw necessarily already scans it out, but that any 2237 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 2238 * 2239 * We have one bit per pipe and per scanout plane type. 2240 */ 2241 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 2242 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 2243 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 2244 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 2245 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 2246 }) 2247 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 2248 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 2249 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 2250 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 2251 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 2252 2253 /* 2254 * Optimised SGL iterator for GEM objects 2255 */ 2256 static __always_inline struct sgt_iter { 2257 struct scatterlist *sgp; 2258 union { 2259 unsigned long pfn; 2260 dma_addr_t dma; 2261 }; 2262 unsigned int curr; 2263 unsigned int max; 2264 } __sgt_iter(struct scatterlist *sgl, bool dma) { 2265 struct sgt_iter s = { .sgp = sgl }; 2266 2267 if (s.sgp) { 2268 s.max = s.curr = s.sgp->offset; 2269 s.max += s.sgp->length; 2270 if (dma) 2271 s.dma = sg_dma_address(s.sgp); 2272 else 2273 s.pfn = page_to_pfn(sg_page(s.sgp)); 2274 } 2275 2276 return s; 2277 } 2278 2279 static inline struct scatterlist *____sg_next(struct scatterlist *sg) 2280 { 2281 ++sg; 2282 if (unlikely(sg_is_chain(sg))) 2283 sg = sg_chain_ptr(sg); 2284 return sg; 2285 } 2286 2287 /** 2288 * __sg_next - return the next scatterlist entry in a list 2289 * @sg: The current sg entry 2290 * 2291 * Description: 2292 * If the entry is the last, return NULL; otherwise, step to the next 2293 * element in the array (@sg@+1). If that's a chain pointer, follow it; 2294 * otherwise just return the pointer to the current element. 2295 **/ 2296 static inline struct scatterlist *__sg_next(struct scatterlist *sg) 2297 { 2298 return sg_is_last(sg) ? NULL : ____sg_next(sg); 2299 } 2300 2301 /** 2302 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table 2303 * @__dmap: DMA address (output) 2304 * @__iter: 'struct sgt_iter' (iterator state, internal) 2305 * @__sgt: sg_table to iterate over (input) 2306 */ 2307 #define for_each_sgt_dma(__dmap, __iter, __sgt) \ 2308 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ 2309 ((__dmap) = (__iter).dma + (__iter).curr); \ 2310 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \ 2311 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0) 2312 2313 /** 2314 * for_each_sgt_page - iterate over the pages of the given sg_table 2315 * @__pp: page pointer (output) 2316 * @__iter: 'struct sgt_iter' (iterator state, internal) 2317 * @__sgt: sg_table to iterate over (input) 2318 */ 2319 #define for_each_sgt_page(__pp, __iter, __sgt) \ 2320 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ 2321 ((__pp) = (__iter).pfn == 0 ? NULL : \ 2322 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ 2323 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ 2324 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0) 2325 2326 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg) 2327 { 2328 unsigned int page_sizes; 2329 2330 page_sizes = 0; 2331 while (sg) { 2332 GEM_BUG_ON(sg->offset); 2333 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE)); 2334 page_sizes |= sg->length; 2335 sg = __sg_next(sg); 2336 } 2337 2338 return page_sizes; 2339 } 2340 2341 static inline unsigned int i915_sg_segment_size(void) 2342 { 2343 unsigned int size = swiotlb_max_segment(); 2344 2345 if (size == 0) 2346 return SCATTERLIST_MAX_SEGMENT; 2347 2348 size = rounddown(size, PAGE_SIZE); 2349 /* swiotlb_max_segment_size can return 1 byte when it means one page. */ 2350 if (size < PAGE_SIZE) 2351 size = PAGE_SIZE; 2352 2353 return size; 2354 } 2355 2356 static inline const struct intel_device_info * 2357 intel_info(const struct drm_i915_private *dev_priv) 2358 { 2359 return &dev_priv->info; 2360 } 2361 2362 #define INTEL_INFO(dev_priv) intel_info((dev_priv)) 2363 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 2364 2365 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) 2366 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) 2367 2368 #define REVID_FOREVER 0xff 2369 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 2370 2371 #define GEN_FOREVER (0) 2372 2373 #define INTEL_GEN_MASK(s, e) ( \ 2374 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 2375 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 2376 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ 2377 (s) != GEN_FOREVER ? (s) - 1 : 0) \ 2378 ) 2379 2380 /* 2381 * Returns true if Gen is in inclusive range [Start, End]. 2382 * 2383 * Use GEN_FOREVER for unbound start and or end. 2384 */ 2385 #define IS_GEN(dev_priv, s, e) \ 2386 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) 2387 2388 /* 2389 * Return true if revision is in range [since,until] inclusive. 2390 * 2391 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 2392 */ 2393 #define IS_REVID(p, since, until) \ 2394 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 2395 2396 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) 2397 2398 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 2399 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 2400 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 2401 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 2402 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 2403 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 2404 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 2405 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 2406 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 2407 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 2408 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 2409 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 2410 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 2411 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) 2412 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) 2413 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 2414 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 2415 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) 2416 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 2417 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 2418 (dev_priv)->info.gt == 1) 2419 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 2420 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 2421 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 2422 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 2423 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 2424 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 2425 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 2426 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 2427 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 2428 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 2429 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 2430 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) 2431 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 2432 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 2433 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ 2434 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ 2435 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ 2436 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) 2437 /* ULX machines are also considered ULT. */ 2438 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ 2439 (INTEL_DEVID(dev_priv) & 0xf) == 0xe) 2440 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 2441 (dev_priv)->info.gt == 3) 2442 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ 2443 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) 2444 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 2445 (dev_priv)->info.gt == 3) 2446 /* ULX machines are also considered ULT. */ 2447 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ 2448 INTEL_DEVID(dev_priv) == 0x0A1E) 2449 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ 2450 INTEL_DEVID(dev_priv) == 0x1913 || \ 2451 INTEL_DEVID(dev_priv) == 0x1916 || \ 2452 INTEL_DEVID(dev_priv) == 0x1921 || \ 2453 INTEL_DEVID(dev_priv) == 0x1926) 2454 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ 2455 INTEL_DEVID(dev_priv) == 0x1915 || \ 2456 INTEL_DEVID(dev_priv) == 0x191E) 2457 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ 2458 INTEL_DEVID(dev_priv) == 0x5913 || \ 2459 INTEL_DEVID(dev_priv) == 0x5916 || \ 2460 INTEL_DEVID(dev_priv) == 0x5921 || \ 2461 INTEL_DEVID(dev_priv) == 0x5926) 2462 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ 2463 INTEL_DEVID(dev_priv) == 0x5915 || \ 2464 INTEL_DEVID(dev_priv) == 0x591E) 2465 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 2466 (dev_priv)->info.gt == 2) 2467 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 2468 (dev_priv)->info.gt == 3) 2469 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 2470 (dev_priv)->info.gt == 4) 2471 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 2472 (dev_priv)->info.gt == 2) 2473 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 2474 (dev_priv)->info.gt == 3) 2475 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2476 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) 2477 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2478 (dev_priv)->info.gt == 2) 2479 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2480 (dev_priv)->info.gt == 3) 2481 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ 2482 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) 2483 2484 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) 2485 2486 #define SKL_REVID_A0 0x0 2487 #define SKL_REVID_B0 0x1 2488 #define SKL_REVID_C0 0x2 2489 #define SKL_REVID_D0 0x3 2490 #define SKL_REVID_E0 0x4 2491 #define SKL_REVID_F0 0x5 2492 #define SKL_REVID_G0 0x6 2493 #define SKL_REVID_H0 0x7 2494 2495 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 2496 2497 #define BXT_REVID_A0 0x0 2498 #define BXT_REVID_A1 0x1 2499 #define BXT_REVID_B0 0x3 2500 #define BXT_REVID_B_LAST 0x8 2501 #define BXT_REVID_C0 0x9 2502 2503 #define IS_BXT_REVID(dev_priv, since, until) \ 2504 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 2505 2506 #define KBL_REVID_A0 0x0 2507 #define KBL_REVID_B0 0x1 2508 #define KBL_REVID_C0 0x2 2509 #define KBL_REVID_D0 0x3 2510 #define KBL_REVID_E0 0x4 2511 2512 #define IS_KBL_REVID(dev_priv, since, until) \ 2513 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 2514 2515 #define GLK_REVID_A0 0x0 2516 #define GLK_REVID_A1 0x1 2517 2518 #define IS_GLK_REVID(dev_priv, since, until) \ 2519 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 2520 2521 #define CNL_REVID_A0 0x0 2522 #define CNL_REVID_B0 0x1 2523 #define CNL_REVID_C0 0x2 2524 2525 #define IS_CNL_REVID(p, since, until) \ 2526 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 2527 2528 #define ICL_REVID_A0 0x0 2529 #define ICL_REVID_A2 0x1 2530 #define ICL_REVID_B0 0x3 2531 #define ICL_REVID_B2 0x4 2532 #define ICL_REVID_C0 0x5 2533 2534 #define IS_ICL_REVID(p, since, until) \ 2535 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 2536 2537 /* 2538 * The genX designation typically refers to the render engine, so render 2539 * capability related checks should use IS_GEN, while display and other checks 2540 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2541 * chips, etc.). 2542 */ 2543 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) 2544 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) 2545 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) 2546 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) 2547 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) 2548 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) 2549 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) 2550 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) 2551 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) 2552 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) 2553 2554 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 2555 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) 2556 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) 2557 2558 #define ENGINE_MASK(id) BIT(id) 2559 #define RENDER_RING ENGINE_MASK(RCS) 2560 #define BSD_RING ENGINE_MASK(VCS) 2561 #define BLT_RING ENGINE_MASK(BCS) 2562 #define VEBOX_RING ENGINE_MASK(VECS) 2563 #define BSD2_RING ENGINE_MASK(VCS2) 2564 #define BSD3_RING ENGINE_MASK(VCS3) 2565 #define BSD4_RING ENGINE_MASK(VCS4) 2566 #define VEBOX2_RING ENGINE_MASK(VECS2) 2567 #define ALL_ENGINES (~0) 2568 2569 #define HAS_ENGINE(dev_priv, id) \ 2570 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) 2571 2572 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) 2573 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) 2574 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) 2575 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) 2576 2577 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) 2578 2579 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) 2580 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) 2581 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) 2582 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 2583 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 2584 2585 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) 2586 2587 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 2588 ((dev_priv)->info.has_logical_ring_contexts) 2589 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 2590 ((dev_priv)->info.has_logical_ring_elsq) 2591 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 2592 ((dev_priv)->info.has_logical_ring_preemption) 2593 2594 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 2595 2596 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) 2597 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) 2598 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3) 2599 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 2600 GEM_BUG_ON((sizes) == 0); \ 2601 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ 2602 }) 2603 2604 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) 2605 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 2606 ((dev_priv)->info.overlay_needs_physical) 2607 2608 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2609 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 2610 2611 /* WaRsDisableCoarsePowerGating:skl,cnl */ 2612 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 2613 (IS_CANNONLAKE(dev_priv) || \ 2614 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) 2615 2616 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 2617 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 2618 IS_GEMINILAKE(dev_priv) || \ 2619 IS_KABYLAKE(dev_priv)) 2620 2621 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2622 * rows, which changed the alignment requirements and fence programming. 2623 */ 2624 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ 2625 !(IS_I915G(dev_priv) || \ 2626 IS_I915GM(dev_priv))) 2627 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) 2628 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) 2629 2630 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 2631 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) 2632 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) 2633 2634 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 2635 2636 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) 2637 2638 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) 2639 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) 2640 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) 2641 2642 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) 2643 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) 2644 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 2645 2646 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) 2647 2648 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) 2649 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) 2650 2651 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) 2652 2653 /* 2654 * For now, anything with a GuC requires uCode loading, and then supports 2655 * command submission once loaded. But these are logically independent 2656 * properties, so we have separate macros to test them. 2657 */ 2658 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) 2659 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) 2660 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) 2661 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) 2662 2663 /* For now, anything with a GuC has also HuC */ 2664 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv)) 2665 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) 2666 2667 /* Having a GuC is not the same as using a GuC */ 2668 #define USES_GUC(dev_priv) intel_uc_is_using_guc() 2669 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission() 2670 #define USES_HUC(dev_priv) intel_uc_is_using_huc() 2671 2672 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) 2673 2674 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 2675 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2676 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2677 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2678 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2679 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2680 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 2681 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 2682 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 2683 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 2684 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 2685 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 2686 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 2687 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 2688 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 2689 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 2690 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ 2691 2692 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) 2693 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) 2694 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) 2695 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) 2696 #define HAS_PCH_CNP_LP(dev_priv) \ 2697 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) 2698 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) 2699 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) 2700 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) 2701 #define HAS_PCH_LPT_LP(dev_priv) \ 2702 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ 2703 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) 2704 #define HAS_PCH_LPT_H(dev_priv) \ 2705 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ 2706 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) 2707 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) 2708 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) 2709 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) 2710 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) 2711 2712 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) 2713 2714 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 2715 2716 /* DPF == dynamic parity feature */ 2717 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) 2718 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 2719 2 : HAS_L3_DPF(dev_priv)) 2720 2721 #define GT_FREQUENCY_MULTIPLIER 50 2722 #define GEN9_FREQ_SCALER 3 2723 2724 #include "i915_trace.h" 2725 2726 static inline bool intel_vtd_active(void) 2727 { 2728 #ifdef CONFIG_INTEL_IOMMU 2729 if (intel_iommu_gfx_mapped) 2730 return true; 2731 #endif 2732 return false; 2733 } 2734 2735 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 2736 { 2737 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 2738 } 2739 2740 static inline bool 2741 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 2742 { 2743 return IS_BROXTON(dev_priv) && intel_vtd_active(); 2744 } 2745 2746 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, 2747 int enable_ppgtt); 2748 2749 /* i915_drv.c */ 2750 void __printf(3, 4) 2751 __i915_printk(struct drm_i915_private *dev_priv, const char *level, 2752 const char *fmt, ...); 2753 2754 #define i915_report_error(dev_priv, fmt, ...) \ 2755 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) 2756 2757 #ifdef CONFIG_COMPAT 2758 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2759 unsigned long arg); 2760 #else 2761 #define i915_compat_ioctl NULL 2762 #endif 2763 extern const struct dev_pm_ops i915_pm_ops; 2764 2765 extern int i915_driver_load(struct pci_dev *pdev, 2766 const struct pci_device_id *ent); 2767 extern void i915_driver_unload(struct drm_device *dev); 2768 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); 2769 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); 2770 2771 extern void i915_reset(struct drm_i915_private *i915, 2772 unsigned int stalled_mask, 2773 const char *reason); 2774 extern int i915_reset_engine(struct intel_engine_cs *engine, 2775 const char *reason); 2776 2777 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); 2778 extern int intel_reset_guc(struct drm_i915_private *dev_priv); 2779 extern int intel_guc_reset_engine(struct intel_guc *guc, 2780 struct intel_engine_cs *engine); 2781 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); 2782 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); 2783 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2784 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2785 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2786 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2787 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2788 2789 int intel_engines_init_mmio(struct drm_i915_private *dev_priv); 2790 int intel_engines_init(struct drm_i915_private *dev_priv); 2791 2792 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv); 2793 2794 /* intel_hotplug.c */ 2795 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, 2796 u32 pin_mask, u32 long_mask); 2797 void intel_hpd_init(struct drm_i915_private *dev_priv); 2798 void intel_hpd_init_work(struct drm_i915_private *dev_priv); 2799 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2800 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, 2801 enum port port); 2802 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); 2803 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); 2804 2805 /* i915_irq.c */ 2806 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) 2807 { 2808 unsigned long delay; 2809 2810 if (unlikely(!i915_modparams.enable_hangcheck)) 2811 return; 2812 2813 /* Don't continually defer the hangcheck so that it is always run at 2814 * least once after work has been scheduled on any ring. Otherwise, 2815 * we will ignore a hung ring if a second ring is kept busy. 2816 */ 2817 2818 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); 2819 queue_delayed_work(system_long_wq, 2820 &dev_priv->gpu_error.hangcheck_work, delay); 2821 } 2822 2823 __printf(4, 5) 2824 void i915_handle_error(struct drm_i915_private *dev_priv, 2825 u32 engine_mask, 2826 unsigned long flags, 2827 const char *fmt, ...); 2828 #define I915_ERROR_CAPTURE BIT(0) 2829 2830 extern void intel_irq_init(struct drm_i915_private *dev_priv); 2831 extern void intel_irq_fini(struct drm_i915_private *dev_priv); 2832 int intel_irq_install(struct drm_i915_private *dev_priv); 2833 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 2834 2835 void i915_clear_error_registers(struct drm_i915_private *dev_priv); 2836 2837 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 2838 { 2839 return dev_priv->gvt; 2840 } 2841 2842 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 2843 { 2844 return dev_priv->vgpu.active; 2845 } 2846 2847 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 2848 enum pipe pipe); 2849 void 2850 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2851 u32 status_mask); 2852 2853 void 2854 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2855 u32 status_mask); 2856 2857 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2858 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2859 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 2860 uint32_t mask, 2861 uint32_t bits); 2862 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 2863 uint32_t interrupt_mask, 2864 uint32_t enabled_irq_mask); 2865 static inline void 2866 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) 2867 { 2868 ilk_update_display_irq(dev_priv, bits, bits); 2869 } 2870 static inline void 2871 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) 2872 { 2873 ilk_update_display_irq(dev_priv, bits, 0); 2874 } 2875 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 2876 enum pipe pipe, 2877 uint32_t interrupt_mask, 2878 uint32_t enabled_irq_mask); 2879 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, 2880 enum pipe pipe, uint32_t bits) 2881 { 2882 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); 2883 } 2884 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, 2885 enum pipe pipe, uint32_t bits) 2886 { 2887 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); 2888 } 2889 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 2890 uint32_t interrupt_mask, 2891 uint32_t enabled_irq_mask); 2892 static inline void 2893 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) 2894 { 2895 ibx_display_interrupt_update(dev_priv, bits, bits); 2896 } 2897 static inline void 2898 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) 2899 { 2900 ibx_display_interrupt_update(dev_priv, bits, 0); 2901 } 2902 2903 /* i915_gem.c */ 2904 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2905 struct drm_file *file_priv); 2906 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2907 struct drm_file *file_priv); 2908 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2909 struct drm_file *file_priv); 2910 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2911 struct drm_file *file_priv); 2912 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2913 struct drm_file *file_priv); 2914 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2915 struct drm_file *file_priv); 2916 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2917 struct drm_file *file_priv); 2918 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, 2919 struct drm_file *file_priv); 2920 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, 2921 struct drm_file *file_priv); 2922 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2923 struct drm_file *file_priv); 2924 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2925 struct drm_file *file); 2926 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2927 struct drm_file *file); 2928 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2929 struct drm_file *file_priv); 2930 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2931 struct drm_file *file_priv); 2932 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2933 struct drm_file *file_priv); 2934 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2935 struct drm_file *file_priv); 2936 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 2937 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 2938 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2939 struct drm_file *file); 2940 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2941 struct drm_file *file_priv); 2942 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2943 struct drm_file *file_priv); 2944 void i915_gem_sanitize(struct drm_i915_private *i915); 2945 int i915_gem_init_early(struct drm_i915_private *dev_priv); 2946 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 2947 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); 2948 int i915_gem_freeze(struct drm_i915_private *dev_priv); 2949 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 2950 2951 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); 2952 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2953 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2954 const struct drm_i915_gem_object_ops *ops); 2955 struct drm_i915_gem_object * 2956 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); 2957 struct drm_i915_gem_object * 2958 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, 2959 const void *data, size_t size); 2960 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); 2961 void i915_gem_free_object(struct drm_gem_object *obj); 2962 2963 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 2964 { 2965 if (!atomic_read(&i915->mm.free_count)) 2966 return; 2967 2968 /* A single pass should suffice to release all the freed objects (along 2969 * most call paths) , but be a little more paranoid in that freeing 2970 * the objects does take a little amount of time, during which the rcu 2971 * callbacks could have added new objects into the freed list, and 2972 * armed the work again. 2973 */ 2974 do { 2975 rcu_barrier(); 2976 } while (flush_work(&i915->mm.free_work)); 2977 } 2978 2979 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 2980 { 2981 /* 2982 * Similar to objects above (see i915_gem_drain_freed-objects), in 2983 * general we have workers that are armed by RCU and then rearm 2984 * themselves in their callbacks. To be paranoid, we need to 2985 * drain the workqueue a second time after waiting for the RCU 2986 * grace period so that we catch work queued via RCU from the first 2987 * pass. As neither drain_workqueue() nor flush_workqueue() report 2988 * a result, we make an assumption that we only don't require more 2989 * than 2 passes to catch all recursive RCU delayed work. 2990 * 2991 */ 2992 int pass = 2; 2993 do { 2994 rcu_barrier(); 2995 drain_workqueue(i915->wq); 2996 } while (--pass); 2997 } 2998 2999 struct i915_vma * __must_check 3000 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 3001 const struct i915_ggtt_view *view, 3002 u64 size, 3003 u64 alignment, 3004 u64 flags); 3005 3006 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 3007 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 3008 3009 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 3010 3011 static inline int __sg_page_count(const struct scatterlist *sg) 3012 { 3013 return sg->length >> PAGE_SHIFT; 3014 } 3015 3016 struct scatterlist * 3017 i915_gem_object_get_sg(struct drm_i915_gem_object *obj, 3018 unsigned int n, unsigned int *offset); 3019 3020 struct page * 3021 i915_gem_object_get_page(struct drm_i915_gem_object *obj, 3022 unsigned int n); 3023 3024 struct page * 3025 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, 3026 unsigned int n); 3027 3028 dma_addr_t 3029 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, 3030 unsigned long n); 3031 3032 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, 3033 struct sg_table *pages, 3034 unsigned int sg_page_sizes); 3035 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 3036 3037 static inline int __must_check 3038 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 3039 { 3040 might_lock(&obj->mm.lock); 3041 3042 if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) 3043 return 0; 3044 3045 return __i915_gem_object_get_pages(obj); 3046 } 3047 3048 static inline bool 3049 i915_gem_object_has_pages(struct drm_i915_gem_object *obj) 3050 { 3051 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages)); 3052 } 3053 3054 static inline void 3055 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 3056 { 3057 GEM_BUG_ON(!i915_gem_object_has_pages(obj)); 3058 3059 atomic_inc(&obj->mm.pages_pin_count); 3060 } 3061 3062 static inline bool 3063 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) 3064 { 3065 return atomic_read(&obj->mm.pages_pin_count); 3066 } 3067 3068 static inline void 3069 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 3070 { 3071 GEM_BUG_ON(!i915_gem_object_has_pages(obj)); 3072 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); 3073 3074 atomic_dec(&obj->mm.pages_pin_count); 3075 } 3076 3077 static inline void 3078 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 3079 { 3080 __i915_gem_object_unpin_pages(obj); 3081 } 3082 3083 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ 3084 I915_MM_NORMAL = 0, 3085 I915_MM_SHRINKER 3086 }; 3087 3088 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, 3089 enum i915_mm_subclass subclass); 3090 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); 3091 3092 enum i915_map_type { 3093 I915_MAP_WB = 0, 3094 I915_MAP_WC, 3095 #define I915_MAP_OVERRIDE BIT(31) 3096 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE, 3097 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE, 3098 }; 3099 3100 static inline enum i915_map_type 3101 i915_coherent_map_type(struct drm_i915_private *i915) 3102 { 3103 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 3104 } 3105 3106 /** 3107 * i915_gem_object_pin_map - return a contiguous mapping of the entire object 3108 * @obj: the object to map into kernel address space 3109 * @type: the type of mapping, used to select pgprot_t 3110 * 3111 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's 3112 * pages and then returns a contiguous mapping of the backing storage into 3113 * the kernel address space. Based on the @type of mapping, the PTE will be 3114 * set to either WriteBack or WriteCombine (via pgprot_t). 3115 * 3116 * The caller is responsible for calling i915_gem_object_unpin_map() when the 3117 * mapping is no longer required. 3118 * 3119 * Returns the pointer through which to access the mapped object, or an 3120 * ERR_PTR() on error. 3121 */ 3122 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, 3123 enum i915_map_type type); 3124 3125 /** 3126 * i915_gem_object_unpin_map - releases an earlier mapping 3127 * @obj: the object to unmap 3128 * 3129 * After pinning the object and mapping its pages, once you are finished 3130 * with your access, call i915_gem_object_unpin_map() to release the pin 3131 * upon the mapping. Once the pin count reaches zero, that mapping may be 3132 * removed. 3133 */ 3134 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) 3135 { 3136 i915_gem_object_unpin_pages(obj); 3137 } 3138 3139 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 3140 unsigned int *needs_clflush); 3141 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, 3142 unsigned int *needs_clflush); 3143 #define CLFLUSH_BEFORE BIT(0) 3144 #define CLFLUSH_AFTER BIT(1) 3145 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) 3146 3147 static inline void 3148 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) 3149 { 3150 i915_gem_object_unpin_pages(obj); 3151 } 3152 3153 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 3154 int i915_gem_dumb_create(struct drm_file *file_priv, 3155 struct drm_device *dev, 3156 struct drm_mode_create_dumb *args); 3157 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 3158 uint32_t handle, uint64_t *offset); 3159 int i915_gem_mmap_gtt_version(void); 3160 3161 void i915_gem_track_fb(struct drm_i915_gem_object *old, 3162 struct drm_i915_gem_object *new, 3163 unsigned frontbuffer_bits); 3164 3165 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 3166 3167 struct i915_request * 3168 i915_gem_find_active_request(struct intel_engine_cs *engine); 3169 3170 static inline bool i915_reset_backoff(struct i915_gpu_error *error) 3171 { 3172 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags)); 3173 } 3174 3175 static inline bool i915_reset_handoff(struct i915_gpu_error *error) 3176 { 3177 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags)); 3178 } 3179 3180 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 3181 { 3182 return unlikely(test_bit(I915_WEDGED, &error->flags)); 3183 } 3184 3185 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error) 3186 { 3187 return i915_reset_backoff(error) | i915_terminally_wedged(error); 3188 } 3189 3190 static inline u32 i915_reset_count(struct i915_gpu_error *error) 3191 { 3192 return READ_ONCE(error->reset_count); 3193 } 3194 3195 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 3196 struct intel_engine_cs *engine) 3197 { 3198 return READ_ONCE(error->reset_engine_count[engine->id]); 3199 } 3200 3201 struct i915_request * 3202 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine); 3203 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); 3204 void i915_gem_reset(struct drm_i915_private *dev_priv, 3205 unsigned int stalled_mask); 3206 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine); 3207 void i915_gem_reset_finish(struct drm_i915_private *dev_priv); 3208 void i915_gem_set_wedged(struct drm_i915_private *dev_priv); 3209 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv); 3210 void i915_gem_reset_engine(struct intel_engine_cs *engine, 3211 struct i915_request *request, 3212 bool stalled); 3213 3214 void i915_gem_init_mmio(struct drm_i915_private *i915); 3215 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 3216 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); 3217 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); 3218 void i915_gem_fini(struct drm_i915_private *dev_priv); 3219 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv); 3220 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, 3221 unsigned int flags, long timeout); 3222 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv); 3223 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 3224 void i915_gem_resume(struct drm_i915_private *dev_priv); 3225 vm_fault_t i915_gem_fault(struct vm_fault *vmf); 3226 int i915_gem_object_wait(struct drm_i915_gem_object *obj, 3227 unsigned int flags, 3228 long timeout, 3229 struct intel_rps_client *rps); 3230 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, 3231 unsigned int flags, 3232 const struct i915_sched_attr *attr); 3233 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX 3234 3235 int __must_check 3236 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); 3237 int __must_check 3238 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); 3239 int __must_check 3240 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 3241 struct i915_vma * __must_check 3242 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 3243 u32 alignment, 3244 const struct i915_ggtt_view *view, 3245 unsigned int flags); 3246 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); 3247 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 3248 int align); 3249 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 3250 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 3251 3252 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 3253 enum i915_cache_level cache_level); 3254 3255 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 3256 struct dma_buf *dma_buf); 3257 3258 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 3259 struct drm_gem_object *gem_obj, int flags); 3260 3261 static inline struct i915_hw_ppgtt * 3262 i915_vm_to_ppgtt(struct i915_address_space *vm) 3263 { 3264 return container_of(vm, struct i915_hw_ppgtt, vm); 3265 } 3266 3267 /* i915_gem_fence_reg.c */ 3268 struct drm_i915_fence_reg * 3269 i915_reserve_fence(struct drm_i915_private *dev_priv); 3270 void i915_unreserve_fence(struct drm_i915_fence_reg *fence); 3271 3272 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); 3273 void i915_gem_restore_fences(struct drm_i915_private *dev_priv); 3274 3275 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); 3276 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, 3277 struct sg_table *pages); 3278 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, 3279 struct sg_table *pages); 3280 3281 static inline struct i915_gem_context * 3282 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 3283 { 3284 return idr_find(&file_priv->context_idr, id); 3285 } 3286 3287 static inline struct i915_gem_context * 3288 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 3289 { 3290 struct i915_gem_context *ctx; 3291 3292 rcu_read_lock(); 3293 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 3294 if (ctx && !kref_get_unless_zero(&ctx->ref)) 3295 ctx = NULL; 3296 rcu_read_unlock(); 3297 3298 return ctx; 3299 } 3300 3301 int i915_perf_open_ioctl(struct drm_device *dev, void *data, 3302 struct drm_file *file); 3303 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, 3304 struct drm_file *file); 3305 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, 3306 struct drm_file *file); 3307 void i915_oa_init_reg_state(struct intel_engine_cs *engine, 3308 struct i915_gem_context *ctx, 3309 uint32_t *reg_state); 3310 3311 /* i915_gem_evict.c */ 3312 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 3313 u64 min_size, u64 alignment, 3314 unsigned cache_level, 3315 u64 start, u64 end, 3316 unsigned flags); 3317 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 3318 struct drm_mm_node *node, 3319 unsigned int flags); 3320 int i915_gem_evict_vm(struct i915_address_space *vm); 3321 3322 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv); 3323 3324 /* belongs in i915_gem_gtt.h */ 3325 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) 3326 { 3327 wmb(); 3328 if (INTEL_GEN(dev_priv) < 6) 3329 intel_gtt_chipset_flush(); 3330 } 3331 3332 /* i915_gem_stolen.c */ 3333 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, 3334 struct drm_mm_node *node, u64 size, 3335 unsigned alignment); 3336 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, 3337 struct drm_mm_node *node, u64 size, 3338 unsigned alignment, u64 start, 3339 u64 end); 3340 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, 3341 struct drm_mm_node *node); 3342 int i915_gem_init_stolen(struct drm_i915_private *dev_priv); 3343 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv); 3344 struct drm_i915_gem_object * 3345 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, 3346 resource_size_t size); 3347 struct drm_i915_gem_object * 3348 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, 3349 resource_size_t stolen_offset, 3350 resource_size_t gtt_offset, 3351 resource_size_t size); 3352 3353 /* i915_gem_internal.c */ 3354 struct drm_i915_gem_object * 3355 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 3356 phys_addr_t size); 3357 3358 /* i915_gem_shrinker.c */ 3359 unsigned long i915_gem_shrink(struct drm_i915_private *i915, 3360 unsigned long target, 3361 unsigned long *nr_scanned, 3362 unsigned flags); 3363 #define I915_SHRINK_PURGEABLE 0x1 3364 #define I915_SHRINK_UNBOUND 0x2 3365 #define I915_SHRINK_BOUND 0x4 3366 #define I915_SHRINK_ACTIVE 0x8 3367 #define I915_SHRINK_VMAPS 0x10 3368 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915); 3369 void i915_gem_shrinker_register(struct drm_i915_private *i915); 3370 void i915_gem_shrinker_unregister(struct drm_i915_private *i915); 3371 void i915_gem_shrinker_taints_mutex(struct mutex *mutex); 3372 3373 /* i915_gem_tiling.c */ 3374 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 3375 { 3376 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 3377 3378 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 3379 i915_gem_object_is_tiled(obj); 3380 } 3381 3382 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 3383 unsigned int tiling, unsigned int stride); 3384 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 3385 unsigned int tiling, unsigned int stride); 3386 3387 /* i915_debugfs.c */ 3388 #ifdef CONFIG_DEBUG_FS 3389 int i915_debugfs_register(struct drm_i915_private *dev_priv); 3390 int i915_debugfs_connector_add(struct drm_connector *connector); 3391 void intel_display_crc_init(struct drm_i915_private *dev_priv); 3392 #else 3393 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} 3394 static inline int i915_debugfs_connector_add(struct drm_connector *connector) 3395 { return 0; } 3396 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} 3397 #endif 3398 3399 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 3400 3401 /* i915_cmd_parser.c */ 3402 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 3403 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 3404 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 3405 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 3406 struct drm_i915_gem_object *batch_obj, 3407 struct drm_i915_gem_object *shadow_batch_obj, 3408 u32 batch_start_offset, 3409 u32 batch_len, 3410 bool is_master); 3411 3412 /* i915_perf.c */ 3413 extern void i915_perf_init(struct drm_i915_private *dev_priv); 3414 extern void i915_perf_fini(struct drm_i915_private *dev_priv); 3415 extern void i915_perf_register(struct drm_i915_private *dev_priv); 3416 extern void i915_perf_unregister(struct drm_i915_private *dev_priv); 3417 3418 /* i915_suspend.c */ 3419 extern int i915_save_state(struct drm_i915_private *dev_priv); 3420 extern int i915_restore_state(struct drm_i915_private *dev_priv); 3421 3422 /* i915_sysfs.c */ 3423 void i915_setup_sysfs(struct drm_i915_private *dev_priv); 3424 void i915_teardown_sysfs(struct drm_i915_private *dev_priv); 3425 3426 /* intel_lpe_audio.c */ 3427 int intel_lpe_audio_init(struct drm_i915_private *dev_priv); 3428 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); 3429 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); 3430 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, 3431 enum pipe pipe, enum port port, 3432 const void *eld, int ls_clock, bool dp_output); 3433 3434 /* intel_i2c.c */ 3435 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); 3436 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); 3437 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 3438 unsigned int pin); 3439 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter); 3440 3441 extern struct i2c_adapter * 3442 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); 3443 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 3444 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 3445 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 3446 { 3447 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 3448 } 3449 extern void intel_i2c_reset(struct drm_i915_private *dev_priv); 3450 3451 /* intel_bios.c */ 3452 void intel_bios_init(struct drm_i915_private *dev_priv); 3453 void intel_bios_cleanup(struct drm_i915_private *dev_priv); 3454 bool intel_bios_is_valid_vbt(const void *buf, size_t size); 3455 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); 3456 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); 3457 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); 3458 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); 3459 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); 3460 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); 3461 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, 3462 enum port port); 3463 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, 3464 enum port port); 3465 3466 /* intel_acpi.c */ 3467 #ifdef CONFIG_ACPI 3468 extern void intel_register_dsm_handler(void); 3469 extern void intel_unregister_dsm_handler(void); 3470 #else 3471 static inline void intel_register_dsm_handler(void) { return; } 3472 static inline void intel_unregister_dsm_handler(void) { return; } 3473 #endif /* CONFIG_ACPI */ 3474 3475 /* intel_device_info.c */ 3476 static inline struct intel_device_info * 3477 mkwrite_device_info(struct drm_i915_private *dev_priv) 3478 { 3479 return (struct intel_device_info *)&dev_priv->info; 3480 } 3481 3482 /* modesetting */ 3483 extern void intel_modeset_init_hw(struct drm_device *dev); 3484 extern int intel_modeset_init(struct drm_device *dev); 3485 extern void intel_modeset_cleanup(struct drm_device *dev); 3486 extern int intel_connector_register(struct drm_connector *); 3487 extern void intel_connector_unregister(struct drm_connector *); 3488 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, 3489 bool state); 3490 extern void intel_display_resume(struct drm_device *dev); 3491 extern void i915_redisable_vga(struct drm_i915_private *dev_priv); 3492 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); 3493 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); 3494 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 3495 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); 3496 extern void intel_rps_mark_interactive(struct drm_i915_private *i915, 3497 bool interactive); 3498 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 3499 bool enable); 3500 3501 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 3502 struct drm_file *file); 3503 3504 /* overlay */ 3505 extern struct intel_overlay_error_state * 3506 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); 3507 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 3508 struct intel_overlay_error_state *error); 3509 3510 extern struct intel_display_error_state * 3511 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 3512 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 3513 struct intel_display_error_state *error); 3514 3515 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3516 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox, 3517 u32 val, int fast_timeout_us, 3518 int slow_timeout_ms); 3519 #define sandybridge_pcode_write(dev_priv, mbox, val) \ 3520 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0) 3521 3522 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, 3523 u32 reply_mask, u32 reply, int timeout_base_ms); 3524 3525 /* intel_sideband.c */ 3526 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); 3527 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); 3528 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 3529 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); 3530 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); 3531 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 3532 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3533 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 3534 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3535 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 3536 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3537 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 3538 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 3539 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 3540 enum intel_sbi_destination destination); 3541 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 3542 enum intel_sbi_destination destination); 3543 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 3544 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3545 3546 /* intel_dpio_phy.c */ 3547 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 3548 enum dpio_phy *phy, enum dpio_channel *ch); 3549 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, 3550 enum port port, u32 margin, u32 scale, 3551 u32 enable, u32 deemphasis); 3552 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); 3553 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); 3554 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 3555 enum dpio_phy phy); 3556 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 3557 enum dpio_phy phy); 3558 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count); 3559 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 3560 uint8_t lane_lat_optim_mask); 3561 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); 3562 3563 void chv_set_phy_signal_level(struct intel_encoder *encoder, 3564 u32 deemph_reg_value, u32 margin_reg_value, 3565 bool uniq_trans_scale); 3566 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 3567 const struct intel_crtc_state *crtc_state, 3568 bool reset); 3569 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 3570 const struct intel_crtc_state *crtc_state); 3571 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 3572 const struct intel_crtc_state *crtc_state); 3573 void chv_phy_release_cl2_override(struct intel_encoder *encoder); 3574 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 3575 const struct intel_crtc_state *old_crtc_state); 3576 3577 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 3578 u32 demph_reg_value, u32 preemph_reg_value, 3579 u32 uniqtranscale_reg_value, u32 tx3_demph); 3580 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 3581 const struct intel_crtc_state *crtc_state); 3582 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 3583 const struct intel_crtc_state *crtc_state); 3584 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 3585 const struct intel_crtc_state *old_crtc_state); 3586 3587 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); 3588 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 3589 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, 3590 const i915_reg_t reg); 3591 3592 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); 3593 3594 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, 3595 const i915_reg_t reg) 3596 { 3597 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); 3598 } 3599 3600 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 3601 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 3602 3603 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 3604 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 3605 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 3606 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 3607 3608 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 3609 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 3610 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 3611 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 3612 3613 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 3614 * will be implemented using 2 32-bit writes in an arbitrary order with 3615 * an arbitrary delay between them. This can cause the hardware to 3616 * act upon the intermediate value, possibly leading to corruption and 3617 * machine death. For this reason we do not support I915_WRITE64, or 3618 * dev_priv->uncore.funcs.mmio_writeq. 3619 * 3620 * When reading a 64-bit value as two 32-bit values, the delay may cause 3621 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that 3622 * occasionally a 64-bit register does not actualy support a full readq 3623 * and must be read using two 32-bit reads. 3624 * 3625 * You have been warned. 3626 */ 3627 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 3628 3629 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 3630 u32 upper, lower, old_upper, loop = 0; \ 3631 upper = I915_READ(upper_reg); \ 3632 do { \ 3633 old_upper = upper; \ 3634 lower = I915_READ(lower_reg); \ 3635 upper = I915_READ(upper_reg); \ 3636 } while (upper != old_upper && loop++ < 2); \ 3637 (u64)upper << 32 | lower; }) 3638 3639 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 3640 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 3641 3642 #define __raw_read(x, s) \ 3643 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \ 3644 i915_reg_t reg) \ 3645 { \ 3646 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ 3647 } 3648 3649 #define __raw_write(x, s) \ 3650 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \ 3651 i915_reg_t reg, uint##x##_t val) \ 3652 { \ 3653 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ 3654 } 3655 __raw_read(8, b) 3656 __raw_read(16, w) 3657 __raw_read(32, l) 3658 __raw_read(64, q) 3659 3660 __raw_write(8, b) 3661 __raw_write(16, w) 3662 __raw_write(32, l) 3663 __raw_write(64, q) 3664 3665 #undef __raw_read 3666 #undef __raw_write 3667 3668 /* These are untraced mmio-accessors that are only valid to be used inside 3669 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 3670 * controlled. 3671 * 3672 * Think twice, and think again, before using these. 3673 * 3674 * As an example, these accessors can possibly be used between: 3675 * 3676 * spin_lock_irq(&dev_priv->uncore.lock); 3677 * intel_uncore_forcewake_get__locked(); 3678 * 3679 * and 3680 * 3681 * intel_uncore_forcewake_put__locked(); 3682 * spin_unlock_irq(&dev_priv->uncore.lock); 3683 * 3684 * 3685 * Note: some registers may not need forcewake held, so 3686 * intel_uncore_forcewake_{get,put} can be omitted, see 3687 * intel_uncore_forcewake_for_reg(). 3688 * 3689 * Certain architectures will die if the same cacheline is concurrently accessed 3690 * by different clients (e.g. on Ivybridge). Access to registers should 3691 * therefore generally be serialised, by either the dev_priv->uncore.lock or 3692 * a more localised lock guarding all access to that bank of registers. 3693 */ 3694 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) 3695 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) 3696 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) 3697 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) 3698 3699 /* "Broadcast RGB" property */ 3700 #define INTEL_BROADCAST_RGB_AUTO 0 3701 #define INTEL_BROADCAST_RGB_FULL 1 3702 #define INTEL_BROADCAST_RGB_LIMITED 2 3703 3704 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) 3705 { 3706 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3707 return VLV_VGACNTRL; 3708 else if (INTEL_GEN(dev_priv) >= 5) 3709 return CPU_VGACNTRL; 3710 else 3711 return VGACNTRL; 3712 } 3713 3714 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 3715 { 3716 unsigned long j = msecs_to_jiffies(m); 3717 3718 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3719 } 3720 3721 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 3722 { 3723 /* nsecs_to_jiffies64() does not guard against overflow */ 3724 if (NSEC_PER_SEC % HZ && 3725 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 3726 return MAX_JIFFY_OFFSET; 3727 3728 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 3729 } 3730 3731 /* 3732 * If you need to wait X milliseconds between events A and B, but event B 3733 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 3734 * when event A happened, then just before event B you call this function and 3735 * pass the timestamp as the first argument, and X as the second argument. 3736 */ 3737 static inline void 3738 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 3739 { 3740 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 3741 3742 /* 3743 * Don't re-read the value of "jiffies" every time since it may change 3744 * behind our back and break the math. 3745 */ 3746 tmp_jiffies = jiffies; 3747 target_jiffies = timestamp_jiffies + 3748 msecs_to_jiffies_timeout(to_wait_ms); 3749 3750 if (time_after(target_jiffies, tmp_jiffies)) { 3751 remaining_jiffies = target_jiffies - tmp_jiffies; 3752 while (remaining_jiffies) 3753 remaining_jiffies = 3754 schedule_timeout_uninterruptible(remaining_jiffies); 3755 } 3756 } 3757 3758 static inline bool 3759 __i915_request_irq_complete(const struct i915_request *rq) 3760 { 3761 struct intel_engine_cs *engine = rq->engine; 3762 u32 seqno; 3763 3764 /* Note that the engine may have wrapped around the seqno, and 3765 * so our request->global_seqno will be ahead of the hardware, 3766 * even though it completed the request before wrapping. We catch 3767 * this by kicking all the waiters before resetting the seqno 3768 * in hardware, and also signal the fence. 3769 */ 3770 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) 3771 return true; 3772 3773 /* The request was dequeued before we were awoken. We check after 3774 * inspecting the hw to confirm that this was the same request 3775 * that generated the HWS update. The memory barriers within 3776 * the request execution are sufficient to ensure that a check 3777 * after reading the value from hw matches this request. 3778 */ 3779 seqno = i915_request_global_seqno(rq); 3780 if (!seqno) 3781 return false; 3782 3783 /* Before we do the heavier coherent read of the seqno, 3784 * check the value (hopefully) in the CPU cacheline. 3785 */ 3786 if (__i915_request_completed(rq, seqno)) 3787 return true; 3788 3789 /* Ensure our read of the seqno is coherent so that we 3790 * do not "miss an interrupt" (i.e. if this is the last 3791 * request and the seqno write from the GPU is not visible 3792 * by the time the interrupt fires, we will see that the 3793 * request is incomplete and go back to sleep awaiting 3794 * another interrupt that will never come.) 3795 * 3796 * Strictly, we only need to do this once after an interrupt, 3797 * but it is easier and safer to do it every time the waiter 3798 * is woken. 3799 */ 3800 if (engine->irq_seqno_barrier && 3801 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { 3802 struct intel_breadcrumbs *b = &engine->breadcrumbs; 3803 3804 /* The ordering of irq_posted versus applying the barrier 3805 * is crucial. The clearing of the current irq_posted must 3806 * be visible before we perform the barrier operation, 3807 * such that if a subsequent interrupt arrives, irq_posted 3808 * is reasserted and our task rewoken (which causes us to 3809 * do another __i915_request_irq_complete() immediately 3810 * and reapply the barrier). Conversely, if the clear 3811 * occurs after the barrier, then an interrupt that arrived 3812 * whilst we waited on the barrier would not trigger a 3813 * barrier on the next pass, and the read may not see the 3814 * seqno update. 3815 */ 3816 engine->irq_seqno_barrier(engine); 3817 3818 /* If we consume the irq, but we are no longer the bottom-half, 3819 * the real bottom-half may not have serialised their own 3820 * seqno check with the irq-barrier (i.e. may have inspected 3821 * the seqno before we believe it coherent since they see 3822 * irq_posted == false but we are still running). 3823 */ 3824 spin_lock_irq(&b->irq_lock); 3825 if (b->irq_wait && b->irq_wait->tsk != current) 3826 /* Note that if the bottom-half is changed as we 3827 * are sending the wake-up, the new bottom-half will 3828 * be woken by whomever made the change. We only have 3829 * to worry about when we steal the irq-posted for 3830 * ourself. 3831 */ 3832 wake_up_process(b->irq_wait->tsk); 3833 spin_unlock_irq(&b->irq_lock); 3834 3835 if (__i915_request_completed(rq, seqno)) 3836 return true; 3837 } 3838 3839 return false; 3840 } 3841 3842 void i915_memcpy_init_early(struct drm_i915_private *dev_priv); 3843 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); 3844 3845 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment, 3846 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot 3847 * perform the operation. To check beforehand, pass in the parameters to 3848 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits, 3849 * you only need to pass in the minor offsets, page-aligned pointers are 3850 * always valid. 3851 * 3852 * For just checking for SSE4.1, in the foreknowledge that the future use 3853 * will be correctly aligned, just use i915_has_memcpy_from_wc(). 3854 */ 3855 #define i915_can_memcpy_from_wc(dst, src, len) \ 3856 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0) 3857 3858 #define i915_has_memcpy_from_wc() \ 3859 i915_memcpy_from_wc(NULL, NULL, 0) 3860 3861 /* i915_mm.c */ 3862 int remap_io_mapping(struct vm_area_struct *vma, 3863 unsigned long addr, unsigned long pfn, unsigned long size, 3864 struct io_mapping *iomap); 3865 3866 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 3867 { 3868 if (INTEL_GEN(i915) >= 10) 3869 return CNL_HWS_CSB_WRITE_INDEX; 3870 else 3871 return I915_HWS_CSB_WRITE_INDEX; 3872 } 3873 3874 #endif 3875