xref: /openbmc/linux/drivers/gpu/drm/i915/i915_drv.h (revision 4800cd83)
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29 
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32 
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 
40 /* General customization:
41  */
42 
43 #define DRIVER_AUTHOR		"Tungsten Graphics, Inc."
44 
45 #define DRIVER_NAME		"i915"
46 #define DRIVER_DESC		"Intel Graphics"
47 #define DRIVER_DATE		"20080730"
48 
49 enum pipe {
50 	PIPE_A = 0,
51 	PIPE_B,
52 };
53 
54 enum plane {
55 	PLANE_A = 0,
56 	PLANE_B,
57 };
58 
59 #define I915_NUM_PIPE	2
60 
61 #define I915_GEM_GPU_DOMAINS	(~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
62 
63 /* Interface history:
64  *
65  * 1.1: Original.
66  * 1.2: Add Power Management
67  * 1.3: Add vblank support
68  * 1.4: Fix cmdbuffer path, add heap destroy
69  * 1.5: Add vblank pipe configuration
70  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71  *      - Support vertical blank on secondary display pipe
72  */
73 #define DRIVER_MAJOR		1
74 #define DRIVER_MINOR		6
75 #define DRIVER_PATCHLEVEL	0
76 
77 #define WATCH_COHERENCY	0
78 #define WATCH_EXEC	0
79 #define WATCH_RELOC	0
80 #define WATCH_LISTS	0
81 #define WATCH_PWRITE	0
82 
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
87 
88 struct drm_i915_gem_phys_object {
89 	int id;
90 	struct page **page_list;
91 	drm_dma_handle_t *handle;
92 	struct drm_i915_gem_object *cur_obj;
93 };
94 
95 struct mem_block {
96 	struct mem_block *next;
97 	struct mem_block *prev;
98 	int start;
99 	int size;
100 	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
101 };
102 
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
107 
108 struct intel_opregion {
109 	struct opregion_header *header;
110 	struct opregion_acpi *acpi;
111 	struct opregion_swsci *swsci;
112 	struct opregion_asle *asle;
113 	void *vbt;
114 };
115 #define OPREGION_SIZE            (8*1024)
116 
117 struct intel_overlay;
118 struct intel_overlay_error_state;
119 
120 struct drm_i915_master_private {
121 	drm_local_map_t *sarea;
122 	struct _drm_i915_sarea *sarea_priv;
123 };
124 #define I915_FENCE_REG_NONE -1
125 
126 struct drm_i915_fence_reg {
127 	struct list_head lru_list;
128 	struct drm_i915_gem_object *obj;
129 	uint32_t setup_seqno;
130 };
131 
132 struct sdvo_device_mapping {
133 	u8 initialized;
134 	u8 dvo_port;
135 	u8 slave_addr;
136 	u8 dvo_wiring;
137 	u8 i2c_pin;
138 	u8 i2c_speed;
139 	u8 ddc_pin;
140 };
141 
142 struct intel_display_error_state;
143 
144 struct drm_i915_error_state {
145 	u32 eir;
146 	u32 pgtbl_er;
147 	u32 pipeastat;
148 	u32 pipebstat;
149 	u32 ipeir;
150 	u32 ipehr;
151 	u32 instdone;
152 	u32 acthd;
153 	u32 error; /* gen6+ */
154 	u32 bcs_acthd; /* gen6+ blt engine */
155 	u32 bcs_ipehr;
156 	u32 bcs_ipeir;
157 	u32 bcs_instdone;
158 	u32 bcs_seqno;
159 	u32 vcs_acthd; /* gen6+ bsd engine */
160 	u32 vcs_ipehr;
161 	u32 vcs_ipeir;
162 	u32 vcs_instdone;
163 	u32 vcs_seqno;
164 	u32 instpm;
165 	u32 instps;
166 	u32 instdone1;
167 	u32 seqno;
168 	u64 bbaddr;
169 	u64 fence[16];
170 	struct timeval time;
171 	struct drm_i915_error_object {
172 		int page_count;
173 		u32 gtt_offset;
174 		u32 *pages[0];
175 	} *ringbuffer, *batchbuffer[I915_NUM_RINGS];
176 	struct drm_i915_error_buffer {
177 		u32 size;
178 		u32 name;
179 		u32 seqno;
180 		u32 gtt_offset;
181 		u32 read_domains;
182 		u32 write_domain;
183 		s32 fence_reg:5;
184 		s32 pinned:2;
185 		u32 tiling:2;
186 		u32 dirty:1;
187 		u32 purgeable:1;
188 		u32 ring:4;
189 		u32 agp_type:1;
190 	} *active_bo, *pinned_bo;
191 	u32 active_bo_count, pinned_bo_count;
192 	struct intel_overlay_error_state *overlay;
193 	struct intel_display_error_state *display;
194 };
195 
196 struct drm_i915_display_funcs {
197 	void (*dpms)(struct drm_crtc *crtc, int mode);
198 	bool (*fbc_enabled)(struct drm_device *dev);
199 	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
200 	void (*disable_fbc)(struct drm_device *dev);
201 	int (*get_display_clock_speed)(struct drm_device *dev);
202 	int (*get_fifo_size)(struct drm_device *dev, int plane);
203 	void (*update_wm)(struct drm_device *dev, int planea_clock,
204 			  int planeb_clock, int sr_hdisplay, int sr_htotal,
205 			  int pixel_size);
206 	/* clock updates for mode set */
207 	/* cursor updates */
208 	/* render clock increase/decrease */
209 	/* display clock increase/decrease */
210 	/* pll clock increase/decrease */
211 	/* clock gating init */
212 };
213 
214 struct intel_device_info {
215 	u8 gen;
216 	u8 is_mobile : 1;
217 	u8 is_i85x : 1;
218 	u8 is_i915g : 1;
219 	u8 is_i945gm : 1;
220 	u8 is_g33 : 1;
221 	u8 need_gfx_hws : 1;
222 	u8 is_g4x : 1;
223 	u8 is_pineview : 1;
224 	u8 is_broadwater : 1;
225 	u8 is_crestline : 1;
226 	u8 has_fbc : 1;
227 	u8 has_pipe_cxsr : 1;
228 	u8 has_hotplug : 1;
229 	u8 cursor_needs_physical : 1;
230 	u8 has_overlay : 1;
231 	u8 overlay_needs_physical : 1;
232 	u8 supports_tv : 1;
233 	u8 has_bsd_ring : 1;
234 	u8 has_blt_ring : 1;
235 };
236 
237 enum no_fbc_reason {
238 	FBC_NO_OUTPUT, /* no outputs enabled to compress */
239 	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
240 	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
241 	FBC_MODE_TOO_LARGE, /* mode too large for compression */
242 	FBC_BAD_PLANE, /* fbc not supported on plane */
243 	FBC_NOT_TILED, /* buffer not tiled */
244 	FBC_MULTIPLE_PIPES, /* more than one pipe active */
245 };
246 
247 enum intel_pch {
248 	PCH_IBX,	/* Ibexpeak PCH */
249 	PCH_CPT,	/* Cougarpoint PCH */
250 };
251 
252 #define QUIRK_PIPEA_FORCE (1<<0)
253 
254 struct intel_fbdev;
255 
256 typedef struct drm_i915_private {
257 	struct drm_device *dev;
258 
259 	const struct intel_device_info *info;
260 
261 	int has_gem;
262 	int relative_constants_mode;
263 
264 	void __iomem *regs;
265 
266 	struct intel_gmbus {
267 		struct i2c_adapter adapter;
268 		struct i2c_adapter *force_bit;
269 		u32 reg0;
270 	} *gmbus;
271 
272 	struct pci_dev *bridge_dev;
273 	struct intel_ring_buffer ring[I915_NUM_RINGS];
274 	uint32_t next_seqno;
275 
276 	drm_dma_handle_t *status_page_dmah;
277 	dma_addr_t dma_status_page;
278 	uint32_t counter;
279 	drm_local_map_t hws_map;
280 	struct drm_i915_gem_object *pwrctx;
281 	struct drm_i915_gem_object *renderctx;
282 
283 	struct resource mch_res;
284 
285 	unsigned int cpp;
286 	int back_offset;
287 	int front_offset;
288 	int current_page;
289 	int page_flipping;
290 
291 	atomic_t irq_received;
292 	u32 trace_irq_seqno;
293 
294 	/* protects the irq masks */
295 	spinlock_t irq_lock;
296 	/** Cached value of IMR to avoid reads in updating the bitfield */
297 	u32 pipestat[2];
298 	u32 irq_mask;
299 	u32 gt_irq_mask;
300 	u32 pch_irq_mask;
301 
302 	u32 hotplug_supported_mask;
303 	struct work_struct hotplug_work;
304 
305 	int tex_lru_log_granularity;
306 	int allow_batchbuffer;
307 	struct mem_block *agp_heap;
308 	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
309 	int vblank_pipe;
310 	int num_pipe;
311 
312 	/* For hangcheck timer */
313 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
314 	struct timer_list hangcheck_timer;
315 	int hangcheck_count;
316 	uint32_t last_acthd;
317 	uint32_t last_instdone;
318 	uint32_t last_instdone1;
319 
320 	unsigned long cfb_size;
321 	unsigned long cfb_pitch;
322 	unsigned long cfb_offset;
323 	int cfb_fence;
324 	int cfb_plane;
325 	int cfb_y;
326 
327 	int irq_enabled;
328 
329 	struct intel_opregion opregion;
330 
331 	/* overlay */
332 	struct intel_overlay *overlay;
333 
334 	/* LVDS info */
335 	int backlight_level;  /* restore backlight to this value */
336 	bool backlight_enabled;
337 	struct drm_display_mode *panel_fixed_mode;
338 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
339 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
340 
341 	/* Feature bits from the VBIOS */
342 	unsigned int int_tv_support:1;
343 	unsigned int lvds_dither:1;
344 	unsigned int lvds_vbt:1;
345 	unsigned int int_crt_support:1;
346 	unsigned int lvds_use_ssc:1;
347 	int lvds_ssc_freq;
348 	struct {
349 		int rate;
350 		int lanes;
351 		int preemphasis;
352 		int vswing;
353 
354 		bool initialized;
355 		bool support;
356 		int bpp;
357 		struct edp_power_seq pps;
358 	} edp;
359 	bool no_aux_handshake;
360 
361 	struct notifier_block lid_notifier;
362 
363 	int crt_ddc_pin;
364 	struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
365 	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
366 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
367 
368 	unsigned int fsb_freq, mem_freq, is_ddr3;
369 
370 	spinlock_t error_lock;
371 	struct drm_i915_error_state *first_error;
372 	struct work_struct error_work;
373 	struct completion error_completion;
374 	struct workqueue_struct *wq;
375 
376 	/* Display functions */
377 	struct drm_i915_display_funcs display;
378 
379 	/* PCH chipset type */
380 	enum intel_pch pch_type;
381 
382 	unsigned long quirks;
383 
384 	/* Register state */
385 	bool modeset_on_lid;
386 	u8 saveLBB;
387 	u32 saveDSPACNTR;
388 	u32 saveDSPBCNTR;
389 	u32 saveDSPARB;
390 	u32 saveHWS;
391 	u32 savePIPEACONF;
392 	u32 savePIPEBCONF;
393 	u32 savePIPEASRC;
394 	u32 savePIPEBSRC;
395 	u32 saveFPA0;
396 	u32 saveFPA1;
397 	u32 saveDPLL_A;
398 	u32 saveDPLL_A_MD;
399 	u32 saveHTOTAL_A;
400 	u32 saveHBLANK_A;
401 	u32 saveHSYNC_A;
402 	u32 saveVTOTAL_A;
403 	u32 saveVBLANK_A;
404 	u32 saveVSYNC_A;
405 	u32 saveBCLRPAT_A;
406 	u32 saveTRANSACONF;
407 	u32 saveTRANS_HTOTAL_A;
408 	u32 saveTRANS_HBLANK_A;
409 	u32 saveTRANS_HSYNC_A;
410 	u32 saveTRANS_VTOTAL_A;
411 	u32 saveTRANS_VBLANK_A;
412 	u32 saveTRANS_VSYNC_A;
413 	u32 savePIPEASTAT;
414 	u32 saveDSPASTRIDE;
415 	u32 saveDSPASIZE;
416 	u32 saveDSPAPOS;
417 	u32 saveDSPAADDR;
418 	u32 saveDSPASURF;
419 	u32 saveDSPATILEOFF;
420 	u32 savePFIT_PGM_RATIOS;
421 	u32 saveBLC_HIST_CTL;
422 	u32 saveBLC_PWM_CTL;
423 	u32 saveBLC_PWM_CTL2;
424 	u32 saveBLC_CPU_PWM_CTL;
425 	u32 saveBLC_CPU_PWM_CTL2;
426 	u32 saveFPB0;
427 	u32 saveFPB1;
428 	u32 saveDPLL_B;
429 	u32 saveDPLL_B_MD;
430 	u32 saveHTOTAL_B;
431 	u32 saveHBLANK_B;
432 	u32 saveHSYNC_B;
433 	u32 saveVTOTAL_B;
434 	u32 saveVBLANK_B;
435 	u32 saveVSYNC_B;
436 	u32 saveBCLRPAT_B;
437 	u32 saveTRANSBCONF;
438 	u32 saveTRANS_HTOTAL_B;
439 	u32 saveTRANS_HBLANK_B;
440 	u32 saveTRANS_HSYNC_B;
441 	u32 saveTRANS_VTOTAL_B;
442 	u32 saveTRANS_VBLANK_B;
443 	u32 saveTRANS_VSYNC_B;
444 	u32 savePIPEBSTAT;
445 	u32 saveDSPBSTRIDE;
446 	u32 saveDSPBSIZE;
447 	u32 saveDSPBPOS;
448 	u32 saveDSPBADDR;
449 	u32 saveDSPBSURF;
450 	u32 saveDSPBTILEOFF;
451 	u32 saveVGA0;
452 	u32 saveVGA1;
453 	u32 saveVGA_PD;
454 	u32 saveVGACNTRL;
455 	u32 saveADPA;
456 	u32 saveLVDS;
457 	u32 savePP_ON_DELAYS;
458 	u32 savePP_OFF_DELAYS;
459 	u32 saveDVOA;
460 	u32 saveDVOB;
461 	u32 saveDVOC;
462 	u32 savePP_ON;
463 	u32 savePP_OFF;
464 	u32 savePP_CONTROL;
465 	u32 savePP_DIVISOR;
466 	u32 savePFIT_CONTROL;
467 	u32 save_palette_a[256];
468 	u32 save_palette_b[256];
469 	u32 saveDPFC_CB_BASE;
470 	u32 saveFBC_CFB_BASE;
471 	u32 saveFBC_LL_BASE;
472 	u32 saveFBC_CONTROL;
473 	u32 saveFBC_CONTROL2;
474 	u32 saveIER;
475 	u32 saveIIR;
476 	u32 saveIMR;
477 	u32 saveDEIER;
478 	u32 saveDEIMR;
479 	u32 saveGTIER;
480 	u32 saveGTIMR;
481 	u32 saveFDI_RXA_IMR;
482 	u32 saveFDI_RXB_IMR;
483 	u32 saveCACHE_MODE_0;
484 	u32 saveMI_ARB_STATE;
485 	u32 saveSWF0[16];
486 	u32 saveSWF1[16];
487 	u32 saveSWF2[3];
488 	u8 saveMSR;
489 	u8 saveSR[8];
490 	u8 saveGR[25];
491 	u8 saveAR_INDEX;
492 	u8 saveAR[21];
493 	u8 saveDACMASK;
494 	u8 saveCR[37];
495 	uint64_t saveFENCE[16];
496 	u32 saveCURACNTR;
497 	u32 saveCURAPOS;
498 	u32 saveCURABASE;
499 	u32 saveCURBCNTR;
500 	u32 saveCURBPOS;
501 	u32 saveCURBBASE;
502 	u32 saveCURSIZE;
503 	u32 saveDP_B;
504 	u32 saveDP_C;
505 	u32 saveDP_D;
506 	u32 savePIPEA_GMCH_DATA_M;
507 	u32 savePIPEB_GMCH_DATA_M;
508 	u32 savePIPEA_GMCH_DATA_N;
509 	u32 savePIPEB_GMCH_DATA_N;
510 	u32 savePIPEA_DP_LINK_M;
511 	u32 savePIPEB_DP_LINK_M;
512 	u32 savePIPEA_DP_LINK_N;
513 	u32 savePIPEB_DP_LINK_N;
514 	u32 saveFDI_RXA_CTL;
515 	u32 saveFDI_TXA_CTL;
516 	u32 saveFDI_RXB_CTL;
517 	u32 saveFDI_TXB_CTL;
518 	u32 savePFA_CTL_1;
519 	u32 savePFB_CTL_1;
520 	u32 savePFA_WIN_SZ;
521 	u32 savePFB_WIN_SZ;
522 	u32 savePFA_WIN_POS;
523 	u32 savePFB_WIN_POS;
524 	u32 savePCH_DREF_CONTROL;
525 	u32 saveDISP_ARB_CTL;
526 	u32 savePIPEA_DATA_M1;
527 	u32 savePIPEA_DATA_N1;
528 	u32 savePIPEA_LINK_M1;
529 	u32 savePIPEA_LINK_N1;
530 	u32 savePIPEB_DATA_M1;
531 	u32 savePIPEB_DATA_N1;
532 	u32 savePIPEB_LINK_M1;
533 	u32 savePIPEB_LINK_N1;
534 	u32 saveMCHBAR_RENDER_STANDBY;
535 
536 	struct {
537 		/** Bridge to intel-gtt-ko */
538 		const struct intel_gtt *gtt;
539 		/** Memory allocator for GTT stolen memory */
540 		struct drm_mm stolen;
541 		/** Memory allocator for GTT */
542 		struct drm_mm gtt_space;
543 		/** List of all objects in gtt_space. Used to restore gtt
544 		 * mappings on resume */
545 		struct list_head gtt_list;
546 
547 		/** Usable portion of the GTT for GEM */
548 		unsigned long gtt_start;
549 		unsigned long gtt_mappable_end;
550 		unsigned long gtt_end;
551 
552 		struct io_mapping *gtt_mapping;
553 		int gtt_mtrr;
554 
555 		struct shrinker inactive_shrinker;
556 
557 		/**
558 		 * List of objects currently involved in rendering.
559 		 *
560 		 * Includes buffers having the contents of their GPU caches
561 		 * flushed, not necessarily primitives.  last_rendering_seqno
562 		 * represents when the rendering involved will be completed.
563 		 *
564 		 * A reference is held on the buffer while on this list.
565 		 */
566 		struct list_head active_list;
567 
568 		/**
569 		 * List of objects which are not in the ringbuffer but which
570 		 * still have a write_domain which needs to be flushed before
571 		 * unbinding.
572 		 *
573 		 * last_rendering_seqno is 0 while an object is in this list.
574 		 *
575 		 * A reference is held on the buffer while on this list.
576 		 */
577 		struct list_head flushing_list;
578 
579 		/**
580 		 * LRU list of objects which are not in the ringbuffer and
581 		 * are ready to unbind, but are still in the GTT.
582 		 *
583 		 * last_rendering_seqno is 0 while an object is in this list.
584 		 *
585 		 * A reference is not held on the buffer while on this list,
586 		 * as merely being GTT-bound shouldn't prevent its being
587 		 * freed, and we'll pull it off the list in the free path.
588 		 */
589 		struct list_head inactive_list;
590 
591 		/**
592 		 * LRU list of objects which are not in the ringbuffer but
593 		 * are still pinned in the GTT.
594 		 */
595 		struct list_head pinned_list;
596 
597 		/** LRU list of objects with fence regs on them. */
598 		struct list_head fence_list;
599 
600 		/**
601 		 * List of objects currently pending being freed.
602 		 *
603 		 * These objects are no longer in use, but due to a signal
604 		 * we were prevented from freeing them at the appointed time.
605 		 */
606 		struct list_head deferred_free_list;
607 
608 		/**
609 		 * We leave the user IRQ off as much as possible,
610 		 * but this means that requests will finish and never
611 		 * be retired once the system goes idle. Set a timer to
612 		 * fire periodically while the ring is running. When it
613 		 * fires, go retire requests.
614 		 */
615 		struct delayed_work retire_work;
616 
617 		/**
618 		 * Flag if the X Server, and thus DRM, is not currently in
619 		 * control of the device.
620 		 *
621 		 * This is set between LeaveVT and EnterVT.  It needs to be
622 		 * replaced with a semaphore.  It also needs to be
623 		 * transitioned away from for kernel modesetting.
624 		 */
625 		int suspended;
626 
627 		/**
628 		 * Flag if the hardware appears to be wedged.
629 		 *
630 		 * This is set when attempts to idle the device timeout.
631 		 * It prevents command submission from occuring and makes
632 		 * every pending request fail
633 		 */
634 		atomic_t wedged;
635 
636 		/** Bit 6 swizzling required for X tiling */
637 		uint32_t bit_6_swizzle_x;
638 		/** Bit 6 swizzling required for Y tiling */
639 		uint32_t bit_6_swizzle_y;
640 
641 		/* storage for physical objects */
642 		struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
643 
644 		/* accounting, useful for userland debugging */
645 		size_t gtt_total;
646 		size_t mappable_gtt_total;
647 		size_t object_memory;
648 		u32 object_count;
649 	} mm;
650 	struct sdvo_device_mapping sdvo_mappings[2];
651 	/* indicate whether the LVDS_BORDER should be enabled or not */
652 	unsigned int lvds_border_bits;
653 	/* Panel fitter placement and size for Ironlake+ */
654 	u32 pch_pf_pos, pch_pf_size;
655 
656 	struct drm_crtc *plane_to_crtc_mapping[2];
657 	struct drm_crtc *pipe_to_crtc_mapping[2];
658 	wait_queue_head_t pending_flip_queue;
659 	bool flip_pending_is_done;
660 
661 	/* Reclocking support */
662 	bool render_reclock_avail;
663 	bool lvds_downclock_avail;
664 	/* indicates the reduced downclock for LVDS*/
665 	int lvds_downclock;
666 	struct work_struct idle_work;
667 	struct timer_list idle_timer;
668 	bool busy;
669 	u16 orig_clock;
670 	int child_dev_num;
671 	struct child_device_config *child_dev;
672 	struct drm_connector *int_lvds_connector;
673 
674 	bool mchbar_need_disable;
675 
676 	u8 cur_delay;
677 	u8 min_delay;
678 	u8 max_delay;
679 	u8 fmax;
680 	u8 fstart;
681 
682 	u64 last_count1;
683 	unsigned long last_time1;
684 	u64 last_count2;
685 	struct timespec last_time2;
686 	unsigned long gfx_power;
687 	int c_m;
688 	int r_t;
689 	u8 corr;
690 	spinlock_t *mchdev_lock;
691 
692 	enum no_fbc_reason no_fbc_reason;
693 
694 	struct drm_mm_node *compressed_fb;
695 	struct drm_mm_node *compressed_llb;
696 
697 	unsigned long last_gpu_reset;
698 
699 	/* list of fbdev register on this device */
700 	struct intel_fbdev *fbdev;
701 } drm_i915_private_t;
702 
703 struct drm_i915_gem_object {
704 	struct drm_gem_object base;
705 
706 	/** Current space allocated to this object in the GTT, if any. */
707 	struct drm_mm_node *gtt_space;
708 	struct list_head gtt_list;
709 
710 	/** This object's place on the active/flushing/inactive lists */
711 	struct list_head ring_list;
712 	struct list_head mm_list;
713 	/** This object's place on GPU write list */
714 	struct list_head gpu_write_list;
715 	/** This object's place in the batchbuffer or on the eviction list */
716 	struct list_head exec_list;
717 
718 	/**
719 	 * This is set if the object is on the active or flushing lists
720 	 * (has pending rendering), and is not set if it's on inactive (ready
721 	 * to be unbound).
722 	 */
723 	unsigned int active : 1;
724 
725 	/**
726 	 * This is set if the object has been written to since last bound
727 	 * to the GTT
728 	 */
729 	unsigned int dirty : 1;
730 
731 	/**
732 	 * This is set if the object has been written to since the last
733 	 * GPU flush.
734 	 */
735 	unsigned int pending_gpu_write : 1;
736 
737 	/**
738 	 * Fence register bits (if any) for this object.  Will be set
739 	 * as needed when mapped into the GTT.
740 	 * Protected by dev->struct_mutex.
741 	 *
742 	 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
743 	 */
744 	signed int fence_reg : 5;
745 
746 	/**
747 	 * Advice: are the backing pages purgeable?
748 	 */
749 	unsigned int madv : 2;
750 
751 	/**
752 	 * Current tiling mode for the object.
753 	 */
754 	unsigned int tiling_mode : 2;
755 	unsigned int tiling_changed : 1;
756 
757 	/** How many users have pinned this object in GTT space. The following
758 	 * users can each hold at most one reference: pwrite/pread, pin_ioctl
759 	 * (via user_pin_count), execbuffer (objects are not allowed multiple
760 	 * times for the same batchbuffer), and the framebuffer code. When
761 	 * switching/pageflipping, the framebuffer code has at most two buffers
762 	 * pinned per crtc.
763 	 *
764 	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
765 	 * bits with absolutely no headroom. So use 4 bits. */
766 	unsigned int pin_count : 4;
767 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
768 
769 	/**
770 	 * Is the object at the current location in the gtt mappable and
771 	 * fenceable? Used to avoid costly recalculations.
772 	 */
773 	unsigned int map_and_fenceable : 1;
774 
775 	/**
776 	 * Whether the current gtt mapping needs to be mappable (and isn't just
777 	 * mappable by accident). Track pin and fault separate for a more
778 	 * accurate mappable working set.
779 	 */
780 	unsigned int fault_mappable : 1;
781 	unsigned int pin_mappable : 1;
782 
783 	/*
784 	 * Is the GPU currently using a fence to access this buffer,
785 	 */
786 	unsigned int pending_fenced_gpu_access:1;
787 	unsigned int fenced_gpu_access:1;
788 
789 	struct page **pages;
790 
791 	/**
792 	 * DMAR support
793 	 */
794 	struct scatterlist *sg_list;
795 	int num_sg;
796 
797 	/**
798 	 * Used for performing relocations during execbuffer insertion.
799 	 */
800 	struct hlist_node exec_node;
801 	unsigned long exec_handle;
802 	struct drm_i915_gem_exec_object2 *exec_entry;
803 
804 	/**
805 	 * Current offset of the object in GTT space.
806 	 *
807 	 * This is the same as gtt_space->start
808 	 */
809 	uint32_t gtt_offset;
810 
811 	/** Breadcrumb of last rendering to the buffer. */
812 	uint32_t last_rendering_seqno;
813 	struct intel_ring_buffer *ring;
814 
815 	/** Breadcrumb of last fenced GPU access to the buffer. */
816 	uint32_t last_fenced_seqno;
817 	struct intel_ring_buffer *last_fenced_ring;
818 
819 	/** Current tiling stride for the object, if it's tiled. */
820 	uint32_t stride;
821 
822 	/** Record of address bit 17 of each page at last unbind. */
823 	unsigned long *bit_17;
824 
825 	/** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
826 	uint32_t agp_type;
827 
828 	/**
829 	 * If present, while GEM_DOMAIN_CPU is in the read domain this array
830 	 * flags which individual pages are valid.
831 	 */
832 	uint8_t *page_cpu_valid;
833 
834 	/** User space pin count and filp owning the pin */
835 	uint32_t user_pin_count;
836 	struct drm_file *pin_filp;
837 
838 	/** for phy allocated objects */
839 	struct drm_i915_gem_phys_object *phys_obj;
840 
841 	/**
842 	 * Number of crtcs where this object is currently the fb, but
843 	 * will be page flipped away on the next vblank.  When it
844 	 * reaches 0, dev_priv->pending_flip_queue will be woken up.
845 	 */
846 	atomic_t pending_flip;
847 };
848 
849 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
850 
851 /**
852  * Request queue structure.
853  *
854  * The request queue allows us to note sequence numbers that have been emitted
855  * and may be associated with active buffers to be retired.
856  *
857  * By keeping this list, we can avoid having to do questionable
858  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
859  * an emission time with seqnos for tracking how far ahead of the GPU we are.
860  */
861 struct drm_i915_gem_request {
862 	/** On Which ring this request was generated */
863 	struct intel_ring_buffer *ring;
864 
865 	/** GEM sequence number associated with this request. */
866 	uint32_t seqno;
867 
868 	/** Time at which this request was emitted, in jiffies. */
869 	unsigned long emitted_jiffies;
870 
871 	/** global list entry for this request */
872 	struct list_head list;
873 
874 	struct drm_i915_file_private *file_priv;
875 	/** file_priv list entry for this request */
876 	struct list_head client_list;
877 };
878 
879 struct drm_i915_file_private {
880 	struct {
881 		struct spinlock lock;
882 		struct list_head request_list;
883 	} mm;
884 };
885 
886 enum intel_chip_family {
887 	CHIP_I8XX = 0x01,
888 	CHIP_I9XX = 0x02,
889 	CHIP_I915 = 0x04,
890 	CHIP_I965 = 0x08,
891 };
892 
893 #define INTEL_INFO(dev)	(((struct drm_i915_private *) (dev)->dev_private)->info)
894 
895 #define IS_I830(dev)		((dev)->pci_device == 0x3577)
896 #define IS_845G(dev)		((dev)->pci_device == 0x2562)
897 #define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
898 #define IS_I865G(dev)		((dev)->pci_device == 0x2572)
899 #define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
900 #define IS_I915GM(dev)		((dev)->pci_device == 0x2592)
901 #define IS_I945G(dev)		((dev)->pci_device == 0x2772)
902 #define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
903 #define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
904 #define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
905 #define IS_GM45(dev)		((dev)->pci_device == 0x2A42)
906 #define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
907 #define IS_PINEVIEW_G(dev)	((dev)->pci_device == 0xa001)
908 #define IS_PINEVIEW_M(dev)	((dev)->pci_device == 0xa011)
909 #define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
910 #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
911 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
912 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
913 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
914 
915 #define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
916 #define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
917 #define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
918 #define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
919 #define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
920 
921 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
922 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
923 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
924 
925 #define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
926 #define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
927 
928 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
929  * rows, which changed the alignment requirements and fence programming.
930  */
931 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
932 						      IS_I915GM(dev)))
933 #define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))
934 #define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
935 #define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
936 #define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))
937 #define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
938 #define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
939 /* dsparb controlled by hw only */
940 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
941 
942 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
943 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
944 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
945 
946 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
947 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
948 
949 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
950 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
951 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
952 
953 #include "i915_trace.h"
954 
955 extern struct drm_ioctl_desc i915_ioctls[];
956 extern int i915_max_ioctl;
957 extern unsigned int i915_fbpercrtc;
958 extern unsigned int i915_powersave;
959 extern unsigned int i915_semaphores;
960 extern unsigned int i915_lvds_downclock;
961 extern unsigned int i915_panel_use_ssc;
962 extern unsigned int i915_enable_rc6;
963 
964 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
965 extern int i915_resume(struct drm_device *dev);
966 extern void i915_save_display(struct drm_device *dev);
967 extern void i915_restore_display(struct drm_device *dev);
968 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
969 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
970 
971 				/* i915_dma.c */
972 extern void i915_kernel_lost_context(struct drm_device * dev);
973 extern int i915_driver_load(struct drm_device *, unsigned long flags);
974 extern int i915_driver_unload(struct drm_device *);
975 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
976 extern void i915_driver_lastclose(struct drm_device * dev);
977 extern void i915_driver_preclose(struct drm_device *dev,
978 				 struct drm_file *file_priv);
979 extern void i915_driver_postclose(struct drm_device *dev,
980 				  struct drm_file *file_priv);
981 extern int i915_driver_device_is_agp(struct drm_device * dev);
982 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
983 			      unsigned long arg);
984 extern int i915_emit_box(struct drm_device *dev,
985 			 struct drm_clip_rect *box,
986 			 int DR1, int DR4);
987 extern int i915_reset(struct drm_device *dev, u8 flags);
988 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
989 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
990 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
991 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
992 
993 
994 /* i915_irq.c */
995 void i915_hangcheck_elapsed(unsigned long data);
996 void i915_handle_error(struct drm_device *dev, bool wedged);
997 extern int i915_irq_emit(struct drm_device *dev, void *data,
998 			 struct drm_file *file_priv);
999 extern int i915_irq_wait(struct drm_device *dev, void *data,
1000 			 struct drm_file *file_priv);
1001 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
1002 extern void i915_enable_interrupt (struct drm_device *dev);
1003 
1004 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1005 extern void i915_driver_irq_preinstall(struct drm_device * dev);
1006 extern int i915_driver_irq_postinstall(struct drm_device *dev);
1007 extern void i915_driver_irq_uninstall(struct drm_device * dev);
1008 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1009 				struct drm_file *file_priv);
1010 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1011 				struct drm_file *file_priv);
1012 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1013 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1014 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1015 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1016 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1017 			    struct drm_file *file_priv);
1018 
1019 void
1020 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1021 
1022 void
1023 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1024 
1025 void intel_enable_asle (struct drm_device *dev);
1026 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1027 			      int *max_error,
1028 			      struct timeval *vblank_time,
1029 			      unsigned flags);
1030 
1031 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1032 			     int *vpos, int *hpos);
1033 
1034 #ifdef CONFIG_DEBUG_FS
1035 extern void i915_destroy_error_state(struct drm_device *dev);
1036 #else
1037 #define i915_destroy_error_state(x)
1038 #endif
1039 
1040 
1041 /* i915_mem.c */
1042 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1043 			  struct drm_file *file_priv);
1044 extern int i915_mem_free(struct drm_device *dev, void *data,
1045 			 struct drm_file *file_priv);
1046 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1047 			      struct drm_file *file_priv);
1048 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1049 				 struct drm_file *file_priv);
1050 extern void i915_mem_takedown(struct mem_block **heap);
1051 extern void i915_mem_release(struct drm_device * dev,
1052 			     struct drm_file *file_priv, struct mem_block *heap);
1053 /* i915_gem.c */
1054 int i915_gem_check_is_wedged(struct drm_device *dev);
1055 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1056 			struct drm_file *file_priv);
1057 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1058 			  struct drm_file *file_priv);
1059 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1060 			 struct drm_file *file_priv);
1061 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1062 			  struct drm_file *file_priv);
1063 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1064 			struct drm_file *file_priv);
1065 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1066 			struct drm_file *file_priv);
1067 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1068 			      struct drm_file *file_priv);
1069 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1070 			     struct drm_file *file_priv);
1071 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1072 			struct drm_file *file_priv);
1073 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1074 			 struct drm_file *file_priv);
1075 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1076 		       struct drm_file *file_priv);
1077 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1078 			 struct drm_file *file_priv);
1079 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1080 			struct drm_file *file_priv);
1081 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1082 			    struct drm_file *file_priv);
1083 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1084 			   struct drm_file *file_priv);
1085 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1086 			   struct drm_file *file_priv);
1087 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1088 			   struct drm_file *file_priv);
1089 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1090 			struct drm_file *file_priv);
1091 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1092 			struct drm_file *file_priv);
1093 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1094 				struct drm_file *file_priv);
1095 void i915_gem_load(struct drm_device *dev);
1096 int i915_gem_init_object(struct drm_gem_object *obj);
1097 int __must_check i915_gem_flush_ring(struct drm_device *dev,
1098 				     struct intel_ring_buffer *ring,
1099 				     uint32_t invalidate_domains,
1100 				     uint32_t flush_domains);
1101 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1102 						  size_t size);
1103 void i915_gem_free_object(struct drm_gem_object *obj);
1104 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1105 				     uint32_t alignment,
1106 				     bool map_and_fenceable);
1107 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1108 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1109 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1110 void i915_gem_lastclose(struct drm_device *dev);
1111 
1112 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1113 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1114 						bool interruptible);
1115 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1116 				    struct intel_ring_buffer *ring,
1117 				    u32 seqno);
1118 
1119 /**
1120  * Returns true if seq1 is later than seq2.
1121  */
1122 static inline bool
1123 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1124 {
1125 	return (int32_t)(seq1 - seq2) >= 0;
1126 }
1127 
1128 static inline u32
1129 i915_gem_next_request_seqno(struct drm_device *dev,
1130 			    struct intel_ring_buffer *ring)
1131 {
1132 	drm_i915_private_t *dev_priv = dev->dev_private;
1133 	return ring->outstanding_lazy_request = dev_priv->next_seqno;
1134 }
1135 
1136 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1137 					   struct intel_ring_buffer *pipelined,
1138 					   bool interruptible);
1139 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1140 
1141 void i915_gem_retire_requests(struct drm_device *dev);
1142 void i915_gem_reset(struct drm_device *dev);
1143 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1144 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1145 					    uint32_t read_domains,
1146 					    uint32_t write_domain);
1147 int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1148 					   bool interruptible);
1149 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1150 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1151 void i915_gem_do_init(struct drm_device *dev,
1152 		      unsigned long start,
1153 		      unsigned long mappable_end,
1154 		      unsigned long end);
1155 int __must_check i915_gpu_idle(struct drm_device *dev);
1156 int __must_check i915_gem_idle(struct drm_device *dev);
1157 int __must_check i915_add_request(struct drm_device *dev,
1158 				  struct drm_file *file_priv,
1159 				  struct drm_i915_gem_request *request,
1160 				  struct intel_ring_buffer *ring);
1161 int __must_check i915_do_wait_request(struct drm_device *dev,
1162 				      uint32_t seqno,
1163 				      bool interruptible,
1164 				      struct intel_ring_buffer *ring);
1165 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1166 int __must_check
1167 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1168 				  bool write);
1169 int __must_check
1170 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1171 				     struct intel_ring_buffer *pipelined);
1172 int i915_gem_attach_phys_object(struct drm_device *dev,
1173 				struct drm_i915_gem_object *obj,
1174 				int id,
1175 				int align);
1176 void i915_gem_detach_phys_object(struct drm_device *dev,
1177 				 struct drm_i915_gem_object *obj);
1178 void i915_gem_free_all_phys_object(struct drm_device *dev);
1179 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1180 
1181 uint32_t
1182 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
1183 
1184 /* i915_gem_gtt.c */
1185 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1186 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1187 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1188 
1189 /* i915_gem_evict.c */
1190 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1191 					  unsigned alignment, bool mappable);
1192 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1193 					   bool purgeable_only);
1194 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1195 					 bool purgeable_only);
1196 
1197 /* i915_gem_tiling.c */
1198 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1199 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1200 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1201 
1202 /* i915_gem_debug.c */
1203 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1204 			  const char *where, uint32_t mark);
1205 #if WATCH_LISTS
1206 int i915_verify_lists(struct drm_device *dev);
1207 #else
1208 #define i915_verify_lists(dev) 0
1209 #endif
1210 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1211 				     int handle);
1212 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1213 			  const char *where, uint32_t mark);
1214 
1215 /* i915_debugfs.c */
1216 int i915_debugfs_init(struct drm_minor *minor);
1217 void i915_debugfs_cleanup(struct drm_minor *minor);
1218 
1219 /* i915_suspend.c */
1220 extern int i915_save_state(struct drm_device *dev);
1221 extern int i915_restore_state(struct drm_device *dev);
1222 
1223 /* i915_suspend.c */
1224 extern int i915_save_state(struct drm_device *dev);
1225 extern int i915_restore_state(struct drm_device *dev);
1226 
1227 /* intel_i2c.c */
1228 extern int intel_setup_gmbus(struct drm_device *dev);
1229 extern void intel_teardown_gmbus(struct drm_device *dev);
1230 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1231 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1232 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1233 {
1234 	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1235 }
1236 extern void intel_i2c_reset(struct drm_device *dev);
1237 
1238 /* intel_opregion.c */
1239 extern int intel_opregion_setup(struct drm_device *dev);
1240 #ifdef CONFIG_ACPI
1241 extern void intel_opregion_init(struct drm_device *dev);
1242 extern void intel_opregion_fini(struct drm_device *dev);
1243 extern void intel_opregion_asle_intr(struct drm_device *dev);
1244 extern void intel_opregion_gse_intr(struct drm_device *dev);
1245 extern void intel_opregion_enable_asle(struct drm_device *dev);
1246 #else
1247 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1248 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1249 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1250 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1251 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1252 #endif
1253 
1254 /* intel_acpi.c */
1255 #ifdef CONFIG_ACPI
1256 extern void intel_register_dsm_handler(void);
1257 extern void intel_unregister_dsm_handler(void);
1258 #else
1259 static inline void intel_register_dsm_handler(void) { return; }
1260 static inline void intel_unregister_dsm_handler(void) { return; }
1261 #endif /* CONFIG_ACPI */
1262 
1263 /* modesetting */
1264 extern void intel_modeset_init(struct drm_device *dev);
1265 extern void intel_modeset_cleanup(struct drm_device *dev);
1266 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1267 extern void i8xx_disable_fbc(struct drm_device *dev);
1268 extern void g4x_disable_fbc(struct drm_device *dev);
1269 extern void ironlake_disable_fbc(struct drm_device *dev);
1270 extern void intel_disable_fbc(struct drm_device *dev);
1271 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1272 extern bool intel_fbc_enabled(struct drm_device *dev);
1273 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1274 extern void ironlake_enable_rc6(struct drm_device *dev);
1275 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1276 extern void intel_detect_pch (struct drm_device *dev);
1277 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1278 
1279 /* overlay */
1280 #ifdef CONFIG_DEBUG_FS
1281 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1282 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1283 
1284 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1285 extern void intel_display_print_error_state(struct seq_file *m,
1286 					    struct drm_device *dev,
1287 					    struct intel_display_error_state *error);
1288 #endif
1289 
1290 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1291 
1292 #define BEGIN_LP_RING(n) \
1293 	intel_ring_begin(LP_RING(dev_priv), (n))
1294 
1295 #define OUT_RING(x) \
1296 	intel_ring_emit(LP_RING(dev_priv), x)
1297 
1298 #define ADVANCE_LP_RING() \
1299 	intel_ring_advance(LP_RING(dev_priv))
1300 
1301 /**
1302  * Lock test for when it's just for synchronization of ring access.
1303  *
1304  * In that case, we don't need to do it when GEM is initialized as nobody else
1305  * has access to the ring.
1306  */
1307 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {			\
1308 	if (LP_RING(dev->dev_private)->obj == NULL)			\
1309 		LOCK_TEST_WITH_RETURN(dev, file);			\
1310 } while (0)
1311 
1312 
1313 #define __i915_read(x, y) \
1314 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1315 	u##x val = read##y(dev_priv->regs + reg); \
1316 	trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1317 	return val; \
1318 }
1319 __i915_read(8, b)
1320 __i915_read(16, w)
1321 __i915_read(32, l)
1322 __i915_read(64, q)
1323 #undef __i915_read
1324 
1325 #define __i915_write(x, y) \
1326 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1327 	trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1328 	write##y(val, dev_priv->regs + reg); \
1329 }
1330 __i915_write(8, b)
1331 __i915_write(16, w)
1332 __i915_write(32, l)
1333 __i915_write(64, q)
1334 #undef __i915_write
1335 
1336 #define I915_READ8(reg)		i915_read8(dev_priv, (reg))
1337 #define I915_WRITE8(reg, val)	i915_write8(dev_priv, (reg), (val))
1338 
1339 #define I915_READ16(reg)	i915_read16(dev_priv, (reg))
1340 #define I915_WRITE16(reg, val)	i915_write16(dev_priv, (reg), (val))
1341 #define I915_READ16_NOTRACE(reg)	readw(dev_priv->regs + (reg))
1342 #define I915_WRITE16_NOTRACE(reg, val)	writew(val, dev_priv->regs + (reg))
1343 
1344 #define I915_READ(reg)		i915_read32(dev_priv, (reg))
1345 #define I915_WRITE(reg, val)	i915_write32(dev_priv, (reg), (val))
1346 #define I915_READ_NOTRACE(reg)		readl(dev_priv->regs + (reg))
1347 #define I915_WRITE_NOTRACE(reg, val)	writel(val, dev_priv->regs + (reg))
1348 
1349 #define I915_WRITE64(reg, val)	i915_write64(dev_priv, (reg), (val))
1350 #define I915_READ64(reg)	i915_read64(dev_priv, (reg))
1351 
1352 #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
1353 #define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
1354 
1355 
1356 /* On SNB platform, before reading ring registers forcewake bit
1357  * must be set to prevent GT core from power down and stale values being
1358  * returned.
1359  */
1360 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1361 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1362 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1363 
1364 static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
1365 {
1366 	u32 val;
1367 
1368 	if (dev_priv->info->gen >= 6) {
1369 		__gen6_gt_force_wake_get(dev_priv);
1370 		val = I915_READ(reg);
1371 		__gen6_gt_force_wake_put(dev_priv);
1372 	} else
1373 		val = I915_READ(reg);
1374 
1375 	return val;
1376 }
1377 
1378 static inline void i915_gt_write(struct drm_i915_private *dev_priv,
1379 				u32 reg, u32 val)
1380 {
1381 	if (dev_priv->info->gen >= 6)
1382 		__gen6_gt_wait_for_fifo(dev_priv);
1383 	I915_WRITE(reg, val);
1384 }
1385 
1386 static inline void
1387 i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1388 {
1389        /* Trace down the write operation before the real write */
1390        trace_i915_reg_rw('W', reg, val, len);
1391        switch (len) {
1392        case 8:
1393                writeq(val, dev_priv->regs + reg);
1394                break;
1395        case 4:
1396                writel(val, dev_priv->regs + reg);
1397                break;
1398        case 2:
1399                writew(val, dev_priv->regs + reg);
1400                break;
1401        case 1:
1402                writeb(val, dev_priv->regs + reg);
1403                break;
1404        }
1405 }
1406 
1407 /**
1408  * Reads a dword out of the status page, which is written to from the command
1409  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1410  * MI_STORE_DATA_IMM.
1411  *
1412  * The following dwords have a reserved meaning:
1413  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1414  * 0x04: ring 0 head pointer
1415  * 0x05: ring 1 head pointer (915-class)
1416  * 0x06: ring 2 head pointer (915-class)
1417  * 0x10-0x1b: Context status DWords (GM45)
1418  * 0x1f: Last written status offset. (GM45)
1419  *
1420  * The area from dword 0x20 to 0x3ff is available for driver usage.
1421  */
1422 #define READ_HWSP(dev_priv, reg)  (((volatile u32 *)\
1423 			(LP_RING(dev_priv)->status_page.page_addr))[reg])
1424 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1425 #define I915_GEM_HWS_INDEX		0x20
1426 #define I915_BREADCRUMB_INDEX		0x21
1427 
1428 #endif
1429