1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <asm/hypervisor.h> 37 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/backlight.h> 42 #include <linux/hash.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/mm_types.h> 46 #include <linux/perf_event.h> 47 #include <linux/pm_qos.h> 48 #include <linux/dma-resv.h> 49 #include <linux/shmem_fs.h> 50 #include <linux/stackdepot.h> 51 #include <linux/xarray.h> 52 53 #include <drm/intel-gtt.h> 54 #include <drm/drm_gem.h> 55 #include <drm/drm_auth.h> 56 #include <drm/drm_cache.h> 57 #include <drm/drm_util.h> 58 #include <drm/drm_dsc.h> 59 #include <drm/drm_atomic.h> 60 #include <drm/drm_connector.h> 61 #include <drm/i915_mei_hdcp_interface.h> 62 #include <drm/ttm/ttm_device.h> 63 64 #include "i915_params.h" 65 #include "i915_reg.h" 66 #include "i915_utils.h" 67 68 #include "display/intel_bios.h" 69 #include "display/intel_display.h" 70 #include "display/intel_display_power.h" 71 #include "display/intel_dmc.h" 72 #include "display/intel_dpll_mgr.h" 73 #include "display/intel_dsb.h" 74 #include "display/intel_frontbuffer.h" 75 #include "display/intel_global_state.h" 76 #include "display/intel_gmbus.h" 77 #include "display/intel_opregion.h" 78 79 #include "gem/i915_gem_context_types.h" 80 #include "gem/i915_gem_shrinker.h" 81 #include "gem/i915_gem_stolen.h" 82 #include "gem/i915_gem_lmem.h" 83 84 #include "gt/intel_engine.h" 85 #include "gt/intel_gt_types.h" 86 #include "gt/intel_region_lmem.h" 87 #include "gt/intel_workarounds.h" 88 #include "gt/uc/intel_uc.h" 89 90 #include "intel_device_info.h" 91 #include "intel_memory_region.h" 92 #include "intel_pch.h" 93 #include "intel_runtime_pm.h" 94 #include "intel_step.h" 95 #include "intel_uncore.h" 96 #include "intel_wakeref.h" 97 #include "intel_wopcm.h" 98 99 #include "i915_gem.h" 100 #include "i915_gem_gtt.h" 101 #include "i915_gpu_error.h" 102 #include "i915_perf_types.h" 103 #include "i915_request.h" 104 #include "i915_scheduler.h" 105 #include "gt/intel_timeline.h" 106 #include "i915_vma.h" 107 #include "i915_irq.h" 108 109 110 /* General customization: 111 */ 112 113 #define DRIVER_NAME "i915" 114 #define DRIVER_DESC "Intel Graphics" 115 #define DRIVER_DATE "20201103" 116 #define DRIVER_TIMESTAMP 1604406085 117 118 struct drm_i915_gem_object; 119 120 enum hpd_pin { 121 HPD_NONE = 0, 122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 123 HPD_CRT, 124 HPD_SDVO_B, 125 HPD_SDVO_C, 126 HPD_PORT_A, 127 HPD_PORT_B, 128 HPD_PORT_C, 129 HPD_PORT_D, 130 HPD_PORT_E, 131 HPD_PORT_TC1, 132 HPD_PORT_TC2, 133 HPD_PORT_TC3, 134 HPD_PORT_TC4, 135 HPD_PORT_TC5, 136 HPD_PORT_TC6, 137 138 HPD_NUM_PINS 139 }; 140 141 #define for_each_hpd_pin(__pin) \ 142 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 143 144 /* Threshold == 5 for long IRQs, 50 for short */ 145 #define HPD_STORM_DEFAULT_THRESHOLD 50 146 147 struct i915_hotplug { 148 struct delayed_work hotplug_work; 149 150 const u32 *hpd, *pch_hpd; 151 152 struct { 153 unsigned long last_jiffies; 154 int count; 155 enum { 156 HPD_ENABLED = 0, 157 HPD_DISABLED = 1, 158 HPD_MARK_DISABLED = 2 159 } state; 160 } stats[HPD_NUM_PINS]; 161 u32 event_bits; 162 u32 retry_bits; 163 struct delayed_work reenable_work; 164 165 u32 long_port_mask; 166 u32 short_port_mask; 167 struct work_struct dig_port_work; 168 169 struct work_struct poll_init_work; 170 bool poll_enabled; 171 172 unsigned int hpd_storm_threshold; 173 /* Whether or not to count short HPD IRQs in HPD storms */ 174 u8 hpd_short_storm_enabled; 175 176 /* 177 * if we get a HPD irq from DP and a HPD irq from non-DP 178 * the non-DP HPD could block the workqueue on a mode config 179 * mutex getting, that userspace may have taken. However 180 * userspace is waiting on the DP workqueue to run which is 181 * blocked behind the non-DP one. 182 */ 183 struct workqueue_struct *dp_wq; 184 }; 185 186 #define I915_GEM_GPU_DOMAINS \ 187 (I915_GEM_DOMAIN_RENDER | \ 188 I915_GEM_DOMAIN_SAMPLER | \ 189 I915_GEM_DOMAIN_COMMAND | \ 190 I915_GEM_DOMAIN_INSTRUCTION | \ 191 I915_GEM_DOMAIN_VERTEX) 192 193 struct drm_i915_private; 194 struct i915_mm_struct; 195 struct i915_mmu_object; 196 197 struct drm_i915_file_private { 198 struct drm_i915_private *dev_priv; 199 200 union { 201 struct drm_file *file; 202 struct rcu_head rcu; 203 }; 204 205 /** @proto_context_lock: Guards all struct i915_gem_proto_context 206 * operations 207 * 208 * This not only guards @proto_context_xa, but is always held 209 * whenever we manipulate any struct i915_gem_proto_context, 210 * including finalizing it on first actual use of the GEM context. 211 * 212 * See i915_gem_proto_context. 213 */ 214 struct mutex proto_context_lock; 215 216 /** @proto_context_xa: xarray of struct i915_gem_proto_context 217 * 218 * Historically, the context uAPI allowed for two methods of 219 * setting context parameters: SET_CONTEXT_PARAM and 220 * CONTEXT_CREATE_EXT_SETPARAM. The former is allowed to be called 221 * at any time while the later happens as part of 222 * GEM_CONTEXT_CREATE. Everything settable via one was settable 223 * via the other. While some params are fairly simple and setting 224 * them on a live context is harmless such as the context priority, 225 * others are far trickier such as the VM or the set of engines. 226 * In order to swap out the VM, for instance, we have to delay 227 * until all current in-flight work is complete, swap in the new 228 * VM, and then continue. This leads to a plethora of potential 229 * race conditions we'd really rather avoid. 230 * 231 * We have since disallowed setting these more complex parameters 232 * on active contexts. This works by delaying the creation of the 233 * actual context until after the client is done configuring it 234 * with SET_CONTEXT_PARAM. From the perspective of the client, it 235 * has the same u32 context ID the whole time. From the 236 * perspective of i915, however, it's a struct i915_gem_proto_context 237 * right up until the point where we attempt to do something which 238 * the proto-context can't handle. Then the struct i915_gem_context 239 * gets created. 240 * 241 * This is accomplished via a little xarray dance. When 242 * GEM_CONTEXT_CREATE is called, we create a struct 243 * i915_gem_proto_context, reserve a slot in @context_xa but leave 244 * it NULL, and place the proto-context in the corresponding slot 245 * in @proto_context_xa. Then, in i915_gem_context_lookup(), we 246 * first check @context_xa. If it's there, we return the struct 247 * i915_gem_context and we're done. If it's not, we look in 248 * @proto_context_xa and, if we find it there, we create the actual 249 * context and kill the proto-context. 250 * 251 * In order for this dance to work properly, everything which ever 252 * touches a struct i915_gem_proto_context is guarded by 253 * @proto_context_lock, including context creation. Yes, this 254 * means context creation now takes a giant global lock but it 255 * can't really be helped and that should never be on any driver's 256 * fast-path anyway. 257 */ 258 struct xarray proto_context_xa; 259 260 /** @context_xa: xarray of fully created i915_gem_context 261 * 262 * Write access to this xarray is guarded by @proto_context_lock. 263 * Otherwise, writers may race with finalize_create_context_locked(). 264 * 265 * See @proto_context_xa. 266 */ 267 struct xarray context_xa; 268 struct xarray vm_xa; 269 270 unsigned int bsd_engine; 271 272 /* 273 * Every context ban increments per client ban score. Also 274 * hangs in short succession increments ban score. If ban threshold 275 * is reached, client is considered banned and submitting more work 276 * will fail. This is a stop gap measure to limit the badly behaving 277 * clients access to gpu. Note that unbannable contexts never increment 278 * the client ban score. 279 */ 280 #define I915_CLIENT_SCORE_HANG_FAST 1 281 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 282 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 283 #define I915_CLIENT_SCORE_BANNED 9 284 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 285 atomic_t ban_score; 286 unsigned long hang_timestamp; 287 }; 288 289 /* Interface history: 290 * 291 * 1.1: Original. 292 * 1.2: Add Power Management 293 * 1.3: Add vblank support 294 * 1.4: Fix cmdbuffer path, add heap destroy 295 * 1.5: Add vblank pipe configuration 296 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 297 * - Support vertical blank on secondary display pipe 298 */ 299 #define DRIVER_MAJOR 1 300 #define DRIVER_MINOR 6 301 #define DRIVER_PATCHLEVEL 0 302 303 struct intel_overlay; 304 struct intel_overlay_error_state; 305 306 struct sdvo_device_mapping { 307 u8 initialized; 308 u8 dvo_port; 309 u8 slave_addr; 310 u8 dvo_wiring; 311 u8 i2c_pin; 312 u8 ddc_pin; 313 }; 314 315 struct intel_connector; 316 struct intel_encoder; 317 struct intel_atomic_state; 318 struct intel_cdclk_config; 319 struct intel_cdclk_state; 320 struct intel_cdclk_vals; 321 struct intel_initial_plane_config; 322 struct intel_crtc; 323 struct intel_limit; 324 struct dpll; 325 326 /* functions used internal in intel_pm.c */ 327 struct drm_i915_clock_gating_funcs { 328 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 329 }; 330 331 /* functions used for watermark calcs for display. */ 332 struct drm_i915_wm_disp_funcs { 333 /* update_wm is for legacy wm management */ 334 void (*update_wm)(struct drm_i915_private *dev_priv); 335 int (*compute_pipe_wm)(struct intel_atomic_state *state, 336 struct intel_crtc *crtc); 337 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 338 struct intel_crtc *crtc); 339 void (*initial_watermarks)(struct intel_atomic_state *state, 340 struct intel_crtc *crtc); 341 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 342 struct intel_crtc *crtc); 343 void (*optimize_watermarks)(struct intel_atomic_state *state, 344 struct intel_crtc *crtc); 345 int (*compute_global_watermarks)(struct intel_atomic_state *state); 346 }; 347 348 struct intel_color_funcs { 349 int (*color_check)(struct intel_crtc_state *crtc_state); 350 /* 351 * Program double buffered color management registers during 352 * vblank evasion. The registers should then latch during the 353 * next vblank start, alongside any other double buffered registers 354 * involved with the same commit. 355 */ 356 void (*color_commit)(const struct intel_crtc_state *crtc_state); 357 /* 358 * Load LUTs (and other single buffered color management 359 * registers). Will (hopefully) be called during the vblank 360 * following the latching of any double buffered registers 361 * involved with the same commit. 362 */ 363 void (*load_luts)(const struct intel_crtc_state *crtc_state); 364 void (*read_luts)(struct intel_crtc_state *crtc_state); 365 }; 366 367 struct intel_audio_funcs { 368 void (*audio_codec_enable)(struct intel_encoder *encoder, 369 const struct intel_crtc_state *crtc_state, 370 const struct drm_connector_state *conn_state); 371 void (*audio_codec_disable)(struct intel_encoder *encoder, 372 const struct intel_crtc_state *old_crtc_state, 373 const struct drm_connector_state *old_conn_state); 374 }; 375 376 struct intel_cdclk_funcs { 377 void (*get_cdclk)(struct drm_i915_private *dev_priv, 378 struct intel_cdclk_config *cdclk_config); 379 void (*set_cdclk)(struct drm_i915_private *dev_priv, 380 const struct intel_cdclk_config *cdclk_config, 381 enum pipe pipe); 382 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); 383 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 384 u8 (*calc_voltage_level)(int cdclk); 385 }; 386 387 struct intel_hotplug_funcs { 388 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 389 }; 390 391 struct intel_fdi_funcs { 392 void (*fdi_link_train)(struct intel_crtc *crtc, 393 const struct intel_crtc_state *crtc_state); 394 }; 395 396 struct intel_dpll_funcs { 397 int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state); 398 }; 399 400 struct drm_i915_display_funcs { 401 /* Returns the active state of the crtc, and if the crtc is active, 402 * fills out the pipe-config with the hw state. */ 403 bool (*get_pipe_config)(struct intel_crtc *, 404 struct intel_crtc_state *); 405 void (*get_initial_plane_config)(struct intel_crtc *, 406 struct intel_initial_plane_config *); 407 void (*crtc_enable)(struct intel_atomic_state *state, 408 struct intel_crtc *crtc); 409 void (*crtc_disable)(struct intel_atomic_state *state, 410 struct intel_crtc *crtc); 411 void (*commit_modeset_enables)(struct intel_atomic_state *state); 412 }; 413 414 415 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 416 417 struct intel_fbc { 418 /* This is always the inner lock when overlapping with struct_mutex and 419 * it's the outer lock when overlapping with stolen_lock. */ 420 struct mutex lock; 421 unsigned int possible_framebuffer_bits; 422 unsigned int busy_bits; 423 struct intel_crtc *crtc; 424 425 struct drm_mm_node compressed_fb; 426 struct drm_mm_node compressed_llb; 427 428 u8 limit; 429 430 bool false_color; 431 432 bool active; 433 bool activated; 434 bool flip_pending; 435 436 bool underrun_detected; 437 struct work_struct underrun_work; 438 439 /* 440 * Due to the atomic rules we can't access some structures without the 441 * appropriate locking, so we cache information here in order to avoid 442 * these problems. 443 */ 444 struct intel_fbc_state_cache { 445 struct { 446 unsigned int mode_flags; 447 u32 hsw_bdw_pixel_rate; 448 } crtc; 449 450 struct { 451 unsigned int rotation; 452 int src_w; 453 int src_h; 454 bool visible; 455 /* 456 * Display surface base address adjustement for 457 * pageflips. Note that on gen4+ this only adjusts up 458 * to a tile, offsets within a tile are handled in 459 * the hw itself (with the TILEOFF register). 460 */ 461 int adjusted_x; 462 int adjusted_y; 463 464 u16 pixel_blend_mode; 465 } plane; 466 467 struct { 468 const struct drm_format_info *format; 469 unsigned int stride; 470 u64 modifier; 471 } fb; 472 473 unsigned int fence_y_offset; 474 u16 interval; 475 s8 fence_id; 476 bool psr2_active; 477 } state_cache; 478 479 /* 480 * This structure contains everything that's relevant to program the 481 * hardware registers. When we want to figure out if we need to disable 482 * and re-enable FBC for a new configuration we just check if there's 483 * something different in the struct. The genx_fbc_activate functions 484 * are supposed to read from it in order to program the registers. 485 */ 486 struct intel_fbc_reg_params { 487 struct { 488 enum pipe pipe; 489 enum i9xx_plane_id i9xx_plane; 490 } crtc; 491 492 struct { 493 const struct drm_format_info *format; 494 unsigned int stride; 495 u64 modifier; 496 } fb; 497 498 unsigned int cfb_stride; 499 unsigned int cfb_size; 500 unsigned int fence_y_offset; 501 u16 override_cfb_stride; 502 u16 interval; 503 s8 fence_id; 504 bool plane_visible; 505 } params; 506 507 const char *no_fbc_reason; 508 }; 509 510 /* 511 * HIGH_RR is the highest eDP panel refresh rate read from EDID 512 * LOW_RR is the lowest eDP panel refresh rate found from EDID 513 * parsing for same resolution. 514 */ 515 enum drrs_refresh_rate_type { 516 DRRS_HIGH_RR, 517 DRRS_LOW_RR, 518 DRRS_MAX_RR, /* RR count */ 519 }; 520 521 enum drrs_support_type { 522 DRRS_NOT_SUPPORTED = 0, 523 STATIC_DRRS_SUPPORT = 1, 524 SEAMLESS_DRRS_SUPPORT = 2 525 }; 526 527 struct intel_dp; 528 struct i915_drrs { 529 struct mutex mutex; 530 struct delayed_work work; 531 struct intel_dp *dp; 532 unsigned busy_frontbuffer_bits; 533 enum drrs_refresh_rate_type refresh_rate_type; 534 enum drrs_support_type type; 535 }; 536 537 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 538 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 539 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 540 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 541 #define QUIRK_INCREASE_T12_DELAY (1<<6) 542 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 543 #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8) 544 545 struct intel_fbdev; 546 struct intel_fbc_work; 547 548 struct intel_gmbus { 549 struct i2c_adapter adapter; 550 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 551 u32 force_bit; 552 u32 reg0; 553 i915_reg_t gpio_reg; 554 struct i2c_algo_bit_data bit_algo; 555 struct drm_i915_private *dev_priv; 556 }; 557 558 struct i915_suspend_saved_registers { 559 u32 saveDSPARB; 560 u32 saveSWF0[16]; 561 u32 saveSWF1[16]; 562 u32 saveSWF3[3]; 563 u16 saveGCDGMBUS; 564 }; 565 566 struct vlv_s0ix_state; 567 568 #define MAX_L3_SLICES 2 569 struct intel_l3_parity { 570 u32 *remap_info[MAX_L3_SLICES]; 571 struct work_struct error_work; 572 int which_slice; 573 }; 574 575 struct i915_gem_mm { 576 /* 577 * Shortcut for the stolen region. This points to either 578 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 579 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 580 * support stolen. 581 */ 582 struct intel_memory_region *stolen_region; 583 /** Memory allocator for GTT stolen memory */ 584 struct drm_mm stolen; 585 /** Protects the usage of the GTT stolen memory allocator. This is 586 * always the inner lock when overlapping with struct_mutex. */ 587 struct mutex stolen_lock; 588 589 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 590 spinlock_t obj_lock; 591 592 /** 593 * List of objects which are purgeable. 594 */ 595 struct list_head purge_list; 596 597 /** 598 * List of objects which have allocated pages and are shrinkable. 599 */ 600 struct list_head shrink_list; 601 602 /** 603 * List of objects which are pending destruction. 604 */ 605 struct llist_head free_list; 606 struct work_struct free_work; 607 /** 608 * Count of objects pending destructions. Used to skip needlessly 609 * waiting on an RCU barrier if no objects are waiting to be freed. 610 */ 611 atomic_t free_count; 612 613 /** 614 * tmpfs instance used for shmem backed objects 615 */ 616 struct vfsmount *gemfs; 617 618 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 619 620 struct notifier_block oom_notifier; 621 struct notifier_block vmap_notifier; 622 struct shrinker shrinker; 623 624 #ifdef CONFIG_MMU_NOTIFIER 625 /** 626 * notifier_lock for mmu notifiers, memory may not be allocated 627 * while holding this lock. 628 */ 629 rwlock_t notifier_lock; 630 #endif 631 632 /* shrinker accounting, also useful for userland debugging */ 633 u64 shrink_memory; 634 u32 shrink_count; 635 }; 636 637 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 638 639 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 640 u64 context); 641 642 static inline unsigned long 643 i915_fence_timeout(const struct drm_i915_private *i915) 644 { 645 return i915_fence_context_timeout(i915, U64_MAX); 646 } 647 648 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 649 #define I915_NUM_QGV_POINTS 8 650 651 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 652 653 /* Amount of PSF GV points, BSpec precisely defines this */ 654 #define I915_NUM_PSF_GV_POINTS 3 655 656 enum psr_lines_to_wait { 657 PSR_0_LINES_TO_WAIT = 0, 658 PSR_1_LINE_TO_WAIT, 659 PSR_4_LINES_TO_WAIT, 660 PSR_8_LINES_TO_WAIT 661 }; 662 663 struct intel_vbt_data { 664 /* bdb version */ 665 u16 version; 666 667 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 668 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 669 670 /* Feature bits */ 671 unsigned int int_tv_support:1; 672 unsigned int lvds_dither:1; 673 unsigned int int_crt_support:1; 674 unsigned int lvds_use_ssc:1; 675 unsigned int int_lvds_support:1; 676 unsigned int display_clock_mode:1; 677 unsigned int fdi_rx_polarity_inverted:1; 678 unsigned int panel_type:4; 679 int lvds_ssc_freq; 680 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 681 enum drm_panel_orientation orientation; 682 683 enum drrs_support_type drrs_type; 684 685 struct { 686 int rate; 687 int lanes; 688 int preemphasis; 689 int vswing; 690 bool low_vswing; 691 bool initialized; 692 int bpp; 693 struct edp_power_seq pps; 694 bool hobl; 695 } edp; 696 697 struct { 698 bool enable; 699 bool full_link; 700 bool require_aux_wakeup; 701 int idle_frames; 702 enum psr_lines_to_wait lines_to_wait; 703 int tp1_wakeup_time_us; 704 int tp2_tp3_wakeup_time_us; 705 int psr2_tp2_tp3_wakeup_time_us; 706 } psr; 707 708 struct { 709 u16 pwm_freq_hz; 710 u16 brightness_precision_bits; 711 bool present; 712 bool active_low_pwm; 713 u8 min_brightness; /* min_brightness/255 of max */ 714 u8 controller; /* brightness controller number */ 715 enum intel_backlight_type type; 716 } backlight; 717 718 /* MIPI DSI */ 719 struct { 720 u16 panel_id; 721 struct mipi_config *config; 722 struct mipi_pps_data *pps; 723 u16 bl_ports; 724 u16 cabc_ports; 725 u8 seq_version; 726 u32 size; 727 u8 *data; 728 const u8 *sequence[MIPI_SEQ_MAX]; 729 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 730 enum drm_panel_orientation orientation; 731 } dsi; 732 733 int crt_ddc_pin; 734 735 struct list_head display_devices; 736 737 struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */ 738 struct sdvo_device_mapping sdvo_mappings[2]; 739 }; 740 741 enum intel_ddb_partitioning { 742 INTEL_DDB_PART_1_2, 743 INTEL_DDB_PART_5_6, /* IVB+ */ 744 }; 745 746 struct ilk_wm_values { 747 u32 wm_pipe[3]; 748 u32 wm_lp[3]; 749 u32 wm_lp_spr[3]; 750 bool enable_fbc_wm; 751 enum intel_ddb_partitioning partitioning; 752 }; 753 754 struct g4x_pipe_wm { 755 u16 plane[I915_MAX_PLANES]; 756 u16 fbc; 757 }; 758 759 struct g4x_sr_wm { 760 u16 plane; 761 u16 cursor; 762 u16 fbc; 763 }; 764 765 struct vlv_wm_ddl_values { 766 u8 plane[I915_MAX_PLANES]; 767 }; 768 769 struct vlv_wm_values { 770 struct g4x_pipe_wm pipe[3]; 771 struct g4x_sr_wm sr; 772 struct vlv_wm_ddl_values ddl[3]; 773 u8 level; 774 bool cxsr; 775 }; 776 777 struct g4x_wm_values { 778 struct g4x_pipe_wm pipe[2]; 779 struct g4x_sr_wm sr; 780 struct g4x_sr_wm hpll; 781 bool cxsr; 782 bool hpll_en; 783 bool fbc_en; 784 }; 785 786 struct skl_ddb_entry { 787 u16 start, end; /* in number of blocks, 'end' is exclusive */ 788 }; 789 790 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 791 { 792 return entry->end - entry->start; 793 } 794 795 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 796 const struct skl_ddb_entry *e2) 797 { 798 if (e1->start == e2->start && e1->end == e2->end) 799 return true; 800 801 return false; 802 } 803 804 struct i915_frontbuffer_tracking { 805 spinlock_t lock; 806 807 /* 808 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 809 * scheduled flips. 810 */ 811 unsigned busy_bits; 812 unsigned flip_bits; 813 }; 814 815 struct i915_virtual_gpu { 816 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 817 bool active; 818 u32 caps; 819 }; 820 821 struct intel_cdclk_config { 822 unsigned int cdclk, vco, ref, bypass; 823 u8 voltage_level; 824 }; 825 826 struct i915_selftest_stash { 827 atomic_t counter; 828 struct ida mock_region_instances; 829 }; 830 831 struct drm_i915_private { 832 struct drm_device drm; 833 834 /* FIXME: Device release actions should all be moved to drmm_ */ 835 bool do_release; 836 837 /* i915 device parameters */ 838 struct i915_params params; 839 840 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 841 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 842 struct intel_driver_caps caps; 843 844 /** 845 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 846 * end of stolen which we can optionally use to create GEM objects 847 * backed by stolen memory. Note that stolen_usable_size tells us 848 * exactly how much of this we are actually allowed to use, given that 849 * some portion of it is in fact reserved for use by hardware functions. 850 */ 851 struct resource dsm; 852 /** 853 * Reseved portion of Data Stolen Memory 854 */ 855 struct resource dsm_reserved; 856 857 /* 858 * Stolen memory is segmented in hardware with different portions 859 * offlimits to certain functions. 860 * 861 * The drm_mm is initialised to the total accessible range, as found 862 * from the PCI config. On Broadwell+, this is further restricted to 863 * avoid the first page! The upper end of stolen memory is reserved for 864 * hardware functions and similarly removed from the accessible range. 865 */ 866 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 867 868 struct intel_uncore uncore; 869 struct intel_uncore_mmio_debug mmio_debug; 870 871 struct i915_virtual_gpu vgpu; 872 873 struct intel_gvt *gvt; 874 875 struct intel_wopcm wopcm; 876 877 struct intel_dmc dmc; 878 879 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 880 881 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 882 * controller on different i2c buses. */ 883 struct mutex gmbus_mutex; 884 885 /** 886 * Base address of where the gmbus and gpio blocks are located (either 887 * on PCH or on SoC for platforms without PCH). 888 */ 889 u32 gpio_mmio_base; 890 891 /* MMIO base address for MIPI regs */ 892 u32 mipi_mmio_base; 893 894 u32 pps_mmio_base; 895 896 wait_queue_head_t gmbus_wait_queue; 897 898 struct pci_dev *bridge_dev; 899 900 struct rb_root uabi_engines; 901 902 struct resource mch_res; 903 904 /* protects the irq masks */ 905 spinlock_t irq_lock; 906 907 bool display_irqs_enabled; 908 909 /* Sideband mailbox protection */ 910 struct mutex sb_lock; 911 struct pm_qos_request sb_qos; 912 913 /** Cached value of IMR to avoid reads in updating the bitfield */ 914 union { 915 u32 irq_mask; 916 u32 de_irq_mask[I915_MAX_PIPES]; 917 }; 918 u32 pipestat_irq_mask[I915_MAX_PIPES]; 919 920 struct i915_hotplug hotplug; 921 struct intel_fbc fbc; 922 struct i915_drrs drrs; 923 struct intel_opregion opregion; 924 struct intel_vbt_data vbt; 925 926 bool preserve_bios_swizzle; 927 928 /* overlay */ 929 struct intel_overlay *overlay; 930 931 /* backlight registers and fields in struct intel_panel */ 932 struct mutex backlight_lock; 933 934 /* protects panel power sequencer state */ 935 struct mutex pps_mutex; 936 937 unsigned int fsb_freq, mem_freq, is_ddr3; 938 unsigned int skl_preferred_vco_freq; 939 unsigned int max_cdclk_freq; 940 941 unsigned int max_dotclk_freq; 942 unsigned int hpll_freq; 943 unsigned int fdi_pll_freq; 944 unsigned int czclk_freq; 945 946 struct { 947 /* The current hardware cdclk configuration */ 948 struct intel_cdclk_config hw; 949 950 /* cdclk, divider, and ratio table from bspec */ 951 const struct intel_cdclk_vals *table; 952 953 struct intel_global_obj obj; 954 } cdclk; 955 956 struct { 957 /* The current hardware dbuf configuration */ 958 u8 enabled_slices; 959 960 struct intel_global_obj obj; 961 } dbuf; 962 963 /** 964 * wq - Driver workqueue for GEM. 965 * 966 * NOTE: Work items scheduled here are not allowed to grab any modeset 967 * locks, for otherwise the flushing done in the pageflip code will 968 * result in deadlocks. 969 */ 970 struct workqueue_struct *wq; 971 972 /* ordered wq for modesets */ 973 struct workqueue_struct *modeset_wq; 974 /* unbound hipri wq for page flips/plane updates */ 975 struct workqueue_struct *flip_wq; 976 977 /* pm private clock gating functions */ 978 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 979 980 /* pm display functions */ 981 const struct drm_i915_wm_disp_funcs *wm_disp; 982 983 /* irq display functions */ 984 const struct intel_hotplug_funcs *hotplug_funcs; 985 986 /* fdi display functions */ 987 const struct intel_fdi_funcs *fdi_funcs; 988 989 /* display pll funcs */ 990 const struct intel_dpll_funcs *dpll_funcs; 991 992 /* Display functions */ 993 const struct drm_i915_display_funcs *display; 994 995 /* Display internal color functions */ 996 const struct intel_color_funcs *color_funcs; 997 998 /* Display internal audio functions */ 999 const struct intel_audio_funcs *audio_funcs; 1000 1001 /* Display CDCLK functions */ 1002 const struct intel_cdclk_funcs *cdclk_funcs; 1003 1004 /* PCH chipset type */ 1005 enum intel_pch pch_type; 1006 unsigned short pch_id; 1007 1008 unsigned long quirks; 1009 1010 struct drm_atomic_state *modeset_restore_state; 1011 struct drm_modeset_acquire_ctx reset_ctx; 1012 1013 struct i915_ggtt ggtt; /* VM representing the global address space */ 1014 1015 struct i915_gem_mm mm; 1016 1017 /* Kernel Modesetting */ 1018 1019 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1020 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1021 1022 /** 1023 * dpll and cdclk state is protected by connection_mutex 1024 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 1025 * Must be global rather than per dpll, because on some platforms plls 1026 * share registers. 1027 */ 1028 struct { 1029 struct mutex lock; 1030 1031 int num_shared_dpll; 1032 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1033 const struct intel_dpll_mgr *mgr; 1034 1035 struct { 1036 int nssc; 1037 int ssc; 1038 } ref_clks; 1039 } dpll; 1040 1041 struct list_head global_obj_list; 1042 1043 /* 1044 * For reading active_pipes holding any crtc lock is 1045 * sufficient, for writing must hold all of them. 1046 */ 1047 u8 active_pipes; 1048 1049 struct i915_frontbuffer_tracking fb_tracking; 1050 1051 struct intel_atomic_helper { 1052 struct llist_head free_list; 1053 struct work_struct free_work; 1054 } atomic_helper; 1055 1056 bool mchbar_need_disable; 1057 1058 struct intel_l3_parity l3_parity; 1059 1060 /* 1061 * HTI (aka HDPORT) state read during initial hw readout. Most 1062 * platforms don't have HTI, so this will just stay 0. Those that do 1063 * will use this later to figure out which PLLs and PHYs are unavailable 1064 * for driver usage. 1065 */ 1066 u32 hti_state; 1067 1068 /* 1069 * edram size in MB. 1070 * Cannot be determined by PCIID. You must always read a register. 1071 */ 1072 u32 edram_size_mb; 1073 1074 struct i915_power_domains power_domains; 1075 1076 struct i915_gpu_error gpu_error; 1077 1078 struct drm_i915_gem_object *vlv_pctx; 1079 1080 /* list of fbdev register on this device */ 1081 struct intel_fbdev *fbdev; 1082 struct work_struct fbdev_suspend_work; 1083 1084 struct drm_property *broadcast_rgb_property; 1085 struct drm_property *force_audio_property; 1086 1087 /* hda/i915 audio component */ 1088 struct i915_audio_component *audio_component; 1089 bool audio_component_registered; 1090 /** 1091 * av_mutex - mutex for audio/video sync 1092 * 1093 */ 1094 struct mutex av_mutex; 1095 int audio_power_refcount; 1096 u32 audio_freq_cntrl; 1097 1098 u32 fdi_rx_config; 1099 1100 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1101 u32 chv_phy_control; 1102 /* 1103 * Shadows for CHV DPLL_MD regs to keep the state 1104 * checker somewhat working in the presence hardware 1105 * crappiness (can't read out DPLL_MD for pipes B & C). 1106 */ 1107 u32 chv_dpll_md[I915_MAX_PIPES]; 1108 u32 bxt_phy_grc; 1109 1110 u32 suspend_count; 1111 bool power_domains_suspended; 1112 struct i915_suspend_saved_registers regfile; 1113 struct vlv_s0ix_state *vlv_s0ix_state; 1114 1115 enum { 1116 I915_SAGV_UNKNOWN = 0, 1117 I915_SAGV_DISABLED, 1118 I915_SAGV_ENABLED, 1119 I915_SAGV_NOT_CONTROLLED 1120 } sagv_status; 1121 1122 u32 sagv_block_time_us; 1123 1124 struct { 1125 /* 1126 * Raw watermark latency values: 1127 * in 0.1us units for WM0, 1128 * in 0.5us units for WM1+. 1129 */ 1130 /* primary */ 1131 u16 pri_latency[5]; 1132 /* sprite */ 1133 u16 spr_latency[5]; 1134 /* cursor */ 1135 u16 cur_latency[5]; 1136 /* 1137 * Raw watermark memory latency values 1138 * for SKL for all 8 levels 1139 * in 1us units. 1140 */ 1141 u16 skl_latency[8]; 1142 1143 /* current hardware state */ 1144 union { 1145 struct ilk_wm_values hw; 1146 struct vlv_wm_values vlv; 1147 struct g4x_wm_values g4x; 1148 }; 1149 1150 u8 max_level; 1151 1152 /* 1153 * Should be held around atomic WM register writing; also 1154 * protects * intel_crtc->wm.active and 1155 * crtc_state->wm.need_postvbl_update. 1156 */ 1157 struct mutex wm_mutex; 1158 } wm; 1159 1160 struct dram_info { 1161 bool wm_lv_0_adjust_needed; 1162 u8 num_channels; 1163 bool symmetric_memory; 1164 enum intel_dram_type { 1165 INTEL_DRAM_UNKNOWN, 1166 INTEL_DRAM_DDR3, 1167 INTEL_DRAM_DDR4, 1168 INTEL_DRAM_LPDDR3, 1169 INTEL_DRAM_LPDDR4, 1170 INTEL_DRAM_DDR5, 1171 INTEL_DRAM_LPDDR5, 1172 } type; 1173 u8 num_qgv_points; 1174 u8 num_psf_gv_points; 1175 } dram_info; 1176 1177 struct intel_bw_info { 1178 /* for each QGV point */ 1179 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1180 /* for each PSF GV point */ 1181 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 1182 u8 num_qgv_points; 1183 u8 num_psf_gv_points; 1184 u8 num_planes; 1185 } max_bw[6]; 1186 1187 struct intel_global_obj bw_obj; 1188 1189 struct intel_runtime_pm runtime_pm; 1190 1191 struct i915_perf perf; 1192 1193 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1194 struct intel_gt gt; 1195 1196 struct { 1197 struct i915_gem_contexts { 1198 spinlock_t lock; /* locks list */ 1199 struct list_head list; 1200 } contexts; 1201 1202 /* 1203 * We replace the local file with a global mappings as the 1204 * backing storage for the mmap is on the device and not 1205 * on the struct file, and we do not want to prolong the 1206 * lifetime of the local fd. To minimise the number of 1207 * anonymous inodes we create, we use a global singleton to 1208 * share the global mapping. 1209 */ 1210 struct file *mmap_singleton; 1211 } gem; 1212 1213 u8 framestart_delay; 1214 1215 /* Window2 specifies time required to program DSB (Window2) in number of scan lines */ 1216 u8 window2_delay; 1217 1218 u8 pch_ssc_use; 1219 1220 /* For i915gm/i945gm vblank irq workaround */ 1221 u8 vblank_enabled; 1222 1223 bool irq_enabled; 1224 1225 /* perform PHY state sanity checks? */ 1226 bool chv_phy_assert[2]; 1227 1228 bool ipc_enabled; 1229 1230 /* Used to save the pipe-to-encoder mapping for audio */ 1231 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1232 1233 /* necessary resource sharing with HDMI LPE audio driver. */ 1234 struct { 1235 struct platform_device *platdev; 1236 int irq; 1237 } lpe_audio; 1238 1239 struct i915_pmu pmu; 1240 1241 struct i915_hdcp_comp_master *hdcp_master; 1242 bool hdcp_comp_added; 1243 1244 /* Mutex to protect the above hdcp component related values. */ 1245 struct mutex hdcp_comp_mutex; 1246 1247 /* The TTM device structure. */ 1248 struct ttm_device bdev; 1249 1250 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1251 1252 /* 1253 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1254 * will be rejected. Instead look for a better place. 1255 */ 1256 }; 1257 1258 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1259 { 1260 return container_of(dev, struct drm_i915_private, drm); 1261 } 1262 1263 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1264 { 1265 return dev_get_drvdata(kdev); 1266 } 1267 1268 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1269 { 1270 return pci_get_drvdata(pdev); 1271 } 1272 1273 /* Simple iterator over all initialised engines */ 1274 #define for_each_engine(engine__, dev_priv__, id__) \ 1275 for ((id__) = 0; \ 1276 (id__) < I915_NUM_ENGINES; \ 1277 (id__)++) \ 1278 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1279 1280 /* Iterator over subset of engines selected by mask */ 1281 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1282 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 1283 (tmp__) ? \ 1284 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1285 0;) 1286 1287 #define rb_to_uabi_engine(rb) \ 1288 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1289 1290 #define for_each_uabi_engine(engine__, i915__) \ 1291 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1292 (engine__); \ 1293 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1294 1295 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 1296 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 1297 (engine__) && (engine__)->uabi_class == (class__); \ 1298 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1299 1300 #define I915_GTT_OFFSET_NONE ((u32)-1) 1301 1302 /* 1303 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1304 * considered to be the frontbuffer for the given plane interface-wise. This 1305 * doesn't mean that the hw necessarily already scans it out, but that any 1306 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1307 * 1308 * We have one bit per pipe and per scanout plane type. 1309 */ 1310 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1311 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1312 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1313 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1314 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1315 }) 1316 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1317 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1318 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1319 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1320 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1321 1322 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1323 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1324 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1325 1326 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1327 1328 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 1329 1330 #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver) 1331 #define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \ 1332 INTEL_INFO(i915)->graphics_rel) 1333 #define IS_GRAPHICS_VER(i915, from, until) \ 1334 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 1335 1336 #define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver) 1337 #define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media_ver, \ 1338 INTEL_INFO(i915)->media_rel) 1339 #define IS_MEDIA_VER(i915, from, until) \ 1340 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 1341 1342 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver) 1343 #define IS_DISPLAY_VER(i915, from, until) \ 1344 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 1345 1346 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) 1347 1348 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1349 1350 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 1351 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step) 1352 1353 #define IS_DISPLAY_STEP(__i915, since, until) \ 1354 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 1355 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 1356 1357 #define IS_GT_STEP(__i915, since, until) \ 1358 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \ 1359 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) < (until)) 1360 1361 static __always_inline unsigned int 1362 __platform_mask_index(const struct intel_runtime_info *info, 1363 enum intel_platform p) 1364 { 1365 const unsigned int pbits = 1366 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1367 1368 /* Expand the platform_mask array if this fails. */ 1369 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1370 pbits * ARRAY_SIZE(info->platform_mask)); 1371 1372 return p / pbits; 1373 } 1374 1375 static __always_inline unsigned int 1376 __platform_mask_bit(const struct intel_runtime_info *info, 1377 enum intel_platform p) 1378 { 1379 const unsigned int pbits = 1380 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1381 1382 return p % pbits + INTEL_SUBPLATFORM_BITS; 1383 } 1384 1385 static inline u32 1386 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1387 { 1388 const unsigned int pi = __platform_mask_index(info, p); 1389 1390 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 1391 } 1392 1393 static __always_inline bool 1394 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1395 { 1396 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1397 const unsigned int pi = __platform_mask_index(info, p); 1398 const unsigned int pb = __platform_mask_bit(info, p); 1399 1400 BUILD_BUG_ON(!__builtin_constant_p(p)); 1401 1402 return info->platform_mask[pi] & BIT(pb); 1403 } 1404 1405 static __always_inline bool 1406 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1407 enum intel_platform p, unsigned int s) 1408 { 1409 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1410 const unsigned int pi = __platform_mask_index(info, p); 1411 const unsigned int pb = __platform_mask_bit(info, p); 1412 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1413 const u32 mask = info->platform_mask[pi]; 1414 1415 BUILD_BUG_ON(!__builtin_constant_p(p)); 1416 BUILD_BUG_ON(!__builtin_constant_p(s)); 1417 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1418 1419 /* Shift and test on the MSB position so sign flag can be used. */ 1420 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1421 } 1422 1423 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1424 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1425 1426 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1427 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1428 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1429 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1430 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1431 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1432 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1433 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1434 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1435 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1436 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1437 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1438 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1439 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1440 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1441 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1442 #define IS_IRONLAKE_M(dev_priv) \ 1443 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1444 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) 1445 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1446 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1447 INTEL_INFO(dev_priv)->gt == 1) 1448 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1449 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1450 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1451 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1452 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1453 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1454 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1455 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1456 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1457 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 1458 #define IS_CANNONLAKE(dev_priv) 0 1459 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1460 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 1461 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1462 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1463 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 1464 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 1465 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) 1466 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) 1467 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) 1468 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) 1469 #define IS_DG2_G10(dev_priv) \ 1470 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) 1471 #define IS_DG2_G11(dev_priv) \ 1472 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) 1473 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1474 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1475 #define IS_BDW_ULT(dev_priv) \ 1476 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1477 #define IS_BDW_ULX(dev_priv) \ 1478 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1479 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1480 INTEL_INFO(dev_priv)->gt == 3) 1481 #define IS_HSW_ULT(dev_priv) \ 1482 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1483 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1484 INTEL_INFO(dev_priv)->gt == 3) 1485 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1486 INTEL_INFO(dev_priv)->gt == 1) 1487 /* ULX machines are also considered ULT. */ 1488 #define IS_HSW_ULX(dev_priv) \ 1489 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1490 #define IS_SKL_ULT(dev_priv) \ 1491 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1492 #define IS_SKL_ULX(dev_priv) \ 1493 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1494 #define IS_KBL_ULT(dev_priv) \ 1495 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1496 #define IS_KBL_ULX(dev_priv) \ 1497 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1498 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1499 INTEL_INFO(dev_priv)->gt == 2) 1500 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1501 INTEL_INFO(dev_priv)->gt == 3) 1502 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1503 INTEL_INFO(dev_priv)->gt == 4) 1504 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1505 INTEL_INFO(dev_priv)->gt == 2) 1506 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1507 INTEL_INFO(dev_priv)->gt == 3) 1508 #define IS_CFL_ULT(dev_priv) \ 1509 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1510 #define IS_CFL_ULX(dev_priv) \ 1511 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1512 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1513 INTEL_INFO(dev_priv)->gt == 2) 1514 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1515 INTEL_INFO(dev_priv)->gt == 3) 1516 1517 #define IS_CML_ULT(dev_priv) \ 1518 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 1519 #define IS_CML_ULX(dev_priv) \ 1520 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 1521 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 1522 INTEL_INFO(dev_priv)->gt == 2) 1523 1524 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1525 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1526 1527 #define IS_TGL_U(dev_priv) \ 1528 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) 1529 1530 #define IS_TGL_Y(dev_priv) \ 1531 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) 1532 1533 #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until)) 1534 1535 #define IS_KBL_GT_STEP(dev_priv, since, until) \ 1536 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until)) 1537 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ 1538 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) 1539 1540 #define IS_JSL_EHL_GT_STEP(p, since, until) \ 1541 (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until)) 1542 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ 1543 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until)) 1544 1545 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ 1546 (IS_TIGERLAKE(__i915) && \ 1547 IS_DISPLAY_STEP(__i915, since, until)) 1548 1549 #define IS_TGL_UY_GT_STEP(__i915, since, until) \ 1550 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ 1551 IS_GT_STEP(__i915, since, until)) 1552 1553 #define IS_TGL_GT_STEP(__i915, since, until) \ 1554 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ 1555 IS_GT_STEP(__i915, since, until)) 1556 1557 #define IS_RKL_DISPLAY_STEP(p, since, until) \ 1558 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) 1559 1560 #define IS_DG1_GT_STEP(p, since, until) \ 1561 (IS_DG1(p) && IS_GT_STEP(p, since, until)) 1562 #define IS_DG1_DISPLAY_STEP(p, since, until) \ 1563 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until)) 1564 1565 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ 1566 (IS_ALDERLAKE_S(__i915) && \ 1567 IS_DISPLAY_STEP(__i915, since, until)) 1568 1569 #define IS_ADLS_GT_STEP(__i915, since, until) \ 1570 (IS_ALDERLAKE_S(__i915) && \ 1571 IS_GT_STEP(__i915, since, until)) 1572 1573 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ 1574 (IS_ALDERLAKE_P(__i915) && \ 1575 IS_DISPLAY_STEP(__i915, since, until)) 1576 1577 #define IS_ADLP_GT_STEP(__i915, since, until) \ 1578 (IS_ALDERLAKE_P(__i915) && \ 1579 IS_GT_STEP(__i915, since, until)) 1580 1581 #define IS_XEHPSDV_GT_STEP(__i915, since, until) \ 1582 (IS_XEHPSDV(__i915) && IS_GT_STEP(__i915, since, until)) 1583 1584 /* 1585 * DG2 hardware steppings are a bit unusual. The hardware design was forked 1586 * to create two variants (G10 and G11) which have distinct workaround sets. 1587 * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its 1588 * first iteration, even though it's more similar to a G10 B0 stepping in terms 1589 * of functionality and workarounds. However the display stepping does not 1590 * reset in the same manner --- a specific stepping like "B0" has a consistent 1591 * meaning regardless of whether it belongs to a G10 or G11 DG2. 1592 * 1593 * TLDR: All GT workarounds and stepping-specific logic must be applied in 1594 * relation to a specific subplatform (G10 or G11), whereas display workarounds 1595 * and stepping-specific logic will be applied with a general DG2-wide stepping 1596 * number. 1597 */ 1598 #define IS_DG2_GT_STEP(__i915, variant, since, until) \ 1599 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ 1600 IS_GT_STEP(__i915, since, until)) 1601 1602 #define IS_DG2_DISP_STEP(__i915, since, until) \ 1603 (IS_DG2(__i915) && \ 1604 IS_DISPLAY_STEP(__i915, since, until)) 1605 1606 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1607 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) 1608 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) 1609 1610 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 1611 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 1612 1613 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ 1614 unsigned int first__ = (first); \ 1615 unsigned int count__ = (count); \ 1616 ((gt)->info.engine_mask & \ 1617 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1618 }) 1619 #define VDBOX_MASK(gt) \ 1620 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 1621 #define VEBOX_MASK(gt) \ 1622 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 1623 1624 /* 1625 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1626 * All later gens can run the final buffer from the ppgtt 1627 */ 1628 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) 1629 1630 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1631 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1632 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1633 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) 1634 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 1635 1636 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1637 1638 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1639 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1640 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1641 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1642 1643 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1644 1645 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1646 #define HAS_PPGTT(dev_priv) \ 1647 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1648 #define HAS_FULL_PPGTT(dev_priv) \ 1649 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1650 1651 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1652 GEM_BUG_ON((sizes) == 0); \ 1653 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1654 }) 1655 1656 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1657 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1658 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1659 1660 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1661 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1662 1663 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1664 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9) 1665 1666 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1667 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1668 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) 1669 1670 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4) 1671 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \ 1672 IS_GEMINILAKE(dev_priv) || \ 1673 IS_KABYLAKE(dev_priv)) 1674 1675 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1676 * rows, which changed the alignment requirements and fence programming. 1677 */ 1678 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ 1679 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) 1680 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1681 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1682 1683 #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2) 1684 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1685 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7) 1686 1687 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1688 1689 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1690 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) 1691 1692 #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) 1693 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1694 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) 1695 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1696 #define HAS_PSR_HW_TRACKING(dev_priv) \ 1697 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 1698 #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12) 1699 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 1700 1701 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1702 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1703 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1704 1705 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1706 1707 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) 1708 1709 #define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12) 1710 1711 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1712 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1713 1714 #define HAS_MSLICES(dev_priv) \ 1715 (INTEL_INFO(dev_priv)->has_mslices) 1716 1717 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1718 1719 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1720 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1721 1722 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1723 1724 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1725 1726 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1727 1728 #define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \ 1729 INTEL_INFO(dev_priv)->has_pxp) && \ 1730 VDBOX_MASK(&dev_priv->gt)) 1731 1732 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1733 1734 #define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10)) 1735 1736 /* DPF == dynamic parity feature */ 1737 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1738 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1739 2 : HAS_L3_DPF(dev_priv)) 1740 1741 #define GT_FREQUENCY_MULTIPLIER 50 1742 #define GEN9_FREQ_SCALER 3 1743 1744 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1745 1746 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1747 1748 #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12) 1749 1750 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 1751 1752 /* Only valid when HAS_DISPLAY() is true */ 1753 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 1754 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) 1755 1756 static inline bool run_as_guest(void) 1757 { 1758 return !hypervisor_is_type(X86_HYPER_NATIVE); 1759 } 1760 1761 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ 1762 IS_ALDERLAKE_S(dev_priv)) 1763 1764 static inline bool intel_vtd_active(void) 1765 { 1766 #ifdef CONFIG_INTEL_IOMMU 1767 if (intel_iommu_gfx_mapped) 1768 return true; 1769 #endif 1770 1771 /* Running as a guest, we assume the host is enforcing VT'd */ 1772 return run_as_guest(); 1773 } 1774 1775 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1776 { 1777 return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(); 1778 } 1779 1780 static inline bool 1781 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) 1782 { 1783 return IS_BROXTON(i915) && intel_vtd_active(); 1784 } 1785 1786 static inline bool 1787 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) 1788 { 1789 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); 1790 } 1791 1792 /* i915_drv.c */ 1793 extern const struct dev_pm_ops i915_pm_ops; 1794 1795 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1796 void i915_driver_remove(struct drm_i915_private *i915); 1797 void i915_driver_shutdown(struct drm_i915_private *i915); 1798 1799 int i915_resume_switcheroo(struct drm_i915_private *i915); 1800 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1801 1802 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1803 struct drm_file *file_priv); 1804 1805 /* i915_gem.c */ 1806 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1807 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1808 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1809 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1810 1811 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1812 { 1813 /* 1814 * A single pass should suffice to release all the freed objects (along 1815 * most call paths) , but be a little more paranoid in that freeing 1816 * the objects does take a little amount of time, during which the rcu 1817 * callbacks could have added new objects into the freed list, and 1818 * armed the work again. 1819 */ 1820 while (atomic_read(&i915->mm.free_count)) { 1821 flush_work(&i915->mm.free_work); 1822 rcu_barrier(); 1823 } 1824 } 1825 1826 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1827 { 1828 /* 1829 * Similar to objects above (see i915_gem_drain_freed-objects), in 1830 * general we have workers that are armed by RCU and then rearm 1831 * themselves in their callbacks. To be paranoid, we need to 1832 * drain the workqueue a second time after waiting for the RCU 1833 * grace period so that we catch work queued via RCU from the first 1834 * pass. As neither drain_workqueue() nor flush_workqueue() report 1835 * a result, we make an assumption that we only don't require more 1836 * than 3 passes to catch all _recursive_ RCU delayed work. 1837 * 1838 */ 1839 int pass = 3; 1840 do { 1841 flush_workqueue(i915->wq); 1842 rcu_barrier(); 1843 i915_gem_drain_freed_objects(i915); 1844 } while (--pass); 1845 drain_workqueue(i915->wq); 1846 } 1847 1848 struct i915_vma * __must_check 1849 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, 1850 struct i915_gem_ww_ctx *ww, 1851 const struct i915_ggtt_view *view, 1852 u64 size, u64 alignment, u64 flags); 1853 1854 static inline struct i915_vma * __must_check 1855 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1856 const struct i915_ggtt_view *view, 1857 u64 size, u64 alignment, u64 flags) 1858 { 1859 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); 1860 } 1861 1862 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1863 unsigned long flags); 1864 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1865 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1866 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2) 1867 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) 1868 1869 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1870 1871 int i915_gem_dumb_create(struct drm_file *file_priv, 1872 struct drm_device *dev, 1873 struct drm_mode_create_dumb *args); 1874 1875 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1876 1877 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1878 { 1879 return atomic_read(&error->reset_count); 1880 } 1881 1882 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1883 const struct intel_engine_cs *engine) 1884 { 1885 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1886 } 1887 1888 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1889 void i915_gem_driver_register(struct drm_i915_private *i915); 1890 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1891 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1892 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1893 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1894 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1895 void i915_gem_resume(struct drm_i915_private *dev_priv); 1896 1897 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1898 1899 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1900 enum i915_cache_level cache_level); 1901 1902 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1903 struct dma_buf *dma_buf); 1904 1905 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1906 1907 static inline struct i915_address_space * 1908 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id) 1909 { 1910 struct i915_address_space *vm; 1911 1912 xa_lock(&file_priv->vm_xa); 1913 vm = xa_load(&file_priv->vm_xa, id); 1914 if (vm) 1915 kref_get(&vm->ref); 1916 xa_unlock(&file_priv->vm_xa); 1917 1918 return vm; 1919 } 1920 1921 /* i915_gem_evict.c */ 1922 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1923 u64 min_size, u64 alignment, 1924 unsigned long color, 1925 u64 start, u64 end, 1926 unsigned flags); 1927 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1928 struct drm_mm_node *node, 1929 unsigned int flags); 1930 int i915_gem_evict_vm(struct i915_address_space *vm); 1931 1932 /* i915_gem_internal.c */ 1933 struct drm_i915_gem_object * 1934 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1935 phys_addr_t size); 1936 1937 /* i915_gem_tiling.c */ 1938 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1939 { 1940 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1941 1942 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1943 i915_gem_object_is_tiled(obj); 1944 } 1945 1946 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1947 unsigned int tiling, unsigned int stride); 1948 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1949 unsigned int tiling, unsigned int stride); 1950 1951 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1952 1953 /* i915_cmd_parser.c */ 1954 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1955 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1956 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1957 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1958 struct i915_vma *batch, 1959 unsigned long batch_offset, 1960 unsigned long batch_length, 1961 struct i915_vma *shadow, 1962 bool trampoline); 1963 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1964 1965 /* intel_device_info.c */ 1966 static inline struct intel_device_info * 1967 mkwrite_device_info(struct drm_i915_private *dev_priv) 1968 { 1969 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1970 } 1971 1972 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1973 struct drm_file *file); 1974 1975 /* i915_mm.c */ 1976 int remap_io_mapping(struct vm_area_struct *vma, 1977 unsigned long addr, unsigned long pfn, unsigned long size, 1978 struct io_mapping *iomap); 1979 int remap_io_sg(struct vm_area_struct *vma, 1980 unsigned long addr, unsigned long size, 1981 struct scatterlist *sgl, resource_size_t iobase); 1982 1983 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1984 { 1985 if (GRAPHICS_VER(i915) >= 11) 1986 return ICL_HWS_CSB_WRITE_INDEX; 1987 else 1988 return I915_HWS_CSB_WRITE_INDEX; 1989 } 1990 1991 static inline enum i915_map_type 1992 i915_coherent_map_type(struct drm_i915_private *i915, 1993 struct drm_i915_gem_object *obj, bool always_coherent) 1994 { 1995 if (i915_gem_object_is_lmem(obj)) 1996 return I915_MAP_WC; 1997 if (HAS_LLC(i915) || always_coherent) 1998 return I915_MAP_WB; 1999 else 2000 return I915_MAP_WC; 2001 } 2002 2003 #endif 2004