1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include "i915_reg.h" 37 #include "intel_bios.h" 38 #include "intel_ringbuffer.h" 39 #include "intel_lrc.h" 40 #include "i915_gem_gtt.h" 41 #include "i915_gem_render_state.h" 42 #include <linux/io-mapping.h> 43 #include <linux/i2c.h> 44 #include <linux/i2c-algo-bit.h> 45 #include <drm/intel-gtt.h> 46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 47 #include <drm/drm_gem.h> 48 #include <linux/backlight.h> 49 #include <linux/hashtable.h> 50 #include <linux/intel-iommu.h> 51 #include <linux/kref.h> 52 #include <linux/pm_qos.h> 53 54 /* General customization: 55 */ 56 57 #define DRIVER_NAME "i915" 58 #define DRIVER_DESC "Intel Graphics" 59 #define DRIVER_DATE "20150522" 60 61 #undef WARN_ON 62 /* Many gcc seem to no see through this and fall over :( */ 63 #if 0 64 #define WARN_ON(x) ({ \ 65 bool __i915_warn_cond = (x); \ 66 if (__builtin_constant_p(__i915_warn_cond)) \ 67 BUILD_BUG_ON(__i915_warn_cond); \ 68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) 69 #else 70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") 71 #endif 72 73 #undef WARN_ON_ONCE 74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")") 75 76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ 77 (long) (x), __func__); 78 79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 81 * which may not necessarily be a user visible problem. This will either 82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 83 * enable distros and users to tailor their preferred amount of i915 abrt 84 * spam. 85 */ 86 #define I915_STATE_WARN(condition, format...) ({ \ 87 int __ret_warn_on = !!(condition); \ 88 if (unlikely(__ret_warn_on)) { \ 89 if (i915.verbose_state_checks) \ 90 WARN(1, format); \ 91 else \ 92 DRM_ERROR(format); \ 93 } \ 94 unlikely(__ret_warn_on); \ 95 }) 96 97 #define I915_STATE_WARN_ON(condition) ({ \ 98 int __ret_warn_on = !!(condition); \ 99 if (unlikely(__ret_warn_on)) { \ 100 if (i915.verbose_state_checks) \ 101 WARN(1, "WARN_ON(" #condition ")\n"); \ 102 else \ 103 DRM_ERROR("WARN_ON(" #condition ")\n"); \ 104 } \ 105 unlikely(__ret_warn_on); \ 106 }) 107 108 enum pipe { 109 INVALID_PIPE = -1, 110 PIPE_A = 0, 111 PIPE_B, 112 PIPE_C, 113 _PIPE_EDP, 114 I915_MAX_PIPES = _PIPE_EDP 115 }; 116 #define pipe_name(p) ((p) + 'A') 117 118 enum transcoder { 119 TRANSCODER_A = 0, 120 TRANSCODER_B, 121 TRANSCODER_C, 122 TRANSCODER_EDP, 123 I915_MAX_TRANSCODERS 124 }; 125 #define transcoder_name(t) ((t) + 'A') 126 127 /* 128 * This is the maximum (across all platforms) number of planes (primary + 129 * sprites) that can be active at the same time on one pipe. 130 * 131 * This value doesn't count the cursor plane. 132 */ 133 #define I915_MAX_PLANES 4 134 135 enum plane { 136 PLANE_A = 0, 137 PLANE_B, 138 PLANE_C, 139 }; 140 #define plane_name(p) ((p) + 'A') 141 142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 143 144 enum port { 145 PORT_A = 0, 146 PORT_B, 147 PORT_C, 148 PORT_D, 149 PORT_E, 150 I915_MAX_PORTS 151 }; 152 #define port_name(p) ((p) + 'A') 153 154 #define I915_NUM_PHYS_VLV 2 155 156 enum dpio_channel { 157 DPIO_CH0, 158 DPIO_CH1 159 }; 160 161 enum dpio_phy { 162 DPIO_PHY0, 163 DPIO_PHY1 164 }; 165 166 enum intel_display_power_domain { 167 POWER_DOMAIN_PIPE_A, 168 POWER_DOMAIN_PIPE_B, 169 POWER_DOMAIN_PIPE_C, 170 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 171 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 172 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 173 POWER_DOMAIN_TRANSCODER_A, 174 POWER_DOMAIN_TRANSCODER_B, 175 POWER_DOMAIN_TRANSCODER_C, 176 POWER_DOMAIN_TRANSCODER_EDP, 177 POWER_DOMAIN_PORT_DDI_A_2_LANES, 178 POWER_DOMAIN_PORT_DDI_A_4_LANES, 179 POWER_DOMAIN_PORT_DDI_B_2_LANES, 180 POWER_DOMAIN_PORT_DDI_B_4_LANES, 181 POWER_DOMAIN_PORT_DDI_C_2_LANES, 182 POWER_DOMAIN_PORT_DDI_C_4_LANES, 183 POWER_DOMAIN_PORT_DDI_D_2_LANES, 184 POWER_DOMAIN_PORT_DDI_D_4_LANES, 185 POWER_DOMAIN_PORT_DSI, 186 POWER_DOMAIN_PORT_CRT, 187 POWER_DOMAIN_PORT_OTHER, 188 POWER_DOMAIN_VGA, 189 POWER_DOMAIN_AUDIO, 190 POWER_DOMAIN_PLLS, 191 POWER_DOMAIN_AUX_A, 192 POWER_DOMAIN_AUX_B, 193 POWER_DOMAIN_AUX_C, 194 POWER_DOMAIN_AUX_D, 195 POWER_DOMAIN_INIT, 196 197 POWER_DOMAIN_NUM, 198 }; 199 200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 203 #define POWER_DOMAIN_TRANSCODER(tran) \ 204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 205 (tran) + POWER_DOMAIN_TRANSCODER_A) 206 207 enum hpd_pin { 208 HPD_NONE = 0, 209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 211 HPD_CRT, 212 HPD_SDVO_B, 213 HPD_SDVO_C, 214 HPD_PORT_B, 215 HPD_PORT_C, 216 HPD_PORT_D, 217 HPD_NUM_PINS 218 }; 219 220 #define I915_GEM_GPU_DOMAINS \ 221 (I915_GEM_DOMAIN_RENDER | \ 222 I915_GEM_DOMAIN_SAMPLER | \ 223 I915_GEM_DOMAIN_COMMAND | \ 224 I915_GEM_DOMAIN_INSTRUCTION | \ 225 I915_GEM_DOMAIN_VERTEX) 226 227 #define for_each_pipe(__dev_priv, __p) \ 228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 229 #define for_each_plane(__dev_priv, __pipe, __p) \ 230 for ((__p) = 0; \ 231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 232 (__p)++) 233 #define for_each_sprite(__dev_priv, __p, __s) \ 234 for ((__s) = 0; \ 235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ 236 (__s)++) 237 238 #define for_each_crtc(dev, crtc) \ 239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 240 241 #define for_each_intel_plane(dev, intel_plane) \ 242 list_for_each_entry(intel_plane, \ 243 &dev->mode_config.plane_list, \ 244 base.head) 245 246 #define for_each_intel_crtc(dev, intel_crtc) \ 247 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 248 249 #define for_each_intel_encoder(dev, intel_encoder) \ 250 list_for_each_entry(intel_encoder, \ 251 &(dev)->mode_config.encoder_list, \ 252 base.head) 253 254 #define for_each_intel_connector(dev, intel_connector) \ 255 list_for_each_entry(intel_connector, \ 256 &dev->mode_config.connector_list, \ 257 base.head) 258 259 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 260 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 261 if ((intel_encoder)->base.crtc == (__crtc)) 262 263 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 264 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 265 if ((intel_connector)->base.encoder == (__encoder)) 266 267 #define for_each_power_domain(domain, mask) \ 268 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 269 if ((1 << (domain)) & (mask)) 270 271 struct drm_i915_private; 272 struct i915_mm_struct; 273 struct i915_mmu_object; 274 275 struct drm_i915_file_private { 276 struct drm_i915_private *dev_priv; 277 struct drm_file *file; 278 279 struct { 280 spinlock_t lock; 281 struct list_head request_list; 282 /* 20ms is a fairly arbitrary limit (greater than the average frame time) 283 * chosen to prevent the CPU getting more than a frame ahead of the GPU 284 * (when using lax throttling for the frontbuffer). We also use it to 285 * offer free GPU waitboosts for severely congested workloads. 286 */ 287 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) 288 } mm; 289 struct idr context_idr; 290 291 struct intel_rps_client { 292 struct list_head link; 293 unsigned boosts; 294 } rps; 295 296 struct intel_engine_cs *bsd_ring; 297 }; 298 299 enum intel_dpll_id { 300 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 301 /* real shared dpll ids must be >= 0 */ 302 DPLL_ID_PCH_PLL_A = 0, 303 DPLL_ID_PCH_PLL_B = 1, 304 /* hsw/bdw */ 305 DPLL_ID_WRPLL1 = 0, 306 DPLL_ID_WRPLL2 = 1, 307 /* skl */ 308 DPLL_ID_SKL_DPLL1 = 0, 309 DPLL_ID_SKL_DPLL2 = 1, 310 DPLL_ID_SKL_DPLL3 = 2, 311 }; 312 #define I915_NUM_PLLS 3 313 314 struct intel_dpll_hw_state { 315 /* i9xx, pch plls */ 316 uint32_t dpll; 317 uint32_t dpll_md; 318 uint32_t fp0; 319 uint32_t fp1; 320 321 /* hsw, bdw */ 322 uint32_t wrpll; 323 324 /* skl */ 325 /* 326 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 327 * lower part of ctrl1 and they get shifted into position when writing 328 * the register. This allows us to easily compare the state to share 329 * the DPLL. 330 */ 331 uint32_t ctrl1; 332 /* HDMI only, 0 when used for DP */ 333 uint32_t cfgcr1, cfgcr2; 334 335 /* bxt */ 336 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12; 337 }; 338 339 struct intel_shared_dpll_config { 340 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ 341 struct intel_dpll_hw_state hw_state; 342 }; 343 344 struct intel_shared_dpll { 345 struct intel_shared_dpll_config config; 346 struct intel_shared_dpll_config *new_config; 347 348 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 349 bool on; /* is the PLL actually active? Disabled during modeset */ 350 const char *name; 351 /* should match the index in the dev_priv->shared_dplls array */ 352 enum intel_dpll_id id; 353 /* The mode_set hook is optional and should be used together with the 354 * intel_prepare_shared_dpll function. */ 355 void (*mode_set)(struct drm_i915_private *dev_priv, 356 struct intel_shared_dpll *pll); 357 void (*enable)(struct drm_i915_private *dev_priv, 358 struct intel_shared_dpll *pll); 359 void (*disable)(struct drm_i915_private *dev_priv, 360 struct intel_shared_dpll *pll); 361 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 362 struct intel_shared_dpll *pll, 363 struct intel_dpll_hw_state *hw_state); 364 }; 365 366 #define SKL_DPLL0 0 367 #define SKL_DPLL1 1 368 #define SKL_DPLL2 2 369 #define SKL_DPLL3 3 370 371 /* Used by dp and fdi links */ 372 struct intel_link_m_n { 373 uint32_t tu; 374 uint32_t gmch_m; 375 uint32_t gmch_n; 376 uint32_t link_m; 377 uint32_t link_n; 378 }; 379 380 void intel_link_compute_m_n(int bpp, int nlanes, 381 int pixel_clock, int link_clock, 382 struct intel_link_m_n *m_n); 383 384 /* Interface history: 385 * 386 * 1.1: Original. 387 * 1.2: Add Power Management 388 * 1.3: Add vblank support 389 * 1.4: Fix cmdbuffer path, add heap destroy 390 * 1.5: Add vblank pipe configuration 391 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 392 * - Support vertical blank on secondary display pipe 393 */ 394 #define DRIVER_MAJOR 1 395 #define DRIVER_MINOR 6 396 #define DRIVER_PATCHLEVEL 0 397 398 #define WATCH_LISTS 0 399 400 struct opregion_header; 401 struct opregion_acpi; 402 struct opregion_swsci; 403 struct opregion_asle; 404 405 struct intel_opregion { 406 struct opregion_header __iomem *header; 407 struct opregion_acpi __iomem *acpi; 408 struct opregion_swsci __iomem *swsci; 409 u32 swsci_gbda_sub_functions; 410 u32 swsci_sbcb_sub_functions; 411 struct opregion_asle __iomem *asle; 412 void __iomem *vbt; 413 u32 __iomem *lid_state; 414 struct work_struct asle_work; 415 }; 416 #define OPREGION_SIZE (8*1024) 417 418 struct intel_overlay; 419 struct intel_overlay_error_state; 420 421 #define I915_FENCE_REG_NONE -1 422 #define I915_MAX_NUM_FENCES 32 423 /* 32 fences + sign bit for FENCE_REG_NONE */ 424 #define I915_MAX_NUM_FENCE_BITS 6 425 426 struct drm_i915_fence_reg { 427 struct list_head lru_list; 428 struct drm_i915_gem_object *obj; 429 int pin_count; 430 }; 431 432 struct sdvo_device_mapping { 433 u8 initialized; 434 u8 dvo_port; 435 u8 slave_addr; 436 u8 dvo_wiring; 437 u8 i2c_pin; 438 u8 ddc_pin; 439 }; 440 441 struct intel_display_error_state; 442 443 struct drm_i915_error_state { 444 struct kref ref; 445 struct timeval time; 446 447 char error_msg[128]; 448 u32 reset_count; 449 u32 suspend_count; 450 451 /* Generic register state */ 452 u32 eir; 453 u32 pgtbl_er; 454 u32 ier; 455 u32 gtier[4]; 456 u32 ccid; 457 u32 derrmr; 458 u32 forcewake; 459 u32 error; /* gen6+ */ 460 u32 err_int; /* gen7 */ 461 u32 fault_data0; /* gen8, gen9 */ 462 u32 fault_data1; /* gen8, gen9 */ 463 u32 done_reg; 464 u32 gac_eco; 465 u32 gam_ecochk; 466 u32 gab_ctl; 467 u32 gfx_mode; 468 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 469 u64 fence[I915_MAX_NUM_FENCES]; 470 struct intel_overlay_error_state *overlay; 471 struct intel_display_error_state *display; 472 struct drm_i915_error_object *semaphore_obj; 473 474 struct drm_i915_error_ring { 475 bool valid; 476 /* Software tracked state */ 477 bool waiting; 478 int hangcheck_score; 479 enum intel_ring_hangcheck_action hangcheck_action; 480 int num_requests; 481 482 /* our own tracking of ring head and tail */ 483 u32 cpu_ring_head; 484 u32 cpu_ring_tail; 485 486 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 487 488 /* Register state */ 489 u32 start; 490 u32 tail; 491 u32 head; 492 u32 ctl; 493 u32 hws; 494 u32 ipeir; 495 u32 ipehr; 496 u32 instdone; 497 u32 bbstate; 498 u32 instpm; 499 u32 instps; 500 u32 seqno; 501 u64 bbaddr; 502 u64 acthd; 503 u32 fault_reg; 504 u64 faddr; 505 u32 rc_psmi; /* sleep state */ 506 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 507 508 struct drm_i915_error_object { 509 int page_count; 510 u32 gtt_offset; 511 u32 *pages[0]; 512 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 513 514 struct drm_i915_error_request { 515 long jiffies; 516 u32 seqno; 517 u32 tail; 518 } *requests; 519 520 struct { 521 u32 gfx_mode; 522 union { 523 u64 pdp[4]; 524 u32 pp_dir_base; 525 }; 526 } vm_info; 527 528 pid_t pid; 529 char comm[TASK_COMM_LEN]; 530 } ring[I915_NUM_RINGS]; 531 532 struct drm_i915_error_buffer { 533 u32 size; 534 u32 name; 535 u32 rseqno[I915_NUM_RINGS], wseqno; 536 u32 gtt_offset; 537 u32 read_domains; 538 u32 write_domain; 539 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 540 s32 pinned:2; 541 u32 tiling:2; 542 u32 dirty:1; 543 u32 purgeable:1; 544 u32 userptr:1; 545 s32 ring:4; 546 u32 cache_level:3; 547 } **active_bo, **pinned_bo; 548 549 u32 *active_bo_count, *pinned_bo_count; 550 u32 vm_count; 551 }; 552 553 struct intel_connector; 554 struct intel_encoder; 555 struct intel_crtc_state; 556 struct intel_initial_plane_config; 557 struct intel_crtc; 558 struct intel_limit; 559 struct dpll; 560 561 struct drm_i915_display_funcs { 562 bool (*fbc_enabled)(struct drm_device *dev); 563 void (*enable_fbc)(struct drm_crtc *crtc); 564 void (*disable_fbc)(struct drm_device *dev); 565 int (*get_display_clock_speed)(struct drm_device *dev); 566 int (*get_fifo_size)(struct drm_device *dev, int plane); 567 /** 568 * find_dpll() - Find the best values for the PLL 569 * @limit: limits for the PLL 570 * @crtc: current CRTC 571 * @target: target frequency in kHz 572 * @refclk: reference clock frequency in kHz 573 * @match_clock: if provided, @best_clock P divider must 574 * match the P divider from @match_clock 575 * used for LVDS downclocking 576 * @best_clock: best PLL values found 577 * 578 * Returns true on success, false on failure. 579 */ 580 bool (*find_dpll)(const struct intel_limit *limit, 581 struct intel_crtc_state *crtc_state, 582 int target, int refclk, 583 struct dpll *match_clock, 584 struct dpll *best_clock); 585 void (*update_wm)(struct drm_crtc *crtc); 586 void (*update_sprite_wm)(struct drm_plane *plane, 587 struct drm_crtc *crtc, 588 uint32_t sprite_width, uint32_t sprite_height, 589 int pixel_size, bool enable, bool scaled); 590 void (*modeset_global_resources)(struct drm_atomic_state *state); 591 /* Returns the active state of the crtc, and if the crtc is active, 592 * fills out the pipe-config with the hw state. */ 593 bool (*get_pipe_config)(struct intel_crtc *, 594 struct intel_crtc_state *); 595 void (*get_initial_plane_config)(struct intel_crtc *, 596 struct intel_initial_plane_config *); 597 int (*crtc_compute_clock)(struct intel_crtc *crtc, 598 struct intel_crtc_state *crtc_state); 599 void (*crtc_enable)(struct drm_crtc *crtc); 600 void (*crtc_disable)(struct drm_crtc *crtc); 601 void (*off)(struct drm_crtc *crtc); 602 void (*audio_codec_enable)(struct drm_connector *connector, 603 struct intel_encoder *encoder, 604 struct drm_display_mode *mode); 605 void (*audio_codec_disable)(struct intel_encoder *encoder); 606 void (*fdi_link_train)(struct drm_crtc *crtc); 607 void (*init_clock_gating)(struct drm_device *dev); 608 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 609 struct drm_framebuffer *fb, 610 struct drm_i915_gem_object *obj, 611 struct intel_engine_cs *ring, 612 uint32_t flags); 613 void (*update_primary_plane)(struct drm_crtc *crtc, 614 struct drm_framebuffer *fb, 615 int x, int y); 616 void (*hpd_irq_setup)(struct drm_device *dev); 617 /* clock updates for mode set */ 618 /* cursor updates */ 619 /* render clock increase/decrease */ 620 /* display clock increase/decrease */ 621 /* pll clock increase/decrease */ 622 623 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); 624 uint32_t (*get_backlight)(struct intel_connector *connector); 625 void (*set_backlight)(struct intel_connector *connector, 626 uint32_t level); 627 void (*disable_backlight)(struct intel_connector *connector); 628 void (*enable_backlight)(struct intel_connector *connector); 629 }; 630 631 enum forcewake_domain_id { 632 FW_DOMAIN_ID_RENDER = 0, 633 FW_DOMAIN_ID_BLITTER, 634 FW_DOMAIN_ID_MEDIA, 635 636 FW_DOMAIN_ID_COUNT 637 }; 638 639 enum forcewake_domains { 640 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), 641 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), 642 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), 643 FORCEWAKE_ALL = (FORCEWAKE_RENDER | 644 FORCEWAKE_BLITTER | 645 FORCEWAKE_MEDIA) 646 }; 647 648 struct intel_uncore_funcs { 649 void (*force_wake_get)(struct drm_i915_private *dev_priv, 650 enum forcewake_domains domains); 651 void (*force_wake_put)(struct drm_i915_private *dev_priv, 652 enum forcewake_domains domains); 653 654 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 655 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 656 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 657 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 658 659 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 660 uint8_t val, bool trace); 661 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 662 uint16_t val, bool trace); 663 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 664 uint32_t val, bool trace); 665 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 666 uint64_t val, bool trace); 667 }; 668 669 struct intel_uncore { 670 spinlock_t lock; /** lock is also taken in irq contexts. */ 671 672 struct intel_uncore_funcs funcs; 673 674 unsigned fifo_count; 675 enum forcewake_domains fw_domains; 676 677 struct intel_uncore_forcewake_domain { 678 struct drm_i915_private *i915; 679 enum forcewake_domain_id id; 680 unsigned wake_count; 681 struct timer_list timer; 682 u32 reg_set; 683 u32 val_set; 684 u32 val_clear; 685 u32 reg_ack; 686 u32 reg_post; 687 u32 val_reset; 688 } fw_domain[FW_DOMAIN_ID_COUNT]; 689 }; 690 691 /* Iterate over initialised fw domains */ 692 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ 693 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ 694 (i__) < FW_DOMAIN_ID_COUNT; \ 695 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ 696 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) 697 698 #define for_each_fw_domain(domain__, dev_priv__, i__) \ 699 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) 700 701 enum csr_state { 702 FW_UNINITIALIZED = 0, 703 FW_LOADED, 704 FW_FAILED 705 }; 706 707 struct intel_csr { 708 const char *fw_path; 709 __be32 *dmc_payload; 710 uint32_t dmc_fw_size; 711 uint32_t mmio_count; 712 uint32_t mmioaddr[8]; 713 uint32_t mmiodata[8]; 714 enum csr_state state; 715 }; 716 717 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 718 func(is_mobile) sep \ 719 func(is_i85x) sep \ 720 func(is_i915g) sep \ 721 func(is_i945gm) sep \ 722 func(is_g33) sep \ 723 func(need_gfx_hws) sep \ 724 func(is_g4x) sep \ 725 func(is_pineview) sep \ 726 func(is_broadwater) sep \ 727 func(is_crestline) sep \ 728 func(is_ivybridge) sep \ 729 func(is_valleyview) sep \ 730 func(is_haswell) sep \ 731 func(is_skylake) sep \ 732 func(is_preliminary) sep \ 733 func(has_fbc) sep \ 734 func(has_pipe_cxsr) sep \ 735 func(has_hotplug) sep \ 736 func(cursor_needs_physical) sep \ 737 func(has_overlay) sep \ 738 func(overlay_needs_physical) sep \ 739 func(supports_tv) sep \ 740 func(has_llc) sep \ 741 func(has_ddi) sep \ 742 func(has_fpga_dbg) 743 744 #define DEFINE_FLAG(name) u8 name:1 745 #define SEP_SEMICOLON ; 746 747 struct intel_device_info { 748 u32 display_mmio_offset; 749 u16 device_id; 750 u8 num_pipes:3; 751 u8 num_sprites[I915_MAX_PIPES]; 752 u8 gen; 753 u8 ring_mask; /* Rings supported by the HW */ 754 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 755 /* Register offsets for the various display pipes and transcoders */ 756 int pipe_offsets[I915_MAX_TRANSCODERS]; 757 int trans_offsets[I915_MAX_TRANSCODERS]; 758 int palette_offsets[I915_MAX_PIPES]; 759 int cursor_offsets[I915_MAX_PIPES]; 760 761 /* Slice/subslice/EU info */ 762 u8 slice_total; 763 u8 subslice_total; 764 u8 subslice_per_slice; 765 u8 eu_total; 766 u8 eu_per_subslice; 767 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 768 u8 subslice_7eu[3]; 769 u8 has_slice_pg:1; 770 u8 has_subslice_pg:1; 771 u8 has_eu_pg:1; 772 }; 773 774 #undef DEFINE_FLAG 775 #undef SEP_SEMICOLON 776 777 enum i915_cache_level { 778 I915_CACHE_NONE = 0, 779 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 780 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 781 caches, eg sampler/render caches, and the 782 large Last-Level-Cache. LLC is coherent with 783 the CPU, but L3 is only visible to the GPU. */ 784 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 785 }; 786 787 struct i915_ctx_hang_stats { 788 /* This context had batch pending when hang was declared */ 789 unsigned batch_pending; 790 791 /* This context had batch active when hang was declared */ 792 unsigned batch_active; 793 794 /* Time when this context was last blamed for a GPU reset */ 795 unsigned long guilty_ts; 796 797 /* If the contexts causes a second GPU hang within this time, 798 * it is permanently banned from submitting any more work. 799 */ 800 unsigned long ban_period_seconds; 801 802 /* This context is banned to submit more work */ 803 bool banned; 804 }; 805 806 /* This must match up with the value previously used for execbuf2.rsvd1. */ 807 #define DEFAULT_CONTEXT_HANDLE 0 808 /** 809 * struct intel_context - as the name implies, represents a context. 810 * @ref: reference count. 811 * @user_handle: userspace tracking identity for this context. 812 * @remap_slice: l3 row remapping information. 813 * @file_priv: filp associated with this context (NULL for global default 814 * context). 815 * @hang_stats: information about the role of this context in possible GPU 816 * hangs. 817 * @ppgtt: virtual memory space used by this context. 818 * @legacy_hw_ctx: render context backing object and whether it is correctly 819 * initialized (legacy ring submission mechanism only). 820 * @link: link in the global list of contexts. 821 * 822 * Contexts are memory images used by the hardware to store copies of their 823 * internal state. 824 */ 825 struct intel_context { 826 struct kref ref; 827 int user_handle; 828 uint8_t remap_slice; 829 struct drm_i915_private *i915; 830 struct drm_i915_file_private *file_priv; 831 struct i915_ctx_hang_stats hang_stats; 832 struct i915_hw_ppgtt *ppgtt; 833 834 /* Legacy ring buffer submission */ 835 struct { 836 struct drm_i915_gem_object *rcs_state; 837 bool initialized; 838 } legacy_hw_ctx; 839 840 /* Execlists */ 841 bool rcs_initialized; 842 struct { 843 struct drm_i915_gem_object *state; 844 struct intel_ringbuffer *ringbuf; 845 int pin_count; 846 } engine[I915_NUM_RINGS]; 847 848 struct list_head link; 849 }; 850 851 enum fb_op_origin { 852 ORIGIN_GTT, 853 ORIGIN_CPU, 854 ORIGIN_CS, 855 ORIGIN_FLIP, 856 }; 857 858 struct i915_fbc { 859 unsigned long uncompressed_size; 860 unsigned threshold; 861 unsigned int fb_id; 862 unsigned int possible_framebuffer_bits; 863 unsigned int busy_bits; 864 struct intel_crtc *crtc; 865 int y; 866 867 struct drm_mm_node compressed_fb; 868 struct drm_mm_node *compressed_llb; 869 870 bool false_color; 871 872 /* Tracks whether the HW is actually enabled, not whether the feature is 873 * possible. */ 874 bool enabled; 875 876 struct intel_fbc_work { 877 struct delayed_work work; 878 struct drm_crtc *crtc; 879 struct drm_framebuffer *fb; 880 } *fbc_work; 881 882 enum no_fbc_reason { 883 FBC_OK, /* FBC is enabled */ 884 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 885 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 886 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 887 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 888 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 889 FBC_BAD_PLANE, /* fbc not supported on plane */ 890 FBC_NOT_TILED, /* buffer not tiled */ 891 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 892 FBC_MODULE_PARAM, 893 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 894 } no_fbc_reason; 895 }; 896 897 /** 898 * HIGH_RR is the highest eDP panel refresh rate read from EDID 899 * LOW_RR is the lowest eDP panel refresh rate found from EDID 900 * parsing for same resolution. 901 */ 902 enum drrs_refresh_rate_type { 903 DRRS_HIGH_RR, 904 DRRS_LOW_RR, 905 DRRS_MAX_RR, /* RR count */ 906 }; 907 908 enum drrs_support_type { 909 DRRS_NOT_SUPPORTED = 0, 910 STATIC_DRRS_SUPPORT = 1, 911 SEAMLESS_DRRS_SUPPORT = 2 912 }; 913 914 struct intel_dp; 915 struct i915_drrs { 916 struct mutex mutex; 917 struct delayed_work work; 918 struct intel_dp *dp; 919 unsigned busy_frontbuffer_bits; 920 enum drrs_refresh_rate_type refresh_rate_type; 921 enum drrs_support_type type; 922 }; 923 924 struct i915_psr { 925 struct mutex lock; 926 bool sink_support; 927 bool source_ok; 928 struct intel_dp *enabled; 929 bool active; 930 struct delayed_work work; 931 unsigned busy_frontbuffer_bits; 932 bool psr2_support; 933 bool aux_frame_sync; 934 }; 935 936 enum intel_pch { 937 PCH_NONE = 0, /* No PCH present */ 938 PCH_IBX, /* Ibexpeak PCH */ 939 PCH_CPT, /* Cougarpoint PCH */ 940 PCH_LPT, /* Lynxpoint PCH */ 941 PCH_SPT, /* Sunrisepoint PCH */ 942 PCH_NOP, 943 }; 944 945 enum intel_sbi_destination { 946 SBI_ICLK, 947 SBI_MPHY, 948 }; 949 950 #define QUIRK_PIPEA_FORCE (1<<0) 951 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 952 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 953 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 954 #define QUIRK_PIPEB_FORCE (1<<4) 955 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 956 957 struct intel_fbdev; 958 struct intel_fbc_work; 959 960 struct intel_gmbus { 961 struct i2c_adapter adapter; 962 u32 force_bit; 963 u32 reg0; 964 u32 gpio_reg; 965 struct i2c_algo_bit_data bit_algo; 966 struct drm_i915_private *dev_priv; 967 }; 968 969 struct i915_suspend_saved_registers { 970 u32 saveDSPARB; 971 u32 saveLVDS; 972 u32 savePP_ON_DELAYS; 973 u32 savePP_OFF_DELAYS; 974 u32 savePP_ON; 975 u32 savePP_OFF; 976 u32 savePP_CONTROL; 977 u32 savePP_DIVISOR; 978 u32 saveFBC_CONTROL; 979 u32 saveCACHE_MODE_0; 980 u32 saveMI_ARB_STATE; 981 u32 saveSWF0[16]; 982 u32 saveSWF1[16]; 983 u32 saveSWF2[3]; 984 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 985 u32 savePCH_PORT_HOTPLUG; 986 u16 saveGCDGMBUS; 987 }; 988 989 struct vlv_s0ix_state { 990 /* GAM */ 991 u32 wr_watermark; 992 u32 gfx_prio_ctrl; 993 u32 arb_mode; 994 u32 gfx_pend_tlb0; 995 u32 gfx_pend_tlb1; 996 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 997 u32 media_max_req_count; 998 u32 gfx_max_req_count; 999 u32 render_hwsp; 1000 u32 ecochk; 1001 u32 bsd_hwsp; 1002 u32 blt_hwsp; 1003 u32 tlb_rd_addr; 1004 1005 /* MBC */ 1006 u32 g3dctl; 1007 u32 gsckgctl; 1008 u32 mbctl; 1009 1010 /* GCP */ 1011 u32 ucgctl1; 1012 u32 ucgctl3; 1013 u32 rcgctl1; 1014 u32 rcgctl2; 1015 u32 rstctl; 1016 u32 misccpctl; 1017 1018 /* GPM */ 1019 u32 gfxpause; 1020 u32 rpdeuhwtc; 1021 u32 rpdeuc; 1022 u32 ecobus; 1023 u32 pwrdwnupctl; 1024 u32 rp_down_timeout; 1025 u32 rp_deucsw; 1026 u32 rcubmabdtmr; 1027 u32 rcedata; 1028 u32 spare2gh; 1029 1030 /* Display 1 CZ domain */ 1031 u32 gt_imr; 1032 u32 gt_ier; 1033 u32 pm_imr; 1034 u32 pm_ier; 1035 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 1036 1037 /* GT SA CZ domain */ 1038 u32 tilectl; 1039 u32 gt_fifoctl; 1040 u32 gtlc_wake_ctrl; 1041 u32 gtlc_survive; 1042 u32 pmwgicz; 1043 1044 /* Display 2 CZ domain */ 1045 u32 gu_ctl0; 1046 u32 gu_ctl1; 1047 u32 pcbr; 1048 u32 clock_gate_dis2; 1049 }; 1050 1051 struct intel_rps_ei { 1052 u32 cz_clock; 1053 u32 render_c0; 1054 u32 media_c0; 1055 }; 1056 1057 struct intel_gen6_power_mgmt { 1058 /* 1059 * work, interrupts_enabled and pm_iir are protected by 1060 * dev_priv->irq_lock 1061 */ 1062 struct work_struct work; 1063 bool interrupts_enabled; 1064 u32 pm_iir; 1065 1066 /* Frequencies are stored in potentially platform dependent multiples. 1067 * In other words, *_freq needs to be multiplied by X to be interesting. 1068 * Soft limits are those which are used for the dynamic reclocking done 1069 * by the driver (raise frequencies under heavy loads, and lower for 1070 * lighter loads). Hard limits are those imposed by the hardware. 1071 * 1072 * A distinction is made for overclocking, which is never enabled by 1073 * default, and is considered to be above the hard limit if it's 1074 * possible at all. 1075 */ 1076 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 1077 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 1078 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 1079 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 1080 u8 min_freq; /* AKA RPn. Minimum frequency */ 1081 u8 idle_freq; /* Frequency to request when we are idle */ 1082 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 1083 u8 rp1_freq; /* "less than" RP0 power/freqency */ 1084 u8 rp0_freq; /* Non-overclocked max frequency. */ 1085 u32 cz_freq; 1086 1087 u8 up_threshold; /* Current %busy required to uplock */ 1088 u8 down_threshold; /* Current %busy required to downclock */ 1089 1090 int last_adj; 1091 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 1092 1093 spinlock_t client_lock; 1094 struct list_head clients; 1095 bool client_boost; 1096 1097 bool enabled; 1098 struct delayed_work delayed_resume_work; 1099 unsigned boosts; 1100 1101 struct intel_rps_client semaphores, mmioflips; 1102 1103 /* manual wa residency calculations */ 1104 struct intel_rps_ei up_ei, down_ei; 1105 1106 /* 1107 * Protects RPS/RC6 register access and PCU communication. 1108 * Must be taken after struct_mutex if nested. Note that 1109 * this lock may be held for long periods of time when 1110 * talking to hw - so only take it when talking to hw! 1111 */ 1112 struct mutex hw_lock; 1113 }; 1114 1115 /* defined intel_pm.c */ 1116 extern spinlock_t mchdev_lock; 1117 1118 struct intel_ilk_power_mgmt { 1119 u8 cur_delay; 1120 u8 min_delay; 1121 u8 max_delay; 1122 u8 fmax; 1123 u8 fstart; 1124 1125 u64 last_count1; 1126 unsigned long last_time1; 1127 unsigned long chipset_power; 1128 u64 last_count2; 1129 u64 last_time2; 1130 unsigned long gfx_power; 1131 u8 corr; 1132 1133 int c_m; 1134 int r_t; 1135 }; 1136 1137 struct drm_i915_private; 1138 struct i915_power_well; 1139 1140 struct i915_power_well_ops { 1141 /* 1142 * Synchronize the well's hw state to match the current sw state, for 1143 * example enable/disable it based on the current refcount. Called 1144 * during driver init and resume time, possibly after first calling 1145 * the enable/disable handlers. 1146 */ 1147 void (*sync_hw)(struct drm_i915_private *dev_priv, 1148 struct i915_power_well *power_well); 1149 /* 1150 * Enable the well and resources that depend on it (for example 1151 * interrupts located on the well). Called after the 0->1 refcount 1152 * transition. 1153 */ 1154 void (*enable)(struct drm_i915_private *dev_priv, 1155 struct i915_power_well *power_well); 1156 /* 1157 * Disable the well and resources that depend on it. Called after 1158 * the 1->0 refcount transition. 1159 */ 1160 void (*disable)(struct drm_i915_private *dev_priv, 1161 struct i915_power_well *power_well); 1162 /* Returns the hw enabled state. */ 1163 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1164 struct i915_power_well *power_well); 1165 }; 1166 1167 /* Power well structure for haswell */ 1168 struct i915_power_well { 1169 const char *name; 1170 bool always_on; 1171 /* power well enable/disable usage count */ 1172 int count; 1173 /* cached hw enabled state */ 1174 bool hw_enabled; 1175 unsigned long domains; 1176 unsigned long data; 1177 const struct i915_power_well_ops *ops; 1178 }; 1179 1180 struct i915_power_domains { 1181 /* 1182 * Power wells needed for initialization at driver init and suspend 1183 * time are on. They are kept on until after the first modeset. 1184 */ 1185 bool init_power_on; 1186 bool initializing; 1187 int power_well_count; 1188 1189 struct mutex lock; 1190 int domain_use_count[POWER_DOMAIN_NUM]; 1191 struct i915_power_well *power_wells; 1192 }; 1193 1194 #define MAX_L3_SLICES 2 1195 struct intel_l3_parity { 1196 u32 *remap_info[MAX_L3_SLICES]; 1197 struct work_struct error_work; 1198 int which_slice; 1199 }; 1200 1201 struct i915_gem_mm { 1202 /** Memory allocator for GTT stolen memory */ 1203 struct drm_mm stolen; 1204 /** List of all objects in gtt_space. Used to restore gtt 1205 * mappings on resume */ 1206 struct list_head bound_list; 1207 /** 1208 * List of objects which are not bound to the GTT (thus 1209 * are idle and not used by the GPU) but still have 1210 * (presumably uncached) pages still attached. 1211 */ 1212 struct list_head unbound_list; 1213 1214 /** Usable portion of the GTT for GEM */ 1215 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1216 1217 /** PPGTT used for aliasing the PPGTT with the GTT */ 1218 struct i915_hw_ppgtt *aliasing_ppgtt; 1219 1220 struct notifier_block oom_notifier; 1221 struct shrinker shrinker; 1222 bool shrinker_no_lock_stealing; 1223 1224 /** LRU list of objects with fence regs on them. */ 1225 struct list_head fence_list; 1226 1227 /** 1228 * We leave the user IRQ off as much as possible, 1229 * but this means that requests will finish and never 1230 * be retired once the system goes idle. Set a timer to 1231 * fire periodically while the ring is running. When it 1232 * fires, go retire requests. 1233 */ 1234 struct delayed_work retire_work; 1235 1236 /** 1237 * When we detect an idle GPU, we want to turn on 1238 * powersaving features. So once we see that there 1239 * are no more requests outstanding and no more 1240 * arrive within a small period of time, we fire 1241 * off the idle_work. 1242 */ 1243 struct delayed_work idle_work; 1244 1245 /** 1246 * Are we in a non-interruptible section of code like 1247 * modesetting? 1248 */ 1249 bool interruptible; 1250 1251 /** 1252 * Is the GPU currently considered idle, or busy executing userspace 1253 * requests? Whilst idle, we attempt to power down the hardware and 1254 * display clocks. In order to reduce the effect on performance, there 1255 * is a slight delay before we do so. 1256 */ 1257 bool busy; 1258 1259 /* the indicator for dispatch video commands on two BSD rings */ 1260 int bsd_ring_dispatch_index; 1261 1262 /** Bit 6 swizzling required for X tiling */ 1263 uint32_t bit_6_swizzle_x; 1264 /** Bit 6 swizzling required for Y tiling */ 1265 uint32_t bit_6_swizzle_y; 1266 1267 /* accounting, useful for userland debugging */ 1268 spinlock_t object_stat_lock; 1269 size_t object_memory; 1270 u32 object_count; 1271 }; 1272 1273 struct drm_i915_error_state_buf { 1274 struct drm_i915_private *i915; 1275 unsigned bytes; 1276 unsigned size; 1277 int err; 1278 u8 *buf; 1279 loff_t start; 1280 loff_t pos; 1281 }; 1282 1283 struct i915_error_state_file_priv { 1284 struct drm_device *dev; 1285 struct drm_i915_error_state *error; 1286 }; 1287 1288 struct i915_gpu_error { 1289 /* For hangcheck timer */ 1290 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1291 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1292 /* Hang gpu twice in this window and your context gets banned */ 1293 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1294 1295 struct workqueue_struct *hangcheck_wq; 1296 struct delayed_work hangcheck_work; 1297 1298 /* For reset and error_state handling. */ 1299 spinlock_t lock; 1300 /* Protected by the above dev->gpu_error.lock. */ 1301 struct drm_i915_error_state *first_error; 1302 1303 unsigned long missed_irq_rings; 1304 1305 /** 1306 * State variable controlling the reset flow and count 1307 * 1308 * This is a counter which gets incremented when reset is triggered, 1309 * and again when reset has been handled. So odd values (lowest bit set) 1310 * means that reset is in progress and even values that 1311 * (reset_counter >> 1):th reset was successfully completed. 1312 * 1313 * If reset is not completed succesfully, the I915_WEDGE bit is 1314 * set meaning that hardware is terminally sour and there is no 1315 * recovery. All waiters on the reset_queue will be woken when 1316 * that happens. 1317 * 1318 * This counter is used by the wait_seqno code to notice that reset 1319 * event happened and it needs to restart the entire ioctl (since most 1320 * likely the seqno it waited for won't ever signal anytime soon). 1321 * 1322 * This is important for lock-free wait paths, where no contended lock 1323 * naturally enforces the correct ordering between the bail-out of the 1324 * waiter and the gpu reset work code. 1325 */ 1326 atomic_t reset_counter; 1327 1328 #define I915_RESET_IN_PROGRESS_FLAG 1 1329 #define I915_WEDGED (1 << 31) 1330 1331 /** 1332 * Waitqueue to signal when the reset has completed. Used by clients 1333 * that wait for dev_priv->mm.wedged to settle. 1334 */ 1335 wait_queue_head_t reset_queue; 1336 1337 /* Userspace knobs for gpu hang simulation; 1338 * combines both a ring mask, and extra flags 1339 */ 1340 u32 stop_rings; 1341 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1342 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1343 1344 /* For missed irq/seqno simulation. */ 1345 unsigned int test_irq_rings; 1346 1347 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 1348 bool reload_in_reset; 1349 }; 1350 1351 enum modeset_restore { 1352 MODESET_ON_LID_OPEN, 1353 MODESET_DONE, 1354 MODESET_SUSPENDED, 1355 }; 1356 1357 struct ddi_vbt_port_info { 1358 /* 1359 * This is an index in the HDMI/DVI DDI buffer translation table. 1360 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1361 * populate this field. 1362 */ 1363 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1364 uint8_t hdmi_level_shift; 1365 1366 uint8_t supports_dvi:1; 1367 uint8_t supports_hdmi:1; 1368 uint8_t supports_dp:1; 1369 }; 1370 1371 enum psr_lines_to_wait { 1372 PSR_0_LINES_TO_WAIT = 0, 1373 PSR_1_LINE_TO_WAIT, 1374 PSR_4_LINES_TO_WAIT, 1375 PSR_8_LINES_TO_WAIT 1376 }; 1377 1378 struct intel_vbt_data { 1379 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1380 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1381 1382 /* Feature bits */ 1383 unsigned int int_tv_support:1; 1384 unsigned int lvds_dither:1; 1385 unsigned int lvds_vbt:1; 1386 unsigned int int_crt_support:1; 1387 unsigned int lvds_use_ssc:1; 1388 unsigned int display_clock_mode:1; 1389 unsigned int fdi_rx_polarity_inverted:1; 1390 unsigned int has_mipi:1; 1391 int lvds_ssc_freq; 1392 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1393 1394 enum drrs_support_type drrs_type; 1395 1396 /* eDP */ 1397 int edp_rate; 1398 int edp_lanes; 1399 int edp_preemphasis; 1400 int edp_vswing; 1401 bool edp_initialized; 1402 bool edp_support; 1403 int edp_bpp; 1404 struct edp_power_seq edp_pps; 1405 1406 struct { 1407 bool full_link; 1408 bool require_aux_wakeup; 1409 int idle_frames; 1410 enum psr_lines_to_wait lines_to_wait; 1411 int tp1_wakeup_time; 1412 int tp2_tp3_wakeup_time; 1413 } psr; 1414 1415 struct { 1416 u16 pwm_freq_hz; 1417 bool present; 1418 bool active_low_pwm; 1419 u8 min_brightness; /* min_brightness/255 of max */ 1420 } backlight; 1421 1422 /* MIPI DSI */ 1423 struct { 1424 u16 port; 1425 u16 panel_id; 1426 struct mipi_config *config; 1427 struct mipi_pps_data *pps; 1428 u8 seq_version; 1429 u32 size; 1430 u8 *data; 1431 u8 *sequence[MIPI_SEQ_MAX]; 1432 } dsi; 1433 1434 int crt_ddc_pin; 1435 1436 int child_dev_num; 1437 union child_device_config *child_dev; 1438 1439 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1440 }; 1441 1442 enum intel_ddb_partitioning { 1443 INTEL_DDB_PART_1_2, 1444 INTEL_DDB_PART_5_6, /* IVB+ */ 1445 }; 1446 1447 struct intel_wm_level { 1448 bool enable; 1449 uint32_t pri_val; 1450 uint32_t spr_val; 1451 uint32_t cur_val; 1452 uint32_t fbc_val; 1453 }; 1454 1455 struct ilk_wm_values { 1456 uint32_t wm_pipe[3]; 1457 uint32_t wm_lp[3]; 1458 uint32_t wm_lp_spr[3]; 1459 uint32_t wm_linetime[3]; 1460 bool enable_fbc_wm; 1461 enum intel_ddb_partitioning partitioning; 1462 }; 1463 1464 struct vlv_wm_values { 1465 struct { 1466 uint16_t primary; 1467 uint16_t sprite[2]; 1468 uint8_t cursor; 1469 } pipe[3]; 1470 1471 struct { 1472 uint16_t plane; 1473 uint8_t cursor; 1474 } sr; 1475 1476 struct { 1477 uint8_t cursor; 1478 uint8_t sprite[2]; 1479 uint8_t primary; 1480 } ddl[3]; 1481 }; 1482 1483 struct skl_ddb_entry { 1484 uint16_t start, end; /* in number of blocks, 'end' is exclusive */ 1485 }; 1486 1487 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) 1488 { 1489 return entry->end - entry->start; 1490 } 1491 1492 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 1493 const struct skl_ddb_entry *e2) 1494 { 1495 if (e1->start == e2->start && e1->end == e2->end) 1496 return true; 1497 1498 return false; 1499 } 1500 1501 struct skl_ddb_allocation { 1502 struct skl_ddb_entry pipe[I915_MAX_PIPES]; 1503 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ 1504 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */ 1505 struct skl_ddb_entry cursor[I915_MAX_PIPES]; 1506 }; 1507 1508 struct skl_wm_values { 1509 bool dirty[I915_MAX_PIPES]; 1510 struct skl_ddb_allocation ddb; 1511 uint32_t wm_linetime[I915_MAX_PIPES]; 1512 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; 1513 uint32_t cursor[I915_MAX_PIPES][8]; 1514 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; 1515 uint32_t cursor_trans[I915_MAX_PIPES]; 1516 }; 1517 1518 struct skl_wm_level { 1519 bool plane_en[I915_MAX_PLANES]; 1520 bool cursor_en; 1521 uint16_t plane_res_b[I915_MAX_PLANES]; 1522 uint8_t plane_res_l[I915_MAX_PLANES]; 1523 uint16_t cursor_res_b; 1524 uint8_t cursor_res_l; 1525 }; 1526 1527 /* 1528 * This struct helps tracking the state needed for runtime PM, which puts the 1529 * device in PCI D3 state. Notice that when this happens, nothing on the 1530 * graphics device works, even register access, so we don't get interrupts nor 1531 * anything else. 1532 * 1533 * Every piece of our code that needs to actually touch the hardware needs to 1534 * either call intel_runtime_pm_get or call intel_display_power_get with the 1535 * appropriate power domain. 1536 * 1537 * Our driver uses the autosuspend delay feature, which means we'll only really 1538 * suspend if we stay with zero refcount for a certain amount of time. The 1539 * default value is currently very conservative (see intel_runtime_pm_enable), but 1540 * it can be changed with the standard runtime PM files from sysfs. 1541 * 1542 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1543 * goes back to false exactly before we reenable the IRQs. We use this variable 1544 * to check if someone is trying to enable/disable IRQs while they're supposed 1545 * to be disabled. This shouldn't happen and we'll print some error messages in 1546 * case it happens. 1547 * 1548 * For more, read the Documentation/power/runtime_pm.txt. 1549 */ 1550 struct i915_runtime_pm { 1551 bool suspended; 1552 bool irqs_enabled; 1553 }; 1554 1555 enum intel_pipe_crc_source { 1556 INTEL_PIPE_CRC_SOURCE_NONE, 1557 INTEL_PIPE_CRC_SOURCE_PLANE1, 1558 INTEL_PIPE_CRC_SOURCE_PLANE2, 1559 INTEL_PIPE_CRC_SOURCE_PF, 1560 INTEL_PIPE_CRC_SOURCE_PIPE, 1561 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1562 INTEL_PIPE_CRC_SOURCE_TV, 1563 INTEL_PIPE_CRC_SOURCE_DP_B, 1564 INTEL_PIPE_CRC_SOURCE_DP_C, 1565 INTEL_PIPE_CRC_SOURCE_DP_D, 1566 INTEL_PIPE_CRC_SOURCE_AUTO, 1567 INTEL_PIPE_CRC_SOURCE_MAX, 1568 }; 1569 1570 struct intel_pipe_crc_entry { 1571 uint32_t frame; 1572 uint32_t crc[5]; 1573 }; 1574 1575 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1576 struct intel_pipe_crc { 1577 spinlock_t lock; 1578 bool opened; /* exclusive access to the result file */ 1579 struct intel_pipe_crc_entry *entries; 1580 enum intel_pipe_crc_source source; 1581 int head, tail; 1582 wait_queue_head_t wq; 1583 }; 1584 1585 struct i915_frontbuffer_tracking { 1586 struct mutex lock; 1587 1588 /* 1589 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1590 * scheduled flips. 1591 */ 1592 unsigned busy_bits; 1593 unsigned flip_bits; 1594 }; 1595 1596 struct i915_wa_reg { 1597 u32 addr; 1598 u32 value; 1599 /* bitmask representing WA bits */ 1600 u32 mask; 1601 }; 1602 1603 #define I915_MAX_WA_REGS 16 1604 1605 struct i915_workarounds { 1606 struct i915_wa_reg reg[I915_MAX_WA_REGS]; 1607 u32 count; 1608 }; 1609 1610 struct i915_virtual_gpu { 1611 bool active; 1612 }; 1613 1614 struct drm_i915_private { 1615 struct drm_device *dev; 1616 struct kmem_cache *objects; 1617 struct kmem_cache *vmas; 1618 struct kmem_cache *requests; 1619 1620 const struct intel_device_info info; 1621 1622 int relative_constants_mode; 1623 1624 void __iomem *regs; 1625 1626 struct intel_uncore uncore; 1627 1628 struct i915_virtual_gpu vgpu; 1629 1630 struct intel_csr csr; 1631 1632 /* Display CSR-related protection */ 1633 struct mutex csr_lock; 1634 1635 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 1636 1637 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1638 * controller on different i2c buses. */ 1639 struct mutex gmbus_mutex; 1640 1641 /** 1642 * Base address of the gmbus and gpio block. 1643 */ 1644 uint32_t gpio_mmio_base; 1645 1646 /* MMIO base address for MIPI regs */ 1647 uint32_t mipi_mmio_base; 1648 1649 wait_queue_head_t gmbus_wait_queue; 1650 1651 struct pci_dev *bridge_dev; 1652 struct intel_engine_cs ring[I915_NUM_RINGS]; 1653 struct drm_i915_gem_object *semaphore_obj; 1654 uint32_t last_seqno, next_seqno; 1655 1656 struct drm_dma_handle *status_page_dmah; 1657 struct resource mch_res; 1658 1659 /* protects the irq masks */ 1660 spinlock_t irq_lock; 1661 1662 /* protects the mmio flip data */ 1663 spinlock_t mmio_flip_lock; 1664 1665 bool display_irqs_enabled; 1666 1667 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1668 struct pm_qos_request pm_qos; 1669 1670 /* Sideband mailbox protection */ 1671 struct mutex sb_lock; 1672 1673 /** Cached value of IMR to avoid reads in updating the bitfield */ 1674 union { 1675 u32 irq_mask; 1676 u32 de_irq_mask[I915_MAX_PIPES]; 1677 }; 1678 u32 gt_irq_mask; 1679 u32 pm_irq_mask; 1680 u32 pm_rps_events; 1681 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1682 1683 struct work_struct hotplug_work; 1684 struct { 1685 unsigned long hpd_last_jiffies; 1686 int hpd_cnt; 1687 enum { 1688 HPD_ENABLED = 0, 1689 HPD_DISABLED = 1, 1690 HPD_MARK_DISABLED = 2 1691 } hpd_mark; 1692 } hpd_stats[HPD_NUM_PINS]; 1693 u32 hpd_event_bits; 1694 struct delayed_work hotplug_reenable_work; 1695 1696 struct i915_fbc fbc; 1697 struct i915_drrs drrs; 1698 struct intel_opregion opregion; 1699 struct intel_vbt_data vbt; 1700 1701 bool preserve_bios_swizzle; 1702 1703 /* overlay */ 1704 struct intel_overlay *overlay; 1705 1706 /* backlight registers and fields in struct intel_panel */ 1707 struct mutex backlight_lock; 1708 1709 /* LVDS info */ 1710 bool no_aux_handshake; 1711 1712 /* protects panel power sequencer state */ 1713 struct mutex pps_mutex; 1714 1715 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1716 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1717 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1718 1719 unsigned int fsb_freq, mem_freq, is_ddr3; 1720 unsigned int skl_boot_cdclk; 1721 unsigned int cdclk_freq; 1722 unsigned int hpll_freq; 1723 1724 /** 1725 * wq - Driver workqueue for GEM. 1726 * 1727 * NOTE: Work items scheduled here are not allowed to grab any modeset 1728 * locks, for otherwise the flushing done in the pageflip code will 1729 * result in deadlocks. 1730 */ 1731 struct workqueue_struct *wq; 1732 1733 /* Display functions */ 1734 struct drm_i915_display_funcs display; 1735 1736 /* PCH chipset type */ 1737 enum intel_pch pch_type; 1738 unsigned short pch_id; 1739 1740 unsigned long quirks; 1741 1742 enum modeset_restore modeset_restore; 1743 struct mutex modeset_restore_lock; 1744 1745 struct list_head vm_list; /* Global list of all address spaces */ 1746 struct i915_gtt gtt; /* VM representing the global address space */ 1747 1748 struct i915_gem_mm mm; 1749 DECLARE_HASHTABLE(mm_structs, 7); 1750 struct mutex mm_lock; 1751 1752 /* Kernel Modesetting */ 1753 1754 struct sdvo_device_mapping sdvo_mappings[2]; 1755 1756 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1757 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1758 wait_queue_head_t pending_flip_queue; 1759 1760 #ifdef CONFIG_DEBUG_FS 1761 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1762 #endif 1763 1764 int num_shared_dpll; 1765 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1766 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1767 1768 struct i915_workarounds workarounds; 1769 1770 /* Reclocking support */ 1771 bool render_reclock_avail; 1772 bool lvds_downclock_avail; 1773 /* indicates the reduced downclock for LVDS*/ 1774 int lvds_downclock; 1775 1776 struct i915_frontbuffer_tracking fb_tracking; 1777 1778 u16 orig_clock; 1779 1780 bool mchbar_need_disable; 1781 1782 struct intel_l3_parity l3_parity; 1783 1784 /* Cannot be determined by PCIID. You must always read a register. */ 1785 size_t ellc_size; 1786 1787 /* gen6+ rps state */ 1788 struct intel_gen6_power_mgmt rps; 1789 1790 /* ilk-only ips/rps state. Everything in here is protected by the global 1791 * mchdev_lock in intel_pm.c */ 1792 struct intel_ilk_power_mgmt ips; 1793 1794 struct i915_power_domains power_domains; 1795 1796 struct i915_psr psr; 1797 1798 struct i915_gpu_error gpu_error; 1799 1800 struct drm_i915_gem_object *vlv_pctx; 1801 1802 #ifdef CONFIG_DRM_I915_FBDEV 1803 /* list of fbdev register on this device */ 1804 struct intel_fbdev *fbdev; 1805 struct work_struct fbdev_suspend_work; 1806 #endif 1807 1808 struct drm_property *broadcast_rgb_property; 1809 struct drm_property *force_audio_property; 1810 1811 /* hda/i915 audio component */ 1812 bool audio_component_registered; 1813 1814 uint32_t hw_context_size; 1815 struct list_head context_list; 1816 1817 u32 fdi_rx_config; 1818 1819 u32 chv_phy_control; 1820 1821 u32 suspend_count; 1822 struct i915_suspend_saved_registers regfile; 1823 struct vlv_s0ix_state vlv_s0ix_state; 1824 1825 struct { 1826 /* 1827 * Raw watermark latency values: 1828 * in 0.1us units for WM0, 1829 * in 0.5us units for WM1+. 1830 */ 1831 /* primary */ 1832 uint16_t pri_latency[5]; 1833 /* sprite */ 1834 uint16_t spr_latency[5]; 1835 /* cursor */ 1836 uint16_t cur_latency[5]; 1837 /* 1838 * Raw watermark memory latency values 1839 * for SKL for all 8 levels 1840 * in 1us units. 1841 */ 1842 uint16_t skl_latency[8]; 1843 1844 /* 1845 * The skl_wm_values structure is a bit too big for stack 1846 * allocation, so we keep the staging struct where we store 1847 * intermediate results here instead. 1848 */ 1849 struct skl_wm_values skl_results; 1850 1851 /* current hardware state */ 1852 union { 1853 struct ilk_wm_values hw; 1854 struct skl_wm_values skl_hw; 1855 struct vlv_wm_values vlv; 1856 }; 1857 } wm; 1858 1859 struct i915_runtime_pm pm; 1860 1861 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; 1862 u32 long_hpd_port_mask; 1863 u32 short_hpd_port_mask; 1864 struct work_struct dig_port_work; 1865 1866 /* 1867 * if we get a HPD irq from DP and a HPD irq from non-DP 1868 * the non-DP HPD could block the workqueue on a mode config 1869 * mutex getting, that userspace may have taken. However 1870 * userspace is waiting on the DP workqueue to run which is 1871 * blocked behind the non-DP one. 1872 */ 1873 struct workqueue_struct *dp_wq; 1874 1875 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1876 struct { 1877 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file, 1878 struct intel_engine_cs *ring, 1879 struct intel_context *ctx, 1880 struct drm_i915_gem_execbuffer2 *args, 1881 struct list_head *vmas, 1882 struct drm_i915_gem_object *batch_obj, 1883 u64 exec_start, u32 flags); 1884 int (*init_rings)(struct drm_device *dev); 1885 void (*cleanup_ring)(struct intel_engine_cs *ring); 1886 void (*stop_ring)(struct intel_engine_cs *ring); 1887 } gt; 1888 1889 bool edp_low_vswing; 1890 1891 /* 1892 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1893 * will be rejected. Instead look for a better place. 1894 */ 1895 }; 1896 1897 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1898 { 1899 return dev->dev_private; 1900 } 1901 1902 static inline struct drm_i915_private *dev_to_i915(struct device *dev) 1903 { 1904 return to_i915(dev_get_drvdata(dev)); 1905 } 1906 1907 /* Iterate over initialised rings */ 1908 #define for_each_ring(ring__, dev_priv__, i__) \ 1909 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1910 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1911 1912 enum hdmi_force_audio { 1913 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1914 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1915 HDMI_AUDIO_AUTO, /* trust EDID */ 1916 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1917 }; 1918 1919 #define I915_GTT_OFFSET_NONE ((u32)-1) 1920 1921 struct drm_i915_gem_object_ops { 1922 /* Interface between the GEM object and its backing storage. 1923 * get_pages() is called once prior to the use of the associated set 1924 * of pages before to binding them into the GTT, and put_pages() is 1925 * called after we no longer need them. As we expect there to be 1926 * associated cost with migrating pages between the backing storage 1927 * and making them available for the GPU (e.g. clflush), we may hold 1928 * onto the pages after they are no longer referenced by the GPU 1929 * in case they may be used again shortly (for example migrating the 1930 * pages to a different memory domain within the GTT). put_pages() 1931 * will therefore most likely be called when the object itself is 1932 * being released or under memory pressure (where we attempt to 1933 * reap pages for the shrinker). 1934 */ 1935 int (*get_pages)(struct drm_i915_gem_object *); 1936 void (*put_pages)(struct drm_i915_gem_object *); 1937 int (*dmabuf_export)(struct drm_i915_gem_object *); 1938 void (*release)(struct drm_i915_gem_object *); 1939 }; 1940 1941 /* 1942 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1943 * considered to be the frontbuffer for the given plane interface-vise. This 1944 * doesn't mean that the hw necessarily already scans it out, but that any 1945 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1946 * 1947 * We have one bit per pipe and per scanout plane type. 1948 */ 1949 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 1950 #define INTEL_FRONTBUFFER_BITS \ 1951 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 1952 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 1953 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1954 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 1955 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1956 #define INTEL_FRONTBUFFER_SPRITE(pipe) \ 1957 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1958 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1959 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1960 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1961 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1962 1963 struct drm_i915_gem_object { 1964 struct drm_gem_object base; 1965 1966 const struct drm_i915_gem_object_ops *ops; 1967 1968 /** List of VMAs backed by this object */ 1969 struct list_head vma_list; 1970 1971 /** Stolen memory for this object, instead of being backed by shmem. */ 1972 struct drm_mm_node *stolen; 1973 struct list_head global_list; 1974 1975 struct list_head ring_list[I915_NUM_RINGS]; 1976 /** Used in execbuf to temporarily hold a ref */ 1977 struct list_head obj_exec_link; 1978 1979 struct list_head batch_pool_link; 1980 1981 /** 1982 * This is set if the object is on the active lists (has pending 1983 * rendering and so a non-zero seqno), and is not set if it i s on 1984 * inactive (ready to be unbound) list. 1985 */ 1986 unsigned int active:I915_NUM_RINGS; 1987 1988 /** 1989 * This is set if the object has been written to since last bound 1990 * to the GTT 1991 */ 1992 unsigned int dirty:1; 1993 1994 /** 1995 * Fence register bits (if any) for this object. Will be set 1996 * as needed when mapped into the GTT. 1997 * Protected by dev->struct_mutex. 1998 */ 1999 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 2000 2001 /** 2002 * Advice: are the backing pages purgeable? 2003 */ 2004 unsigned int madv:2; 2005 2006 /** 2007 * Current tiling mode for the object. 2008 */ 2009 unsigned int tiling_mode:2; 2010 /** 2011 * Whether the tiling parameters for the currently associated fence 2012 * register have changed. Note that for the purposes of tracking 2013 * tiling changes we also treat the unfenced register, the register 2014 * slot that the object occupies whilst it executes a fenced 2015 * command (such as BLT on gen2/3), as a "fence". 2016 */ 2017 unsigned int fence_dirty:1; 2018 2019 /** 2020 * Is the object at the current location in the gtt mappable and 2021 * fenceable? Used to avoid costly recalculations. 2022 */ 2023 unsigned int map_and_fenceable:1; 2024 2025 /** 2026 * Whether the current gtt mapping needs to be mappable (and isn't just 2027 * mappable by accident). Track pin and fault separate for a more 2028 * accurate mappable working set. 2029 */ 2030 unsigned int fault_mappable:1; 2031 2032 /* 2033 * Is the object to be mapped as read-only to the GPU 2034 * Only honoured if hardware has relevant pte bit 2035 */ 2036 unsigned long gt_ro:1; 2037 unsigned int cache_level:3; 2038 unsigned int cache_dirty:1; 2039 2040 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 2041 2042 unsigned int pin_display; 2043 2044 struct sg_table *pages; 2045 int pages_pin_count; 2046 struct get_page { 2047 struct scatterlist *sg; 2048 int last; 2049 } get_page; 2050 2051 /* prime dma-buf support */ 2052 void *dma_buf_vmapping; 2053 int vmapping_count; 2054 2055 /** Breadcrumb of last rendering to the buffer. 2056 * There can only be one writer, but we allow for multiple readers. 2057 * If there is a writer that necessarily implies that all other 2058 * read requests are complete - but we may only be lazily clearing 2059 * the read requests. A read request is naturally the most recent 2060 * request on a ring, so we may have two different write and read 2061 * requests on one ring where the write request is older than the 2062 * read request. This allows for the CPU to read from an active 2063 * buffer by only waiting for the write to complete. 2064 * */ 2065 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; 2066 struct drm_i915_gem_request *last_write_req; 2067 /** Breadcrumb of last fenced GPU access to the buffer. */ 2068 struct drm_i915_gem_request *last_fenced_req; 2069 2070 /** Current tiling stride for the object, if it's tiled. */ 2071 uint32_t stride; 2072 2073 /** References from framebuffers, locks out tiling changes. */ 2074 unsigned long framebuffer_references; 2075 2076 /** Record of address bit 17 of each page at last unbind. */ 2077 unsigned long *bit_17; 2078 2079 union { 2080 /** for phy allocated objects */ 2081 struct drm_dma_handle *phys_handle; 2082 2083 struct i915_gem_userptr { 2084 uintptr_t ptr; 2085 unsigned read_only :1; 2086 unsigned workers :4; 2087 #define I915_GEM_USERPTR_MAX_WORKERS 15 2088 2089 struct i915_mm_struct *mm; 2090 struct i915_mmu_object *mmu_object; 2091 struct work_struct *work; 2092 } userptr; 2093 }; 2094 }; 2095 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 2096 2097 void i915_gem_track_fb(struct drm_i915_gem_object *old, 2098 struct drm_i915_gem_object *new, 2099 unsigned frontbuffer_bits); 2100 2101 /** 2102 * Request queue structure. 2103 * 2104 * The request queue allows us to note sequence numbers that have been emitted 2105 * and may be associated with active buffers to be retired. 2106 * 2107 * By keeping this list, we can avoid having to do questionable sequence 2108 * number comparisons on buffer last_read|write_seqno. It also allows an 2109 * emission time to be associated with the request for tracking how far ahead 2110 * of the GPU the submission is. 2111 * 2112 * The requests are reference counted, so upon creation they should have an 2113 * initial reference taken using kref_init 2114 */ 2115 struct drm_i915_gem_request { 2116 struct kref ref; 2117 2118 /** On Which ring this request was generated */ 2119 struct drm_i915_private *i915; 2120 struct intel_engine_cs *ring; 2121 2122 /** GEM sequence number associated with this request. */ 2123 uint32_t seqno; 2124 2125 /** Position in the ringbuffer of the start of the request */ 2126 u32 head; 2127 2128 /** 2129 * Position in the ringbuffer of the start of the postfix. 2130 * This is required to calculate the maximum available ringbuffer 2131 * space without overwriting the postfix. 2132 */ 2133 u32 postfix; 2134 2135 /** Position in the ringbuffer of the end of the whole request */ 2136 u32 tail; 2137 2138 /** 2139 * Context and ring buffer related to this request 2140 * Contexts are refcounted, so when this request is associated with a 2141 * context, we must increment the context's refcount, to guarantee that 2142 * it persists while any request is linked to it. Requests themselves 2143 * are also refcounted, so the request will only be freed when the last 2144 * reference to it is dismissed, and the code in 2145 * i915_gem_request_free() will then decrement the refcount on the 2146 * context. 2147 */ 2148 struct intel_context *ctx; 2149 struct intel_ringbuffer *ringbuf; 2150 2151 /** Batch buffer related to this request if any */ 2152 struct drm_i915_gem_object *batch_obj; 2153 2154 /** Time at which this request was emitted, in jiffies. */ 2155 unsigned long emitted_jiffies; 2156 2157 /** global list entry for this request */ 2158 struct list_head list; 2159 2160 struct drm_i915_file_private *file_priv; 2161 /** file_priv list entry for this request */ 2162 struct list_head client_list; 2163 2164 /** process identifier submitting this request */ 2165 struct pid *pid; 2166 2167 /** 2168 * The ELSP only accepts two elements at a time, so we queue 2169 * context/tail pairs on a given queue (ring->execlist_queue) until the 2170 * hardware is available. The queue serves a double purpose: we also use 2171 * it to keep track of the up to 2 contexts currently in the hardware 2172 * (usually one in execution and the other queued up by the GPU): We 2173 * only remove elements from the head of the queue when the hardware 2174 * informs us that an element has been completed. 2175 * 2176 * All accesses to the queue are mediated by a spinlock 2177 * (ring->execlist_lock). 2178 */ 2179 2180 /** Execlist link in the submission queue.*/ 2181 struct list_head execlist_link; 2182 2183 /** Execlists no. of times this request has been sent to the ELSP */ 2184 int elsp_submitted; 2185 2186 }; 2187 2188 int i915_gem_request_alloc(struct intel_engine_cs *ring, 2189 struct intel_context *ctx); 2190 void i915_gem_request_free(struct kref *req_ref); 2191 2192 static inline uint32_t 2193 i915_gem_request_get_seqno(struct drm_i915_gem_request *req) 2194 { 2195 return req ? req->seqno : 0; 2196 } 2197 2198 static inline struct intel_engine_cs * 2199 i915_gem_request_get_ring(struct drm_i915_gem_request *req) 2200 { 2201 return req ? req->ring : NULL; 2202 } 2203 2204 static inline struct drm_i915_gem_request * 2205 i915_gem_request_reference(struct drm_i915_gem_request *req) 2206 { 2207 if (req) 2208 kref_get(&req->ref); 2209 return req; 2210 } 2211 2212 static inline void 2213 i915_gem_request_unreference(struct drm_i915_gem_request *req) 2214 { 2215 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); 2216 kref_put(&req->ref, i915_gem_request_free); 2217 } 2218 2219 static inline void 2220 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) 2221 { 2222 struct drm_device *dev; 2223 2224 if (!req) 2225 return; 2226 2227 dev = req->ring->dev; 2228 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) 2229 mutex_unlock(&dev->struct_mutex); 2230 } 2231 2232 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, 2233 struct drm_i915_gem_request *src) 2234 { 2235 if (src) 2236 i915_gem_request_reference(src); 2237 2238 if (*pdst) 2239 i915_gem_request_unreference(*pdst); 2240 2241 *pdst = src; 2242 } 2243 2244 /* 2245 * XXX: i915_gem_request_completed should be here but currently needs the 2246 * definition of i915_seqno_passed() which is below. It will be moved in 2247 * a later patch when the call to i915_seqno_passed() is obsoleted... 2248 */ 2249 2250 /* 2251 * A command that requires special handling by the command parser. 2252 */ 2253 struct drm_i915_cmd_descriptor { 2254 /* 2255 * Flags describing how the command parser processes the command. 2256 * 2257 * CMD_DESC_FIXED: The command has a fixed length if this is set, 2258 * a length mask if not set 2259 * CMD_DESC_SKIP: The command is allowed but does not follow the 2260 * standard length encoding for the opcode range in 2261 * which it falls 2262 * CMD_DESC_REJECT: The command is never allowed 2263 * CMD_DESC_REGISTER: The command should be checked against the 2264 * register whitelist for the appropriate ring 2265 * CMD_DESC_MASTER: The command is allowed if the submitting process 2266 * is the DRM master 2267 */ 2268 u32 flags; 2269 #define CMD_DESC_FIXED (1<<0) 2270 #define CMD_DESC_SKIP (1<<1) 2271 #define CMD_DESC_REJECT (1<<2) 2272 #define CMD_DESC_REGISTER (1<<3) 2273 #define CMD_DESC_BITMASK (1<<4) 2274 #define CMD_DESC_MASTER (1<<5) 2275 2276 /* 2277 * The command's unique identification bits and the bitmask to get them. 2278 * This isn't strictly the opcode field as defined in the spec and may 2279 * also include type, subtype, and/or subop fields. 2280 */ 2281 struct { 2282 u32 value; 2283 u32 mask; 2284 } cmd; 2285 2286 /* 2287 * The command's length. The command is either fixed length (i.e. does 2288 * not include a length field) or has a length field mask. The flag 2289 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 2290 * a length mask. All command entries in a command table must include 2291 * length information. 2292 */ 2293 union { 2294 u32 fixed; 2295 u32 mask; 2296 } length; 2297 2298 /* 2299 * Describes where to find a register address in the command to check 2300 * against the ring's register whitelist. Only valid if flags has the 2301 * CMD_DESC_REGISTER bit set. 2302 * 2303 * A non-zero step value implies that the command may access multiple 2304 * registers in sequence (e.g. LRI), in that case step gives the 2305 * distance in dwords between individual offset fields. 2306 */ 2307 struct { 2308 u32 offset; 2309 u32 mask; 2310 u32 step; 2311 } reg; 2312 2313 #define MAX_CMD_DESC_BITMASKS 3 2314 /* 2315 * Describes command checks where a particular dword is masked and 2316 * compared against an expected value. If the command does not match 2317 * the expected value, the parser rejects it. Only valid if flags has 2318 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2319 * are valid. 2320 * 2321 * If the check specifies a non-zero condition_mask then the parser 2322 * only performs the check when the bits specified by condition_mask 2323 * are non-zero. 2324 */ 2325 struct { 2326 u32 offset; 2327 u32 mask; 2328 u32 expected; 2329 u32 condition_offset; 2330 u32 condition_mask; 2331 } bits[MAX_CMD_DESC_BITMASKS]; 2332 }; 2333 2334 /* 2335 * A table of commands requiring special handling by the command parser. 2336 * 2337 * Each ring has an array of tables. Each table consists of an array of command 2338 * descriptors, which must be sorted with command opcodes in ascending order. 2339 */ 2340 struct drm_i915_cmd_table { 2341 const struct drm_i915_cmd_descriptor *table; 2342 int count; 2343 }; 2344 2345 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2346 #define __I915__(p) ({ \ 2347 struct drm_i915_private *__p; \ 2348 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2349 __p = (struct drm_i915_private *)p; \ 2350 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2351 __p = to_i915((struct drm_device *)p); \ 2352 else \ 2353 BUILD_BUG(); \ 2354 __p; \ 2355 }) 2356 #define INTEL_INFO(p) (&__I915__(p)->info) 2357 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2358 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) 2359 2360 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2361 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2362 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2363 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2364 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2365 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2366 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2367 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2368 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2369 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2370 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2371 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2372 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2373 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2374 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2375 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2376 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2377 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2378 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2379 INTEL_DEVID(dev) == 0x0152 || \ 2380 INTEL_DEVID(dev) == 0x015a) 2381 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2382 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2383 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2384 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2385 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) 2386 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) 2387 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2388 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2389 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2390 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2391 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2392 (INTEL_DEVID(dev) & 0xf) == 0xb || \ 2393 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2394 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2395 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2396 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2397 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2398 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2399 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2400 /* ULX machines are also considered ULT. */ 2401 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2402 INTEL_DEVID(dev) == 0x0A1E) 2403 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2404 2405 #define SKL_REVID_A0 (0x0) 2406 #define SKL_REVID_B0 (0x1) 2407 #define SKL_REVID_C0 (0x2) 2408 #define SKL_REVID_D0 (0x3) 2409 #define SKL_REVID_E0 (0x4) 2410 #define SKL_REVID_F0 (0x5) 2411 2412 #define BXT_REVID_A0 (0x0) 2413 #define BXT_REVID_B0 (0x3) 2414 #define BXT_REVID_C0 (0x6) 2415 2416 /* 2417 * The genX designation typically refers to the render engine, so render 2418 * capability related checks should use IS_GEN, while display and other checks 2419 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2420 * chips, etc.). 2421 */ 2422 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2423 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2424 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2425 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2426 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2427 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2428 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2429 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) 2430 2431 #define RENDER_RING (1<<RCS) 2432 #define BSD_RING (1<<VCS) 2433 #define BLT_RING (1<<BCS) 2434 #define VEBOX_RING (1<<VECS) 2435 #define BSD2_RING (1<<VCS2) 2436 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2437 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2438 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2439 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2440 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2441 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2442 __I915__(dev)->ellc_size) 2443 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2444 2445 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2446 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) 2447 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2448 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) 2449 2450 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2451 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2452 2453 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2454 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2455 /* 2456 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2457 * even when in MSI mode. This results in spurious interrupt warnings if the 2458 * legacy irq no. is shared with another device. The kernel then disables that 2459 * interrupt source and so prevents the other device from working properly. 2460 */ 2461 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2462 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2463 2464 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2465 * rows, which changed the alignment requirements and fence programming. 2466 */ 2467 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2468 IS_I915GM(dev))) 2469 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 2470 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2471 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2472 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2473 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2474 2475 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2476 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2477 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2478 2479 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) 2480 2481 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ 2482 INTEL_INFO(dev)->gen >= 9) 2483 2484 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2485 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2486 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ 2487 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ 2488 IS_SKYLAKE(dev)) 2489 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2490 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ 2491 IS_SKYLAKE(dev)) 2492 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) 2493 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) 2494 2495 #define HAS_CSR(dev) (IS_SKYLAKE(dev)) 2496 2497 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2498 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2499 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2500 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2501 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2502 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2503 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 2504 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 2505 2506 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) 2507 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) 2508 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2509 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2510 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2511 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2512 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2513 2514 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2515 2516 /* DPF == dynamic parity feature */ 2517 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2518 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2519 2520 #define GT_FREQUENCY_MULTIPLIER 50 2521 #define GEN9_FREQ_SCALER 3 2522 2523 #include "i915_trace.h" 2524 2525 extern const struct drm_ioctl_desc i915_ioctls[]; 2526 extern int i915_max_ioctl; 2527 2528 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); 2529 extern int i915_resume_legacy(struct drm_device *dev); 2530 2531 /* i915_params.c */ 2532 struct i915_params { 2533 int modeset; 2534 int panel_ignore_lid; 2535 int semaphores; 2536 unsigned int lvds_downclock; 2537 int lvds_channel_mode; 2538 int panel_use_ssc; 2539 int vbt_sdvo_panel_type; 2540 int enable_rc6; 2541 int enable_fbc; 2542 int enable_ppgtt; 2543 int enable_execlists; 2544 int enable_psr; 2545 unsigned int preliminary_hw_support; 2546 int disable_power_well; 2547 int enable_ips; 2548 int invert_brightness; 2549 int enable_cmd_parser; 2550 /* leave bools at the end to not create holes */ 2551 bool enable_hangcheck; 2552 bool fastboot; 2553 bool prefault_disable; 2554 bool load_detect_test; 2555 bool reset; 2556 bool disable_display; 2557 bool disable_vtd_wa; 2558 int use_mmio_flip; 2559 int mmio_debug; 2560 bool verbose_state_checks; 2561 bool nuclear_pageflip; 2562 int edp_vswing; 2563 }; 2564 extern struct i915_params i915 __read_mostly; 2565 2566 /* i915_dma.c */ 2567 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2568 extern int i915_driver_unload(struct drm_device *); 2569 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2570 extern void i915_driver_lastclose(struct drm_device * dev); 2571 extern void i915_driver_preclose(struct drm_device *dev, 2572 struct drm_file *file); 2573 extern void i915_driver_postclose(struct drm_device *dev, 2574 struct drm_file *file); 2575 extern int i915_driver_device_is_agp(struct drm_device * dev); 2576 #ifdef CONFIG_COMPAT 2577 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2578 unsigned long arg); 2579 #endif 2580 extern int intel_gpu_reset(struct drm_device *dev); 2581 extern int i915_reset(struct drm_device *dev); 2582 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2583 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2584 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2585 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2586 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2587 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2588 void i915_firmware_load_error_print(const char *fw_path, int err); 2589 2590 /* i915_irq.c */ 2591 void i915_queue_hangcheck(struct drm_device *dev); 2592 __printf(3, 4) 2593 void i915_handle_error(struct drm_device *dev, bool wedged, 2594 const char *fmt, ...); 2595 2596 extern void intel_irq_init(struct drm_i915_private *dev_priv); 2597 extern void intel_hpd_init(struct drm_i915_private *dev_priv); 2598 int intel_irq_install(struct drm_i915_private *dev_priv); 2599 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 2600 2601 extern void intel_uncore_sanitize(struct drm_device *dev); 2602 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2603 bool restore_forcewake); 2604 extern void intel_uncore_init(struct drm_device *dev); 2605 extern void intel_uncore_check_errors(struct drm_device *dev); 2606 extern void intel_uncore_fini(struct drm_device *dev); 2607 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); 2608 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); 2609 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 2610 enum forcewake_domains domains); 2611 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 2612 enum forcewake_domains domains); 2613 /* Like above but the caller must manage the uncore.lock itself. 2614 * Must be used with I915_READ_FW and friends. 2615 */ 2616 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, 2617 enum forcewake_domains domains); 2618 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, 2619 enum forcewake_domains domains); 2620 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); 2621 static inline bool intel_vgpu_active(struct drm_device *dev) 2622 { 2623 return to_i915(dev)->vgpu.active; 2624 } 2625 2626 void 2627 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2628 u32 status_mask); 2629 2630 void 2631 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2632 u32 status_mask); 2633 2634 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2635 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2636 void 2637 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2638 void 2639 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2640 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 2641 uint32_t interrupt_mask, 2642 uint32_t enabled_irq_mask); 2643 #define ibx_enable_display_interrupt(dev_priv, bits) \ 2644 ibx_display_interrupt_update((dev_priv), (bits), (bits)) 2645 #define ibx_disable_display_interrupt(dev_priv, bits) \ 2646 ibx_display_interrupt_update((dev_priv), (bits), 0) 2647 2648 /* i915_gem.c */ 2649 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2650 struct drm_file *file_priv); 2651 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2652 struct drm_file *file_priv); 2653 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2654 struct drm_file *file_priv); 2655 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2656 struct drm_file *file_priv); 2657 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2658 struct drm_file *file_priv); 2659 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2660 struct drm_file *file_priv); 2661 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2662 struct drm_file *file_priv); 2663 void i915_gem_execbuffer_move_to_active(struct list_head *vmas, 2664 struct intel_engine_cs *ring); 2665 void i915_gem_execbuffer_retire_commands(struct drm_device *dev, 2666 struct drm_file *file, 2667 struct intel_engine_cs *ring, 2668 struct drm_i915_gem_object *obj); 2669 int i915_gem_ringbuffer_submission(struct drm_device *dev, 2670 struct drm_file *file, 2671 struct intel_engine_cs *ring, 2672 struct intel_context *ctx, 2673 struct drm_i915_gem_execbuffer2 *args, 2674 struct list_head *vmas, 2675 struct drm_i915_gem_object *batch_obj, 2676 u64 exec_start, u32 flags); 2677 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2678 struct drm_file *file_priv); 2679 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2680 struct drm_file *file_priv); 2681 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2682 struct drm_file *file_priv); 2683 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2684 struct drm_file *file); 2685 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2686 struct drm_file *file); 2687 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2688 struct drm_file *file_priv); 2689 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2690 struct drm_file *file_priv); 2691 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2692 struct drm_file *file_priv); 2693 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2694 struct drm_file *file_priv); 2695 int i915_gem_init_userptr(struct drm_device *dev); 2696 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2697 struct drm_file *file); 2698 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2699 struct drm_file *file_priv); 2700 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2701 struct drm_file *file_priv); 2702 void i915_gem_load(struct drm_device *dev); 2703 void *i915_gem_object_alloc(struct drm_device *dev); 2704 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2705 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2706 const struct drm_i915_gem_object_ops *ops); 2707 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2708 size_t size); 2709 void i915_init_vm(struct drm_i915_private *dev_priv, 2710 struct i915_address_space *vm); 2711 void i915_gem_free_object(struct drm_gem_object *obj); 2712 void i915_gem_vma_destroy(struct i915_vma *vma); 2713 2714 /* Flags used by pin/bind&friends. */ 2715 #define PIN_MAPPABLE (1<<0) 2716 #define PIN_NONBLOCK (1<<1) 2717 #define PIN_GLOBAL (1<<2) 2718 #define PIN_OFFSET_BIAS (1<<3) 2719 #define PIN_USER (1<<4) 2720 #define PIN_UPDATE (1<<5) 2721 #define PIN_OFFSET_MASK (~4095) 2722 int __must_check 2723 i915_gem_object_pin(struct drm_i915_gem_object *obj, 2724 struct i915_address_space *vm, 2725 uint32_t alignment, 2726 uint64_t flags); 2727 int __must_check 2728 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 2729 const struct i915_ggtt_view *view, 2730 uint32_t alignment, 2731 uint64_t flags); 2732 2733 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 2734 u32 flags); 2735 int __must_check i915_vma_unbind(struct i915_vma *vma); 2736 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2737 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2738 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2739 2740 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2741 int *needs_clflush); 2742 2743 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2744 2745 static inline int __sg_page_count(struct scatterlist *sg) 2746 { 2747 return sg->length >> PAGE_SHIFT; 2748 } 2749 2750 static inline struct page * 2751 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2752 { 2753 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) 2754 return NULL; 2755 2756 if (n < obj->get_page.last) { 2757 obj->get_page.sg = obj->pages->sgl; 2758 obj->get_page.last = 0; 2759 } 2760 2761 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { 2762 obj->get_page.last += __sg_page_count(obj->get_page.sg++); 2763 if (unlikely(sg_is_chain(obj->get_page.sg))) 2764 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); 2765 } 2766 2767 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); 2768 } 2769 2770 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2771 { 2772 BUG_ON(obj->pages == NULL); 2773 obj->pages_pin_count++; 2774 } 2775 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2776 { 2777 BUG_ON(obj->pages_pin_count == 0); 2778 obj->pages_pin_count--; 2779 } 2780 2781 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2782 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2783 struct intel_engine_cs *to); 2784 void i915_vma_move_to_active(struct i915_vma *vma, 2785 struct intel_engine_cs *ring); 2786 int i915_gem_dumb_create(struct drm_file *file_priv, 2787 struct drm_device *dev, 2788 struct drm_mode_create_dumb *args); 2789 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2790 uint32_t handle, uint64_t *offset); 2791 /** 2792 * Returns true if seq1 is later than seq2. 2793 */ 2794 static inline bool 2795 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2796 { 2797 return (int32_t)(seq1 - seq2) >= 0; 2798 } 2799 2800 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, 2801 bool lazy_coherency) 2802 { 2803 u32 seqno; 2804 2805 BUG_ON(req == NULL); 2806 2807 seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2808 2809 return i915_seqno_passed(seqno, req->seqno); 2810 } 2811 2812 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2813 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2814 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2815 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2816 2817 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2818 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2819 2820 struct drm_i915_gem_request * 2821 i915_gem_find_active_request(struct intel_engine_cs *ring); 2822 2823 bool i915_gem_retire_requests(struct drm_device *dev); 2824 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2825 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2826 bool interruptible); 2827 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); 2828 2829 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2830 { 2831 return unlikely(atomic_read(&error->reset_counter) 2832 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2833 } 2834 2835 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2836 { 2837 return atomic_read(&error->reset_counter) & I915_WEDGED; 2838 } 2839 2840 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2841 { 2842 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2843 } 2844 2845 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2846 { 2847 return dev_priv->gpu_error.stop_rings == 0 || 2848 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2849 } 2850 2851 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2852 { 2853 return dev_priv->gpu_error.stop_rings == 0 || 2854 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2855 } 2856 2857 void i915_gem_reset(struct drm_device *dev); 2858 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2859 int __must_check i915_gem_init(struct drm_device *dev); 2860 int i915_gem_init_rings(struct drm_device *dev); 2861 int __must_check i915_gem_init_hw(struct drm_device *dev); 2862 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2863 void i915_gem_init_swizzling(struct drm_device *dev); 2864 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2865 int __must_check i915_gpu_idle(struct drm_device *dev); 2866 int __must_check i915_gem_suspend(struct drm_device *dev); 2867 int __i915_add_request(struct intel_engine_cs *ring, 2868 struct drm_file *file, 2869 struct drm_i915_gem_object *batch_obj); 2870 #define i915_add_request(ring) \ 2871 __i915_add_request(ring, NULL, NULL) 2872 int __i915_wait_request(struct drm_i915_gem_request *req, 2873 unsigned reset_counter, 2874 bool interruptible, 2875 s64 *timeout, 2876 struct intel_rps_client *rps); 2877 int __must_check i915_wait_request(struct drm_i915_gem_request *req); 2878 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 2879 int __must_check 2880 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 2881 bool readonly); 2882 int __must_check 2883 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2884 bool write); 2885 int __must_check 2886 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2887 int __must_check 2888 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2889 u32 alignment, 2890 struct intel_engine_cs *pipelined, 2891 const struct i915_ggtt_view *view); 2892 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, 2893 const struct i915_ggtt_view *view); 2894 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2895 int align); 2896 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2897 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2898 2899 uint32_t 2900 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2901 uint32_t 2902 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2903 int tiling_mode, bool fenced); 2904 2905 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2906 enum i915_cache_level cache_level); 2907 2908 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2909 struct dma_buf *dma_buf); 2910 2911 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2912 struct drm_gem_object *gem_obj, int flags); 2913 2914 void i915_gem_restore_fences(struct drm_device *dev); 2915 2916 unsigned long 2917 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, 2918 const struct i915_ggtt_view *view); 2919 unsigned long 2920 i915_gem_obj_offset(struct drm_i915_gem_object *o, 2921 struct i915_address_space *vm); 2922 static inline unsigned long 2923 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) 2924 { 2925 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); 2926 } 2927 2928 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2929 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, 2930 const struct i915_ggtt_view *view); 2931 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2932 struct i915_address_space *vm); 2933 2934 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2935 struct i915_address_space *vm); 2936 struct i915_vma * 2937 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2938 struct i915_address_space *vm); 2939 struct i915_vma * 2940 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, 2941 const struct i915_ggtt_view *view); 2942 2943 struct i915_vma * 2944 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2945 struct i915_address_space *vm); 2946 struct i915_vma * 2947 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, 2948 const struct i915_ggtt_view *view); 2949 2950 static inline struct i915_vma * 2951 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) 2952 { 2953 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); 2954 } 2955 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); 2956 2957 /* Some GGTT VM helpers */ 2958 #define i915_obj_to_ggtt(obj) \ 2959 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2960 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2961 { 2962 struct i915_address_space *ggtt = 2963 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2964 return vm == ggtt; 2965 } 2966 2967 static inline struct i915_hw_ppgtt * 2968 i915_vm_to_ppgtt(struct i915_address_space *vm) 2969 { 2970 WARN_ON(i915_is_ggtt(vm)); 2971 2972 return container_of(vm, struct i915_hw_ppgtt, base); 2973 } 2974 2975 2976 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2977 { 2978 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); 2979 } 2980 2981 static inline unsigned long 2982 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2983 { 2984 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); 2985 } 2986 2987 static inline int __must_check 2988 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2989 uint32_t alignment, 2990 unsigned flags) 2991 { 2992 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), 2993 alignment, flags | PIN_GLOBAL); 2994 } 2995 2996 static inline int 2997 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2998 { 2999 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 3000 } 3001 3002 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, 3003 const struct i915_ggtt_view *view); 3004 static inline void 3005 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) 3006 { 3007 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); 3008 } 3009 3010 /* i915_gem_context.c */ 3011 int __must_check i915_gem_context_init(struct drm_device *dev); 3012 void i915_gem_context_fini(struct drm_device *dev); 3013 void i915_gem_context_reset(struct drm_device *dev); 3014 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 3015 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 3016 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 3017 int i915_switch_context(struct intel_engine_cs *ring, 3018 struct intel_context *to); 3019 struct intel_context * 3020 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 3021 void i915_gem_context_free(struct kref *ctx_ref); 3022 struct drm_i915_gem_object * 3023 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); 3024 static inline void i915_gem_context_reference(struct intel_context *ctx) 3025 { 3026 kref_get(&ctx->ref); 3027 } 3028 3029 static inline void i915_gem_context_unreference(struct intel_context *ctx) 3030 { 3031 kref_put(&ctx->ref, i915_gem_context_free); 3032 } 3033 3034 static inline bool i915_gem_context_is_default(const struct intel_context *c) 3035 { 3036 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 3037 } 3038 3039 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 3040 struct drm_file *file); 3041 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 3042 struct drm_file *file); 3043 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 3044 struct drm_file *file_priv); 3045 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 3046 struct drm_file *file_priv); 3047 3048 /* i915_gem_evict.c */ 3049 int __must_check i915_gem_evict_something(struct drm_device *dev, 3050 struct i915_address_space *vm, 3051 int min_size, 3052 unsigned alignment, 3053 unsigned cache_level, 3054 unsigned long start, 3055 unsigned long end, 3056 unsigned flags); 3057 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 3058 int i915_gem_evict_everything(struct drm_device *dev); 3059 3060 /* belongs in i915_gem_gtt.h */ 3061 static inline void i915_gem_chipset_flush(struct drm_device *dev) 3062 { 3063 if (INTEL_INFO(dev)->gen < 6) 3064 intel_gtt_chipset_flush(); 3065 } 3066 3067 /* i915_gem_stolen.c */ 3068 int i915_gem_init_stolen(struct drm_device *dev); 3069 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); 3070 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 3071 void i915_gem_cleanup_stolen(struct drm_device *dev); 3072 struct drm_i915_gem_object * 3073 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 3074 struct drm_i915_gem_object * 3075 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 3076 u32 stolen_offset, 3077 u32 gtt_offset, 3078 u32 size); 3079 3080 /* i915_gem_shrinker.c */ 3081 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 3082 long target, 3083 unsigned flags); 3084 #define I915_SHRINK_PURGEABLE 0x1 3085 #define I915_SHRINK_UNBOUND 0x2 3086 #define I915_SHRINK_BOUND 0x4 3087 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); 3088 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); 3089 3090 3091 /* i915_gem_tiling.c */ 3092 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 3093 { 3094 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 3095 3096 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 3097 obj->tiling_mode != I915_TILING_NONE; 3098 } 3099 3100 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 3101 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 3102 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 3103 3104 /* i915_gem_debug.c */ 3105 #if WATCH_LISTS 3106 int i915_verify_lists(struct drm_device *dev); 3107 #else 3108 #define i915_verify_lists(dev) 0 3109 #endif 3110 3111 /* i915_debugfs.c */ 3112 int i915_debugfs_init(struct drm_minor *minor); 3113 void i915_debugfs_cleanup(struct drm_minor *minor); 3114 #ifdef CONFIG_DEBUG_FS 3115 int i915_debugfs_connector_add(struct drm_connector *connector); 3116 void intel_display_crc_init(struct drm_device *dev); 3117 #else 3118 static inline int i915_debugfs_connector_add(struct drm_connector *connector) 3119 { return 0; } 3120 static inline void intel_display_crc_init(struct drm_device *dev) {} 3121 #endif 3122 3123 /* i915_gpu_error.c */ 3124 __printf(2, 3) 3125 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 3126 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 3127 const struct i915_error_state_file_priv *error); 3128 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 3129 struct drm_i915_private *i915, 3130 size_t count, loff_t pos); 3131 static inline void i915_error_state_buf_release( 3132 struct drm_i915_error_state_buf *eb) 3133 { 3134 kfree(eb->buf); 3135 } 3136 void i915_capture_error_state(struct drm_device *dev, bool wedge, 3137 const char *error_msg); 3138 void i915_error_state_get(struct drm_device *dev, 3139 struct i915_error_state_file_priv *error_priv); 3140 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 3141 void i915_destroy_error_state(struct drm_device *dev); 3142 3143 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 3144 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 3145 3146 /* i915_cmd_parser.c */ 3147 int i915_cmd_parser_get_version(void); 3148 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 3149 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 3150 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 3151 int i915_parse_cmds(struct intel_engine_cs *ring, 3152 struct drm_i915_gem_object *batch_obj, 3153 struct drm_i915_gem_object *shadow_batch_obj, 3154 u32 batch_start_offset, 3155 u32 batch_len, 3156 bool is_master); 3157 3158 /* i915_suspend.c */ 3159 extern int i915_save_state(struct drm_device *dev); 3160 extern int i915_restore_state(struct drm_device *dev); 3161 3162 /* i915_sysfs.c */ 3163 void i915_setup_sysfs(struct drm_device *dev_priv); 3164 void i915_teardown_sysfs(struct drm_device *dev_priv); 3165 3166 /* intel_i2c.c */ 3167 extern int intel_setup_gmbus(struct drm_device *dev); 3168 extern void intel_teardown_gmbus(struct drm_device *dev); 3169 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 3170 unsigned int pin); 3171 3172 extern struct i2c_adapter * 3173 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); 3174 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 3175 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 3176 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 3177 { 3178 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 3179 } 3180 extern void intel_i2c_reset(struct drm_device *dev); 3181 3182 /* intel_opregion.c */ 3183 #ifdef CONFIG_ACPI 3184 extern int intel_opregion_setup(struct drm_device *dev); 3185 extern void intel_opregion_init(struct drm_device *dev); 3186 extern void intel_opregion_fini(struct drm_device *dev); 3187 extern void intel_opregion_asle_intr(struct drm_device *dev); 3188 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 3189 bool enable); 3190 extern int intel_opregion_notify_adapter(struct drm_device *dev, 3191 pci_power_t state); 3192 #else 3193 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 3194 static inline void intel_opregion_init(struct drm_device *dev) { return; } 3195 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 3196 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 3197 static inline int 3198 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 3199 { 3200 return 0; 3201 } 3202 static inline int 3203 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 3204 { 3205 return 0; 3206 } 3207 #endif 3208 3209 /* intel_acpi.c */ 3210 #ifdef CONFIG_ACPI 3211 extern void intel_register_dsm_handler(void); 3212 extern void intel_unregister_dsm_handler(void); 3213 #else 3214 static inline void intel_register_dsm_handler(void) { return; } 3215 static inline void intel_unregister_dsm_handler(void) { return; } 3216 #endif /* CONFIG_ACPI */ 3217 3218 /* modesetting */ 3219 extern void intel_modeset_init_hw(struct drm_device *dev); 3220 extern void intel_modeset_init(struct drm_device *dev); 3221 extern void intel_modeset_gem_init(struct drm_device *dev); 3222 extern void intel_modeset_cleanup(struct drm_device *dev); 3223 extern void intel_connector_unregister(struct intel_connector *); 3224 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 3225 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 3226 bool force_restore); 3227 extern void i915_redisable_vga(struct drm_device *dev); 3228 extern void i915_redisable_vga_power_on(struct drm_device *dev); 3229 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 3230 extern void intel_init_pch_refclk(struct drm_device *dev); 3231 extern void intel_set_rps(struct drm_device *dev, u8 val); 3232 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 3233 bool enable); 3234 extern void intel_detect_pch(struct drm_device *dev); 3235 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 3236 extern int intel_enable_rc6(const struct drm_device *dev); 3237 3238 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 3239 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 3240 struct drm_file *file); 3241 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 3242 struct drm_file *file); 3243 3244 /* overlay */ 3245 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 3246 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 3247 struct intel_overlay_error_state *error); 3248 3249 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 3250 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 3251 struct drm_device *dev, 3252 struct intel_display_error_state *error); 3253 3254 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3255 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 3256 3257 /* intel_sideband.c */ 3258 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); 3259 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); 3260 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 3261 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 3262 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3263 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 3264 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3265 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 3266 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3267 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 3268 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3269 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 3270 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3271 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 3272 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 3273 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 3274 enum intel_sbi_destination destination); 3275 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 3276 enum intel_sbi_destination destination); 3277 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 3278 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3279 3280 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); 3281 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 3282 3283 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 3284 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 3285 3286 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 3287 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 3288 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 3289 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 3290 3291 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 3292 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 3293 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 3294 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 3295 3296 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 3297 * will be implemented using 2 32-bit writes in an arbitrary order with 3298 * an arbitrary delay between them. This can cause the hardware to 3299 * act upon the intermediate value, possibly leading to corruption and 3300 * machine death. You have been warned. 3301 */ 3302 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 3303 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 3304 3305 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 3306 u32 upper, lower, tmp; \ 3307 tmp = I915_READ(upper_reg); \ 3308 do { \ 3309 upper = tmp; \ 3310 lower = I915_READ(lower_reg); \ 3311 tmp = I915_READ(upper_reg); \ 3312 } while (upper != tmp); \ 3313 (u64)upper << 32 | lower; }) 3314 3315 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 3316 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 3317 3318 /* These are untraced mmio-accessors that are only valid to be used inside 3319 * criticial sections inside IRQ handlers where forcewake is explicitly 3320 * controlled. 3321 * Think twice, and think again, before using these. 3322 * Note: Should only be used between intel_uncore_forcewake_irqlock() and 3323 * intel_uncore_forcewake_irqunlock(). 3324 */ 3325 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) 3326 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) 3327 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) 3328 3329 /* "Broadcast RGB" property */ 3330 #define INTEL_BROADCAST_RGB_AUTO 0 3331 #define INTEL_BROADCAST_RGB_FULL 1 3332 #define INTEL_BROADCAST_RGB_LIMITED 2 3333 3334 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 3335 { 3336 if (IS_VALLEYVIEW(dev)) 3337 return VLV_VGACNTRL; 3338 else if (INTEL_INFO(dev)->gen >= 5) 3339 return CPU_VGACNTRL; 3340 else 3341 return VGACNTRL; 3342 } 3343 3344 static inline void __user *to_user_ptr(u64 address) 3345 { 3346 return (void __user *)(uintptr_t)address; 3347 } 3348 3349 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 3350 { 3351 unsigned long j = msecs_to_jiffies(m); 3352 3353 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3354 } 3355 3356 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 3357 { 3358 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 3359 } 3360 3361 static inline unsigned long 3362 timespec_to_jiffies_timeout(const struct timespec *value) 3363 { 3364 unsigned long j = timespec_to_jiffies(value); 3365 3366 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3367 } 3368 3369 /* 3370 * If you need to wait X milliseconds between events A and B, but event B 3371 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 3372 * when event A happened, then just before event B you call this function and 3373 * pass the timestamp as the first argument, and X as the second argument. 3374 */ 3375 static inline void 3376 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 3377 { 3378 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 3379 3380 /* 3381 * Don't re-read the value of "jiffies" every time since it may change 3382 * behind our back and break the math. 3383 */ 3384 tmp_jiffies = jiffies; 3385 target_jiffies = timestamp_jiffies + 3386 msecs_to_jiffies_timeout(to_wait_ms); 3387 3388 if (time_after(target_jiffies, tmp_jiffies)) { 3389 remaining_jiffies = target_jiffies - tmp_jiffies; 3390 while (remaining_jiffies) 3391 remaining_jiffies = 3392 schedule_timeout_uninterruptible(remaining_jiffies); 3393 } 3394 } 3395 3396 static inline void i915_trace_irq_get(struct intel_engine_cs *ring, 3397 struct drm_i915_gem_request *req) 3398 { 3399 if (ring->trace_irq_req == NULL && ring->irq_get(ring)) 3400 i915_gem_request_assign(&ring->trace_irq_req, req); 3401 } 3402 3403 #endif 3404